1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com> 4 <http://rt2x00.serialmonkey.com> 5 6 */ 7 8 /* 9 Module: rt2500pci 10 Abstract: rt2500pci device specific routines. 11 Supported chipsets: RT2560. 12 */ 13 14 #include <linux/delay.h> 15 #include <linux/etherdevice.h> 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/pci.h> 19 #include <linux/eeprom_93cx6.h> 20 #include <linux/slab.h> 21 22 #include "rt2x00.h" 23 #include "rt2x00mmio.h" 24 #include "rt2x00pci.h" 25 #include "rt2500pci.h" 26 27 /* 28 * Register access. 29 * All access to the CSR registers will go through the methods 30 * rt2x00mmio_register_read and rt2x00mmio_register_write. 31 * BBP and RF register require indirect register access, 32 * and use the CSR registers BBPCSR and RFCSR to achieve this. 33 * These indirect registers work with busy bits, 34 * and we will try maximal REGISTER_BUSY_COUNT times to access 35 * the register while taking a REGISTER_BUSY_DELAY us delay 36 * between each attampt. When the busy bit is still set at that time, 37 * the access attempt is considered to have failed, 38 * and we will print an error. 39 */ 40 #define WAIT_FOR_BBP(__dev, __reg) \ 41 rt2x00mmio_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg)) 42 #define WAIT_FOR_RF(__dev, __reg) \ 43 rt2x00mmio_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg)) 44 45 static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev, 46 const unsigned int word, const u8 value) 47 { 48 u32 reg; 49 50 mutex_lock(&rt2x00dev->csr_mutex); 51 52 /* 53 * Wait until the BBP becomes available, afterwards we 54 * can safely write the new data into the register. 55 */ 56 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 57 reg = 0; 58 rt2x00_set_field32(®, BBPCSR_VALUE, value); 59 rt2x00_set_field32(®, BBPCSR_REGNUM, word); 60 rt2x00_set_field32(®, BBPCSR_BUSY, 1); 61 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1); 62 63 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); 64 } 65 66 mutex_unlock(&rt2x00dev->csr_mutex); 67 } 68 69 static u8 rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev, 70 const unsigned int word) 71 { 72 u32 reg; 73 u8 value; 74 75 mutex_lock(&rt2x00dev->csr_mutex); 76 77 /* 78 * Wait until the BBP becomes available, afterwards we 79 * can safely write the read request into the register. 80 * After the data has been written, we wait until hardware 81 * returns the correct value, if at any time the register 82 * doesn't become available in time, reg will be 0xffffffff 83 * which means we return 0xff to the caller. 84 */ 85 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 86 reg = 0; 87 rt2x00_set_field32(®, BBPCSR_REGNUM, word); 88 rt2x00_set_field32(®, BBPCSR_BUSY, 1); 89 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0); 90 91 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); 92 93 WAIT_FOR_BBP(rt2x00dev, ®); 94 } 95 96 value = rt2x00_get_field32(reg, BBPCSR_VALUE); 97 98 mutex_unlock(&rt2x00dev->csr_mutex); 99 100 return value; 101 } 102 103 static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev, 104 const unsigned int word, const u32 value) 105 { 106 u32 reg; 107 108 mutex_lock(&rt2x00dev->csr_mutex); 109 110 /* 111 * Wait until the RF becomes available, afterwards we 112 * can safely write the new data into the register. 113 */ 114 if (WAIT_FOR_RF(rt2x00dev, ®)) { 115 reg = 0; 116 rt2x00_set_field32(®, RFCSR_VALUE, value); 117 rt2x00_set_field32(®, RFCSR_NUMBER_OF_BITS, 20); 118 rt2x00_set_field32(®, RFCSR_IF_SELECT, 0); 119 rt2x00_set_field32(®, RFCSR_BUSY, 1); 120 121 rt2x00mmio_register_write(rt2x00dev, RFCSR, reg); 122 rt2x00_rf_write(rt2x00dev, word, value); 123 } 124 125 mutex_unlock(&rt2x00dev->csr_mutex); 126 } 127 128 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom) 129 { 130 struct rt2x00_dev *rt2x00dev = eeprom->data; 131 u32 reg; 132 133 reg = rt2x00mmio_register_read(rt2x00dev, CSR21); 134 135 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN); 136 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT); 137 eeprom->reg_data_clock = 138 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK); 139 eeprom->reg_chip_select = 140 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT); 141 } 142 143 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom) 144 { 145 struct rt2x00_dev *rt2x00dev = eeprom->data; 146 u32 reg = 0; 147 148 rt2x00_set_field32(®, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in); 149 rt2x00_set_field32(®, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out); 150 rt2x00_set_field32(®, CSR21_EEPROM_DATA_CLOCK, 151 !!eeprom->reg_data_clock); 152 rt2x00_set_field32(®, CSR21_EEPROM_CHIP_SELECT, 153 !!eeprom->reg_chip_select); 154 155 rt2x00mmio_register_write(rt2x00dev, CSR21, reg); 156 } 157 158 #ifdef CONFIG_RT2X00_LIB_DEBUGFS 159 static const struct rt2x00debug rt2500pci_rt2x00debug = { 160 .owner = THIS_MODULE, 161 .csr = { 162 .read = rt2x00mmio_register_read, 163 .write = rt2x00mmio_register_write, 164 .flags = RT2X00DEBUGFS_OFFSET, 165 .word_base = CSR_REG_BASE, 166 .word_size = sizeof(u32), 167 .word_count = CSR_REG_SIZE / sizeof(u32), 168 }, 169 .eeprom = { 170 .read = rt2x00_eeprom_read, 171 .write = rt2x00_eeprom_write, 172 .word_base = EEPROM_BASE, 173 .word_size = sizeof(u16), 174 .word_count = EEPROM_SIZE / sizeof(u16), 175 }, 176 .bbp = { 177 .read = rt2500pci_bbp_read, 178 .write = rt2500pci_bbp_write, 179 .word_base = BBP_BASE, 180 .word_size = sizeof(u8), 181 .word_count = BBP_SIZE / sizeof(u8), 182 }, 183 .rf = { 184 .read = rt2x00_rf_read, 185 .write = rt2500pci_rf_write, 186 .word_base = RF_BASE, 187 .word_size = sizeof(u32), 188 .word_count = RF_SIZE / sizeof(u32), 189 }, 190 }; 191 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 192 193 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev) 194 { 195 u32 reg; 196 197 reg = rt2x00mmio_register_read(rt2x00dev, GPIOCSR); 198 return rt2x00_get_field32(reg, GPIOCSR_VAL0); 199 } 200 201 #ifdef CONFIG_RT2X00_LIB_LEDS 202 static void rt2500pci_brightness_set(struct led_classdev *led_cdev, 203 enum led_brightness brightness) 204 { 205 struct rt2x00_led *led = 206 container_of(led_cdev, struct rt2x00_led, led_dev); 207 unsigned int enabled = brightness != LED_OFF; 208 u32 reg; 209 210 reg = rt2x00mmio_register_read(led->rt2x00dev, LEDCSR); 211 212 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC) 213 rt2x00_set_field32(®, LEDCSR_LINK, enabled); 214 else if (led->type == LED_TYPE_ACTIVITY) 215 rt2x00_set_field32(®, LEDCSR_ACTIVITY, enabled); 216 217 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg); 218 } 219 220 static int rt2500pci_blink_set(struct led_classdev *led_cdev, 221 unsigned long *delay_on, 222 unsigned long *delay_off) 223 { 224 struct rt2x00_led *led = 225 container_of(led_cdev, struct rt2x00_led, led_dev); 226 u32 reg; 227 228 reg = rt2x00mmio_register_read(led->rt2x00dev, LEDCSR); 229 rt2x00_set_field32(®, LEDCSR_ON_PERIOD, *delay_on); 230 rt2x00_set_field32(®, LEDCSR_OFF_PERIOD, *delay_off); 231 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg); 232 233 return 0; 234 } 235 236 static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev, 237 struct rt2x00_led *led, 238 enum led_type type) 239 { 240 led->rt2x00dev = rt2x00dev; 241 led->type = type; 242 led->led_dev.brightness_set = rt2500pci_brightness_set; 243 led->led_dev.blink_set = rt2500pci_blink_set; 244 led->flags = LED_INITIALIZED; 245 } 246 #endif /* CONFIG_RT2X00_LIB_LEDS */ 247 248 /* 249 * Configuration handlers. 250 */ 251 static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev, 252 const unsigned int filter_flags) 253 { 254 u32 reg; 255 256 /* 257 * Start configuration steps. 258 * Note that the version error will always be dropped 259 * and broadcast frames will always be accepted since 260 * there is no filter for it at this time. 261 */ 262 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0); 263 rt2x00_set_field32(®, RXCSR0_DROP_CRC, 264 !(filter_flags & FIF_FCSFAIL)); 265 rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL, 266 !(filter_flags & FIF_PLCPFAIL)); 267 rt2x00_set_field32(®, RXCSR0_DROP_CONTROL, 268 !(filter_flags & FIF_CONTROL)); 269 rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME, 270 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags)); 271 rt2x00_set_field32(®, RXCSR0_DROP_TODS, 272 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags) && 273 !rt2x00dev->intf_ap_count); 274 rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1); 275 rt2x00_set_field32(®, RXCSR0_DROP_MCAST, 276 !(filter_flags & FIF_ALLMULTI)); 277 rt2x00_set_field32(®, RXCSR0_DROP_BCAST, 0); 278 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); 279 } 280 281 static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev, 282 struct rt2x00_intf *intf, 283 struct rt2x00intf_conf *conf, 284 const unsigned int flags) 285 { 286 struct data_queue *queue = rt2x00dev->bcn; 287 unsigned int bcn_preload; 288 u32 reg; 289 290 if (flags & CONFIG_UPDATE_TYPE) { 291 /* 292 * Enable beacon config 293 */ 294 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20); 295 reg = rt2x00mmio_register_read(rt2x00dev, BCNCSR1); 296 rt2x00_set_field32(®, BCNCSR1_PRELOAD, bcn_preload); 297 rt2x00_set_field32(®, BCNCSR1_BEACON_CWMIN, queue->cw_min); 298 rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg); 299 300 /* 301 * Enable synchronisation. 302 */ 303 reg = rt2x00mmio_register_read(rt2x00dev, CSR14); 304 rt2x00_set_field32(®, CSR14_TSF_SYNC, conf->sync); 305 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); 306 } 307 308 if (flags & CONFIG_UPDATE_MAC) 309 rt2x00mmio_register_multiwrite(rt2x00dev, CSR3, 310 conf->mac, sizeof(conf->mac)); 311 312 if (flags & CONFIG_UPDATE_BSSID) 313 rt2x00mmio_register_multiwrite(rt2x00dev, CSR5, 314 conf->bssid, sizeof(conf->bssid)); 315 } 316 317 static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev, 318 struct rt2x00lib_erp *erp, 319 u32 changed) 320 { 321 int preamble_mask; 322 u32 reg; 323 324 /* 325 * When short preamble is enabled, we should set bit 0x08 326 */ 327 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 328 preamble_mask = erp->short_preamble << 3; 329 330 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR1); 331 rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, 0x162); 332 rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, 0xa2); 333 rt2x00_set_field32(®, TXCSR1_TSF_OFFSET, IEEE80211_HEADER); 334 rt2x00_set_field32(®, TXCSR1_AUTORESPONDER, 1); 335 rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg); 336 337 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR2); 338 rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00); 339 rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04); 340 rt2x00_set_field32(®, ARCSR2_LENGTH, 341 GET_DURATION(ACK_SIZE, 10)); 342 rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg); 343 344 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR3); 345 rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask); 346 rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04); 347 rt2x00_set_field32(®, ARCSR2_LENGTH, 348 GET_DURATION(ACK_SIZE, 20)); 349 rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg); 350 351 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR4); 352 rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask); 353 rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04); 354 rt2x00_set_field32(®, ARCSR2_LENGTH, 355 GET_DURATION(ACK_SIZE, 55)); 356 rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg); 357 358 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR5); 359 rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask); 360 rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84); 361 rt2x00_set_field32(®, ARCSR2_LENGTH, 362 GET_DURATION(ACK_SIZE, 110)); 363 rt2x00mmio_register_write(rt2x00dev, ARCSR5, reg); 364 } 365 366 if (changed & BSS_CHANGED_BASIC_RATES) 367 rt2x00mmio_register_write(rt2x00dev, ARCSR1, erp->basic_rates); 368 369 if (changed & BSS_CHANGED_ERP_SLOT) { 370 reg = rt2x00mmio_register_read(rt2x00dev, CSR11); 371 rt2x00_set_field32(®, CSR11_SLOT_TIME, erp->slot_time); 372 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); 373 374 reg = rt2x00mmio_register_read(rt2x00dev, CSR18); 375 rt2x00_set_field32(®, CSR18_SIFS, erp->sifs); 376 rt2x00_set_field32(®, CSR18_PIFS, erp->pifs); 377 rt2x00mmio_register_write(rt2x00dev, CSR18, reg); 378 379 reg = rt2x00mmio_register_read(rt2x00dev, CSR19); 380 rt2x00_set_field32(®, CSR19_DIFS, erp->difs); 381 rt2x00_set_field32(®, CSR19_EIFS, erp->eifs); 382 rt2x00mmio_register_write(rt2x00dev, CSR19, reg); 383 } 384 385 if (changed & BSS_CHANGED_BEACON_INT) { 386 reg = rt2x00mmio_register_read(rt2x00dev, CSR12); 387 rt2x00_set_field32(®, CSR12_BEACON_INTERVAL, 388 erp->beacon_int * 16); 389 rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION, 390 erp->beacon_int * 16); 391 rt2x00mmio_register_write(rt2x00dev, CSR12, reg); 392 } 393 394 } 395 396 static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev, 397 struct antenna_setup *ant) 398 { 399 u32 reg; 400 u8 r14; 401 u8 r2; 402 403 /* 404 * We should never come here because rt2x00lib is supposed 405 * to catch this and send us the correct antenna explicitely. 406 */ 407 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY || 408 ant->tx == ANTENNA_SW_DIVERSITY); 409 410 reg = rt2x00mmio_register_read(rt2x00dev, BBPCSR1); 411 r14 = rt2500pci_bbp_read(rt2x00dev, 14); 412 r2 = rt2500pci_bbp_read(rt2x00dev, 2); 413 414 /* 415 * Configure the TX antenna. 416 */ 417 switch (ant->tx) { 418 case ANTENNA_A: 419 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0); 420 rt2x00_set_field32(®, BBPCSR1_CCK, 0); 421 rt2x00_set_field32(®, BBPCSR1_OFDM, 0); 422 break; 423 case ANTENNA_B: 424 default: 425 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2); 426 rt2x00_set_field32(®, BBPCSR1_CCK, 2); 427 rt2x00_set_field32(®, BBPCSR1_OFDM, 2); 428 break; 429 } 430 431 /* 432 * Configure the RX antenna. 433 */ 434 switch (ant->rx) { 435 case ANTENNA_A: 436 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0); 437 break; 438 case ANTENNA_B: 439 default: 440 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2); 441 break; 442 } 443 444 /* 445 * RT2525E and RT5222 need to flip TX I/Q 446 */ 447 if (rt2x00_rf(rt2x00dev, RF2525E) || rt2x00_rf(rt2x00dev, RF5222)) { 448 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1); 449 rt2x00_set_field32(®, BBPCSR1_CCK_FLIP, 1); 450 rt2x00_set_field32(®, BBPCSR1_OFDM_FLIP, 1); 451 452 /* 453 * RT2525E does not need RX I/Q Flip. 454 */ 455 if (rt2x00_rf(rt2x00dev, RF2525E)) 456 rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0); 457 } else { 458 rt2x00_set_field32(®, BBPCSR1_CCK_FLIP, 0); 459 rt2x00_set_field32(®, BBPCSR1_OFDM_FLIP, 0); 460 } 461 462 rt2x00mmio_register_write(rt2x00dev, BBPCSR1, reg); 463 rt2500pci_bbp_write(rt2x00dev, 14, r14); 464 rt2500pci_bbp_write(rt2x00dev, 2, r2); 465 } 466 467 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev, 468 struct rf_channel *rf, const int txpower) 469 { 470 u8 r70; 471 472 /* 473 * Set TXpower. 474 */ 475 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower)); 476 477 /* 478 * Switch on tuning bits. 479 * For RT2523 devices we do not need to update the R1 register. 480 */ 481 if (!rt2x00_rf(rt2x00dev, RF2523)) 482 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1); 483 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1); 484 485 /* 486 * For RT2525 we should first set the channel to half band higher. 487 */ 488 if (rt2x00_rf(rt2x00dev, RF2525)) { 489 static const u32 vals[] = { 490 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a, 491 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a, 492 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a, 493 0x00080d2e, 0x00080d3a 494 }; 495 496 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1); 497 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]); 498 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3); 499 if (rf->rf4) 500 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4); 501 } 502 503 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1); 504 rt2500pci_rf_write(rt2x00dev, 2, rf->rf2); 505 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3); 506 if (rf->rf4) 507 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4); 508 509 /* 510 * Channel 14 requires the Japan filter bit to be set. 511 */ 512 r70 = 0x46; 513 rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14); 514 rt2500pci_bbp_write(rt2x00dev, 70, r70); 515 516 msleep(1); 517 518 /* 519 * Switch off tuning bits. 520 * For RT2523 devices we do not need to update the R1 register. 521 */ 522 if (!rt2x00_rf(rt2x00dev, RF2523)) { 523 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0); 524 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1); 525 } 526 527 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0); 528 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3); 529 530 /* 531 * Clear false CRC during channel switch. 532 */ 533 rf->rf1 = rt2x00mmio_register_read(rt2x00dev, CNT0); 534 } 535 536 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev, 537 const int txpower) 538 { 539 u32 rf3; 540 541 rf3 = rt2x00_rf_read(rt2x00dev, 3); 542 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower)); 543 rt2500pci_rf_write(rt2x00dev, 3, rf3); 544 } 545 546 static void rt2500pci_config_retry_limit(struct rt2x00_dev *rt2x00dev, 547 struct rt2x00lib_conf *libconf) 548 { 549 u32 reg; 550 551 reg = rt2x00mmio_register_read(rt2x00dev, CSR11); 552 rt2x00_set_field32(®, CSR11_LONG_RETRY, 553 libconf->conf->long_frame_max_tx_count); 554 rt2x00_set_field32(®, CSR11_SHORT_RETRY, 555 libconf->conf->short_frame_max_tx_count); 556 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); 557 } 558 559 static void rt2500pci_config_ps(struct rt2x00_dev *rt2x00dev, 560 struct rt2x00lib_conf *libconf) 561 { 562 enum dev_state state = 563 (libconf->conf->flags & IEEE80211_CONF_PS) ? 564 STATE_SLEEP : STATE_AWAKE; 565 u32 reg; 566 567 if (state == STATE_SLEEP) { 568 reg = rt2x00mmio_register_read(rt2x00dev, CSR20); 569 rt2x00_set_field32(®, CSR20_DELAY_AFTER_TBCN, 570 (rt2x00dev->beacon_int - 20) * 16); 571 rt2x00_set_field32(®, CSR20_TBCN_BEFORE_WAKEUP, 572 libconf->conf->listen_interval - 1); 573 574 /* We must first disable autowake before it can be enabled */ 575 rt2x00_set_field32(®, CSR20_AUTOWAKE, 0); 576 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); 577 578 rt2x00_set_field32(®, CSR20_AUTOWAKE, 1); 579 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); 580 } else { 581 reg = rt2x00mmio_register_read(rt2x00dev, CSR20); 582 rt2x00_set_field32(®, CSR20_AUTOWAKE, 0); 583 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); 584 } 585 586 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 587 } 588 589 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev, 590 struct rt2x00lib_conf *libconf, 591 const unsigned int flags) 592 { 593 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) 594 rt2500pci_config_channel(rt2x00dev, &libconf->rf, 595 libconf->conf->power_level); 596 if ((flags & IEEE80211_CONF_CHANGE_POWER) && 597 !(flags & IEEE80211_CONF_CHANGE_CHANNEL)) 598 rt2500pci_config_txpower(rt2x00dev, 599 libconf->conf->power_level); 600 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) 601 rt2500pci_config_retry_limit(rt2x00dev, libconf); 602 if (flags & IEEE80211_CONF_CHANGE_PS) 603 rt2500pci_config_ps(rt2x00dev, libconf); 604 } 605 606 /* 607 * Link tuning 608 */ 609 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev, 610 struct link_qual *qual) 611 { 612 u32 reg; 613 614 /* 615 * Update FCS error count from register. 616 */ 617 reg = rt2x00mmio_register_read(rt2x00dev, CNT0); 618 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR); 619 620 /* 621 * Update False CCA count from register. 622 */ 623 reg = rt2x00mmio_register_read(rt2x00dev, CNT3); 624 qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA); 625 } 626 627 static inline void rt2500pci_set_vgc(struct rt2x00_dev *rt2x00dev, 628 struct link_qual *qual, u8 vgc_level) 629 { 630 if (qual->vgc_level_reg != vgc_level) { 631 rt2500pci_bbp_write(rt2x00dev, 17, vgc_level); 632 qual->vgc_level = vgc_level; 633 qual->vgc_level_reg = vgc_level; 634 } 635 } 636 637 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev, 638 struct link_qual *qual) 639 { 640 rt2500pci_set_vgc(rt2x00dev, qual, 0x48); 641 } 642 643 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev, 644 struct link_qual *qual, const u32 count) 645 { 646 /* 647 * To prevent collisions with MAC ASIC on chipsets 648 * up to version C the link tuning should halt after 20 649 * seconds while being associated. 650 */ 651 if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D && 652 rt2x00dev->intf_associated && count > 20) 653 return; 654 655 /* 656 * Chipset versions C and lower should directly continue 657 * to the dynamic CCA tuning. Chipset version D and higher 658 * should go straight to dynamic CCA tuning when they 659 * are not associated. 660 */ 661 if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D || 662 !rt2x00dev->intf_associated) 663 goto dynamic_cca_tune; 664 665 /* 666 * A too low RSSI will cause too much false CCA which will 667 * then corrupt the R17 tuning. To remidy this the tuning should 668 * be stopped (While making sure the R17 value will not exceed limits) 669 */ 670 if (qual->rssi < -80 && count > 20) { 671 if (qual->vgc_level_reg >= 0x41) 672 rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level); 673 return; 674 } 675 676 /* 677 * Special big-R17 for short distance 678 */ 679 if (qual->rssi >= -58) { 680 rt2500pci_set_vgc(rt2x00dev, qual, 0x50); 681 return; 682 } 683 684 /* 685 * Special mid-R17 for middle distance 686 */ 687 if (qual->rssi >= -74) { 688 rt2500pci_set_vgc(rt2x00dev, qual, 0x41); 689 return; 690 } 691 692 /* 693 * Leave short or middle distance condition, restore r17 694 * to the dynamic tuning range. 695 */ 696 if (qual->vgc_level_reg >= 0x41) { 697 rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level); 698 return; 699 } 700 701 dynamic_cca_tune: 702 703 /* 704 * R17 is inside the dynamic tuning range, 705 * start tuning the link based on the false cca counter. 706 */ 707 if (qual->false_cca > 512 && qual->vgc_level_reg < 0x40) 708 rt2500pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level_reg); 709 else if (qual->false_cca < 100 && qual->vgc_level_reg > 0x32) 710 rt2500pci_set_vgc(rt2x00dev, qual, --qual->vgc_level_reg); 711 } 712 713 /* 714 * Queue handlers. 715 */ 716 static void rt2500pci_start_queue(struct data_queue *queue) 717 { 718 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; 719 u32 reg; 720 721 switch (queue->qid) { 722 case QID_RX: 723 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0); 724 rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 0); 725 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); 726 break; 727 case QID_BEACON: 728 reg = rt2x00mmio_register_read(rt2x00dev, CSR14); 729 rt2x00_set_field32(®, CSR14_TSF_COUNT, 1); 730 rt2x00_set_field32(®, CSR14_TBCN, 1); 731 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); 732 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); 733 break; 734 default: 735 break; 736 } 737 } 738 739 static void rt2500pci_kick_queue(struct data_queue *queue) 740 { 741 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; 742 u32 reg; 743 744 switch (queue->qid) { 745 case QID_AC_VO: 746 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0); 747 rt2x00_set_field32(®, TXCSR0_KICK_PRIO, 1); 748 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); 749 break; 750 case QID_AC_VI: 751 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0); 752 rt2x00_set_field32(®, TXCSR0_KICK_TX, 1); 753 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); 754 break; 755 case QID_ATIM: 756 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0); 757 rt2x00_set_field32(®, TXCSR0_KICK_ATIM, 1); 758 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); 759 break; 760 default: 761 break; 762 } 763 } 764 765 static void rt2500pci_stop_queue(struct data_queue *queue) 766 { 767 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; 768 u32 reg; 769 770 switch (queue->qid) { 771 case QID_AC_VO: 772 case QID_AC_VI: 773 case QID_ATIM: 774 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0); 775 rt2x00_set_field32(®, TXCSR0_ABORT, 1); 776 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); 777 break; 778 case QID_RX: 779 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0); 780 rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 1); 781 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); 782 break; 783 case QID_BEACON: 784 reg = rt2x00mmio_register_read(rt2x00dev, CSR14); 785 rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); 786 rt2x00_set_field32(®, CSR14_TBCN, 0); 787 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); 788 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); 789 790 /* 791 * Wait for possibly running tbtt tasklets. 792 */ 793 tasklet_kill(&rt2x00dev->tbtt_tasklet); 794 break; 795 default: 796 break; 797 } 798 } 799 800 /* 801 * Initialization functions. 802 */ 803 static bool rt2500pci_get_entry_state(struct queue_entry *entry) 804 { 805 struct queue_entry_priv_mmio *entry_priv = entry->priv_data; 806 u32 word; 807 808 if (entry->queue->qid == QID_RX) { 809 word = rt2x00_desc_read(entry_priv->desc, 0); 810 811 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC); 812 } else { 813 word = rt2x00_desc_read(entry_priv->desc, 0); 814 815 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || 816 rt2x00_get_field32(word, TXD_W0_VALID)); 817 } 818 } 819 820 static void rt2500pci_clear_entry(struct queue_entry *entry) 821 { 822 struct queue_entry_priv_mmio *entry_priv = entry->priv_data; 823 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 824 u32 word; 825 826 if (entry->queue->qid == QID_RX) { 827 word = rt2x00_desc_read(entry_priv->desc, 1); 828 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma); 829 rt2x00_desc_write(entry_priv->desc, 1, word); 830 831 word = rt2x00_desc_read(entry_priv->desc, 0); 832 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); 833 rt2x00_desc_write(entry_priv->desc, 0, word); 834 } else { 835 word = rt2x00_desc_read(entry_priv->desc, 0); 836 rt2x00_set_field32(&word, TXD_W0_VALID, 0); 837 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); 838 rt2x00_desc_write(entry_priv->desc, 0, word); 839 } 840 } 841 842 static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev) 843 { 844 struct queue_entry_priv_mmio *entry_priv; 845 u32 reg; 846 847 /* 848 * Initialize registers. 849 */ 850 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR2); 851 rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size); 852 rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit); 853 rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit); 854 rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); 855 rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg); 856 857 entry_priv = rt2x00dev->tx[1].entries[0].priv_data; 858 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR3); 859 rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER, 860 entry_priv->desc_dma); 861 rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg); 862 863 entry_priv = rt2x00dev->tx[0].entries[0].priv_data; 864 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR5); 865 rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER, 866 entry_priv->desc_dma); 867 rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg); 868 869 entry_priv = rt2x00dev->atim->entries[0].priv_data; 870 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR4); 871 rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER, 872 entry_priv->desc_dma); 873 rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg); 874 875 entry_priv = rt2x00dev->bcn->entries[0].priv_data; 876 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR6); 877 rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER, 878 entry_priv->desc_dma); 879 rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg); 880 881 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR1); 882 rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size); 883 rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit); 884 rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg); 885 886 entry_priv = rt2x00dev->rx->entries[0].priv_data; 887 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR2); 888 rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER, 889 entry_priv->desc_dma); 890 rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg); 891 892 return 0; 893 } 894 895 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev) 896 { 897 u32 reg; 898 899 rt2x00mmio_register_write(rt2x00dev, PSCSR0, 0x00020002); 900 rt2x00mmio_register_write(rt2x00dev, PSCSR1, 0x00000002); 901 rt2x00mmio_register_write(rt2x00dev, PSCSR2, 0x00020002); 902 rt2x00mmio_register_write(rt2x00dev, PSCSR3, 0x00000002); 903 904 reg = rt2x00mmio_register_read(rt2x00dev, TIMECSR); 905 rt2x00_set_field32(®, TIMECSR_US_COUNT, 33); 906 rt2x00_set_field32(®, TIMECSR_US_64_COUNT, 63); 907 rt2x00_set_field32(®, TIMECSR_BEACON_EXPECT, 0); 908 rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg); 909 910 reg = rt2x00mmio_register_read(rt2x00dev, CSR9); 911 rt2x00_set_field32(®, CSR9_MAX_FRAME_UNIT, 912 rt2x00dev->rx->data_size / 128); 913 rt2x00mmio_register_write(rt2x00dev, CSR9, reg); 914 915 /* 916 * Always use CWmin and CWmax set in descriptor. 917 */ 918 reg = rt2x00mmio_register_read(rt2x00dev, CSR11); 919 rt2x00_set_field32(®, CSR11_CW_SELECT, 0); 920 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); 921 922 reg = rt2x00mmio_register_read(rt2x00dev, CSR14); 923 rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); 924 rt2x00_set_field32(®, CSR14_TSF_SYNC, 0); 925 rt2x00_set_field32(®, CSR14_TBCN, 0); 926 rt2x00_set_field32(®, CSR14_TCFP, 0); 927 rt2x00_set_field32(®, CSR14_TATIMW, 0); 928 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); 929 rt2x00_set_field32(®, CSR14_CFP_COUNT_PRELOAD, 0); 930 rt2x00_set_field32(®, CSR14_TBCM_PRELOAD, 0); 931 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); 932 933 rt2x00mmio_register_write(rt2x00dev, CNT3, 0); 934 935 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR8); 936 rt2x00_set_field32(®, TXCSR8_BBP_ID0, 10); 937 rt2x00_set_field32(®, TXCSR8_BBP_ID0_VALID, 1); 938 rt2x00_set_field32(®, TXCSR8_BBP_ID1, 11); 939 rt2x00_set_field32(®, TXCSR8_BBP_ID1_VALID, 1); 940 rt2x00_set_field32(®, TXCSR8_BBP_ID2, 13); 941 rt2x00_set_field32(®, TXCSR8_BBP_ID2_VALID, 1); 942 rt2x00_set_field32(®, TXCSR8_BBP_ID3, 12); 943 rt2x00_set_field32(®, TXCSR8_BBP_ID3_VALID, 1); 944 rt2x00mmio_register_write(rt2x00dev, TXCSR8, reg); 945 946 reg = rt2x00mmio_register_read(rt2x00dev, ARTCSR0); 947 rt2x00_set_field32(®, ARTCSR0_ACK_CTS_1MBS, 112); 948 rt2x00_set_field32(®, ARTCSR0_ACK_CTS_2MBS, 56); 949 rt2x00_set_field32(®, ARTCSR0_ACK_CTS_5_5MBS, 20); 950 rt2x00_set_field32(®, ARTCSR0_ACK_CTS_11MBS, 10); 951 rt2x00mmio_register_write(rt2x00dev, ARTCSR0, reg); 952 953 reg = rt2x00mmio_register_read(rt2x00dev, ARTCSR1); 954 rt2x00_set_field32(®, ARTCSR1_ACK_CTS_6MBS, 45); 955 rt2x00_set_field32(®, ARTCSR1_ACK_CTS_9MBS, 37); 956 rt2x00_set_field32(®, ARTCSR1_ACK_CTS_12MBS, 33); 957 rt2x00_set_field32(®, ARTCSR1_ACK_CTS_18MBS, 29); 958 rt2x00mmio_register_write(rt2x00dev, ARTCSR1, reg); 959 960 reg = rt2x00mmio_register_read(rt2x00dev, ARTCSR2); 961 rt2x00_set_field32(®, ARTCSR2_ACK_CTS_24MBS, 29); 962 rt2x00_set_field32(®, ARTCSR2_ACK_CTS_36MBS, 25); 963 rt2x00_set_field32(®, ARTCSR2_ACK_CTS_48MBS, 25); 964 rt2x00_set_field32(®, ARTCSR2_ACK_CTS_54MBS, 25); 965 rt2x00mmio_register_write(rt2x00dev, ARTCSR2, reg); 966 967 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR3); 968 rt2x00_set_field32(®, RXCSR3_BBP_ID0, 47); /* CCK Signal */ 969 rt2x00_set_field32(®, RXCSR3_BBP_ID0_VALID, 1); 970 rt2x00_set_field32(®, RXCSR3_BBP_ID1, 51); /* Rssi */ 971 rt2x00_set_field32(®, RXCSR3_BBP_ID1_VALID, 1); 972 rt2x00_set_field32(®, RXCSR3_BBP_ID2, 42); /* OFDM Rate */ 973 rt2x00_set_field32(®, RXCSR3_BBP_ID2_VALID, 1); 974 rt2x00_set_field32(®, RXCSR3_BBP_ID3, 51); /* RSSI */ 975 rt2x00_set_field32(®, RXCSR3_BBP_ID3_VALID, 1); 976 rt2x00mmio_register_write(rt2x00dev, RXCSR3, reg); 977 978 reg = rt2x00mmio_register_read(rt2x00dev, PCICSR); 979 rt2x00_set_field32(®, PCICSR_BIG_ENDIAN, 0); 980 rt2x00_set_field32(®, PCICSR_RX_TRESHOLD, 0); 981 rt2x00_set_field32(®, PCICSR_TX_TRESHOLD, 3); 982 rt2x00_set_field32(®, PCICSR_BURST_LENTH, 1); 983 rt2x00_set_field32(®, PCICSR_ENABLE_CLK, 1); 984 rt2x00_set_field32(®, PCICSR_READ_MULTIPLE, 1); 985 rt2x00_set_field32(®, PCICSR_WRITE_INVALID, 1); 986 rt2x00mmio_register_write(rt2x00dev, PCICSR, reg); 987 988 rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100); 989 990 rt2x00mmio_register_write(rt2x00dev, GPIOCSR, 0x0000ff00); 991 rt2x00mmio_register_write(rt2x00dev, TESTCSR, 0x000000f0); 992 993 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE)) 994 return -EBUSY; 995 996 rt2x00mmio_register_write(rt2x00dev, MACCSR0, 0x00213223); 997 rt2x00mmio_register_write(rt2x00dev, MACCSR1, 0x00235518); 998 999 reg = rt2x00mmio_register_read(rt2x00dev, MACCSR2); 1000 rt2x00_set_field32(®, MACCSR2_DELAY, 64); 1001 rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg); 1002 1003 reg = rt2x00mmio_register_read(rt2x00dev, RALINKCSR); 1004 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA0, 17); 1005 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID0, 26); 1006 rt2x00_set_field32(®, RALINKCSR_AR_BBP_VALID0, 1); 1007 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA1, 0); 1008 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID1, 26); 1009 rt2x00_set_field32(®, RALINKCSR_AR_BBP_VALID1, 1); 1010 rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg); 1011 1012 rt2x00mmio_register_write(rt2x00dev, BBPCSR1, 0x82188200); 1013 1014 rt2x00mmio_register_write(rt2x00dev, TXACKCSR0, 0x00000020); 1015 1016 reg = rt2x00mmio_register_read(rt2x00dev, CSR1); 1017 rt2x00_set_field32(®, CSR1_SOFT_RESET, 1); 1018 rt2x00_set_field32(®, CSR1_BBP_RESET, 0); 1019 rt2x00_set_field32(®, CSR1_HOST_READY, 0); 1020 rt2x00mmio_register_write(rt2x00dev, CSR1, reg); 1021 1022 reg = rt2x00mmio_register_read(rt2x00dev, CSR1); 1023 rt2x00_set_field32(®, CSR1_SOFT_RESET, 0); 1024 rt2x00_set_field32(®, CSR1_HOST_READY, 1); 1025 rt2x00mmio_register_write(rt2x00dev, CSR1, reg); 1026 1027 /* 1028 * We must clear the FCS and FIFO error count. 1029 * These registers are cleared on read, 1030 * so we may pass a useless variable to store the value. 1031 */ 1032 reg = rt2x00mmio_register_read(rt2x00dev, CNT0); 1033 reg = rt2x00mmio_register_read(rt2x00dev, CNT4); 1034 1035 return 0; 1036 } 1037 1038 static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) 1039 { 1040 unsigned int i; 1041 u8 value; 1042 1043 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 1044 value = rt2500pci_bbp_read(rt2x00dev, 0); 1045 if ((value != 0xff) && (value != 0x00)) 1046 return 0; 1047 udelay(REGISTER_BUSY_DELAY); 1048 } 1049 1050 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n"); 1051 return -EACCES; 1052 } 1053 1054 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev) 1055 { 1056 unsigned int i; 1057 u16 eeprom; 1058 u8 reg_id; 1059 u8 value; 1060 1061 if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev))) 1062 return -EACCES; 1063 1064 rt2500pci_bbp_write(rt2x00dev, 3, 0x02); 1065 rt2500pci_bbp_write(rt2x00dev, 4, 0x19); 1066 rt2500pci_bbp_write(rt2x00dev, 14, 0x1c); 1067 rt2500pci_bbp_write(rt2x00dev, 15, 0x30); 1068 rt2500pci_bbp_write(rt2x00dev, 16, 0xac); 1069 rt2500pci_bbp_write(rt2x00dev, 18, 0x18); 1070 rt2500pci_bbp_write(rt2x00dev, 19, 0xff); 1071 rt2500pci_bbp_write(rt2x00dev, 20, 0x1e); 1072 rt2500pci_bbp_write(rt2x00dev, 21, 0x08); 1073 rt2500pci_bbp_write(rt2x00dev, 22, 0x08); 1074 rt2500pci_bbp_write(rt2x00dev, 23, 0x08); 1075 rt2500pci_bbp_write(rt2x00dev, 24, 0x70); 1076 rt2500pci_bbp_write(rt2x00dev, 25, 0x40); 1077 rt2500pci_bbp_write(rt2x00dev, 26, 0x08); 1078 rt2500pci_bbp_write(rt2x00dev, 27, 0x23); 1079 rt2500pci_bbp_write(rt2x00dev, 30, 0x10); 1080 rt2500pci_bbp_write(rt2x00dev, 31, 0x2b); 1081 rt2500pci_bbp_write(rt2x00dev, 32, 0xb9); 1082 rt2500pci_bbp_write(rt2x00dev, 34, 0x12); 1083 rt2500pci_bbp_write(rt2x00dev, 35, 0x50); 1084 rt2500pci_bbp_write(rt2x00dev, 39, 0xc4); 1085 rt2500pci_bbp_write(rt2x00dev, 40, 0x02); 1086 rt2500pci_bbp_write(rt2x00dev, 41, 0x60); 1087 rt2500pci_bbp_write(rt2x00dev, 53, 0x10); 1088 rt2500pci_bbp_write(rt2x00dev, 54, 0x18); 1089 rt2500pci_bbp_write(rt2x00dev, 56, 0x08); 1090 rt2500pci_bbp_write(rt2x00dev, 57, 0x10); 1091 rt2500pci_bbp_write(rt2x00dev, 58, 0x08); 1092 rt2500pci_bbp_write(rt2x00dev, 61, 0x6d); 1093 rt2500pci_bbp_write(rt2x00dev, 62, 0x10); 1094 1095 for (i = 0; i < EEPROM_BBP_SIZE; i++) { 1096 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i); 1097 1098 if (eeprom != 0xffff && eeprom != 0x0000) { 1099 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); 1100 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); 1101 rt2500pci_bbp_write(rt2x00dev, reg_id, value); 1102 } 1103 } 1104 1105 return 0; 1106 } 1107 1108 /* 1109 * Device state switch handlers. 1110 */ 1111 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev, 1112 enum dev_state state) 1113 { 1114 int mask = (state == STATE_RADIO_IRQ_OFF); 1115 u32 reg; 1116 unsigned long flags; 1117 1118 /* 1119 * When interrupts are being enabled, the interrupt registers 1120 * should clear the register to assure a clean state. 1121 */ 1122 if (state == STATE_RADIO_IRQ_ON) { 1123 reg = rt2x00mmio_register_read(rt2x00dev, CSR7); 1124 rt2x00mmio_register_write(rt2x00dev, CSR7, reg); 1125 } 1126 1127 /* 1128 * Only toggle the interrupts bits we are going to use. 1129 * Non-checked interrupt bits are disabled by default. 1130 */ 1131 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags); 1132 1133 reg = rt2x00mmio_register_read(rt2x00dev, CSR8); 1134 rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask); 1135 rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask); 1136 rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask); 1137 rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask); 1138 rt2x00_set_field32(®, CSR8_RXDONE, mask); 1139 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); 1140 1141 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags); 1142 1143 if (state == STATE_RADIO_IRQ_OFF) { 1144 /* 1145 * Ensure that all tasklets are finished. 1146 */ 1147 tasklet_kill(&rt2x00dev->txstatus_tasklet); 1148 tasklet_kill(&rt2x00dev->rxdone_tasklet); 1149 tasklet_kill(&rt2x00dev->tbtt_tasklet); 1150 } 1151 } 1152 1153 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev) 1154 { 1155 /* 1156 * Initialize all registers. 1157 */ 1158 if (unlikely(rt2500pci_init_queues(rt2x00dev) || 1159 rt2500pci_init_registers(rt2x00dev) || 1160 rt2500pci_init_bbp(rt2x00dev))) 1161 return -EIO; 1162 1163 return 0; 1164 } 1165 1166 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev) 1167 { 1168 /* 1169 * Disable power 1170 */ 1171 rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0); 1172 } 1173 1174 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev, 1175 enum dev_state state) 1176 { 1177 u32 reg, reg2; 1178 unsigned int i; 1179 char put_to_sleep; 1180 char bbp_state; 1181 char rf_state; 1182 1183 put_to_sleep = (state != STATE_AWAKE); 1184 1185 reg = rt2x00mmio_register_read(rt2x00dev, PWRCSR1); 1186 rt2x00_set_field32(®, PWRCSR1_SET_STATE, 1); 1187 rt2x00_set_field32(®, PWRCSR1_BBP_DESIRE_STATE, state); 1188 rt2x00_set_field32(®, PWRCSR1_RF_DESIRE_STATE, state); 1189 rt2x00_set_field32(®, PWRCSR1_PUT_TO_SLEEP, put_to_sleep); 1190 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg); 1191 1192 /* 1193 * Device is not guaranteed to be in the requested state yet. 1194 * We must wait until the register indicates that the 1195 * device has entered the correct state. 1196 */ 1197 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 1198 reg2 = rt2x00mmio_register_read(rt2x00dev, PWRCSR1); 1199 bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE); 1200 rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE); 1201 if (bbp_state == state && rf_state == state) 1202 return 0; 1203 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg); 1204 msleep(10); 1205 } 1206 1207 return -EBUSY; 1208 } 1209 1210 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev, 1211 enum dev_state state) 1212 { 1213 int retval = 0; 1214 1215 switch (state) { 1216 case STATE_RADIO_ON: 1217 retval = rt2500pci_enable_radio(rt2x00dev); 1218 break; 1219 case STATE_RADIO_OFF: 1220 rt2500pci_disable_radio(rt2x00dev); 1221 break; 1222 case STATE_RADIO_IRQ_ON: 1223 case STATE_RADIO_IRQ_OFF: 1224 rt2500pci_toggle_irq(rt2x00dev, state); 1225 break; 1226 case STATE_DEEP_SLEEP: 1227 case STATE_SLEEP: 1228 case STATE_STANDBY: 1229 case STATE_AWAKE: 1230 retval = rt2500pci_set_state(rt2x00dev, state); 1231 break; 1232 default: 1233 retval = -ENOTSUPP; 1234 break; 1235 } 1236 1237 if (unlikely(retval)) 1238 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n", 1239 state, retval); 1240 1241 return retval; 1242 } 1243 1244 /* 1245 * TX descriptor initialization 1246 */ 1247 static void rt2500pci_write_tx_desc(struct queue_entry *entry, 1248 struct txentry_desc *txdesc) 1249 { 1250 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 1251 struct queue_entry_priv_mmio *entry_priv = entry->priv_data; 1252 __le32 *txd = entry_priv->desc; 1253 u32 word; 1254 1255 /* 1256 * Start writing the descriptor words. 1257 */ 1258 word = rt2x00_desc_read(txd, 1); 1259 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma); 1260 rt2x00_desc_write(txd, 1, word); 1261 1262 word = rt2x00_desc_read(txd, 2); 1263 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER); 1264 rt2x00_set_field32(&word, TXD_W2_AIFS, entry->queue->aifs); 1265 rt2x00_set_field32(&word, TXD_W2_CWMIN, entry->queue->cw_min); 1266 rt2x00_set_field32(&word, TXD_W2_CWMAX, entry->queue->cw_max); 1267 rt2x00_desc_write(txd, 2, word); 1268 1269 word = rt2x00_desc_read(txd, 3); 1270 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal); 1271 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service); 1272 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, 1273 txdesc->u.plcp.length_low); 1274 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, 1275 txdesc->u.plcp.length_high); 1276 rt2x00_desc_write(txd, 3, word); 1277 1278 word = rt2x00_desc_read(txd, 10); 1279 rt2x00_set_field32(&word, TXD_W10_RTS, 1280 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)); 1281 rt2x00_desc_write(txd, 10, word); 1282 1283 /* 1284 * Writing TXD word 0 must the last to prevent a race condition with 1285 * the device, whereby the device may take hold of the TXD before we 1286 * finished updating it. 1287 */ 1288 word = rt2x00_desc_read(txd, 0); 1289 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1); 1290 rt2x00_set_field32(&word, TXD_W0_VALID, 1); 1291 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, 1292 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); 1293 rt2x00_set_field32(&word, TXD_W0_ACK, 1294 test_bit(ENTRY_TXD_ACK, &txdesc->flags)); 1295 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP, 1296 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); 1297 rt2x00_set_field32(&word, TXD_W0_OFDM, 1298 (txdesc->rate_mode == RATE_MODE_OFDM)); 1299 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1); 1300 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs); 1301 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, 1302 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); 1303 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length); 1304 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE); 1305 rt2x00_desc_write(txd, 0, word); 1306 1307 /* 1308 * Register descriptor details in skb frame descriptor. 1309 */ 1310 skbdesc->desc = txd; 1311 skbdesc->desc_len = TXD_DESC_SIZE; 1312 } 1313 1314 /* 1315 * TX data initialization 1316 */ 1317 static void rt2500pci_write_beacon(struct queue_entry *entry, 1318 struct txentry_desc *txdesc) 1319 { 1320 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1321 u32 reg; 1322 1323 /* 1324 * Disable beaconing while we are reloading the beacon data, 1325 * otherwise we might be sending out invalid data. 1326 */ 1327 reg = rt2x00mmio_register_read(rt2x00dev, CSR14); 1328 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); 1329 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); 1330 1331 if (rt2x00queue_map_txskb(entry)) { 1332 rt2x00_err(rt2x00dev, "Fail to map beacon, aborting\n"); 1333 goto out; 1334 } 1335 1336 /* 1337 * Write the TX descriptor for the beacon. 1338 */ 1339 rt2500pci_write_tx_desc(entry, txdesc); 1340 1341 /* 1342 * Dump beacon to userspace through debugfs. 1343 */ 1344 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry); 1345 out: 1346 /* 1347 * Enable beaconing again. 1348 */ 1349 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); 1350 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); 1351 } 1352 1353 /* 1354 * RX control handlers 1355 */ 1356 static void rt2500pci_fill_rxdone(struct queue_entry *entry, 1357 struct rxdone_entry_desc *rxdesc) 1358 { 1359 struct queue_entry_priv_mmio *entry_priv = entry->priv_data; 1360 u32 word0; 1361 u32 word2; 1362 1363 word0 = rt2x00_desc_read(entry_priv->desc, 0); 1364 word2 = rt2x00_desc_read(entry_priv->desc, 2); 1365 1366 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) 1367 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; 1368 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR)) 1369 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC; 1370 1371 /* 1372 * Obtain the status about this packet. 1373 * When frame was received with an OFDM bitrate, 1374 * the signal is the PLCP value. If it was received with 1375 * a CCK bitrate the signal is the rate in 100kbit/s. 1376 */ 1377 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL); 1378 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) - 1379 entry->queue->rt2x00dev->rssi_offset; 1380 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); 1381 1382 if (rt2x00_get_field32(word0, RXD_W0_OFDM)) 1383 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP; 1384 else 1385 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE; 1386 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS)) 1387 rxdesc->dev_flags |= RXDONE_MY_BSS; 1388 } 1389 1390 /* 1391 * Interrupt functions. 1392 */ 1393 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, 1394 const enum data_queue_qid queue_idx) 1395 { 1396 struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx); 1397 struct queue_entry_priv_mmio *entry_priv; 1398 struct queue_entry *entry; 1399 struct txdone_entry_desc txdesc; 1400 u32 word; 1401 1402 while (!rt2x00queue_empty(queue)) { 1403 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1404 entry_priv = entry->priv_data; 1405 word = rt2x00_desc_read(entry_priv->desc, 0); 1406 1407 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || 1408 !rt2x00_get_field32(word, TXD_W0_VALID)) 1409 break; 1410 1411 /* 1412 * Obtain the status about this packet. 1413 */ 1414 txdesc.flags = 0; 1415 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) { 1416 case 0: /* Success */ 1417 case 1: /* Success with retry */ 1418 __set_bit(TXDONE_SUCCESS, &txdesc.flags); 1419 break; 1420 case 2: /* Failure, excessive retries */ 1421 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags); 1422 fallthrough; /* this is a failed frame! */ 1423 default: /* Failure */ 1424 __set_bit(TXDONE_FAILURE, &txdesc.flags); 1425 } 1426 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT); 1427 1428 rt2x00lib_txdone(entry, &txdesc); 1429 } 1430 } 1431 1432 static inline void rt2500pci_enable_interrupt(struct rt2x00_dev *rt2x00dev, 1433 struct rt2x00_field32 irq_field) 1434 { 1435 u32 reg; 1436 1437 /* 1438 * Enable a single interrupt. The interrupt mask register 1439 * access needs locking. 1440 */ 1441 spin_lock_irq(&rt2x00dev->irqmask_lock); 1442 1443 reg = rt2x00mmio_register_read(rt2x00dev, CSR8); 1444 rt2x00_set_field32(®, irq_field, 0); 1445 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); 1446 1447 spin_unlock_irq(&rt2x00dev->irqmask_lock); 1448 } 1449 1450 static void rt2500pci_txstatus_tasklet(struct tasklet_struct *t) 1451 { 1452 struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t, 1453 txstatus_tasklet); 1454 u32 reg; 1455 1456 /* 1457 * Handle all tx queues. 1458 */ 1459 rt2500pci_txdone(rt2x00dev, QID_ATIM); 1460 rt2500pci_txdone(rt2x00dev, QID_AC_VO); 1461 rt2500pci_txdone(rt2x00dev, QID_AC_VI); 1462 1463 /* 1464 * Enable all TXDONE interrupts again. 1465 */ 1466 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) { 1467 spin_lock_irq(&rt2x00dev->irqmask_lock); 1468 1469 reg = rt2x00mmio_register_read(rt2x00dev, CSR8); 1470 rt2x00_set_field32(®, CSR8_TXDONE_TXRING, 0); 1471 rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, 0); 1472 rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, 0); 1473 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); 1474 1475 spin_unlock_irq(&rt2x00dev->irqmask_lock); 1476 } 1477 } 1478 1479 static void rt2500pci_tbtt_tasklet(struct tasklet_struct *t) 1480 { 1481 struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t, tbtt_tasklet); 1482 rt2x00lib_beacondone(rt2x00dev); 1483 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) 1484 rt2500pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE); 1485 } 1486 1487 static void rt2500pci_rxdone_tasklet(struct tasklet_struct *t) 1488 { 1489 struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t, 1490 rxdone_tasklet); 1491 if (rt2x00mmio_rxdone(rt2x00dev)) 1492 tasklet_schedule(&rt2x00dev->rxdone_tasklet); 1493 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) 1494 rt2500pci_enable_interrupt(rt2x00dev, CSR8_RXDONE); 1495 } 1496 1497 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance) 1498 { 1499 struct rt2x00_dev *rt2x00dev = dev_instance; 1500 u32 reg, mask; 1501 1502 /* 1503 * Get the interrupt sources & saved to local variable. 1504 * Write register value back to clear pending interrupts. 1505 */ 1506 reg = rt2x00mmio_register_read(rt2x00dev, CSR7); 1507 rt2x00mmio_register_write(rt2x00dev, CSR7, reg); 1508 1509 if (!reg) 1510 return IRQ_NONE; 1511 1512 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) 1513 return IRQ_HANDLED; 1514 1515 mask = reg; 1516 1517 /* 1518 * Schedule tasklets for interrupt handling. 1519 */ 1520 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE)) 1521 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet); 1522 1523 if (rt2x00_get_field32(reg, CSR7_RXDONE)) 1524 tasklet_schedule(&rt2x00dev->rxdone_tasklet); 1525 1526 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) || 1527 rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) || 1528 rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) { 1529 tasklet_schedule(&rt2x00dev->txstatus_tasklet); 1530 /* 1531 * Mask out all txdone interrupts. 1532 */ 1533 rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1); 1534 rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1); 1535 rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1); 1536 } 1537 1538 /* 1539 * Disable all interrupts for which a tasklet was scheduled right now, 1540 * the tasklet will reenable the appropriate interrupts. 1541 */ 1542 spin_lock(&rt2x00dev->irqmask_lock); 1543 1544 reg = rt2x00mmio_register_read(rt2x00dev, CSR8); 1545 reg |= mask; 1546 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); 1547 1548 spin_unlock(&rt2x00dev->irqmask_lock); 1549 1550 return IRQ_HANDLED; 1551 } 1552 1553 /* 1554 * Device probe functions. 1555 */ 1556 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev) 1557 { 1558 struct eeprom_93cx6 eeprom; 1559 u32 reg; 1560 u16 word; 1561 u8 *mac; 1562 1563 reg = rt2x00mmio_register_read(rt2x00dev, CSR21); 1564 1565 eeprom.data = rt2x00dev; 1566 eeprom.register_read = rt2500pci_eepromregister_read; 1567 eeprom.register_write = rt2500pci_eepromregister_write; 1568 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ? 1569 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66; 1570 eeprom.reg_data_in = 0; 1571 eeprom.reg_data_out = 0; 1572 eeprom.reg_data_clock = 0; 1573 eeprom.reg_chip_select = 0; 1574 1575 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom, 1576 EEPROM_SIZE / sizeof(u16)); 1577 1578 /* 1579 * Start validation of the data that has been read. 1580 */ 1581 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); 1582 rt2x00lib_set_mac_address(rt2x00dev, mac); 1583 1584 word = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA); 1585 if (word == 0xffff) { 1586 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2); 1587 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, 1588 ANTENNA_SW_DIVERSITY); 1589 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, 1590 ANTENNA_SW_DIVERSITY); 1591 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE, 1592 LED_MODE_DEFAULT); 1593 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0); 1594 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0); 1595 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522); 1596 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word); 1597 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word); 1598 } 1599 1600 word = rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC); 1601 if (word == 0xffff) { 1602 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0); 1603 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0); 1604 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0); 1605 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word); 1606 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word); 1607 } 1608 1609 word = rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET); 1610 if (word == 0xffff) { 1611 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI, 1612 DEFAULT_RSSI_OFFSET); 1613 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word); 1614 rt2x00_eeprom_dbg(rt2x00dev, "Calibrate offset: 0x%04x\n", 1615 word); 1616 } 1617 1618 return 0; 1619 } 1620 1621 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev) 1622 { 1623 u32 reg; 1624 u16 value; 1625 u16 eeprom; 1626 1627 /* 1628 * Read EEPROM word for configuration. 1629 */ 1630 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA); 1631 1632 /* 1633 * Identify RF chipset. 1634 */ 1635 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); 1636 reg = rt2x00mmio_register_read(rt2x00dev, CSR0); 1637 rt2x00_set_chip(rt2x00dev, RT2560, value, 1638 rt2x00_get_field32(reg, CSR0_REVISION)); 1639 1640 if (!rt2x00_rf(rt2x00dev, RF2522) && 1641 !rt2x00_rf(rt2x00dev, RF2523) && 1642 !rt2x00_rf(rt2x00dev, RF2524) && 1643 !rt2x00_rf(rt2x00dev, RF2525) && 1644 !rt2x00_rf(rt2x00dev, RF2525E) && 1645 !rt2x00_rf(rt2x00dev, RF5222)) { 1646 rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n"); 1647 return -ENODEV; 1648 } 1649 1650 /* 1651 * Identify default antenna configuration. 1652 */ 1653 rt2x00dev->default_ant.tx = 1654 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT); 1655 rt2x00dev->default_ant.rx = 1656 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT); 1657 1658 /* 1659 * Store led mode, for correct led behaviour. 1660 */ 1661 #ifdef CONFIG_RT2X00_LIB_LEDS 1662 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE); 1663 1664 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); 1665 if (value == LED_MODE_TXRX_ACTIVITY || 1666 value == LED_MODE_DEFAULT || 1667 value == LED_MODE_ASUS) 1668 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual, 1669 LED_TYPE_ACTIVITY); 1670 #endif /* CONFIG_RT2X00_LIB_LEDS */ 1671 1672 /* 1673 * Detect if this device has an hardware controlled radio. 1674 */ 1675 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO)) { 1676 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags); 1677 /* 1678 * On this device RFKILL initialized during probe does not work. 1679 */ 1680 __set_bit(REQUIRE_DELAYED_RFKILL, &rt2x00dev->cap_flags); 1681 } 1682 1683 /* 1684 * Check if the BBP tuning should be enabled. 1685 */ 1686 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC); 1687 if (!rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE)) 1688 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags); 1689 1690 /* 1691 * Read the RSSI <-> dBm offset information. 1692 */ 1693 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET); 1694 rt2x00dev->rssi_offset = 1695 rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI); 1696 1697 return 0; 1698 } 1699 1700 /* 1701 * RF value list for RF2522 1702 * Supports: 2.4 GHz 1703 */ 1704 static const struct rf_channel rf_vals_bg_2522[] = { 1705 { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 }, 1706 { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 }, 1707 { 3, 0x00002050, 0x000c2002, 0x00000101, 0 }, 1708 { 4, 0x00002050, 0x000c2016, 0x00000101, 0 }, 1709 { 5, 0x00002050, 0x000c202a, 0x00000101, 0 }, 1710 { 6, 0x00002050, 0x000c203e, 0x00000101, 0 }, 1711 { 7, 0x00002050, 0x000c2052, 0x00000101, 0 }, 1712 { 8, 0x00002050, 0x000c2066, 0x00000101, 0 }, 1713 { 9, 0x00002050, 0x000c207a, 0x00000101, 0 }, 1714 { 10, 0x00002050, 0x000c208e, 0x00000101, 0 }, 1715 { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 }, 1716 { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 }, 1717 { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 }, 1718 { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 }, 1719 }; 1720 1721 /* 1722 * RF value list for RF2523 1723 * Supports: 2.4 GHz 1724 */ 1725 static const struct rf_channel rf_vals_bg_2523[] = { 1726 { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b }, 1727 { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b }, 1728 { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b }, 1729 { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b }, 1730 { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b }, 1731 { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b }, 1732 { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b }, 1733 { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b }, 1734 { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b }, 1735 { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b }, 1736 { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b }, 1737 { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b }, 1738 { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b }, 1739 { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 }, 1740 }; 1741 1742 /* 1743 * RF value list for RF2524 1744 * Supports: 2.4 GHz 1745 */ 1746 static const struct rf_channel rf_vals_bg_2524[] = { 1747 { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b }, 1748 { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b }, 1749 { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b }, 1750 { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b }, 1751 { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b }, 1752 { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b }, 1753 { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b }, 1754 { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b }, 1755 { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b }, 1756 { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b }, 1757 { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b }, 1758 { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b }, 1759 { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b }, 1760 { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 }, 1761 }; 1762 1763 /* 1764 * RF value list for RF2525 1765 * Supports: 2.4 GHz 1766 */ 1767 static const struct rf_channel rf_vals_bg_2525[] = { 1768 { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b }, 1769 { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b }, 1770 { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b }, 1771 { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b }, 1772 { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b }, 1773 { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b }, 1774 { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b }, 1775 { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b }, 1776 { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b }, 1777 { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b }, 1778 { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b }, 1779 { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b }, 1780 { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b }, 1781 { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 }, 1782 }; 1783 1784 /* 1785 * RF value list for RF2525e 1786 * Supports: 2.4 GHz 1787 */ 1788 static const struct rf_channel rf_vals_bg_2525e[] = { 1789 { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b }, 1790 { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b }, 1791 { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b }, 1792 { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b }, 1793 { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b }, 1794 { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b }, 1795 { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b }, 1796 { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b }, 1797 { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b }, 1798 { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b }, 1799 { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b }, 1800 { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b }, 1801 { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b }, 1802 { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b }, 1803 }; 1804 1805 /* 1806 * RF value list for RF5222 1807 * Supports: 2.4 GHz & 5.2 GHz 1808 */ 1809 static const struct rf_channel rf_vals_5222[] = { 1810 { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b }, 1811 { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b }, 1812 { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b }, 1813 { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b }, 1814 { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b }, 1815 { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b }, 1816 { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b }, 1817 { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b }, 1818 { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b }, 1819 { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b }, 1820 { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b }, 1821 { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b }, 1822 { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b }, 1823 { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b }, 1824 1825 /* 802.11 UNI / HyperLan 2 */ 1826 { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f }, 1827 { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f }, 1828 { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f }, 1829 { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f }, 1830 { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f }, 1831 { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f }, 1832 { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f }, 1833 { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f }, 1834 1835 /* 802.11 HyperLan 2 */ 1836 { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f }, 1837 { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f }, 1838 { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f }, 1839 { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f }, 1840 { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f }, 1841 { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f }, 1842 { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f }, 1843 { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f }, 1844 { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f }, 1845 { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f }, 1846 1847 /* 802.11 UNII */ 1848 { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f }, 1849 { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 }, 1850 { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 }, 1851 { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 }, 1852 { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 }, 1853 }; 1854 1855 static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev) 1856 { 1857 struct hw_mode_spec *spec = &rt2x00dev->spec; 1858 struct channel_info *info; 1859 char *tx_power; 1860 unsigned int i; 1861 1862 /* 1863 * Initialize all hw fields. 1864 */ 1865 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK); 1866 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS); 1867 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING); 1868 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM); 1869 1870 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); 1871 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, 1872 rt2x00_eeprom_addr(rt2x00dev, 1873 EEPROM_MAC_ADDR_0)); 1874 1875 /* 1876 * Disable powersaving as default. 1877 */ 1878 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 1879 1880 /* 1881 * Initialize hw_mode information. 1882 */ 1883 spec->supported_bands = SUPPORT_BAND_2GHZ; 1884 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; 1885 1886 if (rt2x00_rf(rt2x00dev, RF2522)) { 1887 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522); 1888 spec->channels = rf_vals_bg_2522; 1889 } else if (rt2x00_rf(rt2x00dev, RF2523)) { 1890 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523); 1891 spec->channels = rf_vals_bg_2523; 1892 } else if (rt2x00_rf(rt2x00dev, RF2524)) { 1893 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524); 1894 spec->channels = rf_vals_bg_2524; 1895 } else if (rt2x00_rf(rt2x00dev, RF2525)) { 1896 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525); 1897 spec->channels = rf_vals_bg_2525; 1898 } else if (rt2x00_rf(rt2x00dev, RF2525E)) { 1899 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e); 1900 spec->channels = rf_vals_bg_2525e; 1901 } else if (rt2x00_rf(rt2x00dev, RF5222)) { 1902 spec->supported_bands |= SUPPORT_BAND_5GHZ; 1903 spec->num_channels = ARRAY_SIZE(rf_vals_5222); 1904 spec->channels = rf_vals_5222; 1905 } 1906 1907 /* 1908 * Create channel information array 1909 */ 1910 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL); 1911 if (!info) 1912 return -ENOMEM; 1913 1914 spec->channels_info = info; 1915 1916 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START); 1917 for (i = 0; i < 14; i++) { 1918 info[i].max_power = MAX_TXPOWER; 1919 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]); 1920 } 1921 1922 if (spec->num_channels > 14) { 1923 for (i = 14; i < spec->num_channels; i++) { 1924 info[i].max_power = MAX_TXPOWER; 1925 info[i].default_power1 = DEFAULT_TXPOWER; 1926 } 1927 } 1928 1929 return 0; 1930 } 1931 1932 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev) 1933 { 1934 int retval; 1935 u32 reg; 1936 1937 /* 1938 * Allocate eeprom data. 1939 */ 1940 retval = rt2500pci_validate_eeprom(rt2x00dev); 1941 if (retval) 1942 return retval; 1943 1944 retval = rt2500pci_init_eeprom(rt2x00dev); 1945 if (retval) 1946 return retval; 1947 1948 /* 1949 * Enable rfkill polling by setting GPIO direction of the 1950 * rfkill switch GPIO pin correctly. 1951 */ 1952 reg = rt2x00mmio_register_read(rt2x00dev, GPIOCSR); 1953 rt2x00_set_field32(®, GPIOCSR_DIR0, 1); 1954 rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg); 1955 1956 /* 1957 * Initialize hw specifications. 1958 */ 1959 retval = rt2500pci_probe_hw_mode(rt2x00dev); 1960 if (retval) 1961 return retval; 1962 1963 /* 1964 * This device requires the atim queue and DMA-mapped skbs. 1965 */ 1966 __set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags); 1967 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags); 1968 __set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags); 1969 1970 /* 1971 * Set the rssi offset. 1972 */ 1973 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; 1974 1975 return 0; 1976 } 1977 1978 /* 1979 * IEEE80211 stack callback functions. 1980 */ 1981 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw, 1982 struct ieee80211_vif *vif) 1983 { 1984 struct rt2x00_dev *rt2x00dev = hw->priv; 1985 u64 tsf; 1986 u32 reg; 1987 1988 reg = rt2x00mmio_register_read(rt2x00dev, CSR17); 1989 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32; 1990 reg = rt2x00mmio_register_read(rt2x00dev, CSR16); 1991 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER); 1992 1993 return tsf; 1994 } 1995 1996 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw) 1997 { 1998 struct rt2x00_dev *rt2x00dev = hw->priv; 1999 u32 reg; 2000 2001 reg = rt2x00mmio_register_read(rt2x00dev, CSR15); 2002 return rt2x00_get_field32(reg, CSR15_BEACON_SENT); 2003 } 2004 2005 static const struct ieee80211_ops rt2500pci_mac80211_ops = { 2006 .tx = rt2x00mac_tx, 2007 .start = rt2x00mac_start, 2008 .stop = rt2x00mac_stop, 2009 .add_interface = rt2x00mac_add_interface, 2010 .remove_interface = rt2x00mac_remove_interface, 2011 .config = rt2x00mac_config, 2012 .configure_filter = rt2x00mac_configure_filter, 2013 .sw_scan_start = rt2x00mac_sw_scan_start, 2014 .sw_scan_complete = rt2x00mac_sw_scan_complete, 2015 .get_stats = rt2x00mac_get_stats, 2016 .bss_info_changed = rt2x00mac_bss_info_changed, 2017 .conf_tx = rt2x00mac_conf_tx, 2018 .get_tsf = rt2500pci_get_tsf, 2019 .tx_last_beacon = rt2500pci_tx_last_beacon, 2020 .rfkill_poll = rt2x00mac_rfkill_poll, 2021 .flush = rt2x00mac_flush, 2022 .set_antenna = rt2x00mac_set_antenna, 2023 .get_antenna = rt2x00mac_get_antenna, 2024 .get_ringparam = rt2x00mac_get_ringparam, 2025 .tx_frames_pending = rt2x00mac_tx_frames_pending, 2026 }; 2027 2028 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = { 2029 .irq_handler = rt2500pci_interrupt, 2030 .txstatus_tasklet = rt2500pci_txstatus_tasklet, 2031 .tbtt_tasklet = rt2500pci_tbtt_tasklet, 2032 .rxdone_tasklet = rt2500pci_rxdone_tasklet, 2033 .probe_hw = rt2500pci_probe_hw, 2034 .initialize = rt2x00mmio_initialize, 2035 .uninitialize = rt2x00mmio_uninitialize, 2036 .get_entry_state = rt2500pci_get_entry_state, 2037 .clear_entry = rt2500pci_clear_entry, 2038 .set_device_state = rt2500pci_set_device_state, 2039 .rfkill_poll = rt2500pci_rfkill_poll, 2040 .link_stats = rt2500pci_link_stats, 2041 .reset_tuner = rt2500pci_reset_tuner, 2042 .link_tuner = rt2500pci_link_tuner, 2043 .start_queue = rt2500pci_start_queue, 2044 .kick_queue = rt2500pci_kick_queue, 2045 .stop_queue = rt2500pci_stop_queue, 2046 .flush_queue = rt2x00mmio_flush_queue, 2047 .write_tx_desc = rt2500pci_write_tx_desc, 2048 .write_beacon = rt2500pci_write_beacon, 2049 .fill_rxdone = rt2500pci_fill_rxdone, 2050 .config_filter = rt2500pci_config_filter, 2051 .config_intf = rt2500pci_config_intf, 2052 .config_erp = rt2500pci_config_erp, 2053 .config_ant = rt2500pci_config_ant, 2054 .config = rt2500pci_config, 2055 }; 2056 2057 static void rt2500pci_queue_init(struct data_queue *queue) 2058 { 2059 switch (queue->qid) { 2060 case QID_RX: 2061 queue->limit = 32; 2062 queue->data_size = DATA_FRAME_SIZE; 2063 queue->desc_size = RXD_DESC_SIZE; 2064 queue->priv_size = sizeof(struct queue_entry_priv_mmio); 2065 break; 2066 2067 case QID_AC_VO: 2068 case QID_AC_VI: 2069 case QID_AC_BE: 2070 case QID_AC_BK: 2071 queue->limit = 32; 2072 queue->data_size = DATA_FRAME_SIZE; 2073 queue->desc_size = TXD_DESC_SIZE; 2074 queue->priv_size = sizeof(struct queue_entry_priv_mmio); 2075 break; 2076 2077 case QID_BEACON: 2078 queue->limit = 1; 2079 queue->data_size = MGMT_FRAME_SIZE; 2080 queue->desc_size = TXD_DESC_SIZE; 2081 queue->priv_size = sizeof(struct queue_entry_priv_mmio); 2082 break; 2083 2084 case QID_ATIM: 2085 queue->limit = 8; 2086 queue->data_size = DATA_FRAME_SIZE; 2087 queue->desc_size = TXD_DESC_SIZE; 2088 queue->priv_size = sizeof(struct queue_entry_priv_mmio); 2089 break; 2090 2091 default: 2092 BUG(); 2093 break; 2094 } 2095 } 2096 2097 static const struct rt2x00_ops rt2500pci_ops = { 2098 .name = KBUILD_MODNAME, 2099 .max_ap_intf = 1, 2100 .eeprom_size = EEPROM_SIZE, 2101 .rf_size = RF_SIZE, 2102 .tx_queues = NUM_TX_QUEUES, 2103 .queue_init = rt2500pci_queue_init, 2104 .lib = &rt2500pci_rt2x00_ops, 2105 .hw = &rt2500pci_mac80211_ops, 2106 #ifdef CONFIG_RT2X00_LIB_DEBUGFS 2107 .debugfs = &rt2500pci_rt2x00debug, 2108 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 2109 }; 2110 2111 /* 2112 * RT2500pci module information. 2113 */ 2114 static const struct pci_device_id rt2500pci_device_table[] = { 2115 { PCI_DEVICE(0x1814, 0x0201) }, 2116 { 0, } 2117 }; 2118 2119 MODULE_AUTHOR(DRV_PROJECT); 2120 MODULE_VERSION(DRV_VERSION); 2121 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver."); 2122 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table); 2123 MODULE_LICENSE("GPL"); 2124 2125 static int rt2500pci_probe(struct pci_dev *pci_dev, 2126 const struct pci_device_id *id) 2127 { 2128 return rt2x00pci_probe(pci_dev, &rt2500pci_ops); 2129 } 2130 2131 static struct pci_driver rt2500pci_driver = { 2132 .name = KBUILD_MODNAME, 2133 .id_table = rt2500pci_device_table, 2134 .probe = rt2500pci_probe, 2135 .remove = rt2x00pci_remove, 2136 .driver.pm = &rt2x00pci_pm_ops, 2137 }; 2138 2139 module_pci_driver(rt2500pci_driver); 2140