1 /* 2 * Copyright (c) 2015-2016 Quantenna Communications, Inc. 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 2 8 * of the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 */ 16 17 #ifndef _QTN_FMAC_PCIE_IPC_H_ 18 #define _QTN_FMAC_PCIE_IPC_H_ 19 20 #include <linux/types.h> 21 22 #include "shm_ipc_defs.h" 23 24 /* bitmap for EP status and flags: updated by EP, read by RC */ 25 #define QTN_EP_HAS_UBOOT BIT(0) 26 #define QTN_EP_HAS_FIRMWARE BIT(1) 27 #define QTN_EP_REQ_UBOOT BIT(2) 28 #define QTN_EP_REQ_FIRMWARE BIT(3) 29 #define QTN_EP_ERROR_UBOOT BIT(4) 30 #define QTN_EP_ERROR_FIRMWARE BIT(5) 31 32 #define QTN_EP_FW_LOADRDY BIT(8) 33 #define QTN_EP_FW_SYNC BIT(9) 34 #define QTN_EP_FW_RETRY BIT(10) 35 #define QTN_EP_FW_QLINK_DONE BIT(15) 36 #define QTN_EP_FW_DONE BIT(16) 37 38 /* bitmap for RC status and flags: updated by RC, read by EP */ 39 #define QTN_RC_PCIE_LINK BIT(0) 40 #define QTN_RC_NET_LINK BIT(1) 41 #define QTN_RC_FW_FLASHBOOT BIT(5) 42 #define QTN_RC_FW_QLINK BIT(7) 43 #define QTN_RC_FW_LOADRDY BIT(8) 44 #define QTN_RC_FW_SYNC BIT(9) 45 46 #define PCIE_HDP_INT_RX_BITS (0 \ 47 | PCIE_HDP_INT_EP_TXDMA \ 48 | PCIE_HDP_INT_EP_TXEMPTY \ 49 | PCIE_HDP_INT_HHBM_UF \ 50 ) 51 52 #define PCIE_HDP_INT_TX_BITS (0 \ 53 | PCIE_HDP_INT_EP_RXDMA \ 54 ) 55 56 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 57 #define QTN_HOST_HI32(a) ((u32)(((u64)a) >> 32)) 58 #define QTN_HOST_LO32(a) ((u32)(((u64)a) & 0xffffffffUL)) 59 #define QTN_HOST_ADDR(h, l) ((((u64)h) << 32) | ((u64)l)) 60 #else 61 #define QTN_HOST_HI32(a) 0 62 #define QTN_HOST_LO32(a) ((u32)(((u32)a) & 0xffffffffUL)) 63 #define QTN_HOST_ADDR(h, l) ((u32)l) 64 #endif 65 66 #define QTN_PCIE_BDA_VERSION 0x1002 67 68 #define PCIE_BDA_NAMELEN 32 69 #define PCIE_HHBM_MAX_SIZE 2048 70 71 #define QTN_PCIE_BOARDFLG "PCIEQTN" 72 #define QTN_PCIE_FW_DLMASK 0xF 73 #define QTN_PCIE_FW_BUFSZ 2048 74 75 #define QTN_ENET_ADDR_LENGTH 6 76 77 #define QTN_TXDONE_MASK ((u32)0x80000000) 78 #define QTN_GET_LEN(x) ((x) & 0xFFFF) 79 80 #define QTN_PCIE_TX_DESC_LEN_MASK 0xFFFF 81 #define QTN_PCIE_TX_DESC_LEN_SHIFT 0 82 #define QTN_PCIE_TX_DESC_PORT_MASK 0xF 83 #define QTN_PCIE_TX_DESC_PORT_SHIFT 16 84 #define QTN_PCIE_TX_DESC_TQE_BIT BIT(24) 85 86 #define QTN_EP_LHOST_TQE_PORT 4 87 88 enum qtnf_pcie_bda_ipc_flags { 89 QTN_PCIE_IPC_FLAG_HBM_MAGIC = BIT(0), 90 QTN_PCIE_IPC_FLAG_SHM_PIO = BIT(1), 91 }; 92 93 enum qtnf_fw_loadtype { 94 QTN_FW_DBEGIN, 95 QTN_FW_DSUB, 96 QTN_FW_DEND, 97 QTN_FW_CTRL 98 }; 99 100 #endif /* _QTN_FMAC_PCIE_IPC_H_ */ 101