1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (c) 2018 Quantenna Communications, Inc. All rights reserved. */ 3 4 #include <linux/printk.h> 5 #include <linux/pci.h> 6 #include <linux/spinlock.h> 7 #include <linux/mutex.h> 8 #include <linux/netdevice.h> 9 #include <linux/seq_file.h> 10 #include <linux/workqueue.h> 11 #include <linux/completion.h> 12 13 #include "pcie_priv.h" 14 #include "bus.h" 15 #include "shm_ipc.h" 16 #include "core.h" 17 #include "debug.h" 18 19 #undef pr_fmt 20 #define pr_fmt(fmt) "qtnf_pcie: %s: " fmt, __func__ 21 22 #define QTN_SYSCTL_BAR 0 23 #define QTN_SHMEM_BAR 2 24 #define QTN_DMA_BAR 3 25 26 int qtnf_pcie_control_tx(struct qtnf_bus *bus, struct sk_buff *skb) 27 { 28 struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus); 29 int ret; 30 31 ret = qtnf_shm_ipc_send(&priv->shm_ipc_ep_in, skb->data, skb->len); 32 33 if (ret == -ETIMEDOUT) { 34 pr_err("EP firmware is dead\n"); 35 bus->fw_state = QTNF_FW_STATE_EP_DEAD; 36 } 37 38 return ret; 39 } 40 41 int qtnf_pcie_alloc_skb_array(struct qtnf_pcie_bus_priv *priv) 42 { 43 struct sk_buff **vaddr; 44 int len; 45 46 len = priv->tx_bd_num * sizeof(*priv->tx_skb) + 47 priv->rx_bd_num * sizeof(*priv->rx_skb); 48 vaddr = devm_kzalloc(&priv->pdev->dev, len, GFP_KERNEL); 49 50 if (!vaddr) 51 return -ENOMEM; 52 53 priv->tx_skb = vaddr; 54 55 vaddr += priv->tx_bd_num; 56 priv->rx_skb = vaddr; 57 58 return 0; 59 } 60 61 void qtnf_pcie_bringup_fw_async(struct qtnf_bus *bus) 62 { 63 struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus); 64 struct pci_dev *pdev = priv->pdev; 65 66 get_device(&pdev->dev); 67 schedule_work(&bus->fw_work); 68 } 69 70 static int qtnf_dbg_mps_show(struct seq_file *s, void *data) 71 { 72 struct qtnf_bus *bus = dev_get_drvdata(s->private); 73 struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus); 74 75 seq_printf(s, "%d\n", priv->mps); 76 77 return 0; 78 } 79 80 static int qtnf_dbg_msi_show(struct seq_file *s, void *data) 81 { 82 struct qtnf_bus *bus = dev_get_drvdata(s->private); 83 struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus); 84 85 seq_printf(s, "%u\n", priv->msi_enabled); 86 87 return 0; 88 } 89 90 static int qtnf_dbg_shm_stats(struct seq_file *s, void *data) 91 { 92 struct qtnf_bus *bus = dev_get_drvdata(s->private); 93 struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus); 94 95 seq_printf(s, "shm_ipc_ep_in.tx_packet_count(%zu)\n", 96 priv->shm_ipc_ep_in.tx_packet_count); 97 seq_printf(s, "shm_ipc_ep_in.rx_packet_count(%zu)\n", 98 priv->shm_ipc_ep_in.rx_packet_count); 99 seq_printf(s, "shm_ipc_ep_out.tx_packet_count(%zu)\n", 100 priv->shm_ipc_ep_out.tx_timeout_count); 101 seq_printf(s, "shm_ipc_ep_out.rx_packet_count(%zu)\n", 102 priv->shm_ipc_ep_out.rx_packet_count); 103 104 return 0; 105 } 106 107 void qtnf_pcie_fw_boot_done(struct qtnf_bus *bus, bool boot_success, 108 const char *drv_name) 109 { 110 struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus); 111 struct pci_dev *pdev = priv->pdev; 112 int ret; 113 114 if (boot_success) { 115 bus->fw_state = QTNF_FW_STATE_FW_DNLD_DONE; 116 117 ret = qtnf_core_attach(bus); 118 if (ret) { 119 pr_err("failed to attach core\n"); 120 boot_success = false; 121 } 122 } 123 124 if (boot_success) { 125 qtnf_debugfs_init(bus, drv_name); 126 qtnf_debugfs_add_entry(bus, "mps", qtnf_dbg_mps_show); 127 qtnf_debugfs_add_entry(bus, "msi_enabled", qtnf_dbg_msi_show); 128 qtnf_debugfs_add_entry(bus, "shm_stats", qtnf_dbg_shm_stats); 129 } else { 130 bus->fw_state = QTNF_FW_STATE_DETACHED; 131 } 132 133 put_device(&pdev->dev); 134 } 135 136 static void qtnf_tune_pcie_mps(struct qtnf_pcie_bus_priv *priv) 137 { 138 struct pci_dev *pdev = priv->pdev; 139 struct pci_dev *parent; 140 int mps_p, mps_o, mps_m, mps; 141 int ret; 142 143 /* current mps */ 144 mps_o = pcie_get_mps(pdev); 145 146 /* maximum supported mps */ 147 mps_m = 128 << pdev->pcie_mpss; 148 149 /* suggested new mps value */ 150 mps = mps_m; 151 152 if (pdev->bus && pdev->bus->self) { 153 /* parent (bus) mps */ 154 parent = pdev->bus->self; 155 156 if (pci_is_pcie(parent)) { 157 mps_p = pcie_get_mps(parent); 158 mps = min(mps_m, mps_p); 159 } 160 } 161 162 ret = pcie_set_mps(pdev, mps); 163 if (ret) { 164 pr_err("failed to set mps to %d, keep using current %d\n", 165 mps, mps_o); 166 priv->mps = mps_o; 167 return; 168 } 169 170 pr_debug("set mps to %d (was %d, max %d)\n", mps, mps_o, mps_m); 171 priv->mps = mps; 172 } 173 174 static void qtnf_pcie_init_irq(struct qtnf_pcie_bus_priv *priv, bool use_msi) 175 { 176 struct pci_dev *pdev = priv->pdev; 177 178 /* fall back to legacy INTx interrupts by default */ 179 priv->msi_enabled = 0; 180 181 /* check if MSI capability is available */ 182 if (use_msi) { 183 if (!pci_enable_msi(pdev)) { 184 pr_debug("enabled MSI interrupt\n"); 185 priv->msi_enabled = 1; 186 } else { 187 pr_warn("failed to enable MSI interrupts"); 188 } 189 } 190 191 if (!priv->msi_enabled) { 192 pr_warn("legacy PCIE interrupts enabled\n"); 193 pci_intx(pdev, 1); 194 } 195 } 196 197 static void __iomem *qtnf_map_bar(struct qtnf_pcie_bus_priv *priv, u8 index) 198 { 199 void __iomem *vaddr; 200 dma_addr_t busaddr; 201 size_t len; 202 int ret; 203 204 ret = pcim_iomap_regions(priv->pdev, 1 << index, "qtnfmac_pcie"); 205 if (ret) 206 return IOMEM_ERR_PTR(ret); 207 208 busaddr = pci_resource_start(priv->pdev, index); 209 len = pci_resource_len(priv->pdev, index); 210 vaddr = pcim_iomap_table(priv->pdev)[index]; 211 if (!vaddr) 212 return IOMEM_ERR_PTR(-ENOMEM); 213 214 pr_debug("BAR%u vaddr=0x%p busaddr=%pad len=%u\n", 215 index, vaddr, &busaddr, (int)len); 216 217 return vaddr; 218 } 219 220 static int qtnf_pcie_init_memory(struct qtnf_pcie_bus_priv *priv) 221 { 222 int ret = -ENOMEM; 223 224 priv->sysctl_bar = qtnf_map_bar(priv, QTN_SYSCTL_BAR); 225 if (IS_ERR(priv->sysctl_bar)) { 226 pr_err("failed to map BAR%u\n", QTN_SYSCTL_BAR); 227 return ret; 228 } 229 230 priv->dmareg_bar = qtnf_map_bar(priv, QTN_DMA_BAR); 231 if (IS_ERR(priv->dmareg_bar)) { 232 pr_err("failed to map BAR%u\n", QTN_DMA_BAR); 233 return ret; 234 } 235 236 priv->epmem_bar = qtnf_map_bar(priv, QTN_SHMEM_BAR); 237 if (IS_ERR(priv->epmem_bar)) { 238 pr_err("failed to map BAR%u\n", QTN_SHMEM_BAR); 239 return ret; 240 } 241 242 return 0; 243 } 244 245 static void qtnf_pcie_control_rx_callback(void *arg, const u8 __iomem *buf, 246 size_t len) 247 { 248 struct qtnf_pcie_bus_priv *priv = arg; 249 struct qtnf_bus *bus = pci_get_drvdata(priv->pdev); 250 struct sk_buff *skb; 251 252 if (unlikely(len == 0)) { 253 pr_warn("zero length packet received\n"); 254 return; 255 } 256 257 skb = __dev_alloc_skb(len, GFP_KERNEL); 258 259 if (unlikely(!skb)) { 260 pr_err("failed to allocate skb\n"); 261 return; 262 } 263 264 memcpy_fromio(skb_put(skb, len), buf, len); 265 266 qtnf_trans_handle_rx_ctl_packet(bus, skb); 267 } 268 269 void qtnf_pcie_init_shm_ipc(struct qtnf_pcie_bus_priv *priv, 270 struct qtnf_shm_ipc_region __iomem *ipc_tx_reg, 271 struct qtnf_shm_ipc_region __iomem *ipc_rx_reg, 272 const struct qtnf_shm_ipc_int *ipc_int) 273 { 274 const struct qtnf_shm_ipc_rx_callback rx_callback = { 275 qtnf_pcie_control_rx_callback, priv }; 276 277 qtnf_shm_ipc_init(&priv->shm_ipc_ep_in, QTNF_SHM_IPC_OUTBOUND, 278 ipc_tx_reg, priv->workqueue, 279 ipc_int, &rx_callback); 280 qtnf_shm_ipc_init(&priv->shm_ipc_ep_out, QTNF_SHM_IPC_INBOUND, 281 ipc_rx_reg, priv->workqueue, 282 ipc_int, &rx_callback); 283 } 284 285 int qtnf_pcie_probe(struct pci_dev *pdev, size_t priv_size, 286 const struct qtnf_bus_ops *bus_ops, u64 dma_mask, 287 bool use_msi) 288 { 289 struct qtnf_pcie_bus_priv *pcie_priv; 290 struct qtnf_bus *bus; 291 int ret; 292 293 bus = devm_kzalloc(&pdev->dev, 294 sizeof(*bus) + priv_size, GFP_KERNEL); 295 if (!bus) 296 return -ENOMEM; 297 298 pcie_priv = get_bus_priv(bus); 299 300 pci_set_drvdata(pdev, bus); 301 bus->bus_ops = bus_ops; 302 bus->dev = &pdev->dev; 303 bus->fw_state = QTNF_FW_STATE_RESET; 304 pcie_priv->pdev = pdev; 305 pcie_priv->tx_stopped = 0; 306 307 mutex_init(&bus->bus_lock); 308 spin_lock_init(&pcie_priv->tx_lock); 309 spin_lock_init(&pcie_priv->tx_reclaim_lock); 310 311 pcie_priv->tx_full_count = 0; 312 pcie_priv->tx_done_count = 0; 313 pcie_priv->pcie_irq_count = 0; 314 pcie_priv->tx_reclaim_done = 0; 315 pcie_priv->tx_reclaim_req = 0; 316 317 pcie_priv->workqueue = create_singlethread_workqueue("QTNF_PCIE"); 318 if (!pcie_priv->workqueue) { 319 pr_err("failed to alloc bus workqueue\n"); 320 ret = -ENODEV; 321 goto err_init; 322 } 323 324 init_dummy_netdev(&bus->mux_dev); 325 326 if (!pci_is_pcie(pdev)) { 327 pr_err("device %s is not PCI Express\n", pci_name(pdev)); 328 ret = -EIO; 329 goto err_base; 330 } 331 332 qtnf_tune_pcie_mps(pcie_priv); 333 334 ret = pcim_enable_device(pdev); 335 if (ret) { 336 pr_err("failed to init PCI device %x\n", pdev->device); 337 goto err_base; 338 } else { 339 pr_debug("successful init of PCI device %x\n", pdev->device); 340 } 341 342 ret = dma_set_mask_and_coherent(&pdev->dev, dma_mask); 343 if (ret) { 344 pr_err("PCIE DMA coherent mask init failed\n"); 345 goto err_base; 346 } 347 348 pci_set_master(pdev); 349 qtnf_pcie_init_irq(pcie_priv, use_msi); 350 351 ret = qtnf_pcie_init_memory(pcie_priv); 352 if (ret < 0) { 353 pr_err("PCIE memory init failed\n"); 354 goto err_base; 355 } 356 357 pci_save_state(pdev); 358 359 return 0; 360 361 err_base: 362 flush_workqueue(pcie_priv->workqueue); 363 destroy_workqueue(pcie_priv->workqueue); 364 err_init: 365 pci_set_drvdata(pdev, NULL); 366 367 return ret; 368 } 369 370 static void qtnf_pcie_free_shm_ipc(struct qtnf_pcie_bus_priv *priv) 371 { 372 qtnf_shm_ipc_free(&priv->shm_ipc_ep_in); 373 qtnf_shm_ipc_free(&priv->shm_ipc_ep_out); 374 } 375 376 void qtnf_pcie_remove(struct qtnf_bus *bus, struct qtnf_pcie_bus_priv *priv) 377 { 378 cancel_work_sync(&bus->fw_work); 379 380 if (bus->fw_state == QTNF_FW_STATE_ACTIVE || 381 bus->fw_state == QTNF_FW_STATE_EP_DEAD) 382 qtnf_core_detach(bus); 383 384 netif_napi_del(&bus->mux_napi); 385 flush_workqueue(priv->workqueue); 386 destroy_workqueue(priv->workqueue); 387 tasklet_kill(&priv->reclaim_tq); 388 389 qtnf_pcie_free_shm_ipc(priv); 390 qtnf_debugfs_remove(bus); 391 pci_set_drvdata(priv->pdev, NULL); 392 } 393