1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (c) 2018 Quantenna Communications, Inc. All rights reserved. */ 3 4 #include <linux/module.h> 5 #include <linux/printk.h> 6 #include <linux/pci.h> 7 #include <linux/spinlock.h> 8 #include <linux/mutex.h> 9 #include <linux/netdevice.h> 10 #include <linux/seq_file.h> 11 #include <linux/workqueue.h> 12 #include <linux/completion.h> 13 14 #include "pcie_priv.h" 15 #include "bus.h" 16 #include "shm_ipc.h" 17 #include "core.h" 18 #include "debug.h" 19 #include "util.h" 20 #include "qtn_hw_ids.h" 21 22 #define QTN_SYSCTL_BAR 0 23 #define QTN_SHMEM_BAR 2 24 #define QTN_DMA_BAR 3 25 26 #define QTN_PCIE_MAX_FW_BUFSZ (1 * 1024 * 1024) 27 28 static bool use_msi = true; 29 module_param(use_msi, bool, 0644); 30 MODULE_PARM_DESC(use_msi, "set 0 to use legacy interrupt"); 31 32 static unsigned int tx_bd_size_param; 33 module_param(tx_bd_size_param, uint, 0644); 34 MODULE_PARM_DESC(tx_bd_size_param, "Tx descriptors queue size"); 35 36 static unsigned int rx_bd_size_param = 256; 37 module_param(rx_bd_size_param, uint, 0644); 38 MODULE_PARM_DESC(rx_bd_size_param, "Rx descriptors queue size"); 39 40 static u8 flashboot = 1; 41 module_param(flashboot, byte, 0644); 42 MODULE_PARM_DESC(flashboot, "set to 0 to use FW binary file on FS"); 43 44 static unsigned int fw_blksize_param = QTN_PCIE_MAX_FW_BUFSZ; 45 module_param(fw_blksize_param, uint, 0644); 46 MODULE_PARM_DESC(fw_blksize_param, "firmware loading block size in bytes"); 47 48 #define DRV_NAME "qtnfmac_pcie" 49 50 int qtnf_pcie_control_tx(struct qtnf_bus *bus, struct sk_buff *skb) 51 { 52 struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus); 53 int ret; 54 55 ret = qtnf_shm_ipc_send(&priv->shm_ipc_ep_in, skb->data, skb->len); 56 57 if (ret == -ETIMEDOUT) { 58 pr_err("EP firmware is dead\n"); 59 bus->fw_state = QTNF_FW_STATE_DEAD; 60 } 61 62 return ret; 63 } 64 65 int qtnf_pcie_alloc_skb_array(struct qtnf_pcie_bus_priv *priv) 66 { 67 struct sk_buff **vaddr; 68 int len; 69 70 len = priv->tx_bd_num * sizeof(*priv->tx_skb) + 71 priv->rx_bd_num * sizeof(*priv->rx_skb); 72 vaddr = devm_kzalloc(&priv->pdev->dev, len, GFP_KERNEL); 73 74 if (!vaddr) 75 return -ENOMEM; 76 77 priv->tx_skb = vaddr; 78 79 vaddr += priv->tx_bd_num; 80 priv->rx_skb = vaddr; 81 82 return 0; 83 } 84 85 static void qtnf_pcie_bringup_fw_async(struct qtnf_bus *bus) 86 { 87 struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus); 88 struct pci_dev *pdev = priv->pdev; 89 90 get_device(&pdev->dev); 91 schedule_work(&bus->fw_work); 92 } 93 94 static int qtnf_dbg_mps_show(struct seq_file *s, void *data) 95 { 96 struct qtnf_bus *bus = dev_get_drvdata(s->private); 97 struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus); 98 99 seq_printf(s, "%d\n", pcie_get_mps(priv->pdev)); 100 101 return 0; 102 } 103 104 static int qtnf_dbg_msi_show(struct seq_file *s, void *data) 105 { 106 struct qtnf_bus *bus = dev_get_drvdata(s->private); 107 struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus); 108 109 seq_printf(s, "%u\n", priv->msi_enabled); 110 111 return 0; 112 } 113 114 static int qtnf_dbg_shm_stats(struct seq_file *s, void *data) 115 { 116 struct qtnf_bus *bus = dev_get_drvdata(s->private); 117 struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus); 118 119 seq_printf(s, "shm_ipc_ep_in.tx_packet_count(%zu)\n", 120 priv->shm_ipc_ep_in.tx_packet_count); 121 seq_printf(s, "shm_ipc_ep_in.rx_packet_count(%zu)\n", 122 priv->shm_ipc_ep_in.rx_packet_count); 123 seq_printf(s, "shm_ipc_ep_out.tx_packet_count(%zu)\n", 124 priv->shm_ipc_ep_out.tx_timeout_count); 125 seq_printf(s, "shm_ipc_ep_out.rx_packet_count(%zu)\n", 126 priv->shm_ipc_ep_out.rx_packet_count); 127 128 return 0; 129 } 130 131 int qtnf_pcie_fw_boot_done(struct qtnf_bus *bus) 132 { 133 int ret; 134 135 bus->fw_state = QTNF_FW_STATE_BOOT_DONE; 136 ret = qtnf_core_attach(bus); 137 if (ret) { 138 pr_err("failed to attach core\n"); 139 } else { 140 qtnf_debugfs_init(bus, DRV_NAME); 141 qtnf_debugfs_add_entry(bus, "mps", qtnf_dbg_mps_show); 142 qtnf_debugfs_add_entry(bus, "msi_enabled", qtnf_dbg_msi_show); 143 qtnf_debugfs_add_entry(bus, "shm_stats", qtnf_dbg_shm_stats); 144 } 145 146 return ret; 147 } 148 149 static void qtnf_tune_pcie_mps(struct pci_dev *pdev) 150 { 151 struct pci_dev *parent; 152 int mps_p, mps_o, mps_m, mps; 153 int ret; 154 155 /* current mps */ 156 mps_o = pcie_get_mps(pdev); 157 158 /* maximum supported mps */ 159 mps_m = 128 << pdev->pcie_mpss; 160 161 /* suggested new mps value */ 162 mps = mps_m; 163 164 if (pdev->bus && pdev->bus->self) { 165 /* parent (bus) mps */ 166 parent = pdev->bus->self; 167 168 if (pci_is_pcie(parent)) { 169 mps_p = pcie_get_mps(parent); 170 mps = min(mps_m, mps_p); 171 } 172 } 173 174 ret = pcie_set_mps(pdev, mps); 175 if (ret) { 176 pr_err("failed to set mps to %d, keep using current %d\n", 177 mps, mps_o); 178 return; 179 } 180 181 pr_debug("set mps to %d (was %d, max %d)\n", mps, mps_o, mps_m); 182 } 183 184 static void qtnf_pcie_init_irq(struct qtnf_pcie_bus_priv *priv, bool use_msi) 185 { 186 struct pci_dev *pdev = priv->pdev; 187 188 /* fall back to legacy INTx interrupts by default */ 189 priv->msi_enabled = 0; 190 191 /* check if MSI capability is available */ 192 if (use_msi) { 193 if (!pci_enable_msi(pdev)) { 194 pr_debug("enabled MSI interrupt\n"); 195 priv->msi_enabled = 1; 196 } else { 197 pr_warn("failed to enable MSI interrupts"); 198 } 199 } 200 201 if (!priv->msi_enabled) { 202 pr_warn("legacy PCIE interrupts enabled\n"); 203 pci_intx(pdev, 1); 204 } 205 } 206 207 static void __iomem *qtnf_map_bar(struct pci_dev *pdev, u8 index) 208 { 209 void __iomem *vaddr; 210 dma_addr_t busaddr; 211 size_t len; 212 int ret; 213 214 ret = pcim_iomap_regions(pdev, 1 << index, "qtnfmac_pcie"); 215 if (ret) 216 return IOMEM_ERR_PTR(ret); 217 218 busaddr = pci_resource_start(pdev, index); 219 len = pci_resource_len(pdev, index); 220 vaddr = pcim_iomap_table(pdev)[index]; 221 if (!vaddr) 222 return IOMEM_ERR_PTR(-ENOMEM); 223 224 pr_debug("BAR%u vaddr=0x%p busaddr=%pad len=%u\n", 225 index, vaddr, &busaddr, (int)len); 226 227 return vaddr; 228 } 229 230 static void qtnf_pcie_control_rx_callback(void *arg, const u8 __iomem *buf, 231 size_t len) 232 { 233 struct qtnf_pcie_bus_priv *priv = arg; 234 struct qtnf_bus *bus = pci_get_drvdata(priv->pdev); 235 struct sk_buff *skb; 236 237 if (unlikely(len == 0)) { 238 pr_warn("zero length packet received\n"); 239 return; 240 } 241 242 skb = __dev_alloc_skb(len, GFP_KERNEL); 243 244 if (unlikely(!skb)) { 245 pr_err("failed to allocate skb\n"); 246 return; 247 } 248 249 memcpy_fromio(skb_put(skb, len), buf, len); 250 251 qtnf_trans_handle_rx_ctl_packet(bus, skb); 252 } 253 254 void qtnf_pcie_init_shm_ipc(struct qtnf_pcie_bus_priv *priv, 255 struct qtnf_shm_ipc_region __iomem *ipc_tx_reg, 256 struct qtnf_shm_ipc_region __iomem *ipc_rx_reg, 257 const struct qtnf_shm_ipc_int *ipc_int) 258 { 259 const struct qtnf_shm_ipc_rx_callback rx_callback = { 260 qtnf_pcie_control_rx_callback, priv }; 261 262 qtnf_shm_ipc_init(&priv->shm_ipc_ep_in, QTNF_SHM_IPC_OUTBOUND, 263 ipc_tx_reg, priv->workqueue, 264 ipc_int, &rx_callback); 265 qtnf_shm_ipc_init(&priv->shm_ipc_ep_out, QTNF_SHM_IPC_INBOUND, 266 ipc_rx_reg, priv->workqueue, 267 ipc_int, &rx_callback); 268 } 269 270 static int qtnf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) 271 { 272 struct qtnf_pcie_bus_priv *pcie_priv; 273 struct qtnf_bus *bus; 274 void __iomem *sysctl_bar; 275 void __iomem *epmem_bar; 276 void __iomem *dmareg_bar; 277 unsigned int chipid; 278 int ret; 279 280 if (!pci_is_pcie(pdev)) { 281 pr_err("device %s is not PCI Express\n", pci_name(pdev)); 282 return -EIO; 283 } 284 285 qtnf_tune_pcie_mps(pdev); 286 287 ret = pcim_enable_device(pdev); 288 if (ret) { 289 pr_err("failed to init PCI device %x\n", pdev->device); 290 return ret; 291 } 292 293 pci_set_master(pdev); 294 295 sysctl_bar = qtnf_map_bar(pdev, QTN_SYSCTL_BAR); 296 if (IS_ERR(sysctl_bar)) { 297 pr_err("failed to map BAR%u\n", QTN_SYSCTL_BAR); 298 return ret; 299 } 300 301 dmareg_bar = qtnf_map_bar(pdev, QTN_DMA_BAR); 302 if (IS_ERR(dmareg_bar)) { 303 pr_err("failed to map BAR%u\n", QTN_DMA_BAR); 304 return ret; 305 } 306 307 epmem_bar = qtnf_map_bar(pdev, QTN_SHMEM_BAR); 308 if (IS_ERR(epmem_bar)) { 309 pr_err("failed to map BAR%u\n", QTN_SHMEM_BAR); 310 return ret; 311 } 312 313 chipid = qtnf_chip_id_get(sysctl_bar); 314 315 pr_info("identified device: %s\n", qtnf_chipid_to_string(chipid)); 316 317 switch (chipid) { 318 case QTN_CHIP_ID_PEARL: 319 case QTN_CHIP_ID_PEARL_B: 320 case QTN_CHIP_ID_PEARL_C: 321 bus = qtnf_pcie_pearl_alloc(pdev); 322 break; 323 case QTN_CHIP_ID_TOPAZ: 324 bus = qtnf_pcie_topaz_alloc(pdev); 325 break; 326 default: 327 pr_err("unsupported chip ID 0x%x\n", chipid); 328 return -ENOTSUPP; 329 } 330 331 if (!bus) 332 return -ENOMEM; 333 334 pcie_priv = get_bus_priv(bus); 335 pci_set_drvdata(pdev, bus); 336 bus->dev = &pdev->dev; 337 bus->fw_state = QTNF_FW_STATE_DETACHED; 338 pcie_priv->pdev = pdev; 339 pcie_priv->tx_stopped = 0; 340 pcie_priv->rx_bd_num = rx_bd_size_param; 341 pcie_priv->flashboot = flashboot; 342 343 if (fw_blksize_param > QTN_PCIE_MAX_FW_BUFSZ) 344 pcie_priv->fw_blksize = QTN_PCIE_MAX_FW_BUFSZ; 345 else 346 pcie_priv->fw_blksize = fw_blksize_param; 347 348 mutex_init(&bus->bus_lock); 349 spin_lock_init(&pcie_priv->tx_lock); 350 spin_lock_init(&pcie_priv->tx_reclaim_lock); 351 352 pcie_priv->tx_full_count = 0; 353 pcie_priv->tx_done_count = 0; 354 pcie_priv->pcie_irq_count = 0; 355 pcie_priv->tx_reclaim_done = 0; 356 pcie_priv->tx_reclaim_req = 0; 357 pcie_priv->tx_eapol = 0; 358 359 pcie_priv->workqueue = create_singlethread_workqueue("QTNF_PCIE"); 360 if (!pcie_priv->workqueue) { 361 pr_err("failed to alloc bus workqueue\n"); 362 return -ENODEV; 363 } 364 365 ret = dma_set_mask_and_coherent(&pdev->dev, 366 pcie_priv->dma_mask_get_cb()); 367 if (ret) { 368 pr_err("PCIE DMA coherent mask init failed 0x%llx\n", 369 pcie_priv->dma_mask_get_cb()); 370 goto error; 371 } 372 373 init_dummy_netdev(&bus->mux_dev); 374 qtnf_pcie_init_irq(pcie_priv, use_msi); 375 pcie_priv->sysctl_bar = sysctl_bar; 376 pcie_priv->dmareg_bar = dmareg_bar; 377 pcie_priv->epmem_bar = epmem_bar; 378 pci_save_state(pdev); 379 380 ret = pcie_priv->probe_cb(bus, tx_bd_size_param); 381 if (ret) 382 goto error; 383 384 qtnf_pcie_bringup_fw_async(bus); 385 return 0; 386 387 error: 388 flush_workqueue(pcie_priv->workqueue); 389 destroy_workqueue(pcie_priv->workqueue); 390 pci_set_drvdata(pdev, NULL); 391 return ret; 392 } 393 394 static void qtnf_pcie_free_shm_ipc(struct qtnf_pcie_bus_priv *priv) 395 { 396 qtnf_shm_ipc_free(&priv->shm_ipc_ep_in); 397 qtnf_shm_ipc_free(&priv->shm_ipc_ep_out); 398 } 399 400 static void qtnf_pcie_remove(struct pci_dev *dev) 401 { 402 struct qtnf_pcie_bus_priv *priv; 403 struct qtnf_bus *bus; 404 405 bus = pci_get_drvdata(dev); 406 if (!bus) 407 return; 408 409 priv = get_bus_priv(bus); 410 411 cancel_work_sync(&bus->fw_work); 412 413 if (qtnf_fw_is_attached(bus)) 414 qtnf_core_detach(bus); 415 416 netif_napi_del(&bus->mux_napi); 417 flush_workqueue(priv->workqueue); 418 destroy_workqueue(priv->workqueue); 419 tasklet_kill(&priv->reclaim_tq); 420 421 qtnf_pcie_free_shm_ipc(priv); 422 qtnf_debugfs_remove(bus); 423 priv->remove_cb(bus); 424 pci_set_drvdata(priv->pdev, NULL); 425 } 426 427 #ifdef CONFIG_PM_SLEEP 428 static int qtnf_pcie_suspend(struct device *dev) 429 { 430 struct qtnf_pcie_bus_priv *priv; 431 struct qtnf_bus *bus; 432 433 bus = dev_get_drvdata(dev); 434 if (!bus) 435 return -EFAULT; 436 437 priv = get_bus_priv(bus); 438 return priv->suspend_cb(bus); 439 } 440 441 static int qtnf_pcie_resume(struct device *dev) 442 { 443 struct qtnf_pcie_bus_priv *priv; 444 struct qtnf_bus *bus; 445 446 bus = dev_get_drvdata(dev); 447 if (!bus) 448 return -EFAULT; 449 450 priv = get_bus_priv(bus); 451 return priv->resume_cb(bus); 452 } 453 454 /* Power Management Hooks */ 455 static SIMPLE_DEV_PM_OPS(qtnf_pcie_pm_ops, qtnf_pcie_suspend, 456 qtnf_pcie_resume); 457 #endif 458 459 static const struct pci_device_id qtnf_pcie_devid_table[] = { 460 { 461 PCIE_VENDOR_ID_QUANTENNA, PCIE_DEVICE_ID_QSR, 462 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 463 }, 464 { }, 465 }; 466 467 MODULE_DEVICE_TABLE(pci, qtnf_pcie_devid_table); 468 469 static struct pci_driver qtnf_pcie_drv_data = { 470 .name = DRV_NAME, 471 .id_table = qtnf_pcie_devid_table, 472 .probe = qtnf_pcie_probe, 473 .remove = qtnf_pcie_remove, 474 #ifdef CONFIG_PM_SLEEP 475 .driver = { 476 .pm = &qtnf_pcie_pm_ops, 477 }, 478 #endif 479 }; 480 481 static int __init qtnf_pcie_register(void) 482 { 483 return pci_register_driver(&qtnf_pcie_drv_data); 484 } 485 486 static void __exit qtnf_pcie_exit(void) 487 { 488 pci_unregister_driver(&qtnf_pcie_drv_data); 489 } 490 491 module_init(qtnf_pcie_register); 492 module_exit(qtnf_pcie_exit); 493 494 MODULE_AUTHOR("Quantenna Communications"); 495 MODULE_DESCRIPTION("Quantenna PCIe bus driver for 802.11 wireless LAN."); 496 MODULE_LICENSE("GPL"); 497