xref: /linux/drivers/net/wireless/morsemicro/mm81x/command_defs.h (revision 91ec2035134982b98fab0609a9fd8480e8217dc1)
1*b1906ceaSLachlan Hodges /* SPDX-License-Identifier: GPL-2.0-only */
2*b1906ceaSLachlan Hodges /*
3*b1906ceaSLachlan Hodges  * Copyright (c) 2017-2026 Morse Micro
4*b1906ceaSLachlan Hodges  */
5*b1906ceaSLachlan Hodges #ifndef _MM81X_COMMAND_DEFS_H_
6*b1906ceaSLachlan Hodges #define _MM81X_COMMAND_DEFS_H_
7*b1906ceaSLachlan Hodges 
8*b1906ceaSLachlan Hodges #include <linux/types.h>
9*b1906ceaSLachlan Hodges 
10*b1906ceaSLachlan Hodges #define __sle16 __le16
11*b1906ceaSLachlan Hodges #define __sle32 __le32
12*b1906ceaSLachlan Hodges #define __sle64 __le64
13*b1906ceaSLachlan Hodges 
14*b1906ceaSLachlan Hodges #define HOST_CMD_SEMVER_MAJOR 56
15*b1906ceaSLachlan Hodges #define HOST_CMD_SEMVER_MINOR 17
16*b1906ceaSLachlan Hodges #define HOST_CMD_SEMVER_PATCH 0
17*b1906ceaSLachlan Hodges 
18*b1906ceaSLachlan Hodges #define HOST_CMD_TYPE_REQ BIT(0)
19*b1906ceaSLachlan Hodges #define HOST_CMD_TYPE_RESP BIT(1)
20*b1906ceaSLachlan Hodges #define HOST_CMD_TYPE_EVT BIT(2)
21*b1906ceaSLachlan Hodges 
22*b1906ceaSLachlan Hodges #define HOST_CMD_SSID_MAX_LEN 32
23*b1906ceaSLachlan Hodges #define HOST_CMD_MAC_ADDR_LEN 6
24*b1906ceaSLachlan Hodges 
25*b1906ceaSLachlan Hodges enum host_cmd_id {
26*b1906ceaSLachlan Hodges 	HOST_CMD_ID_SET_CHANNEL = 0x0001,
27*b1906ceaSLachlan Hodges 	HOST_CMD_ID_GET_CHANNEL = 0x001D,
28*b1906ceaSLachlan Hodges 	HOST_CMD_ID_GET_CHANNEL_FULL = 0x0013,
29*b1906ceaSLachlan Hodges 	HOST_CMD_ID_GET_CHANNEL_DTIM = 0x001C,
30*b1906ceaSLachlan Hodges 	HOST_CMD_ID_GET_VERSION = 0x0002,
31*b1906ceaSLachlan Hodges 	HOST_CMD_ID_SET_TXPOWER = 0x0003,
32*b1906ceaSLachlan Hodges 	HOST_CMD_ID_GET_MAX_TXPOWER = 0x0024,
33*b1906ceaSLachlan Hodges 	HOST_CMD_ID_ADD_INTERFACE = 0x0004,
34*b1906ceaSLachlan Hodges 	HOST_CMD_ID_REMOVE_INTERFACE = 0x0005,
35*b1906ceaSLachlan Hodges 	HOST_CMD_ID_BSS_CONFIG = 0x0006,
36*b1906ceaSLachlan Hodges 	HOST_CMD_ID_SCAN_CONFIG = 0x0010,
37*b1906ceaSLachlan Hodges 	HOST_CMD_ID_SET_QOS_PARAMS = 0x0011,
38*b1906ceaSLachlan Hodges 	HOST_CMD_ID_GET_QOS_PARAMS = 0x0012,
39*b1906ceaSLachlan Hodges 	HOST_CMD_ID_SET_STA_STATE = 0x0014,
40*b1906ceaSLachlan Hodges 	HOST_CMD_ID_SET_BSS_COLOR = 0x0015,
41*b1906ceaSLachlan Hodges 	HOST_CMD_ID_CONFIG_PS = 0x0016,
42*b1906ceaSLachlan Hodges 	HOST_CMD_ID_HEALTH_CHECK = 0x0019,
43*b1906ceaSLachlan Hodges 	HOST_CMD_ID_CTS_SELF_PS = 0x001A,
44*b1906ceaSLachlan Hodges 	HOST_CMD_ID_DTIM_CHANNEL_ENABLE = 0x001B,
45*b1906ceaSLachlan Hodges 	HOST_CMD_ID_ARP_OFFLOAD = 0x0020,
46*b1906ceaSLachlan Hodges 	HOST_CMD_ID_SET_LONG_SLEEP_CONFIG = 0x0021,
47*b1906ceaSLachlan Hodges 	HOST_CMD_ID_SET_DUTY_CYCLE = 0x0022,
48*b1906ceaSLachlan Hodges 	HOST_CMD_ID_GET_DUTY_CYCLE = 0x0023,
49*b1906ceaSLachlan Hodges 	HOST_CMD_ID_GET_CAPABILITIES = 0x0025,
50*b1906ceaSLachlan Hodges 	HOST_CMD_ID_TWT_AGREEMENT_INSTALL = 0x0026,
51*b1906ceaSLachlan Hodges 	HOST_CMD_ID_TWT_AGREEMENT_VALIDATE = 0x0036,
52*b1906ceaSLachlan Hodges 	HOST_CMD_ID_TWT_AGREEMENT_REMOVE = 0x0027,
53*b1906ceaSLachlan Hodges 	HOST_CMD_ID_GET_TSF = 0x0028,
54*b1906ceaSLachlan Hodges 	HOST_CMD_ID_MAC_ADDR = 0x0029,
55*b1906ceaSLachlan Hodges 	HOST_CMD_ID_MPSW_CONFIG = 0x0030,
56*b1906ceaSLachlan Hodges 	HOST_CMD_ID_INSTALL_KEY = 0x000A,
57*b1906ceaSLachlan Hodges 	HOST_CMD_ID_DISABLE_KEY = 0x000B,
58*b1906ceaSLachlan Hodges 	HOST_CMD_ID_DHCP_OFFLOAD = 0x0032,
59*b1906ceaSLachlan Hodges 	HOST_CMD_ID_SET_KEEP_ALIVE_OFFLOAD = 0x0033,
60*b1906ceaSLachlan Hodges 	HOST_CMD_ID_UPDATE_OUI_FILTER = 0x0034,
61*b1906ceaSLachlan Hodges 	HOST_CMD_ID_IBSS_CONFIG = 0x0035,
62*b1906ceaSLachlan Hodges 	HOST_CMD_ID_OCS = 0x0038,
63*b1906ceaSLachlan Hodges 	HOST_CMD_ID_MESH_CONFIG = 0x0039,
64*b1906ceaSLachlan Hodges 	HOST_CMD_ID_SET_OFFSET_TSF = 0x003A,
65*b1906ceaSLachlan Hodges 	HOST_CMD_ID_GET_CHANNEL_USAGE = 0x003B,
66*b1906ceaSLachlan Hodges 	HOST_CMD_ID_MCAST_FILTER = 0x003C,
67*b1906ceaSLachlan Hodges 	HOST_CMD_ID_BSS_BEACON_CONFIG = 0x003D,
68*b1906ceaSLachlan Hodges 	HOST_CMD_ID_UAPSD_CONFIG = 0x0040,
69*b1906ceaSLachlan Hodges 	HOST_CMD_ID_PAGE_SLICING_CONFIG = 0x0043,
70*b1906ceaSLachlan Hodges 	HOST_CMD_ID_HW_SCAN = 0x0044,
71*b1906ceaSLachlan Hodges 	HOST_CMD_ID_SET_WHITELIST = 0x0045,
72*b1906ceaSLachlan Hodges 	HOST_CMD_ID_ARP_PERIODIC_REFRESH = 0x0046,
73*b1906ceaSLachlan Hodges 	HOST_CMD_ID_SET_TCP_KEEPALIVE = 0x0047,
74*b1906ceaSLachlan Hodges 	HOST_CMD_ID_FORCE_POWER_MODE = 0x0048,
75*b1906ceaSLachlan Hodges 	HOST_CMD_ID_LI_SLEEP = 0x0049,
76*b1906ceaSLachlan Hodges 	HOST_CMD_ID_GET_DISABLED_CHANNELS = 0x004A,
77*b1906ceaSLachlan Hodges 	HOST_CMD_ID_SET_CQM_RSSI = 0x004F,
78*b1906ceaSLachlan Hodges 	HOST_CMD_ID_GET_APF_CAPABILITIES = 0x0050,
79*b1906ceaSLachlan Hodges 	HOST_CMD_ID_READ_WRITE_APF = 0x0051,
80*b1906ceaSLachlan Hodges 	HOST_CMD_ID_BSSID_SET = 0x0052,
81*b1906ceaSLachlan Hodges 	HOST_CMD_ID_BEACON_OFFLOAD = 0x0053,
82*b1906ceaSLachlan Hodges 	HOST_CMD_ID_PROBE_RESPONSE_OFFLOAD = 0x0054,
83*b1906ceaSLachlan Hodges 	HOST_CMD_ID_HOST_STATS_LOG = 0x2007,
84*b1906ceaSLachlan Hodges 	HOST_CMD_ID_HOST_STATS_RESET = 0x2008,
85*b1906ceaSLachlan Hodges 	HOST_CMD_ID_MAC_STATS_LOG = 0x200C,
86*b1906ceaSLachlan Hodges 	HOST_CMD_ID_MAC_STATS_RESET = 0x200D,
87*b1906ceaSLachlan Hodges 	HOST_CMD_ID_UPHY_STATS_LOG = 0x200E,
88*b1906ceaSLachlan Hodges 	HOST_CMD_ID_UPHY_STATS_RESET = 0x200F,
89*b1906ceaSLachlan Hodges 	HOST_CMD_ID_SET_STA_TYPE = 0xA000,
90*b1906ceaSLachlan Hodges 	HOST_CMD_ID_SET_ENC_MODE = 0xA001,
91*b1906ceaSLachlan Hodges 	HOST_CMD_ID_TEST_BA = 0xA002,
92*b1906ceaSLachlan Hodges 	HOST_CMD_ID_SET_LISTEN_INTERVAL = 0xA003,
93*b1906ceaSLachlan Hodges 	HOST_CMD_ID_SET_AMPDU = 0xA004,
94*b1906ceaSLachlan Hodges 	HOST_CMD_ID_COREDUMP = 0xA006,
95*b1906ceaSLachlan Hodges 	HOST_CMD_ID_SET_S1G_OP_CLASS = 0xA007,
96*b1906ceaSLachlan Hodges 	HOST_CMD_ID_SEND_WAKE_ACTION_FRAME = 0xA008,
97*b1906ceaSLachlan Hodges 	HOST_CMD_ID_VENDOR_IE_CONFIG = 0xA009,
98*b1906ceaSLachlan Hodges 	HOST_CMD_ID_SET_TWT_CONF = 0xA010,
99*b1906ceaSLachlan Hodges 	HOST_CMD_ID_GET_AVAILABLE_CHANNELS = 0xA011,
100*b1906ceaSLachlan Hodges 	HOST_CMD_ID_SET_ECSA_S1G_INFO = 0xA012,
101*b1906ceaSLachlan Hodges 	HOST_CMD_ID_GET_HW_VERSION = 0xA013,
102*b1906ceaSLachlan Hodges 	HOST_CMD_ID_CAC = 0xA014,
103*b1906ceaSLachlan Hodges 	HOST_CMD_ID_DRIVER_SET_DUTY_CYCLE = 0xA015,
104*b1906ceaSLachlan Hodges 	HOST_CMD_ID_OCS_DRIVER = 0xA017,
105*b1906ceaSLachlan Hodges 	HOST_CMD_ID_MBSSID = 0xA016,
106*b1906ceaSLachlan Hodges 	HOST_CMD_ID_SET_MESH_CONFIG = 0xA018,
107*b1906ceaSLachlan Hodges 	HOST_CMD_ID_SET_MCBA_CONF = 0xA019,
108*b1906ceaSLachlan Hodges 	HOST_CMD_ID_DYNAMIC_PEERING_CONFIG = 0xA020,
109*b1906ceaSLachlan Hodges 	HOST_CMD_ID_CONFIG_RAW = 0xA021,
110*b1906ceaSLachlan Hodges 	HOST_CMD_ID_CONFIG_BSS_STATS = 0xA022,
111*b1906ceaSLachlan Hodges 	HOST_CMD_ID_GET_RSSI = 0x1002,
112*b1906ceaSLachlan Hodges 	HOST_CMD_ID_SET_IFS = 0x1003,
113*b1906ceaSLachlan Hodges 	HOST_CMD_ID_SET_FEM_SETTINGS = 0x1005,
114*b1906ceaSLachlan Hodges 	HOST_CMD_ID_SET_TXOP = 0x1008,
115*b1906ceaSLachlan Hodges 	HOST_CMD_ID_SET_CONTROL_RESPONSE = 0x1009,
116*b1906ceaSLachlan Hodges 	HOST_CMD_ID_SET_PERIODIC_CAL = 0x100A,
117*b1906ceaSLachlan Hodges 	HOST_CMD_ID_SET_BCN_RSSI_THRESHOLD = 0x100B,
118*b1906ceaSLachlan Hodges 	HOST_CMD_ID_SET_TX_PKT_LIFETIME_USECS = 0x100C,
119*b1906ceaSLachlan Hodges 	HOST_CMD_ID_SET_PHYSM_WATCHDOG = 0x100D,
120*b1906ceaSLachlan Hodges 	HOST_CMD_ID_TX_POLAR = 0x100E,
121*b1906ceaSLachlan Hodges 	HOST_CMD_ID_EVT_STA_STATE = 0x4001,
122*b1906ceaSLachlan Hodges 	HOST_CMD_ID_EVT_BEACON_LOSS = 0x4002,
123*b1906ceaSLachlan Hodges 	HOST_CMD_ID_EVT_SIG_FIELD_ERROR = 0x4003,
124*b1906ceaSLachlan Hodges 	HOST_CMD_ID_EVT_UMAC_TRAFFIC_CONTROL = 0x4004,
125*b1906ceaSLachlan Hodges 	HOST_CMD_ID_EVT_DHCP_LEASE_UPDATE = 0x4005,
126*b1906ceaSLachlan Hodges 	HOST_CMD_ID_EVT_OCS_DONE = 0x4006,
127*b1906ceaSLachlan Hodges 	HOST_CMD_ID_EVT_HW_SCAN_DONE = 0x4011,
128*b1906ceaSLachlan Hodges 	HOST_CMD_ID_EVT_CHANNEL_USAGE = 0x4012,
129*b1906ceaSLachlan Hodges 	HOST_CMD_ID_EVT_CONNECTION_LOSS = 0x4013,
130*b1906ceaSLachlan Hodges 	HOST_CMD_ID_EVT_SCHED_SCAN_RESULTS = 0x4014,
131*b1906ceaSLachlan Hodges 	HOST_CMD_ID_EVT_CQM_RSSI_NOTIFY = 0x4015,
132*b1906ceaSLachlan Hodges 	HOST_CMD_ID_EVT_SCAN_DONE = 0x4007,
133*b1906ceaSLachlan Hodges 	HOST_CMD_ID_EVT_SCAN_RESULT = 0x4008,
134*b1906ceaSLachlan Hodges 	HOST_CMD_ID_EVT_CONNECTED = 0x4009,
135*b1906ceaSLachlan Hodges 	HOST_CMD_ID_EVT_DISCONNECTED = 0x4010,
136*b1906ceaSLachlan Hodges 	HOST_CMD_ID_EVT_BEACON_FILTER_MATCH = 0x4016,
137*b1906ceaSLachlan Hodges 	HOST_CMD_ID_SET_CAPABILITIES = 0x8118,
138*b1906ceaSLachlan Hodges 	HOST_CMD_ID_SET_TRANSMISSION_RATE = 0x8009,
139*b1906ceaSLachlan Hodges 	HOST_CMD_ID_FORCE_ASSERT = 0x800E,
140*b1906ceaSLachlan Hodges 	HOST_CMD_ID_GET_SET_GENERIC_PARAM = 0x003E,
141*b1906ceaSLachlan Hodges };
142*b1906ceaSLachlan Hodges 
143*b1906ceaSLachlan Hodges struct host_cmd_mac_addr {
144*b1906ceaSLachlan Hodges 	u8 octet[HOST_CMD_MAC_ADDR_LEN];
145*b1906ceaSLachlan Hodges };
146*b1906ceaSLachlan Hodges 
147*b1906ceaSLachlan Hodges enum host_cmd_ocs_subcmd {
148*b1906ceaSLachlan Hodges 	HOST_CMD_OCS_SUBCMD_CONFIG = 1,
149*b1906ceaSLachlan Hodges 	HOST_CMD_OCS_SUBCMD_STATUS = 2,
150*b1906ceaSLachlan Hodges };
151*b1906ceaSLachlan Hodges 
152*b1906ceaSLachlan Hodges enum host_cmd_headless_cfg_option {
153*b1906ceaSLachlan Hodges 	HOST_CMD_HEADLESS_CFG_OPTION_KEEP_IFACES = BIT(0),
154*b1906ceaSLachlan Hodges 	HOST_CMD_HEADLESS_CFG_OPTION_BUFFER_RX = BIT(1),
155*b1906ceaSLachlan Hodges 	HOST_CMD_HEADLESS_CFG_OPTION_NOTIFY_ON_ANY_RX = BIT(2),
156*b1906ceaSLachlan Hodges };
157*b1906ceaSLachlan Hodges 
158*b1906ceaSLachlan Hodges struct host_cmd_header {
159*b1906ceaSLachlan Hodges 	__le16 flags;
160*b1906ceaSLachlan Hodges 	__le16 message_id;
161*b1906ceaSLachlan Hodges 	__le16 len;
162*b1906ceaSLachlan Hodges 	__le16 host_id;
163*b1906ceaSLachlan Hodges 	__le16 vif_id;
164*b1906ceaSLachlan Hodges 	__le16 pad;
165*b1906ceaSLachlan Hodges };
166*b1906ceaSLachlan Hodges 
167*b1906ceaSLachlan Hodges #define HOST_CMD_CHANNEL_BW_NOT_SET 0xFF
168*b1906ceaSLachlan Hodges #define HOST_CMD_CHANNEL_IDX_NOT_SET 0xFF
169*b1906ceaSLachlan Hodges #define HOST_CMD_CHANNEL_FREQ_NOT_SET 0xFFFFFFFF
170*b1906ceaSLachlan Hodges 
171*b1906ceaSLachlan Hodges enum host_cmd_dot11_proto_mode {
172*b1906ceaSLachlan Hodges 	HOST_CMD_DOT11_PROTO_MODE_AH = 0,
173*b1906ceaSLachlan Hodges };
174*b1906ceaSLachlan Hodges 
175*b1906ceaSLachlan Hodges struct host_cmd_req_set_channel {
176*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
177*b1906ceaSLachlan Hodges 	__le32 op_chan_freq_hz;
178*b1906ceaSLachlan Hodges 	u8 op_bw_mhz;
179*b1906ceaSLachlan Hodges 	u8 pri_bw_mhz;
180*b1906ceaSLachlan Hodges 	u8 pri_1mhz_chan_idx;
181*b1906ceaSLachlan Hodges 	u8 dot11_mode;
182*b1906ceaSLachlan Hodges 	u8 __deprecated_reg_tx_power_set;
183*b1906ceaSLachlan Hodges 	u8 is_off_channel;
184*b1906ceaSLachlan Hodges } __packed;
185*b1906ceaSLachlan Hodges 
186*b1906ceaSLachlan Hodges struct host_cmd_resp_set_channel {
187*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
188*b1906ceaSLachlan Hodges 	__le32 status;
189*b1906ceaSLachlan Hodges 	__sle32 power_qdbm;
190*b1906ceaSLachlan Hodges } __packed;
191*b1906ceaSLachlan Hodges 
192*b1906ceaSLachlan Hodges struct host_cmd_req_get_channel {
193*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
194*b1906ceaSLachlan Hodges } __packed;
195*b1906ceaSLachlan Hodges 
196*b1906ceaSLachlan Hodges struct host_cmd_resp_get_channel {
197*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
198*b1906ceaSLachlan Hodges 	__le32 status;
199*b1906ceaSLachlan Hodges 	__le32 op_chan_freq_hz;
200*b1906ceaSLachlan Hodges 	u8 op_chan_bw_mhz;
201*b1906ceaSLachlan Hodges 	u8 pri_chan_bw_mhz;
202*b1906ceaSLachlan Hodges 	u8 pri_1mhz_chan_idx;
203*b1906ceaSLachlan Hodges } __packed;
204*b1906ceaSLachlan Hodges 
205*b1906ceaSLachlan Hodges #define HOST_CMD_MAX_VERSION_LEN 128
206*b1906ceaSLachlan Hodges 
207*b1906ceaSLachlan Hodges struct host_cmd_req_get_version {
208*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
209*b1906ceaSLachlan Hodges } __packed;
210*b1906ceaSLachlan Hodges 
211*b1906ceaSLachlan Hodges struct host_cmd_resp_get_version {
212*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
213*b1906ceaSLachlan Hodges 	__le32 status;
214*b1906ceaSLachlan Hodges 	__sle32 length;
215*b1906ceaSLachlan Hodges 	u8 version[];
216*b1906ceaSLachlan Hodges } __packed;
217*b1906ceaSLachlan Hodges 
218*b1906ceaSLachlan Hodges struct host_cmd_req_set_txpower {
219*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
220*b1906ceaSLachlan Hodges 	__sle32 power_qdbm;
221*b1906ceaSLachlan Hodges } __packed;
222*b1906ceaSLachlan Hodges 
223*b1906ceaSLachlan Hodges struct host_cmd_resp_set_txpower {
224*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
225*b1906ceaSLachlan Hodges 	__le32 status;
226*b1906ceaSLachlan Hodges 	__sle32 power_qdbm;
227*b1906ceaSLachlan Hodges } __packed;
228*b1906ceaSLachlan Hodges 
229*b1906ceaSLachlan Hodges struct host_cmd_req_get_max_txpower {
230*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
231*b1906ceaSLachlan Hodges } __packed;
232*b1906ceaSLachlan Hodges 
233*b1906ceaSLachlan Hodges struct host_cmd_resp_get_max_txpower {
234*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
235*b1906ceaSLachlan Hodges 	__le32 status;
236*b1906ceaSLachlan Hodges 	__sle32 power_qdbm;
237*b1906ceaSLachlan Hodges } __packed;
238*b1906ceaSLachlan Hodges 
239*b1906ceaSLachlan Hodges enum host_cmd_interface_type {
240*b1906ceaSLachlan Hodges 	HOST_CMD_INTERFACE_TYPE_INVALID = 0,
241*b1906ceaSLachlan Hodges 	HOST_CMD_INTERFACE_TYPE_STA = 1,
242*b1906ceaSLachlan Hodges 	HOST_CMD_INTERFACE_TYPE_AP = 2,
243*b1906ceaSLachlan Hodges 	HOST_CMD_INTERFACE_TYPE_MON = 3,
244*b1906ceaSLachlan Hodges 	HOST_CMD_INTERFACE_TYPE_ADHOC = 4,
245*b1906ceaSLachlan Hodges 	HOST_CMD_INTERFACE_TYPE_MESH = 5,
246*b1906ceaSLachlan Hodges 	HOST_CMD_INTERFACE_TYPE_LAST = HOST_CMD_INTERFACE_TYPE_MESH,
247*b1906ceaSLachlan Hodges };
248*b1906ceaSLachlan Hodges 
249*b1906ceaSLachlan Hodges struct host_cmd_req_add_interface {
250*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
251*b1906ceaSLachlan Hodges 	struct host_cmd_mac_addr addr;
252*b1906ceaSLachlan Hodges 	__le32 interface_type;
253*b1906ceaSLachlan Hodges } __packed;
254*b1906ceaSLachlan Hodges 
255*b1906ceaSLachlan Hodges struct host_cmd_resp_add_interface {
256*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
257*b1906ceaSLachlan Hodges 	__le32 status;
258*b1906ceaSLachlan Hodges } __packed;
259*b1906ceaSLachlan Hodges 
260*b1906ceaSLachlan Hodges struct host_cmd_req_remove_interface {
261*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
262*b1906ceaSLachlan Hodges } __packed;
263*b1906ceaSLachlan Hodges 
264*b1906ceaSLachlan Hodges struct host_cmd_resp_remove_interface {
265*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
266*b1906ceaSLachlan Hodges 	__le32 status;
267*b1906ceaSLachlan Hodges } __packed;
268*b1906ceaSLachlan Hodges 
269*b1906ceaSLachlan Hodges struct host_cmd_req_bss_config {
270*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
271*b1906ceaSLachlan Hodges 	__le16 beacon_interval_tu;
272*b1906ceaSLachlan Hodges 	__le16 dtim_period;
273*b1906ceaSLachlan Hodges 	u8 __padding[2];
274*b1906ceaSLachlan Hodges 	__le32 cssid;
275*b1906ceaSLachlan Hodges } __packed;
276*b1906ceaSLachlan Hodges 
277*b1906ceaSLachlan Hodges struct host_cmd_resp_bss_config {
278*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
279*b1906ceaSLachlan Hodges 	__le32 status;
280*b1906ceaSLachlan Hodges } __packed;
281*b1906ceaSLachlan Hodges 
282*b1906ceaSLachlan Hodges struct host_cmd_req_scan_config {
283*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
284*b1906ceaSLachlan Hodges 	u8 enabled;
285*b1906ceaSLachlan Hodges 	u8 is_survey;
286*b1906ceaSLachlan Hodges } __packed;
287*b1906ceaSLachlan Hodges 
288*b1906ceaSLachlan Hodges struct host_cmd_resp_scan_config {
289*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
290*b1906ceaSLachlan Hodges 	__le32 status;
291*b1906ceaSLachlan Hodges } __packed;
292*b1906ceaSLachlan Hodges 
293*b1906ceaSLachlan Hodges struct host_cmd_req_set_qos_params {
294*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
295*b1906ceaSLachlan Hodges 	u8 uapsd;
296*b1906ceaSLachlan Hodges 	u8 queue_idx;
297*b1906ceaSLachlan Hodges 	u8 aifs_slot_count;
298*b1906ceaSLachlan Hodges 	__le16 contention_window_min;
299*b1906ceaSLachlan Hodges 	__le16 contention_window_max;
300*b1906ceaSLachlan Hodges 	__le32 max_txop_usec;
301*b1906ceaSLachlan Hodges } __packed;
302*b1906ceaSLachlan Hodges 
303*b1906ceaSLachlan Hodges struct host_cmd_resp_set_qos_params {
304*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
305*b1906ceaSLachlan Hodges 	__le32 status;
306*b1906ceaSLachlan Hodges } __packed;
307*b1906ceaSLachlan Hodges 
308*b1906ceaSLachlan Hodges struct host_cmd_req_get_qos_params {
309*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
310*b1906ceaSLachlan Hodges 	u8 queue_idx;
311*b1906ceaSLachlan Hodges } __packed;
312*b1906ceaSLachlan Hodges 
313*b1906ceaSLachlan Hodges struct host_cmd_resp_get_qos_params {
314*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
315*b1906ceaSLachlan Hodges 	__le32 status;
316*b1906ceaSLachlan Hodges 	u8 aifs_slot_count;
317*b1906ceaSLachlan Hodges 	__le16 contention_window_min;
318*b1906ceaSLachlan Hodges 	__le16 contention_window_max;
319*b1906ceaSLachlan Hodges 	__le32 max_txop_usec;
320*b1906ceaSLachlan Hodges } __packed;
321*b1906ceaSLachlan Hodges 
322*b1906ceaSLachlan Hodges struct host_cmd_req_set_sta_state {
323*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
324*b1906ceaSLachlan Hodges 	u8 sta_addr[HOST_CMD_MAC_ADDR_LEN];
325*b1906ceaSLachlan Hodges 	__le16 aid;
326*b1906ceaSLachlan Hodges 	__le16 state;
327*b1906ceaSLachlan Hodges 	u8 uapsd_queues;
328*b1906ceaSLachlan Hodges 	__le32 flags;
329*b1906ceaSLachlan Hodges } __packed;
330*b1906ceaSLachlan Hodges 
331*b1906ceaSLachlan Hodges struct host_cmd_resp_set_sta_state {
332*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
333*b1906ceaSLachlan Hodges 	__le32 status;
334*b1906ceaSLachlan Hodges } __packed;
335*b1906ceaSLachlan Hodges 
336*b1906ceaSLachlan Hodges struct host_cmd_req_set_bss_color {
337*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
338*b1906ceaSLachlan Hodges 	u8 bss_color;
339*b1906ceaSLachlan Hodges } __packed;
340*b1906ceaSLachlan Hodges 
341*b1906ceaSLachlan Hodges struct host_cmd_resp_set_bss_color {
342*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
343*b1906ceaSLachlan Hodges 	__le32 status;
344*b1906ceaSLachlan Hodges } __packed;
345*b1906ceaSLachlan Hodges 
346*b1906ceaSLachlan Hodges struct host_cmd_req_config_ps {
347*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
348*b1906ceaSLachlan Hodges 	u8 enabled;
349*b1906ceaSLachlan Hodges 	u8 dynamic_ps_offload;
350*b1906ceaSLachlan Hodges } __packed;
351*b1906ceaSLachlan Hodges 
352*b1906ceaSLachlan Hodges struct host_cmd_resp_config_ps {
353*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
354*b1906ceaSLachlan Hodges 	__le32 status;
355*b1906ceaSLachlan Hodges } __packed;
356*b1906ceaSLachlan Hodges 
357*b1906ceaSLachlan Hodges struct host_cmd_req_health_check {
358*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
359*b1906ceaSLachlan Hodges } __packed;
360*b1906ceaSLachlan Hodges 
361*b1906ceaSLachlan Hodges struct host_cmd_resp_health_check {
362*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
363*b1906ceaSLachlan Hodges 	__le32 status;
364*b1906ceaSLachlan Hodges } __packed;
365*b1906ceaSLachlan Hodges 
366*b1906ceaSLachlan Hodges struct host_cmd_req_cts_self_ps {
367*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
368*b1906ceaSLachlan Hodges 	u8 enable;
369*b1906ceaSLachlan Hodges } __packed;
370*b1906ceaSLachlan Hodges 
371*b1906ceaSLachlan Hodges struct host_cmd_resp_cts_self_ps {
372*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
373*b1906ceaSLachlan Hodges 	__le32 status;
374*b1906ceaSLachlan Hodges } __packed;
375*b1906ceaSLachlan Hodges 
376*b1906ceaSLachlan Hodges struct host_cmd_req_dtim_channel_enable {
377*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
378*b1906ceaSLachlan Hodges 	u8 enable;
379*b1906ceaSLachlan Hodges } __packed;
380*b1906ceaSLachlan Hodges 
381*b1906ceaSLachlan Hodges struct host_cmd_resp_dtim_channel_enable {
382*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
383*b1906ceaSLachlan Hodges 	__le32 status;
384*b1906ceaSLachlan Hodges } __packed;
385*b1906ceaSLachlan Hodges 
386*b1906ceaSLachlan Hodges #define HOST_CMD_ARP_OFFLOAD_MAX_IP_ADDRESSES 4
387*b1906ceaSLachlan Hodges 
388*b1906ceaSLachlan Hodges struct host_cmd_req_arp_offload {
389*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
390*b1906ceaSLachlan Hodges 	__be32 ip_table[HOST_CMD_ARP_OFFLOAD_MAX_IP_ADDRESSES];
391*b1906ceaSLachlan Hodges } __packed;
392*b1906ceaSLachlan Hodges 
393*b1906ceaSLachlan Hodges struct host_cmd_resp_arp_offload {
394*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
395*b1906ceaSLachlan Hodges 	__le32 status;
396*b1906ceaSLachlan Hodges } __packed;
397*b1906ceaSLachlan Hodges 
398*b1906ceaSLachlan Hodges struct host_cmd_req_set_long_sleep_config {
399*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
400*b1906ceaSLachlan Hodges 	u8 enabled;
401*b1906ceaSLachlan Hodges } __packed;
402*b1906ceaSLachlan Hodges 
403*b1906ceaSLachlan Hodges struct host_cmd_resp_set_long_sleep_config {
404*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
405*b1906ceaSLachlan Hodges 	__le32 status;
406*b1906ceaSLachlan Hodges } __packed;
407*b1906ceaSLachlan Hodges 
408*b1906ceaSLachlan Hodges #define HOST_CMD_DUTY_CYCLE_SET_CFG_DUTY_CYCLE BIT(0)
409*b1906ceaSLachlan Hodges #define HOST_CMD_DUTY_CYCLE_SET_CFG_OMIT_CONTROL_RESP BIT(1)
410*b1906ceaSLachlan Hodges #define HOST_CMD_DUTY_CYCLE_SET_CFG_EXT BIT(2)
411*b1906ceaSLachlan Hodges #define HOST_CMD_DUTY_CYCLE_SET_CFG_BURST_RECORD_UNIT BIT(3)
412*b1906ceaSLachlan Hodges 
413*b1906ceaSLachlan Hodges enum host_cmd_duty_cycle_mode {
414*b1906ceaSLachlan Hodges 	HOST_CMD_DUTY_CYCLE_MODE_SPREAD = 0,
415*b1906ceaSLachlan Hodges 	HOST_CMD_DUTY_CYCLE_MODE_BURST = 1,
416*b1906ceaSLachlan Hodges 	HOST_CMD_DUTY_CYCLE_MODE_LAST = HOST_CMD_DUTY_CYCLE_MODE_BURST,
417*b1906ceaSLachlan Hodges };
418*b1906ceaSLachlan Hodges 
419*b1906ceaSLachlan Hodges struct host_cmd_duty_cycle_configuration {
420*b1906ceaSLachlan Hodges 	u8 omit_control_responses;
421*b1906ceaSLachlan Hodges 	__le32 duty_cycle;
422*b1906ceaSLachlan Hodges } __packed;
423*b1906ceaSLachlan Hodges 
424*b1906ceaSLachlan Hodges struct host_cmd_duty_cycle_set_configuration_ext {
425*b1906ceaSLachlan Hodges 	__le32 burst_record_unit_us;
426*b1906ceaSLachlan Hodges 	u8 mode;
427*b1906ceaSLachlan Hodges } __packed;
428*b1906ceaSLachlan Hodges 
429*b1906ceaSLachlan Hodges struct host_cmd_duty_cycle_configuration_ext {
430*b1906ceaSLachlan Hodges 	__le32 airtime_remaining_us;
431*b1906ceaSLachlan Hodges 	__le32 burst_window_duration_us;
432*b1906ceaSLachlan Hodges 	struct host_cmd_duty_cycle_set_configuration_ext set;
433*b1906ceaSLachlan Hodges } __packed;
434*b1906ceaSLachlan Hodges 
435*b1906ceaSLachlan Hodges struct host_cmd_req_set_duty_cycle {
436*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
437*b1906ceaSLachlan Hodges 	struct host_cmd_duty_cycle_configuration config;
438*b1906ceaSLachlan Hodges 	u8 set_cfgs;
439*b1906ceaSLachlan Hodges 	struct host_cmd_duty_cycle_set_configuration_ext config_ext;
440*b1906ceaSLachlan Hodges } __packed;
441*b1906ceaSLachlan Hodges 
442*b1906ceaSLachlan Hodges struct host_cmd_resp_get_duty_cycle {
443*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
444*b1906ceaSLachlan Hodges 	__le32 status;
445*b1906ceaSLachlan Hodges 	struct host_cmd_duty_cycle_configuration config;
446*b1906ceaSLachlan Hodges 	struct host_cmd_duty_cycle_configuration_ext config_ext;
447*b1906ceaSLachlan Hodges } __packed;
448*b1906ceaSLachlan Hodges 
449*b1906ceaSLachlan Hodges #define HOST_CMD_SET_S1G_CAP_FLAGS BIT(0)
450*b1906ceaSLachlan Hodges #define HOST_CMD_SET_S1G_CAP_AMPDU_MSS BIT(1)
451*b1906ceaSLachlan Hodges #define HOST_CMD_SET_S1G_CAP_BEAM_STS BIT(2)
452*b1906ceaSLachlan Hodges #define HOST_CMD_SET_S1G_CAP_NUM_SOUND_DIMS BIT(3)
453*b1906ceaSLachlan Hodges #define HOST_CMD_SET_S1G_CAP_MAX_AMPDU_LEXP BIT(4)
454*b1906ceaSLachlan Hodges #define HOST_CMD_SET_MORSE_CAP_MMSS_OFFSET BIT(5)
455*b1906ceaSLachlan Hodges #define HOST_CMD_S1G_CAPABILITY_FLAGS_WIDTH 4
456*b1906ceaSLachlan Hodges 
457*b1906ceaSLachlan Hodges struct host_cmd_mm_capabilities {
458*b1906ceaSLachlan Hodges 	__le32 flags[HOST_CMD_S1G_CAPABILITY_FLAGS_WIDTH];
459*b1906ceaSLachlan Hodges 	u8 ampdu_mss;
460*b1906ceaSLachlan Hodges 	u8 beamformee_sts_capability;
461*b1906ceaSLachlan Hodges 	u8 number_sounding_dimensions;
462*b1906ceaSLachlan Hodges 	u8 maximum_ampdu_length_exponent;
463*b1906ceaSLachlan Hodges } __packed;
464*b1906ceaSLachlan Hodges 
465*b1906ceaSLachlan Hodges struct host_cmd_req_get_capabilities {
466*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
467*b1906ceaSLachlan Hodges } __packed;
468*b1906ceaSLachlan Hodges 
469*b1906ceaSLachlan Hodges struct host_cmd_resp_get_capabilities {
470*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
471*b1906ceaSLachlan Hodges 	__le32 status;
472*b1906ceaSLachlan Hodges 	struct host_cmd_mm_capabilities capabilities;
473*b1906ceaSLachlan Hodges 	u8 morse_mmss_offset;
474*b1906ceaSLachlan Hodges } __packed;
475*b1906ceaSLachlan Hodges 
476*b1906ceaSLachlan Hodges #define HOST_CMD_DOT11_TWT_AGREEMENT_MAX_LEN 20
477*b1906ceaSLachlan Hodges 
478*b1906ceaSLachlan Hodges struct host_cmd_req_twt_agreement_install {
479*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
480*b1906ceaSLachlan Hodges 	u8 flow_id;
481*b1906ceaSLachlan Hodges 	u8 agreement_len;
482*b1906ceaSLachlan Hodges 	u8 agreement[HOST_CMD_DOT11_TWT_AGREEMENT_MAX_LEN];
483*b1906ceaSLachlan Hodges } __packed;
484*b1906ceaSLachlan Hodges 
485*b1906ceaSLachlan Hodges struct host_cmd_resp_twt_agreement_install {
486*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
487*b1906ceaSLachlan Hodges 	__le32 status;
488*b1906ceaSLachlan Hodges } __packed;
489*b1906ceaSLachlan Hodges 
490*b1906ceaSLachlan Hodges struct host_cmd_req_twt_agreement_validate {
491*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
492*b1906ceaSLachlan Hodges 	u8 flow_id;
493*b1906ceaSLachlan Hodges 	u8 agreement_len;
494*b1906ceaSLachlan Hodges 	u8 agreement[HOST_CMD_DOT11_TWT_AGREEMENT_MAX_LEN];
495*b1906ceaSLachlan Hodges } __packed;
496*b1906ceaSLachlan Hodges 
497*b1906ceaSLachlan Hodges struct host_cmd_resp_twt_agreement_validate {
498*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
499*b1906ceaSLachlan Hodges 	__le32 status;
500*b1906ceaSLachlan Hodges } __packed;
501*b1906ceaSLachlan Hodges 
502*b1906ceaSLachlan Hodges struct host_cmd_req_twt_agreement_remove {
503*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
504*b1906ceaSLachlan Hodges 	u8 flow_id;
505*b1906ceaSLachlan Hodges } __packed;
506*b1906ceaSLachlan Hodges 
507*b1906ceaSLachlan Hodges struct host_cmd_req_get_tsf {
508*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
509*b1906ceaSLachlan Hodges } __packed;
510*b1906ceaSLachlan Hodges 
511*b1906ceaSLachlan Hodges struct host_cmd_resp_get_tsf {
512*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
513*b1906ceaSLachlan Hodges 	__le32 status;
514*b1906ceaSLachlan Hodges 	__le64 now_tsf;
515*b1906ceaSLachlan Hodges 	__le64 now_chip_ts;
516*b1906ceaSLachlan Hodges } __packed;
517*b1906ceaSLachlan Hodges 
518*b1906ceaSLachlan Hodges struct host_cmd_req_mac_addr {
519*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
520*b1906ceaSLachlan Hodges 	u8 write;
521*b1906ceaSLachlan Hodges 	u8 octet[HOST_CMD_MAC_ADDR_LEN];
522*b1906ceaSLachlan Hodges } __packed;
523*b1906ceaSLachlan Hodges 
524*b1906ceaSLachlan Hodges struct host_cmd_resp_mac_addr {
525*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
526*b1906ceaSLachlan Hodges 	__le32 status;
527*b1906ceaSLachlan Hodges 	u8 octet[HOST_CMD_MAC_ADDR_LEN];
528*b1906ceaSLachlan Hodges } __packed;
529*b1906ceaSLachlan Hodges 
530*b1906ceaSLachlan Hodges #define HOST_CMD_SET_MPSW_CFG_AIRTIME_BOUNDS BIT(0)
531*b1906ceaSLachlan Hodges #define HOST_CMD_SET_MPSW_CFG_PKT_SPC_WIN_LEN BIT(1)
532*b1906ceaSLachlan Hodges #define HOST_CMD_SET_MPSW_CFG_ENABLED BIT(2)
533*b1906ceaSLachlan Hodges 
534*b1906ceaSLachlan Hodges struct host_cmd_mpsw_configuration {
535*b1906ceaSLachlan Hodges 	__le32 airtime_max_us;
536*b1906ceaSLachlan Hodges 	__le32 airtime_min_us;
537*b1906ceaSLachlan Hodges 	__le32 packet_space_window_length_us;
538*b1906ceaSLachlan Hodges 	u8 enable;
539*b1906ceaSLachlan Hodges } __packed;
540*b1906ceaSLachlan Hodges 
541*b1906ceaSLachlan Hodges struct host_cmd_req_mpsw_config {
542*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
543*b1906ceaSLachlan Hodges 	struct host_cmd_mpsw_configuration config;
544*b1906ceaSLachlan Hodges 	u8 set_cfgs;
545*b1906ceaSLachlan Hodges } __packed;
546*b1906ceaSLachlan Hodges 
547*b1906ceaSLachlan Hodges struct host_cmd_resp_mpsw_config {
548*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
549*b1906ceaSLachlan Hodges 	__le32 status;
550*b1906ceaSLachlan Hodges 	struct host_cmd_mpsw_configuration config;
551*b1906ceaSLachlan Hodges } __packed;
552*b1906ceaSLachlan Hodges 
553*b1906ceaSLachlan Hodges #define HOST_CMD_MAX_KEY_LEN 32
554*b1906ceaSLachlan Hodges 
555*b1906ceaSLachlan Hodges enum host_cmd_key_cipher {
556*b1906ceaSLachlan Hodges 	HOST_CMD_KEY_CIPHER_INVALID = 0,
557*b1906ceaSLachlan Hodges 	HOST_CMD_KEY_CIPHER_AES_CCM = 1,
558*b1906ceaSLachlan Hodges 	HOST_CMD_KEY_CIPHER_AES_GCM = 2,
559*b1906ceaSLachlan Hodges 	HOST_CMD_KEY_CIPHER_AES_CMAC = 3,
560*b1906ceaSLachlan Hodges 	HOST_CMD_KEY_CIPHER_AES_GMAC = 4,
561*b1906ceaSLachlan Hodges 	HOST_CMD_KEY_CIPHER_LAST = HOST_CMD_KEY_CIPHER_AES_GMAC,
562*b1906ceaSLachlan Hodges };
563*b1906ceaSLachlan Hodges 
564*b1906ceaSLachlan Hodges enum host_cmd_aes_key_len {
565*b1906ceaSLachlan Hodges 	HOST_CMD_AES_KEY_LEN_INVALID = 0,
566*b1906ceaSLachlan Hodges 	HOST_CMD_AES_KEY_LEN_LENGTH_128 = 1,
567*b1906ceaSLachlan Hodges 	HOST_CMD_AES_KEY_LEN_LENGTH_256 = 2,
568*b1906ceaSLachlan Hodges 	HOST_CMD_AES_KEY_LEN_LENGTH_LAST = HOST_CMD_AES_KEY_LEN_LENGTH_256,
569*b1906ceaSLachlan Hodges };
570*b1906ceaSLachlan Hodges 
571*b1906ceaSLachlan Hodges enum host_cmd_temporal_key_type {
572*b1906ceaSLachlan Hodges 	HOST_CMD_TEMPORAL_KEY_TYPE_INVALID = 0,
573*b1906ceaSLachlan Hodges 	HOST_CMD_TEMPORAL_KEY_TYPE_GTK = 1,
574*b1906ceaSLachlan Hodges 	HOST_CMD_TEMPORAL_KEY_TYPE_PTK = 2,
575*b1906ceaSLachlan Hodges 	HOST_CMD_TEMPORAL_KEY_TYPE_IGTK = 3,
576*b1906ceaSLachlan Hodges 	HOST_CMD_TEMPORAL_KEY_TYPE_LAST = HOST_CMD_TEMPORAL_KEY_TYPE_IGTK,
577*b1906ceaSLachlan Hodges };
578*b1906ceaSLachlan Hodges 
579*b1906ceaSLachlan Hodges struct host_cmd_req_install_key {
580*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
581*b1906ceaSLachlan Hodges 	__le64 pn;
582*b1906ceaSLachlan Hodges 	__le32 aid;
583*b1906ceaSLachlan Hodges 	u8 key_idx;
584*b1906ceaSLachlan Hodges 	u8 cipher;
585*b1906ceaSLachlan Hodges 	u8 key_length;
586*b1906ceaSLachlan Hodges 	u8 key_type;
587*b1906ceaSLachlan Hodges 	u8 __padding[2];
588*b1906ceaSLachlan Hodges 	u8 key[HOST_CMD_MAX_KEY_LEN];
589*b1906ceaSLachlan Hodges } __packed;
590*b1906ceaSLachlan Hodges 
591*b1906ceaSLachlan Hodges struct host_cmd_resp_install_key {
592*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
593*b1906ceaSLachlan Hodges 	__le32 status;
594*b1906ceaSLachlan Hodges 	u8 key_idx;
595*b1906ceaSLachlan Hodges } __packed;
596*b1906ceaSLachlan Hodges 
597*b1906ceaSLachlan Hodges struct host_cmd_req_disable_key {
598*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
599*b1906ceaSLachlan Hodges 	__le32 key_type;
600*b1906ceaSLachlan Hodges 	__le32 aid;
601*b1906ceaSLachlan Hodges 	u8 key_idx;
602*b1906ceaSLachlan Hodges } __packed;
603*b1906ceaSLachlan Hodges 
604*b1906ceaSLachlan Hodges struct host_cmd_resp_disable_key {
605*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
606*b1906ceaSLachlan Hodges 	__le32 status;
607*b1906ceaSLachlan Hodges } __packed;
608*b1906ceaSLachlan Hodges 
609*b1906ceaSLachlan Hodges enum host_cmd_dhcp_opcode {
610*b1906ceaSLachlan Hodges 	HOST_CMD_DHCP_OPCODE_ENABLE = 0,
611*b1906ceaSLachlan Hodges 	HOST_CMD_DHCP_OPCODE_DO_DISCOVERY = 1,
612*b1906ceaSLachlan Hodges 	HOST_CMD_DHCP_OPCODE_GET_LEASE = 2,
613*b1906ceaSLachlan Hodges 	HOST_CMD_DHCP_OPCODE_CLEAR_LEASE = 3,
614*b1906ceaSLachlan Hodges 	HOST_CMD_DHCP_OPCODE_RENEW_LEASE = 4,
615*b1906ceaSLachlan Hodges 	HOST_CMD_DHCP_OPCODE_REBIND_LEASE = 5,
616*b1906ceaSLachlan Hodges 	HOST_CMD_DHCP_OPCODE_SEND_LEASE_UPDATE = 6,
617*b1906ceaSLachlan Hodges };
618*b1906ceaSLachlan Hodges 
619*b1906ceaSLachlan Hodges enum host_cmd_dhcp_retcode {
620*b1906ceaSLachlan Hodges 	HOST_CMD_DHCP_RETCODE_SUCCESS = 0,
621*b1906ceaSLachlan Hodges 	HOST_CMD_DHCP_RETCODE_NOT_ENABLED = 1,
622*b1906ceaSLachlan Hodges 	HOST_CMD_DHCP_RETCODE_ALREADY_ENABLED = 2,
623*b1906ceaSLachlan Hodges 	HOST_CMD_DHCP_RETCODE_NO_LEASE = 3,
624*b1906ceaSLachlan Hodges 	HOST_CMD_DHCP_RETCODE_HAVE_LEASE = 4,
625*b1906ceaSLachlan Hodges 	HOST_CMD_DHCP_RETCODE_BUSY = 5,
626*b1906ceaSLachlan Hodges 	HOST_CMD_DHCP_RETCODE_BAD_VIF = 6,
627*b1906ceaSLachlan Hodges };
628*b1906ceaSLachlan Hodges 
629*b1906ceaSLachlan Hodges struct host_cmd_req_dhcp_offload {
630*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
631*b1906ceaSLachlan Hodges 	__le32 opcode;
632*b1906ceaSLachlan Hodges } __packed;
633*b1906ceaSLachlan Hodges 
634*b1906ceaSLachlan Hodges struct host_cmd_resp_dhcp_offload {
635*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
636*b1906ceaSLachlan Hodges 	__le32 status;
637*b1906ceaSLachlan Hodges 	__le32 retcode;
638*b1906ceaSLachlan Hodges 	__le32 my_ip;
639*b1906ceaSLachlan Hodges 	__le32 netmask;
640*b1906ceaSLachlan Hodges 	__le32 router;
641*b1906ceaSLachlan Hodges 	__le32 dns;
642*b1906ceaSLachlan Hodges } __packed;
643*b1906ceaSLachlan Hodges 
644*b1906ceaSLachlan Hodges struct host_cmd_req_set_keep_alive_offload {
645*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
646*b1906ceaSLachlan Hodges 	__le16 bss_max_idle_period;
647*b1906ceaSLachlan Hodges 	u8 interpret_as_11ah;
648*b1906ceaSLachlan Hodges } __packed;
649*b1906ceaSLachlan Hodges 
650*b1906ceaSLachlan Hodges #define HOST_CMD_MAX_OUI_FILTERS 5
651*b1906ceaSLachlan Hodges #define HOST_CMD_OUI_SIZE 3
652*b1906ceaSLachlan Hodges #define HOST_CMD_MAX_OUI_FILTER_ARRAY_SIZE 15
653*b1906ceaSLachlan Hodges 
654*b1906ceaSLachlan Hodges struct host_cmd_req_update_oui_filter {
655*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
656*b1906ceaSLachlan Hodges 	u8 n_ouis;
657*b1906ceaSLachlan Hodges 	u8 ouis[HOST_CMD_MAX_OUI_FILTERS][HOST_CMD_OUI_SIZE];
658*b1906ceaSLachlan Hodges } __packed;
659*b1906ceaSLachlan Hodges 
660*b1906ceaSLachlan Hodges enum host_cmd_ibss_config_opcode {
661*b1906ceaSLachlan Hodges 	HOST_CMD_IBSS_CONFIG_OPCODE_CREATE = 0,
662*b1906ceaSLachlan Hodges 	HOST_CMD_IBSS_CONFIG_OPCODE_JOIN = 1,
663*b1906ceaSLachlan Hodges 	HOST_CMD_IBSS_CONFIG_OPCODE_STOP = 2,
664*b1906ceaSLachlan Hodges };
665*b1906ceaSLachlan Hodges 
666*b1906ceaSLachlan Hodges struct host_cmd_req_ibss_config {
667*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
668*b1906ceaSLachlan Hodges 	u8 ibss_bssid[HOST_CMD_MAC_ADDR_LEN];
669*b1906ceaSLachlan Hodges 	u8 ibss_cfg_opcode;
670*b1906ceaSLachlan Hodges 	u8 ibss_probe_filtering;
671*b1906ceaSLachlan Hodges } __packed;
672*b1906ceaSLachlan Hodges 
673*b1906ceaSLachlan Hodges enum host_cmd_ocs_type {
674*b1906ceaSLachlan Hodges 	HOST_CMD_OCS_TYPE_QNULL = 0,
675*b1906ceaSLachlan Hodges 	HOST_CMD_OCS_TYPE_RAW = 1,
676*b1906ceaSLachlan Hodges };
677*b1906ceaSLachlan Hodges 
678*b1906ceaSLachlan Hodges struct host_cmd_ocs_config_req {
679*b1906ceaSLachlan Hodges 	__le32 op_channel_freq_hz;
680*b1906ceaSLachlan Hodges 	u8 op_channel_bw_mhz;
681*b1906ceaSLachlan Hodges 	u8 pri_channel_bw_mhz;
682*b1906ceaSLachlan Hodges 	u8 pri_1mhz_channel_index;
683*b1906ceaSLachlan Hodges 	__le16 aid;
684*b1906ceaSLachlan Hodges 	u8 type;
685*b1906ceaSLachlan Hodges } __packed;
686*b1906ceaSLachlan Hodges 
687*b1906ceaSLachlan Hodges struct host_cmd_ocs_status_resp {
688*b1906ceaSLachlan Hodges 	u8 running;
689*b1906ceaSLachlan Hodges } __packed;
690*b1906ceaSLachlan Hodges 
691*b1906ceaSLachlan Hodges struct host_cmd_req_ocs {
692*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
693*b1906ceaSLachlan Hodges 	__le32 subcmd;
694*b1906ceaSLachlan Hodges 	union {
695*b1906ceaSLachlan Hodges 		u8 opaque[0];
696*b1906ceaSLachlan Hodges 		struct host_cmd_ocs_config_req config;
697*b1906ceaSLachlan Hodges 	};
698*b1906ceaSLachlan Hodges } __packed;
699*b1906ceaSLachlan Hodges 
700*b1906ceaSLachlan Hodges struct host_cmd_resp_ocs {
701*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
702*b1906ceaSLachlan Hodges 	__le32 status;
703*b1906ceaSLachlan Hodges 	__le32 subcmd;
704*b1906ceaSLachlan Hodges 	union {
705*b1906ceaSLachlan Hodges 		u8 opaque[0];
706*b1906ceaSLachlan Hodges 		struct host_cmd_ocs_status_resp ocs_status;
707*b1906ceaSLachlan Hodges 	};
708*b1906ceaSLachlan Hodges } __packed;
709*b1906ceaSLachlan Hodges 
710*b1906ceaSLachlan Hodges enum host_cmd_mesh_config_opcode {
711*b1906ceaSLachlan Hodges 	HOST_CMD_MESH_CONFIG_OPCODE_START = 0,
712*b1906ceaSLachlan Hodges 	HOST_CMD_MESH_CONFIG_OPCODE_STOP = 1,
713*b1906ceaSLachlan Hodges };
714*b1906ceaSLachlan Hodges 
715*b1906ceaSLachlan Hodges struct host_cmd_req_mesh_config {
716*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
717*b1906ceaSLachlan Hodges 	u8 mesh_cfg_opcode;
718*b1906ceaSLachlan Hodges 	u8 enable_beaconing;
719*b1906ceaSLachlan Hodges 	u8 mbca_config;
720*b1906ceaSLachlan Hodges 	u8 min_beacon_gap_ms;
721*b1906ceaSLachlan Hodges 	__le16 mbss_start_scan_duration_ms;
722*b1906ceaSLachlan Hodges 	__le16 tbtt_adj_timer_interval_ms;
723*b1906ceaSLachlan Hodges } __packed;
724*b1906ceaSLachlan Hodges 
725*b1906ceaSLachlan Hodges struct host_cmd_req_set_offset_tsf {
726*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
727*b1906ceaSLachlan Hodges 	__sle64 offset_tsf;
728*b1906ceaSLachlan Hodges } __packed;
729*b1906ceaSLachlan Hodges 
730*b1906ceaSLachlan Hodges struct host_cmd_req_get_channel_usage {
731*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
732*b1906ceaSLachlan Hodges } __packed;
733*b1906ceaSLachlan Hodges 
734*b1906ceaSLachlan Hodges struct host_cmd_resp_get_channel_usage {
735*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
736*b1906ceaSLachlan Hodges 	__le32 status;
737*b1906ceaSLachlan Hodges 	__le64 time_listen;
738*b1906ceaSLachlan Hodges 	__le64 busy_time;
739*b1906ceaSLachlan Hodges 	__le32 freq_hz;
740*b1906ceaSLachlan Hodges 	s8 noise;
741*b1906ceaSLachlan Hodges 	u8 bw_mhz;
742*b1906ceaSLachlan Hodges } __packed;
743*b1906ceaSLachlan Hodges 
744*b1906ceaSLachlan Hodges #define HOST_CMD_MAX_MCAST_FILTERS 12
745*b1906ceaSLachlan Hodges 
746*b1906ceaSLachlan Hodges struct host_cmd_req_mcast_filter {
747*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
748*b1906ceaSLachlan Hodges 	u8 count;
749*b1906ceaSLachlan Hodges 	__le32 hw_addr[];
750*b1906ceaSLachlan Hodges } __packed;
751*b1906ceaSLachlan Hodges 
752*b1906ceaSLachlan Hodges struct host_cmd_req_bss_beacon_config {
753*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
754*b1906ceaSLachlan Hodges 	u8 enable;
755*b1906ceaSLachlan Hodges } __packed;
756*b1906ceaSLachlan Hodges 
757*b1906ceaSLachlan Hodges struct host_cmd_resp_bss_beacon_config {
758*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
759*b1906ceaSLachlan Hodges 	__le32 status;
760*b1906ceaSLachlan Hodges 	__le16 interface_id;
761*b1906ceaSLachlan Hodges } __packed;
762*b1906ceaSLachlan Hodges 
763*b1906ceaSLachlan Hodges struct host_cmd_req_uapsd_config {
764*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
765*b1906ceaSLachlan Hodges 	u8 auto_trigger_enabled;
766*b1906ceaSLachlan Hodges 	__le32 auto_trigger_timeout;
767*b1906ceaSLachlan Hodges } __packed;
768*b1906ceaSLachlan Hodges 
769*b1906ceaSLachlan Hodges struct host_cmd_resp_uapsd_config {
770*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
771*b1906ceaSLachlan Hodges 	__le32 status;
772*b1906ceaSLachlan Hodges 	u8 auto_trigger_enabled;
773*b1906ceaSLachlan Hodges } __packed;
774*b1906ceaSLachlan Hodges 
775*b1906ceaSLachlan Hodges struct host_cmd_req_page_slicing_config {
776*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
777*b1906ceaSLachlan Hodges 	u8 enable;
778*b1906ceaSLachlan Hodges } __packed;
779*b1906ceaSLachlan Hodges 
780*b1906ceaSLachlan Hodges #define HOST_CMD_HW_SCAN_FLAGS_START BIT(0)
781*b1906ceaSLachlan Hodges #define HOST_CMD_HW_SCAN_FLAGS_ABORT BIT(1)
782*b1906ceaSLachlan Hodges #define HOST_CMD_HW_SCAN_FLAGS_SURVEY BIT(2)
783*b1906ceaSLachlan Hodges #define HOST_CMD_HW_SCAN_FLAGS_STORE BIT(3)
784*b1906ceaSLachlan Hodges #define HOST_CMD_HW_SCAN_FLAGS_1MHZ_PROBES BIT(4)
785*b1906ceaSLachlan Hodges #define HOST_CMD_HW_SCAN_FLAGS_SCHED_START BIT(5)
786*b1906ceaSLachlan Hodges #define HOST_CMD_HW_SCAN_FLAGS_SCHED_STOP BIT(6)
787*b1906ceaSLachlan Hodges #define HOST_CMD_HW_SCAN_FLAGS_PROBE_ON_DOZE_BEACON BIT(7)
788*b1906ceaSLachlan Hodges 
789*b1906ceaSLachlan Hodges enum host_cmd_hw_scan_tlv_tag {
790*b1906ceaSLachlan Hodges 	HOST_CMD_HW_SCAN_TLV_TAG_PAD = 0,
791*b1906ceaSLachlan Hodges 	HOST_CMD_HW_SCAN_TLV_TAG_PROBE_REQ = 1,
792*b1906ceaSLachlan Hodges 	HOST_CMD_HW_SCAN_TLV_TAG_CHAN_LIST = 2,
793*b1906ceaSLachlan Hodges 	HOST_CMD_HW_SCAN_TLV_TAG_POWER_LIST = 3,
794*b1906ceaSLachlan Hodges 	HOST_CMD_HW_SCAN_TLV_TAG_DWELL_ON_HOME = 4,
795*b1906ceaSLachlan Hodges 	HOST_CMD_HW_SCAN_TLV_TAG_SCHED = 5,
796*b1906ceaSLachlan Hodges 	HOST_CMD_HW_SCAN_TLV_TAG_FILTER = 6,
797*b1906ceaSLachlan Hodges 	HOST_CMD_HW_SCAN_TLV_TAG_SCHED_PARAMS = 7,
798*b1906ceaSLachlan Hodges };
799*b1906ceaSLachlan Hodges 
800*b1906ceaSLachlan Hodges struct host_cmd_hw_scan_tlv {
801*b1906ceaSLachlan Hodges 	__le16 tag;
802*b1906ceaSLachlan Hodges 	__le16 len;
803*b1906ceaSLachlan Hodges 	u8 value[];
804*b1906ceaSLachlan Hodges } __packed;
805*b1906ceaSLachlan Hodges 
806*b1906ceaSLachlan Hodges struct host_cmd_req_hw_scan {
807*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
808*b1906ceaSLachlan Hodges 	__le32 flags;
809*b1906ceaSLachlan Hodges 	__le32 dwell_time_ms;
810*b1906ceaSLachlan Hodges 	u8 variable[];
811*b1906ceaSLachlan Hodges } __packed;
812*b1906ceaSLachlan Hodges 
813*b1906ceaSLachlan Hodges #define HOST_CMD_WHITELIST_FLAGS_CLEAR BIT(0)
814*b1906ceaSLachlan Hodges 
815*b1906ceaSLachlan Hodges struct host_cmd_req_set_whitelist {
816*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
817*b1906ceaSLachlan Hodges 	u8 flags;
818*b1906ceaSLachlan Hodges 	u8 ip_protocol;
819*b1906ceaSLachlan Hodges 	__be16 llc_protocol;
820*b1906ceaSLachlan Hodges 	__be32 src_ip;
821*b1906ceaSLachlan Hodges 	__be32 dest_ip;
822*b1906ceaSLachlan Hodges 	__be32 netmask;
823*b1906ceaSLachlan Hodges 	__be16 src_port;
824*b1906ceaSLachlan Hodges 	__be16 dest_port;
825*b1906ceaSLachlan Hodges } __packed;
826*b1906ceaSLachlan Hodges 
827*b1906ceaSLachlan Hodges struct host_cmd_arp_periodic_params {
828*b1906ceaSLachlan Hodges 	__le32 refresh_period_s;
829*b1906ceaSLachlan Hodges 	__le32 destination_ip;
830*b1906ceaSLachlan Hodges 	u8 send_as_garp;
831*b1906ceaSLachlan Hodges } __packed;
832*b1906ceaSLachlan Hodges 
833*b1906ceaSLachlan Hodges struct host_cmd_req_arp_periodic_refresh {
834*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
835*b1906ceaSLachlan Hodges 	struct host_cmd_arp_periodic_params config;
836*b1906ceaSLachlan Hodges } __packed;
837*b1906ceaSLachlan Hodges 
838*b1906ceaSLachlan Hodges #define HOST_CMD_TCP_KEEPALIVE_SET_CFG_PERIOD BIT(0)
839*b1906ceaSLachlan Hodges #define HOST_CMD_TCP_KEEPALIVE_SET_CFG_RETRY_COUNT BIT(1)
840*b1906ceaSLachlan Hodges #define HOST_CMD_TCP_KEEPALIVE_SET_CFG_RETRY_INTERVAL BIT(2)
841*b1906ceaSLachlan Hodges #define HOST_CMD_TCP_KEEPALIVE_SET_CFG_SRC_IP_ADDR BIT(3)
842*b1906ceaSLachlan Hodges #define HOST_CMD_TCP_KEEPALIVE_SET_CFG_DEST_IP_ADDR BIT(4)
843*b1906ceaSLachlan Hodges #define HOST_CMD_TCP_KEEPALIVE_SET_CFG_SRC_PORT BIT(5)
844*b1906ceaSLachlan Hodges #define HOST_CMD_TCP_KEEPALIVE_SET_CFG_DEST_PORT BIT(6)
845*b1906ceaSLachlan Hodges 
846*b1906ceaSLachlan Hodges struct host_cmd_req_set_tcp_keepalive {
847*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
848*b1906ceaSLachlan Hodges 	u8 enabled;
849*b1906ceaSLachlan Hodges 	u8 retry_count;
850*b1906ceaSLachlan Hodges 	u8 retry_interval_s;
851*b1906ceaSLachlan Hodges 	u8 set_cfgs;
852*b1906ceaSLachlan Hodges 	__be32 src_ip;
853*b1906ceaSLachlan Hodges 	__be32 dest_ip;
854*b1906ceaSLachlan Hodges 	__be16 src_port;
855*b1906ceaSLachlan Hodges 	__be16 dest_port;
856*b1906ceaSLachlan Hodges 	__le16 period_s;
857*b1906ceaSLachlan Hodges } __packed;
858*b1906ceaSLachlan Hodges 
859*b1906ceaSLachlan Hodges enum host_cmd_power_mode {
860*b1906ceaSLachlan Hodges 	HOST_CMD_POWER_MODE_SNOOZE = 0,
861*b1906ceaSLachlan Hodges 	HOST_CMD_POWER_MODE_DEEP_SLEEP = 1,
862*b1906ceaSLachlan Hodges 	HOST_CMD_POWER_MODE_HIBERNATE = 2,
863*b1906ceaSLachlan Hodges };
864*b1906ceaSLachlan Hodges 
865*b1906ceaSLachlan Hodges struct host_cmd_req_force_power_mode {
866*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
867*b1906ceaSLachlan Hodges 	__le32 mode;
868*b1906ceaSLachlan Hodges } __packed;
869*b1906ceaSLachlan Hodges 
870*b1906ceaSLachlan Hodges struct host_cmd_req_li_sleep {
871*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
872*b1906ceaSLachlan Hodges 	__le32 listen_interval;
873*b1906ceaSLachlan Hodges } __packed;
874*b1906ceaSLachlan Hodges 
875*b1906ceaSLachlan Hodges struct host_cmd_disabled_channel_entry {
876*b1906ceaSLachlan Hodges 	__le16 freq_100khz;
877*b1906ceaSLachlan Hodges 	u8 bw_mhz;
878*b1906ceaSLachlan Hodges } __packed;
879*b1906ceaSLachlan Hodges 
880*b1906ceaSLachlan Hodges struct host_cmd_resp_get_disabled_channels {
881*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
882*b1906ceaSLachlan Hodges 	__le32 status;
883*b1906ceaSLachlan Hodges 	__le32 n_channels;
884*b1906ceaSLachlan Hodges 	struct host_cmd_disabled_channel_entry channels[];
885*b1906ceaSLachlan Hodges } __packed;
886*b1906ceaSLachlan Hodges 
887*b1906ceaSLachlan Hodges struct host_cmd_req_set_cqm_rssi {
888*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
889*b1906ceaSLachlan Hodges 	__sle32 threshold;
890*b1906ceaSLachlan Hodges 	__le32 hysteresis;
891*b1906ceaSLachlan Hodges } __packed;
892*b1906ceaSLachlan Hodges 
893*b1906ceaSLachlan Hodges struct host_cmd_req_get_apf_capabilities {
894*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
895*b1906ceaSLachlan Hodges } __packed;
896*b1906ceaSLachlan Hodges 
897*b1906ceaSLachlan Hodges struct host_cmd_resp_get_apf_capabilities {
898*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
899*b1906ceaSLachlan Hodges 	__le32 status;
900*b1906ceaSLachlan Hodges 	__le32 max_length;
901*b1906ceaSLachlan Hodges 	u8 version;
902*b1906ceaSLachlan Hodges } __packed;
903*b1906ceaSLachlan Hodges 
904*b1906ceaSLachlan Hodges struct host_cmd_req_read_write_apf {
905*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
906*b1906ceaSLachlan Hodges 	__le32 offset;
907*b1906ceaSLachlan Hodges 	__le16 program_length;
908*b1906ceaSLachlan Hodges 	u8 write;
909*b1906ceaSLachlan Hodges 	u8 program[];
910*b1906ceaSLachlan Hodges } __packed;
911*b1906ceaSLachlan Hodges 
912*b1906ceaSLachlan Hodges struct host_cmd_resp_read_write_apf {
913*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
914*b1906ceaSLachlan Hodges 	__le32 status;
915*b1906ceaSLachlan Hodges 	__le16 program_length;
916*b1906ceaSLachlan Hodges 	u8 program[];
917*b1906ceaSLachlan Hodges } __packed;
918*b1906ceaSLachlan Hodges 
919*b1906ceaSLachlan Hodges struct host_cmd_req_bssid_set {
920*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
921*b1906ceaSLachlan Hodges 	struct host_cmd_mac_addr bssid;
922*b1906ceaSLachlan Hodges } __packed;
923*b1906ceaSLachlan Hodges 
924*b1906ceaSLachlan Hodges #define HOST_CMD_BEACON_OFFLOAD_FLAGS_START BIT(0)
925*b1906ceaSLachlan Hodges #define HOST_CMD_BEACON_OFFLOAD_FLAGS_STOP BIT(1)
926*b1906ceaSLachlan Hodges #define HOST_CMD_BEACON_OFFLOAD_CSSID_LEN 4
927*b1906ceaSLachlan Hodges 
928*b1906ceaSLachlan Hodges enum host_cmd_beacon_offload_tlv_tag {
929*b1906ceaSLachlan Hodges 	HOST_CMD_BEACON_OFFLOAD_TLV_TAG_DTIM_CNT = 0,
930*b1906ceaSLachlan Hodges 	HOST_CMD_BEACON_OFFLOAD_TLV_TAG_FRAME_CTRL = 1,
931*b1906ceaSLachlan Hodges 	HOST_CMD_BEACON_OFFLOAD_TLV_TAG_CHANGE_SEQ = 2,
932*b1906ceaSLachlan Hodges 	HOST_CMD_BEACON_OFFLOAD_TLV_TAG_CSSID = 3,
933*b1906ceaSLachlan Hodges 	HOST_CMD_BEACON_OFFLOAD_TLV_TAG_IES = 4,
934*b1906ceaSLachlan Hodges 	HOST_CMD_BEACON_OFFLOAD_TLV_TAG_TX_INFO = 5,
935*b1906ceaSLachlan Hodges };
936*b1906ceaSLachlan Hodges 
937*b1906ceaSLachlan Hodges struct host_cmd_beacon_offload_tlv_hdr {
938*b1906ceaSLachlan Hodges 	__le16 tag;
939*b1906ceaSLachlan Hodges 	__le16 len;
940*b1906ceaSLachlan Hodges } __packed;
941*b1906ceaSLachlan Hodges 
942*b1906ceaSLachlan Hodges struct host_cmd_beacon_offload_tlv_generic {
943*b1906ceaSLachlan Hodges 	struct host_cmd_beacon_offload_tlv_hdr hdr;
944*b1906ceaSLachlan Hodges 	u8 value[];
945*b1906ceaSLachlan Hodges } __packed;
946*b1906ceaSLachlan Hodges 
947*b1906ceaSLachlan Hodges struct host_cmd_beacon_offload_tlv_dtim_cnt {
948*b1906ceaSLachlan Hodges 	struct host_cmd_beacon_offload_tlv_hdr hdr;
949*b1906ceaSLachlan Hodges 	__le16 dtim_cnt;
950*b1906ceaSLachlan Hodges } __packed;
951*b1906ceaSLachlan Hodges 
952*b1906ceaSLachlan Hodges struct host_cmd_beacon_offload_tlv_frame_ctrl {
953*b1906ceaSLachlan Hodges 	struct host_cmd_beacon_offload_tlv_hdr hdr;
954*b1906ceaSLachlan Hodges 	u8 frame_ctrl[2];
955*b1906ceaSLachlan Hodges } __packed;
956*b1906ceaSLachlan Hodges 
957*b1906ceaSLachlan Hodges struct host_cmd_beacon_offload_tlv_change_seq {
958*b1906ceaSLachlan Hodges 	struct host_cmd_beacon_offload_tlv_hdr hdr;
959*b1906ceaSLachlan Hodges 	__le16 change_seq;
960*b1906ceaSLachlan Hodges } __packed;
961*b1906ceaSLachlan Hodges 
962*b1906ceaSLachlan Hodges struct host_cmd_beacon_offload_tlv_tx_info {
963*b1906ceaSLachlan Hodges 	struct host_cmd_beacon_offload_tlv_hdr hdr;
964*b1906ceaSLachlan Hodges 	u8 bw_mhz;
965*b1906ceaSLachlan Hodges } __packed;
966*b1906ceaSLachlan Hodges 
967*b1906ceaSLachlan Hodges struct host_cmd_beacon_offload_tlv_cssid {
968*b1906ceaSLachlan Hodges 	struct host_cmd_beacon_offload_tlv_hdr hdr;
969*b1906ceaSLachlan Hodges 	u8 cssid[HOST_CMD_BEACON_OFFLOAD_CSSID_LEN];
970*b1906ceaSLachlan Hodges } __packed;
971*b1906ceaSLachlan Hodges 
972*b1906ceaSLachlan Hodges struct host_cmd_beacon_offload_tlv_ies {
973*b1906ceaSLachlan Hodges 	struct host_cmd_beacon_offload_tlv_hdr hdr;
974*b1906ceaSLachlan Hodges 	u8 buf[];
975*b1906ceaSLachlan Hodges } __packed;
976*b1906ceaSLachlan Hodges 
977*b1906ceaSLachlan Hodges struct host_cmd_req_beacon_offload {
978*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
979*b1906ceaSLachlan Hodges 	__le32 flags;
980*b1906ceaSLachlan Hodges 	u8 variable[];
981*b1906ceaSLachlan Hodges } __packed;
982*b1906ceaSLachlan Hodges 
983*b1906ceaSLachlan Hodges struct host_cmd_resp_beacon_offload {
984*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
985*b1906ceaSLachlan Hodges 	__le32 status;
986*b1906ceaSLachlan Hodges 	__le16 dtim_count;
987*b1906ceaSLachlan Hodges } __packed;
988*b1906ceaSLachlan Hodges 
989*b1906ceaSLachlan Hodges struct host_cmd_req_probe_response_offload {
990*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
991*b1906ceaSLachlan Hodges 	u8 enable;
992*b1906ceaSLachlan Hodges 	__le16 probe_resp_len;
993*b1906ceaSLachlan Hodges 	u8 probe_resp_buf[];
994*b1906ceaSLachlan Hodges } __packed;
995*b1906ceaSLachlan Hodges 
996*b1906ceaSLachlan Hodges struct host_cmd_resp_probe_response_offload {
997*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
998*b1906ceaSLachlan Hodges 	__le32 status;
999*b1906ceaSLachlan Hodges } __packed;
1000*b1906ceaSLachlan Hodges 
1001*b1906ceaSLachlan Hodges struct host_cmd_req_set_sta_type {
1002*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1003*b1906ceaSLachlan Hodges 	u8 sta_type;
1004*b1906ceaSLachlan Hodges } __packed;
1005*b1906ceaSLachlan Hodges 
1006*b1906ceaSLachlan Hodges struct host_cmd_req_set_enc_mode {
1007*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1008*b1906ceaSLachlan Hodges 	u8 enc_mode;
1009*b1906ceaSLachlan Hodges } __packed;
1010*b1906ceaSLachlan Hodges 
1011*b1906ceaSLachlan Hodges struct host_cmd_req_test_ba {
1012*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1013*b1906ceaSLachlan Hodges 	u8 addr[HOST_CMD_MAC_ADDR_LEN];
1014*b1906ceaSLachlan Hodges 	u8 start;
1015*b1906ceaSLachlan Hodges 	u8 tx;
1016*b1906ceaSLachlan Hodges 	__le32 tid;
1017*b1906ceaSLachlan Hodges } __packed;
1018*b1906ceaSLachlan Hodges 
1019*b1906ceaSLachlan Hodges struct host_cmd_req_set_listen_interval {
1020*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1021*b1906ceaSLachlan Hodges 	__le16 listen_interval;
1022*b1906ceaSLachlan Hodges } __packed;
1023*b1906ceaSLachlan Hodges 
1024*b1906ceaSLachlan Hodges struct host_cmd_req_set_ampdu {
1025*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1026*b1906ceaSLachlan Hodges 	u8 ampdu_enabled;
1027*b1906ceaSLachlan Hodges } __packed;
1028*b1906ceaSLachlan Hodges 
1029*b1906ceaSLachlan Hodges struct host_cmd_req_set_s1g_op_class {
1030*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1031*b1906ceaSLachlan Hodges 	u8 opclass;
1032*b1906ceaSLachlan Hodges 	u8 prim_opclass;
1033*b1906ceaSLachlan Hodges } __packed;
1034*b1906ceaSLachlan Hodges 
1035*b1906ceaSLachlan Hodges struct host_cmd_req_send_wake_action_frame {
1036*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1037*b1906ceaSLachlan Hodges 	u8 dest_addr[HOST_CMD_MAC_ADDR_LEN];
1038*b1906ceaSLachlan Hodges 	__le32 payload_size;
1039*b1906ceaSLachlan Hodges 	u8 payload[];
1040*b1906ceaSLachlan Hodges } __packed;
1041*b1906ceaSLachlan Hodges 
1042*b1906ceaSLachlan Hodges #define HOST_CMD_MAX_VENDOR_IE_LENGTH 255
1043*b1906ceaSLachlan Hodges #define HOST_CMD_VENDOR_IE_TYPE_FLAG_BEACON BIT(0)
1044*b1906ceaSLachlan Hodges #define HOST_CMD_VENDOR_IE_TYPE_FLAG_PROBE_REQ BIT(1)
1045*b1906ceaSLachlan Hodges #define HOST_CMD_VENDOR_IE_TYPE_FLAG_PROBE_RESP BIT(2)
1046*b1906ceaSLachlan Hodges #define HOST_CMD_VENDOR_IE_TYPE_FLAG_ASSOC_REQ BIT(3)
1047*b1906ceaSLachlan Hodges #define HOST_CMD_VENDOR_IE_TYPE_FLAG_ASSOC_RESP BIT(4)
1048*b1906ceaSLachlan Hodges 
1049*b1906ceaSLachlan Hodges enum host_cmd_vendor_ie_op {
1050*b1906ceaSLachlan Hodges 	HOST_CMD_VENDOR_IE_OP_ADD_ELEMENT = 0,
1051*b1906ceaSLachlan Hodges 	HOST_CMD_VENDOR_IE_OP_CLEAR_ELEMENTS = 1,
1052*b1906ceaSLachlan Hodges 	HOST_CMD_VENDOR_IE_OP_ADD_FILTER = 2,
1053*b1906ceaSLachlan Hodges 	HOST_CMD_VENDOR_IE_OP_CLEAR_FILTERS = 3,
1054*b1906ceaSLachlan Hodges 	HOST_CMD_VENDOR_IE_OP_INVALID = U16_MAX,
1055*b1906ceaSLachlan Hodges };
1056*b1906ceaSLachlan Hodges 
1057*b1906ceaSLachlan Hodges struct host_cmd_req_vendor_ie_config {
1058*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1059*b1906ceaSLachlan Hodges 	__le16 opcode;
1060*b1906ceaSLachlan Hodges 	__le16 mgmt_type_mask;
1061*b1906ceaSLachlan Hodges 	u8 data[HOST_CMD_MAX_VENDOR_IE_LENGTH];
1062*b1906ceaSLachlan Hodges } __packed;
1063*b1906ceaSLachlan Hodges 
1064*b1906ceaSLachlan Hodges struct host_cmd_resp_vendor_ie_config {
1065*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1066*b1906ceaSLachlan Hodges 	__le32 status;
1067*b1906ceaSLachlan Hodges } __packed;
1068*b1906ceaSLachlan Hodges 
1069*b1906ceaSLachlan Hodges enum host_cmd_twt_conf_op {
1070*b1906ceaSLachlan Hodges 	HOST_CMD_TWT_CONF_OP_CONFIGURE = 0,
1071*b1906ceaSLachlan Hodges 	HOST_CMD_TWT_CONF_OP_FORCE_INSTALL_AGREEMENT = 1,
1072*b1906ceaSLachlan Hodges 	HOST_CMD_TWT_CONF_OP_REMOVE_AGREEMENT = 2,
1073*b1906ceaSLachlan Hodges 	HOST_CMD_TWT_CONF_OP_CONFIGURE_EXPLICIT = 3,
1074*b1906ceaSLachlan Hodges };
1075*b1906ceaSLachlan Hodges 
1076*b1906ceaSLachlan Hodges struct host_cmd_explicit_twt_wake_interval {
1077*b1906ceaSLachlan Hodges 	__le16 wake_interval_mantissa;
1078*b1906ceaSLachlan Hodges 	u8 wake_interval_exponent;
1079*b1906ceaSLachlan Hodges 	u8 __padding[5];
1080*b1906ceaSLachlan Hodges } __packed;
1081*b1906ceaSLachlan Hodges 
1082*b1906ceaSLachlan Hodges union host_cmd_wake_interval {
1083*b1906ceaSLachlan Hodges 	__le64 wake_interval_us;
1084*b1906ceaSLachlan Hodges 	struct host_cmd_explicit_twt_wake_interval explicit_twt;
1085*b1906ceaSLachlan Hodges } __packed;
1086*b1906ceaSLachlan Hodges 
1087*b1906ceaSLachlan Hodges struct host_cmd_req_set_twt_conf {
1088*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1089*b1906ceaSLachlan Hodges 	u8 opcode;
1090*b1906ceaSLachlan Hodges 	u8 flow_id;
1091*b1906ceaSLachlan Hodges 	__le64 target_wake_time;
1092*b1906ceaSLachlan Hodges 	union host_cmd_wake_interval wake_interval;
1093*b1906ceaSLachlan Hodges 	__le32 wake_duration_us;
1094*b1906ceaSLachlan Hodges 	u8 twt_setup_command;
1095*b1906ceaSLachlan Hodges 	u8 __padding[3];
1096*b1906ceaSLachlan Hodges } __packed;
1097*b1906ceaSLachlan Hodges 
1098*b1906ceaSLachlan Hodges #define HOST_CMD_MAX_AVAILABLE_CHANNELS 255
1099*b1906ceaSLachlan Hodges 
1100*b1906ceaSLachlan Hodges struct host_cmd_channel_info {
1101*b1906ceaSLachlan Hodges 	__le32 frequency_khz;
1102*b1906ceaSLachlan Hodges 	u8 channel_5g;
1103*b1906ceaSLachlan Hodges 	u8 channel_s1g;
1104*b1906ceaSLachlan Hodges 	u8 bandwidth_mhz;
1105*b1906ceaSLachlan Hodges } __packed;
1106*b1906ceaSLachlan Hodges 
1107*b1906ceaSLachlan Hodges struct host_cmd_resp_get_available_channels {
1108*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1109*b1906ceaSLachlan Hodges 	__le32 status;
1110*b1906ceaSLachlan Hodges 	__le32 num_channels;
1111*b1906ceaSLachlan Hodges 	struct host_cmd_channel_info channels[HOST_CMD_MAX_AVAILABLE_CHANNELS];
1112*b1906ceaSLachlan Hodges } __packed;
1113*b1906ceaSLachlan Hodges 
1114*b1906ceaSLachlan Hodges #define HOST_CMD_S1G_CAP0_S1G_LONG BIT(0)
1115*b1906ceaSLachlan Hodges #define HOST_CMD_S1G_CAP0_SGI_1MHZ BIT(1)
1116*b1906ceaSLachlan Hodges #define HOST_CMD_S1G_CAP0_SGI_2MHZ BIT(2)
1117*b1906ceaSLachlan Hodges #define HOST_CMD_S1G_CAP0_SGI_4MHZ BIT(3)
1118*b1906ceaSLachlan Hodges #define HOST_CMD_S1G_CAP0_SGI_8MHZ BIT(4)
1119*b1906ceaSLachlan Hodges #define HOST_CMD_S1G_CAP0_SGI_16MHZ BIT(5)
1120*b1906ceaSLachlan Hodges 
1121*b1906ceaSLachlan Hodges struct host_cmd_req_set_ecsa_s1g_info {
1122*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1123*b1906ceaSLachlan Hodges 	__le32 operating_channel_freq_hz;
1124*b1906ceaSLachlan Hodges 	u8 opclass;
1125*b1906ceaSLachlan Hodges 	u8 primary_channel_bw_mhz;
1126*b1906ceaSLachlan Hodges 	u8 prim_1mhz_ch_idx;
1127*b1906ceaSLachlan Hodges 	u8 operating_channel_bw_mhz;
1128*b1906ceaSLachlan Hodges 	u8 prim_opclass;
1129*b1906ceaSLachlan Hodges 	u8 s1g_cap0;
1130*b1906ceaSLachlan Hodges 	u8 s1g_cap1;
1131*b1906ceaSLachlan Hodges 	u8 s1g_cap2;
1132*b1906ceaSLachlan Hodges 	u8 s1g_cap3;
1133*b1906ceaSLachlan Hodges } __packed;
1134*b1906ceaSLachlan Hodges 
1135*b1906ceaSLachlan Hodges struct host_cmd_resp_get_hw_version {
1136*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1137*b1906ceaSLachlan Hodges 	__le32 status;
1138*b1906ceaSLachlan Hodges 	u8 hw_version[64];
1139*b1906ceaSLachlan Hodges } __packed;
1140*b1906ceaSLachlan Hodges 
1141*b1906ceaSLachlan Hodges #define HOST_CMD_CAC_CFG_CHANGE_RULE_MAX 8
1142*b1906ceaSLachlan Hodges #define HOST_CMD_CAC_CFG_ARFS_MAX 99
1143*b1906ceaSLachlan Hodges #define HOST_CMD_CAC_CFG_CHANGE_MAX 99
1144*b1906ceaSLachlan Hodges #define HOST_CMD_CAC_CFG_CHANGE_STEP 5
1145*b1906ceaSLachlan Hodges 
1146*b1906ceaSLachlan Hodges enum host_cmd_cac_op {
1147*b1906ceaSLachlan Hodges 	HOST_CMD_CAC_OP_DISABLE = 0,
1148*b1906ceaSLachlan Hodges 	HOST_CMD_CAC_OP_ENABLE = 1,
1149*b1906ceaSLachlan Hodges 	HOST_CMD_CAC_OP_CFG_GET = 2,
1150*b1906ceaSLachlan Hodges 	HOST_CMD_CAC_OP_CFG_SET = 3,
1151*b1906ceaSLachlan Hodges };
1152*b1906ceaSLachlan Hodges 
1153*b1906ceaSLachlan Hodges struct host_cmd_cac_change_rule {
1154*b1906ceaSLachlan Hodges 	__le16 arfs;
1155*b1906ceaSLachlan Hodges 	__sle16 threshold_change;
1156*b1906ceaSLachlan Hodges } __packed;
1157*b1906ceaSLachlan Hodges 
1158*b1906ceaSLachlan Hodges struct host_cmd_req_cac {
1159*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1160*b1906ceaSLachlan Hodges 	u8 opcode;
1161*b1906ceaSLachlan Hodges 	u8 rule_tot;
1162*b1906ceaSLachlan Hodges 	struct host_cmd_cac_change_rule rule[HOST_CMD_CAC_CFG_CHANGE_RULE_MAX];
1163*b1906ceaSLachlan Hodges } __packed;
1164*b1906ceaSLachlan Hodges 
1165*b1906ceaSLachlan Hodges struct host_cmd_resp_cac {
1166*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1167*b1906ceaSLachlan Hodges 	__le32 status;
1168*b1906ceaSLachlan Hodges 	u8 rule_tot;
1169*b1906ceaSLachlan Hodges 	struct host_cmd_cac_change_rule rule[HOST_CMD_CAC_CFG_CHANGE_RULE_MAX];
1170*b1906ceaSLachlan Hodges } __packed;
1171*b1906ceaSLachlan Hodges 
1172*b1906ceaSLachlan Hodges struct host_cmd_ocs_driver_req {
1173*b1906ceaSLachlan Hodges 	__le32 op_channel_freq_hz;
1174*b1906ceaSLachlan Hodges 	u8 op_channel_bw_mhz;
1175*b1906ceaSLachlan Hodges 	u8 pri_channel_bw_mhz;
1176*b1906ceaSLachlan Hodges 	u8 pri_1mhz_channel_index;
1177*b1906ceaSLachlan Hodges } __packed;
1178*b1906ceaSLachlan Hodges 
1179*b1906ceaSLachlan Hodges struct host_cmd_ocs_driver_resp {
1180*b1906ceaSLachlan Hodges 	u8 running;
1181*b1906ceaSLachlan Hodges } __packed;
1182*b1906ceaSLachlan Hodges 
1183*b1906ceaSLachlan Hodges struct host_cmd_req_ocs_driver {
1184*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1185*b1906ceaSLachlan Hodges 	__le32 subcmd;
1186*b1906ceaSLachlan Hodges 	union {
1187*b1906ceaSLachlan Hodges 		u8 opaque[0];
1188*b1906ceaSLachlan Hodges 		struct host_cmd_ocs_driver_req config;
1189*b1906ceaSLachlan Hodges 	};
1190*b1906ceaSLachlan Hodges } __packed;
1191*b1906ceaSLachlan Hodges 
1192*b1906ceaSLachlan Hodges struct host_cmd_resp_ocs_driver {
1193*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1194*b1906ceaSLachlan Hodges 	__le32 status;
1195*b1906ceaSLachlan Hodges 	__le32 subcmd;
1196*b1906ceaSLachlan Hodges 	union {
1197*b1906ceaSLachlan Hodges 		u8 opaque[0];
1198*b1906ceaSLachlan Hodges 		struct host_cmd_ocs_driver_resp ocs_status;
1199*b1906ceaSLachlan Hodges 	};
1200*b1906ceaSLachlan Hodges } __packed;
1201*b1906ceaSLachlan Hodges 
1202*b1906ceaSLachlan Hodges #define HOST_CMD_IFNAMSIZ 16
1203*b1906ceaSLachlan Hodges 
1204*b1906ceaSLachlan Hodges struct host_cmd_req_mbssid {
1205*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1206*b1906ceaSLachlan Hodges 	u8 max_bssid_indicator;
1207*b1906ceaSLachlan Hodges 	s8 transmitter_iface[HOST_CMD_IFNAMSIZ];
1208*b1906ceaSLachlan Hodges } __packed;
1209*b1906ceaSLachlan Hodges 
1210*b1906ceaSLachlan Hodges #define HOST_CMD_MESH_ID_LEN_MAX 32
1211*b1906ceaSLachlan Hodges #define HOST_CMD_MESH_BEACONLESS_MODE_DISABLE 0
1212*b1906ceaSLachlan Hodges #define HOST_CMD_MESH_BEACONLESS_MODE_ENABLE 1
1213*b1906ceaSLachlan Hodges #define HOST_CMD_MESH_PEER_LINKS_MIN 0
1214*b1906ceaSLachlan Hodges #define HOST_CMD_MESH_PEER_LINKS_MAX 10
1215*b1906ceaSLachlan Hodges 
1216*b1906ceaSLachlan Hodges struct host_cmd_req_set_mesh_config {
1217*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1218*b1906ceaSLachlan Hodges 	u8 mesh_id_len;
1219*b1906ceaSLachlan Hodges 	u8 mesh_id[HOST_CMD_MESH_ID_LEN_MAX];
1220*b1906ceaSLachlan Hodges 	u8 mesh_beaconless_mode;
1221*b1906ceaSLachlan Hodges 	u8 max_plinks;
1222*b1906ceaSLachlan Hodges } __packed;
1223*b1906ceaSLachlan Hodges 
1224*b1906ceaSLachlan Hodges struct host_cmd_req_set_mcba_conf {
1225*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1226*b1906ceaSLachlan Hodges 	u8 mbca_config;
1227*b1906ceaSLachlan Hodges 	u8 beacon_timing_report_interval;
1228*b1906ceaSLachlan Hodges 	u8 min_beacon_gap_ms;
1229*b1906ceaSLachlan Hodges 	__le16 mbss_start_scan_duration_ms;
1230*b1906ceaSLachlan Hodges 	__le16 tbtt_adj_interval_ms;
1231*b1906ceaSLachlan Hodges } __packed;
1232*b1906ceaSLachlan Hodges 
1233*b1906ceaSLachlan Hodges struct host_cmd_req_dynamic_peering_config {
1234*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1235*b1906ceaSLachlan Hodges 	u8 enabled;
1236*b1906ceaSLachlan Hodges 	u8 rssi_margin;
1237*b1906ceaSLachlan Hodges 	__le32 blacklist_timeout;
1238*b1906ceaSLachlan Hodges } __packed;
1239*b1906ceaSLachlan Hodges 
1240*b1906ceaSLachlan Hodges #define HOST_CMD_CFG_RAW_FLAG_ENABLE BIT(0)
1241*b1906ceaSLachlan Hodges #define HOST_CMD_CFG_RAW_FLAG_DELETE BIT(1)
1242*b1906ceaSLachlan Hodges #define HOST_CMD_CFG_RAW_FLAG_UPDATE BIT(2)
1243*b1906ceaSLachlan Hodges #define HOST_CMD_CFG_RAW_FLAG_DYNAMIC BIT(3)
1244*b1906ceaSLachlan Hodges #define HOST_CMD_RAW_RESERVED_AID_DCS 2008
1245*b1906ceaSLachlan Hodges #define HOST_CMD_RAW_RESERVED_AID_DOWNLINK 2009
1246*b1906ceaSLachlan Hodges 
1247*b1906ceaSLachlan Hodges enum host_cmd_raw_tlv_tag {
1248*b1906ceaSLachlan Hodges 	HOST_CMD_RAW_TLV_TAG_SLOT_DEF = 0,
1249*b1906ceaSLachlan Hodges 	HOST_CMD_RAW_TLV_TAG_GROUP = 1,
1250*b1906ceaSLachlan Hodges 	HOST_CMD_RAW_TLV_TAG_START_TIME = 2,
1251*b1906ceaSLachlan Hodges 	HOST_CMD_RAW_TLV_TAG_PRAW = 3,
1252*b1906ceaSLachlan Hodges 	HOST_CMD_RAW_TLV_TAG_BCN_SPREAD = 4,
1253*b1906ceaSLachlan Hodges 	HOST_CMD_RAW_TLV_TAG_DYN_GLOBAL = 5,
1254*b1906ceaSLachlan Hodges 	HOST_CMD_RAW_TLV_TAG_DYN_CONFIG = 6,
1255*b1906ceaSLachlan Hodges 	HOST_CMD_RAW_TLV_TAG_LAST = 7,
1256*b1906ceaSLachlan Hodges };
1257*b1906ceaSLachlan Hodges 
1258*b1906ceaSLachlan Hodges struct host_cmd_raw_tlv_slot_def {
1259*b1906ceaSLachlan Hodges 	u8 tag;
1260*b1906ceaSLachlan Hodges 	__le32 raw_duration_us;
1261*b1906ceaSLachlan Hodges 	u8 num_slots;
1262*b1906ceaSLachlan Hodges 	u8 cross_slot_bleed;
1263*b1906ceaSLachlan Hodges } __packed;
1264*b1906ceaSLachlan Hodges 
1265*b1906ceaSLachlan Hodges struct host_cmd_raw_tlv_group {
1266*b1906ceaSLachlan Hodges 	u8 tag;
1267*b1906ceaSLachlan Hodges 	__le16 aid_start;
1268*b1906ceaSLachlan Hodges 	__le16 aid_end;
1269*b1906ceaSLachlan Hodges } __packed;
1270*b1906ceaSLachlan Hodges 
1271*b1906ceaSLachlan Hodges struct host_cmd_raw_tlv_start_time {
1272*b1906ceaSLachlan Hodges 	u8 tag;
1273*b1906ceaSLachlan Hodges 	__le32 start_time_us;
1274*b1906ceaSLachlan Hodges } __packed;
1275*b1906ceaSLachlan Hodges 
1276*b1906ceaSLachlan Hodges struct host_cmd_raw_tlv_praw {
1277*b1906ceaSLachlan Hodges 	u8 tag;
1278*b1906ceaSLachlan Hodges 	u8 periodicity;
1279*b1906ceaSLachlan Hodges 	u8 validity;
1280*b1906ceaSLachlan Hodges 	u8 start_offset;
1281*b1906ceaSLachlan Hodges 	u8 refresh_on_expiry;
1282*b1906ceaSLachlan Hodges } __packed;
1283*b1906ceaSLachlan Hodges 
1284*b1906ceaSLachlan Hodges struct host_cmd_raw_tlv_bcn_spread {
1285*b1906ceaSLachlan Hodges 	u8 tag;
1286*b1906ceaSLachlan Hodges 	__le16 max_spread;
1287*b1906ceaSLachlan Hodges 	__le16 nominal_sta_per_bcn;
1288*b1906ceaSLachlan Hodges } __packed;
1289*b1906ceaSLachlan Hodges 
1290*b1906ceaSLachlan Hodges struct host_cmd_raw_tlv_dyn_global {
1291*b1906ceaSLachlan Hodges 	u8 tag;
1292*b1906ceaSLachlan Hodges 	__le16 num_configs;
1293*b1906ceaSLachlan Hodges 	__le16 num_bcn_indexes;
1294*b1906ceaSLachlan Hodges } __packed;
1295*b1906ceaSLachlan Hodges 
1296*b1906ceaSLachlan Hodges struct host_cmd_raw_tlv_dyn_config {
1297*b1906ceaSLachlan Hodges 	u8 tag;
1298*b1906ceaSLachlan Hodges 	__le16 id;
1299*b1906ceaSLachlan Hodges 	__le16 index;
1300*b1906ceaSLachlan Hodges 	__le16 len;
1301*b1906ceaSLachlan Hodges 	u8 variable[];
1302*b1906ceaSLachlan Hodges } __packed;
1303*b1906ceaSLachlan Hodges 
1304*b1906ceaSLachlan Hodges union host_cmd_raw_tlvs {
1305*b1906ceaSLachlan Hodges 	u8 tag;
1306*b1906ceaSLachlan Hodges 	struct host_cmd_raw_tlv_slot_def slot_def;
1307*b1906ceaSLachlan Hodges 	struct host_cmd_raw_tlv_group group;
1308*b1906ceaSLachlan Hodges 	struct host_cmd_raw_tlv_start_time start_time;
1309*b1906ceaSLachlan Hodges 	struct host_cmd_raw_tlv_praw praw;
1310*b1906ceaSLachlan Hodges 	struct host_cmd_raw_tlv_bcn_spread bcn_spread;
1311*b1906ceaSLachlan Hodges 	struct host_cmd_raw_tlv_dyn_global dyn_global;
1312*b1906ceaSLachlan Hodges 	struct host_cmd_raw_tlv_dyn_config dyn_config;
1313*b1906ceaSLachlan Hodges } __packed;
1314*b1906ceaSLachlan Hodges 
1315*b1906ceaSLachlan Hodges struct host_cmd_req_config_raw {
1316*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1317*b1906ceaSLachlan Hodges 	__le32 flags;
1318*b1906ceaSLachlan Hodges 	__le16 id;
1319*b1906ceaSLachlan Hodges 	u8 variable[];
1320*b1906ceaSLachlan Hodges } __packed;
1321*b1906ceaSLachlan Hodges 
1322*b1906ceaSLachlan Hodges struct host_cmd_req_config_bss_stats {
1323*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1324*b1906ceaSLachlan Hodges 	u8 enable;
1325*b1906ceaSLachlan Hodges 	__le32 monitor_window_ms;
1326*b1906ceaSLachlan Hodges } __packed;
1327*b1906ceaSLachlan Hodges 
1328*b1906ceaSLachlan Hodges struct host_cmd_req_get_rssi {
1329*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1330*b1906ceaSLachlan Hodges } __packed;
1331*b1906ceaSLachlan Hodges 
1332*b1906ceaSLachlan Hodges struct host_cmd_resp_get_rssi {
1333*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1334*b1906ceaSLachlan Hodges 	__le32 status;
1335*b1906ceaSLachlan Hodges 	__sle32 rssi0;
1336*b1906ceaSLachlan Hodges 	__sle32 rssi1;
1337*b1906ceaSLachlan Hodges 	__sle32 rssi2;
1338*b1906ceaSLachlan Hodges 	__sle32 rssi3;
1339*b1906ceaSLachlan Hodges 	__sle32 rssi4;
1340*b1906ceaSLachlan Hodges 	__sle32 rssi5;
1341*b1906ceaSLachlan Hodges 	__sle32 rssi6;
1342*b1906ceaSLachlan Hodges 	__sle32 rssi7;
1343*b1906ceaSLachlan Hodges } __packed;
1344*b1906ceaSLachlan Hodges 
1345*b1906ceaSLachlan Hodges #define HOST_CMD_SET_IFS_MIN_USECS 160
1346*b1906ceaSLachlan Hodges 
1347*b1906ceaSLachlan Hodges struct host_cmd_req_set_ifs {
1348*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1349*b1906ceaSLachlan Hodges 	__le32 period_usecs;
1350*b1906ceaSLachlan Hodges } __packed;
1351*b1906ceaSLachlan Hodges 
1352*b1906ceaSLachlan Hodges struct host_cmd_resp_set_ifs {
1353*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1354*b1906ceaSLachlan Hodges 	__le32 status;
1355*b1906ceaSLachlan Hodges } __packed;
1356*b1906ceaSLachlan Hodges 
1357*b1906ceaSLachlan Hodges struct host_cmd_req_set_fem_settings {
1358*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1359*b1906ceaSLachlan Hodges 	__le32 tx_antenna;
1360*b1906ceaSLachlan Hodges 	__le32 rx_antenna;
1361*b1906ceaSLachlan Hodges 	__le32 lna_enabled;
1362*b1906ceaSLachlan Hodges 	__le32 pa_enabled;
1363*b1906ceaSLachlan Hodges } __packed;
1364*b1906ceaSLachlan Hodges 
1365*b1906ceaSLachlan Hodges struct host_cmd_resp_set_fem_settings {
1366*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1367*b1906ceaSLachlan Hodges 	__le32 status;
1368*b1906ceaSLachlan Hodges } __packed;
1369*b1906ceaSLachlan Hodges 
1370*b1906ceaSLachlan Hodges struct host_cmd_req_set_txop {
1371*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1372*b1906ceaSLachlan Hodges 	u8 min_packet_count;
1373*b1906ceaSLachlan Hodges } __packed;
1374*b1906ceaSLachlan Hodges 
1375*b1906ceaSLachlan Hodges struct host_cmd_resp_set_txop {
1376*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1377*b1906ceaSLachlan Hodges 	__le32 status;
1378*b1906ceaSLachlan Hodges } __packed;
1379*b1906ceaSLachlan Hodges 
1380*b1906ceaSLachlan Hodges struct host_cmd_req_set_control_response {
1381*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1382*b1906ceaSLachlan Hodges 	u8 direction;
1383*b1906ceaSLachlan Hodges 	u8 control_response_1mhz_en;
1384*b1906ceaSLachlan Hodges } __packed;
1385*b1906ceaSLachlan Hodges 
1386*b1906ceaSLachlan Hodges struct host_cmd_resp_set_control_response {
1387*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1388*b1906ceaSLachlan Hodges 	__le32 status;
1389*b1906ceaSLachlan Hodges } __packed;
1390*b1906ceaSLachlan Hodges 
1391*b1906ceaSLachlan Hodges struct host_cmd_req_set_periodic_cal {
1392*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1393*b1906ceaSLachlan Hodges 	__le32 periodic_cal_en_mask;
1394*b1906ceaSLachlan Hodges } __packed;
1395*b1906ceaSLachlan Hodges 
1396*b1906ceaSLachlan Hodges struct host_cmd_resp_set_periodic_cal {
1397*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1398*b1906ceaSLachlan Hodges 	__le32 status;
1399*b1906ceaSLachlan Hodges } __packed;
1400*b1906ceaSLachlan Hodges 
1401*b1906ceaSLachlan Hodges struct host_cmd_req_set_bcn_rssi_threshold {
1402*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1403*b1906ceaSLachlan Hodges 	u8 threshold_db;
1404*b1906ceaSLachlan Hodges } __packed;
1405*b1906ceaSLachlan Hodges 
1406*b1906ceaSLachlan Hodges struct host_cmd_resp_set_bcn_rssi_threshold {
1407*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1408*b1906ceaSLachlan Hodges 	__le32 status;
1409*b1906ceaSLachlan Hodges } __packed;
1410*b1906ceaSLachlan Hodges 
1411*b1906ceaSLachlan Hodges struct host_cmd_req_set_tx_pkt_lifetime_usecs {
1412*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1413*b1906ceaSLachlan Hodges 	__le32 lifetime_usecs;
1414*b1906ceaSLachlan Hodges } __packed;
1415*b1906ceaSLachlan Hodges 
1416*b1906ceaSLachlan Hodges struct host_cmd_resp_set_tx_pkt_lifetime_usecs {
1417*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1418*b1906ceaSLachlan Hodges 	__le32 status;
1419*b1906ceaSLachlan Hodges } __packed;
1420*b1906ceaSLachlan Hodges 
1421*b1906ceaSLachlan Hodges struct host_cmd_req_set_physm_watchdog {
1422*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1423*b1906ceaSLachlan Hodges 	u8 physm_watchdog_en;
1424*b1906ceaSLachlan Hodges } __packed;
1425*b1906ceaSLachlan Hodges 
1426*b1906ceaSLachlan Hodges struct host_cmd_req_tx_polar {
1427*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1428*b1906ceaSLachlan Hodges 	u8 enable;
1429*b1906ceaSLachlan Hodges } __packed;
1430*b1906ceaSLachlan Hodges 
1431*b1906ceaSLachlan Hodges struct host_cmd_evt_sta_state {
1432*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1433*b1906ceaSLachlan Hodges 	u8 sta_addr[HOST_CMD_MAC_ADDR_LEN];
1434*b1906ceaSLachlan Hodges 	__le16 aid;
1435*b1906ceaSLachlan Hodges 	__le16 state;
1436*b1906ceaSLachlan Hodges } __packed;
1437*b1906ceaSLachlan Hodges 
1438*b1906ceaSLachlan Hodges struct host_cmd_evt_beacon_loss {
1439*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1440*b1906ceaSLachlan Hodges 	__le32 num_bcns;
1441*b1906ceaSLachlan Hodges } __packed;
1442*b1906ceaSLachlan Hodges 
1443*b1906ceaSLachlan Hodges struct host_cmd_evt_sig_field_error {
1444*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1445*b1906ceaSLachlan Hodges 	__le64 start_timestamp;
1446*b1906ceaSLachlan Hodges 	__le64 end_timestamp;
1447*b1906ceaSLachlan Hodges } __packed;
1448*b1906ceaSLachlan Hodges 
1449*b1906ceaSLachlan Hodges #define HOST_CMD_UMAC_TRAFFIC_CONTROL_SOURCE_TWT BIT(0)
1450*b1906ceaSLachlan Hodges #define HOST_CMD_UMAC_TRAFFIC_CONTROL_SOURCE_DUTY_CYCLE BIT(1)
1451*b1906ceaSLachlan Hodges 
1452*b1906ceaSLachlan Hodges struct host_cmd_evt_umac_traffic_control {
1453*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1454*b1906ceaSLachlan Hodges 	u8 pause_data_traffic;
1455*b1906ceaSLachlan Hodges 	__le32 sources;
1456*b1906ceaSLachlan Hodges } __packed;
1457*b1906ceaSLachlan Hodges 
1458*b1906ceaSLachlan Hodges struct host_cmd_evt_dhcp_lease_update {
1459*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1460*b1906ceaSLachlan Hodges 	__le32 my_ip;
1461*b1906ceaSLachlan Hodges 	__le32 netmask;
1462*b1906ceaSLachlan Hodges 	__le32 router;
1463*b1906ceaSLachlan Hodges 	__le32 dns;
1464*b1906ceaSLachlan Hodges } __packed;
1465*b1906ceaSLachlan Hodges 
1466*b1906ceaSLachlan Hodges struct host_cmd_evt_ocs_done {
1467*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1468*b1906ceaSLachlan Hodges 	__le64 time_listen;
1469*b1906ceaSLachlan Hodges 	__le64 time_rx;
1470*b1906ceaSLachlan Hodges 	s8 noise;
1471*b1906ceaSLachlan Hodges 	u8 metric;
1472*b1906ceaSLachlan Hodges } __packed;
1473*b1906ceaSLachlan Hodges 
1474*b1906ceaSLachlan Hodges struct host_cmd_evt_hw_scan_done {
1475*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1476*b1906ceaSLachlan Hodges 	u8 aborted;
1477*b1906ceaSLachlan Hodges } __packed;
1478*b1906ceaSLachlan Hodges 
1479*b1906ceaSLachlan Hodges struct host_cmd_evt_channel_usage {
1480*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1481*b1906ceaSLachlan Hodges 	__le64 time_listen;
1482*b1906ceaSLachlan Hodges 	__le64 busy_time;
1483*b1906ceaSLachlan Hodges 	__le32 freq_hz;
1484*b1906ceaSLachlan Hodges 	u8 noise;
1485*b1906ceaSLachlan Hodges 	u8 bw_mhz;
1486*b1906ceaSLachlan Hodges } __packed;
1487*b1906ceaSLachlan Hodges 
1488*b1906ceaSLachlan Hodges enum host_cmd_connection_loss_reason {
1489*b1906ceaSLachlan Hodges 	HOST_CMD_CONNECTION_LOSS_REASON_TSF_RESET = 0,
1490*b1906ceaSLachlan Hodges };
1491*b1906ceaSLachlan Hodges 
1492*b1906ceaSLachlan Hodges struct host_cmd_evt_connection_loss {
1493*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1494*b1906ceaSLachlan Hodges 	__le32 reason;
1495*b1906ceaSLachlan Hodges } __packed;
1496*b1906ceaSLachlan Hodges 
1497*b1906ceaSLachlan Hodges struct host_cmd_evt_sched_scan_results {
1498*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1499*b1906ceaSLachlan Hodges } __packed;
1500*b1906ceaSLachlan Hodges 
1501*b1906ceaSLachlan Hodges enum host_cmd_cqm_rssi_threshold_event {
1502*b1906ceaSLachlan Hodges 	HOST_CMD_CQM_RSSI_THRESHOLD_EVENT_LOW = 0,
1503*b1906ceaSLachlan Hodges 	HOST_CMD_CQM_RSSI_THRESHOLD_EVENT_HIGH = 1,
1504*b1906ceaSLachlan Hodges };
1505*b1906ceaSLachlan Hodges 
1506*b1906ceaSLachlan Hodges struct host_cmd_evt_cqm_rssi_notify {
1507*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1508*b1906ceaSLachlan Hodges 	__sle16 rssi;
1509*b1906ceaSLachlan Hodges 	__le16 event;
1510*b1906ceaSLachlan Hodges } __packed;
1511*b1906ceaSLachlan Hodges 
1512*b1906ceaSLachlan Hodges struct host_cmd_evt_scan_done {
1513*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1514*b1906ceaSLachlan Hodges 	u8 aborted;
1515*b1906ceaSLachlan Hodges } __packed;
1516*b1906ceaSLachlan Hodges 
1517*b1906ceaSLachlan Hodges enum host_cmd_scan_result_frame {
1518*b1906ceaSLachlan Hodges 	HOST_CMD_SCAN_RESULT_FRAME_UNKNOWN = 0,
1519*b1906ceaSLachlan Hodges 	HOST_CMD_SCAN_RESULT_FRAME_BEACON = 1,
1520*b1906ceaSLachlan Hodges 	HOST_CMD_SCAN_RESULT_FRAME_PROBE_RESPONSE = 2,
1521*b1906ceaSLachlan Hodges };
1522*b1906ceaSLachlan Hodges 
1523*b1906ceaSLachlan Hodges struct host_cmd_evt_scan_result {
1524*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1525*b1906ceaSLachlan Hodges 	__le32 channel_freq_hz;
1526*b1906ceaSLachlan Hodges 	u8 bw_mhz;
1527*b1906ceaSLachlan Hodges 	u8 frame_type;
1528*b1906ceaSLachlan Hodges 	__sle16 rssi;
1529*b1906ceaSLachlan Hodges 	u8 bssid[HOST_CMD_MAC_ADDR_LEN];
1530*b1906ceaSLachlan Hodges 	__le16 beacon_interval;
1531*b1906ceaSLachlan Hodges 	__le16 capability_info;
1532*b1906ceaSLachlan Hodges 	__le64 tsf;
1533*b1906ceaSLachlan Hodges 	__le16 ies_len;
1534*b1906ceaSLachlan Hodges 	u8 ies[];
1535*b1906ceaSLachlan Hodges } __packed;
1536*b1906ceaSLachlan Hodges 
1537*b1906ceaSLachlan Hodges struct host_cmd_evt_connected {
1538*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1539*b1906ceaSLachlan Hodges 	u8 bssid[HOST_CMD_MAC_ADDR_LEN];
1540*b1906ceaSLachlan Hodges 	__sle16 rssi;
1541*b1906ceaSLachlan Hodges 	u8 padding_0[8];
1542*b1906ceaSLachlan Hodges 	__le16 assoc_resp_ies_len;
1543*b1906ceaSLachlan Hodges 	u8 assoc_resp_ies[];
1544*b1906ceaSLachlan Hodges } __packed;
1545*b1906ceaSLachlan Hodges 
1546*b1906ceaSLachlan Hodges struct host_cmd_evt_beacon_filter_match {
1547*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1548*b1906ceaSLachlan Hodges 	u8 padding_0[4];
1549*b1906ceaSLachlan Hodges 	__le32 ies_len;
1550*b1906ceaSLachlan Hodges 	u8 ies[];
1551*b1906ceaSLachlan Hodges } __packed;
1552*b1906ceaSLachlan Hodges 
1553*b1906ceaSLachlan Hodges struct host_cmd_req_set_capabilities {
1554*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1555*b1906ceaSLachlan Hodges 	struct host_cmd_mm_capabilities capabilities;
1556*b1906ceaSLachlan Hodges 	u8 set_caps;
1557*b1906ceaSLachlan Hodges 	u8 morse_mmss_offset;
1558*b1906ceaSLachlan Hodges } __packed;
1559*b1906ceaSLachlan Hodges 
1560*b1906ceaSLachlan Hodges struct host_cmd_resp_set_capabilities {
1561*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1562*b1906ceaSLachlan Hodges 	__le32 status;
1563*b1906ceaSLachlan Hodges } __packed;
1564*b1906ceaSLachlan Hodges 
1565*b1906ceaSLachlan Hodges struct host_cmd_req_set_transmission_rate {
1566*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1567*b1906ceaSLachlan Hodges 	__sle32 mcs_index;
1568*b1906ceaSLachlan Hodges 	__sle32 bandwidth_mhz;
1569*b1906ceaSLachlan Hodges 	__sle32 tx_80211ah_format;
1570*b1906ceaSLachlan Hodges 	s8 use_traveling_pilots;
1571*b1906ceaSLachlan Hodges 	s8 use_sgi;
1572*b1906ceaSLachlan Hodges 	u8 enabled;
1573*b1906ceaSLachlan Hodges 	s8 nss_idx;
1574*b1906ceaSLachlan Hodges 	s8 use_ldpc;
1575*b1906ceaSLachlan Hodges 	s8 use_stbc;
1576*b1906ceaSLachlan Hodges } __packed;
1577*b1906ceaSLachlan Hodges 
1578*b1906ceaSLachlan Hodges struct host_cmd_resp_set_transmission_rate {
1579*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1580*b1906ceaSLachlan Hodges 	__le32 status;
1581*b1906ceaSLachlan Hodges } __packed;
1582*b1906ceaSLachlan Hodges 
1583*b1906ceaSLachlan Hodges enum host_cmd_hart_id {
1584*b1906ceaSLachlan Hodges 	HOST_CMD_HART_ID_HOST = 0,
1585*b1906ceaSLachlan Hodges 	HOST_CMD_HART_ID_MAC = 1,
1586*b1906ceaSLachlan Hodges 	HOST_CMD_HART_ID_UPHY = 2,
1587*b1906ceaSLachlan Hodges 	HOST_CMD_HART_ID_LPHY = 3,
1588*b1906ceaSLachlan Hodges };
1589*b1906ceaSLachlan Hodges 
1590*b1906ceaSLachlan Hodges struct host_cmd_req_force_assert {
1591*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1592*b1906ceaSLachlan Hodges 	__le32 hart_id;
1593*b1906ceaSLachlan Hodges } __packed;
1594*b1906ceaSLachlan Hodges 
1595*b1906ceaSLachlan Hodges #define HOST_CMD_HOST_BLOCK_TX_FRAMES BIT(0)
1596*b1906ceaSLachlan Hodges #define HOST_CMD_HOST_BLOCK_TX_CMD BIT(1)
1597*b1906ceaSLachlan Hodges 
1598*b1906ceaSLachlan Hodges enum host_cmd_param_action {
1599*b1906ceaSLachlan Hodges 	HOST_CMD_PARAM_ACTION_SET = 0,
1600*b1906ceaSLachlan Hodges 	HOST_CMD_PARAM_ACTION_GET = 1,
1601*b1906ceaSLachlan Hodges 	HOST_CMD_PARAM_ACTION_LAST = 2,
1602*b1906ceaSLachlan Hodges };
1603*b1906ceaSLachlan Hodges 
1604*b1906ceaSLachlan Hodges enum host_cmd_slow_clock_mode {
1605*b1906ceaSLachlan Hodges 	HOST_CMD_SLOW_CLOCK_MODE_AUTO = 0,
1606*b1906ceaSLachlan Hodges 	HOST_CMD_SLOW_CLOCK_MODE_INTERNAL = 1,
1607*b1906ceaSLachlan Hodges };
1608*b1906ceaSLachlan Hodges 
1609*b1906ceaSLachlan Hodges enum host_cmd_param_id {
1610*b1906ceaSLachlan Hodges 	HOST_CMD_PARAM_ID_MAX_TRAFFIC_DELIVERY_WAIT_US = 0,
1611*b1906ceaSLachlan Hodges 	HOST_CMD_PARAM_ID_EXTRA_ACK_TIMEOUT_ADJUST_US = 1,
1612*b1906ceaSLachlan Hodges 	HOST_CMD_PARAM_ID_TX_STATUS_FLUSH_WATERMARK = 2,
1613*b1906ceaSLachlan Hodges 	HOST_CMD_PARAM_ID_TX_STATUS_FLUSH_MIN_AMPDU_SIZE = 3,
1614*b1906ceaSLachlan Hodges 	HOST_CMD_PARAM_ID_POWERSAVE_TYPE = 4,
1615*b1906ceaSLachlan Hodges 	HOST_CMD_PARAM_ID_SNOOZE_DURATION_ADJUST_US = 5,
1616*b1906ceaSLachlan Hodges 	HOST_CMD_PARAM_ID_TX_BLOCK = 6,
1617*b1906ceaSLachlan Hodges 	HOST_CMD_PARAM_ID_FORCED_SNOOZE_PERIOD_US = 7,
1618*b1906ceaSLachlan Hodges 	HOST_CMD_PARAM_ID_WAKE_ACTION_GPIO = 8,
1619*b1906ceaSLachlan Hodges 	HOST_CMD_PARAM_ID_WAKE_ACTION_GPIO_PULSE_MS = 9,
1620*b1906ceaSLachlan Hodges 	HOST_CMD_PARAM_ID_CONNECTION_MONITOR_GPIO = 10,
1621*b1906ceaSLachlan Hodges 	HOST_CMD_PARAM_ID_INPUT_TRIGGER_GPIO = 11,
1622*b1906ceaSLachlan Hodges 	HOST_CMD_PARAM_ID_INPUT_TRIGGER_MODE = 12,
1623*b1906ceaSLachlan Hodges 	HOST_CMD_PARAM_ID_COUNTRY = 13,
1624*b1906ceaSLachlan Hodges 	HOST_CMD_PARAM_ID_RTS_THRESHOLD = 14,
1625*b1906ceaSLachlan Hodges 	HOST_CMD_PARAM_ID_HOST_TX_BLOCK = 15,
1626*b1906ceaSLachlan Hodges 	HOST_CMD_PARAM_ID_MEM_RETENTION_CODE = 16,
1627*b1906ceaSLachlan Hodges 	HOST_CMD_PARAM_ID_NON_TIM_MODE = 17,
1628*b1906ceaSLachlan Hodges 	HOST_CMD_PARAM_ID_DYNAMIC_PS_TIMEOUT_MS = 18,
1629*b1906ceaSLachlan Hodges 	HOST_CMD_PARAM_ID_HOME_CHANNEL_DWELL_MS = 19,
1630*b1906ceaSLachlan Hodges 	HOST_CMD_PARAM_ID_SLOW_CLOCK_MODE = 20,
1631*b1906ceaSLachlan Hodges 	HOST_CMD_PARAM_ID_FRAGMENT_THRESHOLD = 21,
1632*b1906ceaSLachlan Hodges 	HOST_CMD_PARAM_ID_BEACON_LOSS_COUNT = 22,
1633*b1906ceaSLachlan Hodges 	HOST_CMD_PARAM_ID_AP_POWER_SAVE = 23,
1634*b1906ceaSLachlan Hodges 	HOST_CMD_PARAM_ID_BEACON_OFFLOAD = 24,
1635*b1906ceaSLachlan Hodges 	HOST_CMD_PARAM_ID_PROBE_RESP_OFFLOAD = 25,
1636*b1906ceaSLachlan Hodges 	HOST_CMD_PARAM_ID_BSS_MAX_AWAY_DURATION = 26,
1637*b1906ceaSLachlan Hodges 	HOST_CMD_PARAM_ID_DEFAULT_ACTIVE_SCAN_DWELL_MS = 27,
1638*b1906ceaSLachlan Hodges 	HOST_CMD_PARAM_ID_CTS_TO_SELF = 28,
1639*b1906ceaSLachlan Hodges 	HOST_CMD_PARAM_ID_CHANNELIZATION = 29,
1640*b1906ceaSLachlan Hodges 	HOST_CMD_PARAM_ID_LAST = 30,
1641*b1906ceaSLachlan Hodges };
1642*b1906ceaSLachlan Hodges 
1643*b1906ceaSLachlan Hodges struct host_cmd_req_get_set_generic_param {
1644*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1645*b1906ceaSLachlan Hodges 	__le32 param_id;
1646*b1906ceaSLachlan Hodges 	__le32 action;
1647*b1906ceaSLachlan Hodges 	__le32 flags;
1648*b1906ceaSLachlan Hodges 	__le32 value;
1649*b1906ceaSLachlan Hodges } __packed;
1650*b1906ceaSLachlan Hodges 
1651*b1906ceaSLachlan Hodges struct host_cmd_resp_get_set_generic_param {
1652*b1906ceaSLachlan Hodges 	struct host_cmd_header hdr;
1653*b1906ceaSLachlan Hodges 	__le32 status;
1654*b1906ceaSLachlan Hodges 	__le32 flags;
1655*b1906ceaSLachlan Hodges 	__le32 value;
1656*b1906ceaSLachlan Hodges } __packed;
1657*b1906ceaSLachlan Hodges 
1658*b1906ceaSLachlan Hodges #endif
1659