1*b1906ceaSLachlan Hodges /* SPDX-License-Identifier: GPL-2.0-only */ 2*b1906ceaSLachlan Hodges /* 3*b1906ceaSLachlan Hodges * Copyright (c) 2017-2026 Morse Micro 4*b1906ceaSLachlan Hodges */ 5*b1906ceaSLachlan Hodges 6*b1906ceaSLachlan Hodges #ifndef _MM81X_COMMAND_H_ 7*b1906ceaSLachlan Hodges #define _MM81X_COMMAND_H_ 8*b1906ceaSLachlan Hodges 9*b1906ceaSLachlan Hodges #include <linux/skbuff.h> 10*b1906ceaSLachlan Hodges #include <linux/workqueue.h> 11*b1906ceaSLachlan Hodges #include "core.h" 12*b1906ceaSLachlan Hodges #include "command_defs.h" 13*b1906ceaSLachlan Hodges 14*b1906ceaSLachlan Hodges #define HOST_CMD_IS_REQ(cmd) (le16_to_cpu((cmd)->hdr.flags) & HOST_CMD_TYPE_REQ) 15*b1906ceaSLachlan Hodges #define HOST_CMD_IS_RESP(cmd) \ 16*b1906ceaSLachlan Hodges (le16_to_cpu((cmd)->hdr.flags) & HOST_CMD_TYPE_RESP) 17*b1906ceaSLachlan Hodges #define HOST_CMD_IS_EVT(cmd) (le16_to_cpu((cmd)->hdr.flags) & HOST_CMD_TYPE_EVT) 18*b1906ceaSLachlan Hodges 19*b1906ceaSLachlan Hodges struct mm81x_queue_params; 20*b1906ceaSLachlan Hodges 21*b1906ceaSLachlan Hodges enum mm81x_cmd_return_code { 22*b1906ceaSLachlan Hodges MM81X_RET_SUCCESS = 0, 23*b1906ceaSLachlan Hodges MM81X_RET_EPERM = -1, 24*b1906ceaSLachlan Hodges MM81X_RET_ENOMEM = -12, 25*b1906ceaSLachlan Hodges MM81X_RET_CMD_NOT_HANDLED = -32757, 26*b1906ceaSLachlan Hodges }; 27*b1906ceaSLachlan Hodges 28*b1906ceaSLachlan Hodges #define HOST_CMD_HOST_ID_SEQ_MAX 0xFFF 29*b1906ceaSLachlan Hodges #define HOST_CMD_HOST_ID_RETRY_MASK 0x000F 30*b1906ceaSLachlan Hodges #define HOST_CMD_HOST_ID_SEQ_SHIFT 4 31*b1906ceaSLachlan Hodges #define HOST_CMD_HOST_ID_SEQ_MASK 0xFFF0 32*b1906ceaSLachlan Hodges 33*b1906ceaSLachlan Hodges struct host_cmd_req { 34*b1906ceaSLachlan Hodges struct host_cmd_header hdr; 35*b1906ceaSLachlan Hodges u8 data[]; 36*b1906ceaSLachlan Hodges } __packed; 37*b1906ceaSLachlan Hodges 38*b1906ceaSLachlan Hodges struct host_cmd_resp { 39*b1906ceaSLachlan Hodges struct host_cmd_header hdr; 40*b1906ceaSLachlan Hodges __le32 status; 41*b1906ceaSLachlan Hodges u8 data[]; 42*b1906ceaSLachlan Hodges } __packed; 43*b1906ceaSLachlan Hodges 44*b1906ceaSLachlan Hodges struct host_cmd_event { 45*b1906ceaSLachlan Hodges struct host_cmd_header hdr; 46*b1906ceaSLachlan Hodges u8 data[]; 47*b1906ceaSLachlan Hodges } __packed; 48*b1906ceaSLachlan Hodges 49*b1906ceaSLachlan Hodges int mm81x_cmd_resp_process(struct mm81x *mors, struct sk_buff *skb); 50*b1906ceaSLachlan Hodges int mm81x_cmd_add_if(struct mm81x *mors, u16 *vif_id, const u8 *addr, 51*b1906ceaSLachlan Hodges enum nl80211_iftype type); 52*b1906ceaSLachlan Hodges int mm81x_cmd_get_capabilities(struct mm81x *mors, u16 vif_id, 53*b1906ceaSLachlan Hodges struct mm81x_fw_caps *capabilities); 54*b1906ceaSLachlan Hodges int mm81x_cmd_cfg_qos(struct mm81x *mors, struct mm81x_queue_params *params); 55*b1906ceaSLachlan Hodges int mm81x_cmd_config_beacon_timer(struct mm81x *mors, void *mm81x_vif, 56*b1906ceaSLachlan Hodges bool enabled); 57*b1906ceaSLachlan Hodges int mm81x_cmd_cfg_bss(struct mm81x *mors, u16 vif_id, u16 beacon_int, 58*b1906ceaSLachlan Hodges u16 dtim_period, u32 cssid); 59*b1906ceaSLachlan Hodges int mm81x_cmd_set_channel(struct mm81x *mors, u32 op_chan_freq_hz, 60*b1906ceaSLachlan Hodges u8 pri_1mhz_chan_idx, u8 op_bw_mhz, u8 pri_bw_mhz, 61*b1906ceaSLachlan Hodges s32 *power_mbm); 62*b1906ceaSLachlan Hodges int mm81x_cmd_get_max_txpower(struct mm81x *mors, s32 *out_power_mbm); 63*b1906ceaSLachlan Hodges int mm81x_cmd_set_txpower(struct mm81x *mors, s32 *out_power_mbm, 64*b1906ceaSLachlan Hodges int txpower_mbm); 65*b1906ceaSLachlan Hodges int mm81x_cmd_hw_scan(struct mm81x *mors, struct mm81x_hw_scan_params *params, 66*b1906ceaSLachlan Hodges bool store); 67*b1906ceaSLachlan Hodges int mm81x_cmd_set_ps(struct mm81x *mors, bool enabled); 68*b1906ceaSLachlan Hodges int mm81x_cmd_cfg_multicast_filter(struct mm81x *mors, 69*b1906ceaSLachlan Hodges struct mm81x_vif *mors_vif); 70*b1906ceaSLachlan Hodges int mm81x_cmd_sta_state(struct mm81x *mors, struct mm81x_vif *mors_vif, u16 aid, 71*b1906ceaSLachlan Hodges struct ieee80211_sta *sta, 72*b1906ceaSLachlan Hodges enum ieee80211_sta_state state); 73*b1906ceaSLachlan Hodges int mm81x_cmd_install_key(struct mm81x *mors, struct mm81x_vif *mors_vif, 74*b1906ceaSLachlan Hodges u16 aid, struct ieee80211_key_conf *key, 75*b1906ceaSLachlan Hodges enum host_cmd_key_cipher cipher, 76*b1906ceaSLachlan Hodges enum host_cmd_aes_key_len length); 77*b1906ceaSLachlan Hodges int mm81x_cmd_disable_key(struct mm81x *mors, struct mm81x_vif *mors_vif, 78*b1906ceaSLachlan Hodges u16 aid, struct ieee80211_key_conf *key); 79*b1906ceaSLachlan Hodges int mm81x_cmd_rm_if(struct mm81x *mors, u16 vif_id); 80*b1906ceaSLachlan Hodges int mm81x_cmd_set_frag_threshold(struct mm81x *mors, u32 frag_threshold); 81*b1906ceaSLachlan Hodges int mm81x_cmd_get_disabled_channels( 82*b1906ceaSLachlan Hodges struct mm81x *mors, struct host_cmd_resp_get_disabled_channels *resp, 83*b1906ceaSLachlan Hodges uint resp_len); 84*b1906ceaSLachlan Hodges 85*b1906ceaSLachlan Hodges #endif /* !_MM81X_COMMAND_H_ */ 86