1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries. 4 * All rights reserved. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/spi/spi.h> 9 #include <linux/crc7.h> 10 11 #include "netdev.h" 12 #include "cfg80211.h" 13 14 /* 15 * For CMD_SINGLE_READ and CMD_INTERNAL_READ, WILC may insert one or 16 * more zero bytes between the command response and the DATA Start tag 17 * (0xf3). This behavior appears to be undocumented in "ATWILC1000 18 * USER GUIDE" (https://tinyurl.com/4hhshdts) but we have observed 1-4 19 * zero bytes when the SPI bus operates at 48MHz and none when it 20 * operates at 1MHz. 21 */ 22 #define WILC_SPI_RSP_HDR_EXTRA_DATA 8 23 24 struct wilc_spi { 25 int crc_off; 26 }; 27 28 static const struct wilc_hif_func wilc_hif_spi; 29 30 /******************************************** 31 * 32 * Spi protocol Function 33 * 34 ********************************************/ 35 36 #define CMD_DMA_WRITE 0xc1 37 #define CMD_DMA_READ 0xc2 38 #define CMD_INTERNAL_WRITE 0xc3 39 #define CMD_INTERNAL_READ 0xc4 40 #define CMD_TERMINATE 0xc5 41 #define CMD_REPEAT 0xc6 42 #define CMD_DMA_EXT_WRITE 0xc7 43 #define CMD_DMA_EXT_READ 0xc8 44 #define CMD_SINGLE_WRITE 0xc9 45 #define CMD_SINGLE_READ 0xca 46 #define CMD_RESET 0xcf 47 48 #define SPI_ENABLE_VMM_RETRY_LIMIT 2 49 #define DATA_PKT_SZ_256 256 50 #define DATA_PKT_SZ_512 512 51 #define DATA_PKT_SZ_1K 1024 52 #define DATA_PKT_SZ_4K (4 * 1024) 53 #define DATA_PKT_SZ_8K (8 * 1024) 54 #define DATA_PKT_SZ DATA_PKT_SZ_8K 55 56 #define USE_SPI_DMA 0 57 58 #define WILC_SPI_COMMAND_STAT_SUCCESS 0 59 #define WILC_GET_RESP_HDR_START(h) (((h) >> 4) & 0xf) 60 61 struct wilc_spi_cmd { 62 u8 cmd_type; 63 union { 64 struct { 65 u8 addr[3]; 66 u8 crc[]; 67 } __packed simple_cmd; 68 struct { 69 u8 addr[3]; 70 u8 size[2]; 71 u8 crc[]; 72 } __packed dma_cmd; 73 struct { 74 u8 addr[3]; 75 u8 size[3]; 76 u8 crc[]; 77 } __packed dma_cmd_ext; 78 struct { 79 u8 addr[2]; 80 __be32 data; 81 u8 crc[]; 82 } __packed internal_w_cmd; 83 struct { 84 u8 addr[3]; 85 __be32 data; 86 u8 crc[]; 87 } __packed w_cmd; 88 } u; 89 } __packed; 90 91 struct wilc_spi_read_rsp_data { 92 u8 header; 93 u8 data[4]; 94 u8 crc[]; 95 } __packed; 96 97 struct wilc_spi_rsp_data { 98 u8 rsp_cmd_type; 99 u8 status; 100 u8 data[]; 101 } __packed; 102 103 static int wilc_bus_probe(struct spi_device *spi) 104 { 105 int ret; 106 struct wilc *wilc; 107 struct wilc_spi *spi_priv; 108 109 spi_priv = kzalloc(sizeof(*spi_priv), GFP_KERNEL); 110 if (!spi_priv) 111 return -ENOMEM; 112 113 ret = wilc_cfg80211_init(&wilc, &spi->dev, WILC_HIF_SPI, &wilc_hif_spi); 114 if (ret) { 115 kfree(spi_priv); 116 return ret; 117 } 118 119 spi_set_drvdata(spi, wilc); 120 wilc->dev = &spi->dev; 121 wilc->bus_data = spi_priv; 122 wilc->dev_irq_num = spi->irq; 123 124 wilc->rtc_clk = devm_clk_get(&spi->dev, "rtc_clk"); 125 if (PTR_ERR_OR_ZERO(wilc->rtc_clk) == -EPROBE_DEFER) { 126 kfree(spi_priv); 127 return -EPROBE_DEFER; 128 } else if (!IS_ERR(wilc->rtc_clk)) 129 clk_prepare_enable(wilc->rtc_clk); 130 131 return 0; 132 } 133 134 static int wilc_bus_remove(struct spi_device *spi) 135 { 136 struct wilc *wilc = spi_get_drvdata(spi); 137 138 if (!IS_ERR(wilc->rtc_clk)) 139 clk_disable_unprepare(wilc->rtc_clk); 140 141 wilc_netdev_cleanup(wilc); 142 return 0; 143 } 144 145 static const struct of_device_id wilc_of_match[] = { 146 { .compatible = "microchip,wilc1000", }, 147 { /* sentinel */ } 148 }; 149 MODULE_DEVICE_TABLE(of, wilc_of_match); 150 151 static struct spi_driver wilc_spi_driver = { 152 .driver = { 153 .name = MODALIAS, 154 .of_match_table = wilc_of_match, 155 }, 156 .probe = wilc_bus_probe, 157 .remove = wilc_bus_remove, 158 }; 159 module_spi_driver(wilc_spi_driver); 160 MODULE_LICENSE("GPL"); 161 162 static int wilc_spi_tx(struct wilc *wilc, u8 *b, u32 len) 163 { 164 struct spi_device *spi = to_spi_device(wilc->dev); 165 int ret; 166 struct spi_message msg; 167 168 if (len > 0 && b) { 169 struct spi_transfer tr = { 170 .tx_buf = b, 171 .len = len, 172 .delay = { 173 .value = 0, 174 .unit = SPI_DELAY_UNIT_USECS 175 }, 176 }; 177 char *r_buffer = kzalloc(len, GFP_KERNEL); 178 179 if (!r_buffer) 180 return -ENOMEM; 181 182 tr.rx_buf = r_buffer; 183 dev_dbg(&spi->dev, "Request writing %d bytes\n", len); 184 185 memset(&msg, 0, sizeof(msg)); 186 spi_message_init(&msg); 187 msg.spi = spi; 188 msg.is_dma_mapped = USE_SPI_DMA; 189 spi_message_add_tail(&tr, &msg); 190 191 ret = spi_sync(spi, &msg); 192 if (ret < 0) 193 dev_err(&spi->dev, "SPI transaction failed\n"); 194 195 kfree(r_buffer); 196 } else { 197 dev_err(&spi->dev, 198 "can't write data with the following length: %d\n", 199 len); 200 ret = -EINVAL; 201 } 202 203 return ret; 204 } 205 206 static int wilc_spi_rx(struct wilc *wilc, u8 *rb, u32 rlen) 207 { 208 struct spi_device *spi = to_spi_device(wilc->dev); 209 int ret; 210 211 if (rlen > 0) { 212 struct spi_message msg; 213 struct spi_transfer tr = { 214 .rx_buf = rb, 215 .len = rlen, 216 .delay = { 217 .value = 0, 218 .unit = SPI_DELAY_UNIT_USECS 219 }, 220 221 }; 222 char *t_buffer = kzalloc(rlen, GFP_KERNEL); 223 224 if (!t_buffer) 225 return -ENOMEM; 226 227 tr.tx_buf = t_buffer; 228 229 memset(&msg, 0, sizeof(msg)); 230 spi_message_init(&msg); 231 msg.spi = spi; 232 msg.is_dma_mapped = USE_SPI_DMA; 233 spi_message_add_tail(&tr, &msg); 234 235 ret = spi_sync(spi, &msg); 236 if (ret < 0) 237 dev_err(&spi->dev, "SPI transaction failed\n"); 238 kfree(t_buffer); 239 } else { 240 dev_err(&spi->dev, 241 "can't read data with the following length: %u\n", 242 rlen); 243 ret = -EINVAL; 244 } 245 246 return ret; 247 } 248 249 static int wilc_spi_tx_rx(struct wilc *wilc, u8 *wb, u8 *rb, u32 rlen) 250 { 251 struct spi_device *spi = to_spi_device(wilc->dev); 252 int ret; 253 254 if (rlen > 0) { 255 struct spi_message msg; 256 struct spi_transfer tr = { 257 .rx_buf = rb, 258 .tx_buf = wb, 259 .len = rlen, 260 .bits_per_word = 8, 261 .delay = { 262 .value = 0, 263 .unit = SPI_DELAY_UNIT_USECS 264 }, 265 266 }; 267 268 memset(&msg, 0, sizeof(msg)); 269 spi_message_init(&msg); 270 msg.spi = spi; 271 msg.is_dma_mapped = USE_SPI_DMA; 272 273 spi_message_add_tail(&tr, &msg); 274 ret = spi_sync(spi, &msg); 275 if (ret < 0) 276 dev_err(&spi->dev, "SPI transaction failed\n"); 277 } else { 278 dev_err(&spi->dev, 279 "can't read data with the following length: %u\n", 280 rlen); 281 ret = -EINVAL; 282 } 283 284 return ret; 285 } 286 287 static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz) 288 { 289 struct spi_device *spi = to_spi_device(wilc->dev); 290 struct wilc_spi *spi_priv = wilc->bus_data; 291 int ix, nbytes; 292 int result = 0; 293 u8 cmd, order, crc[2] = {0}; 294 295 /* 296 * Data 297 */ 298 ix = 0; 299 do { 300 if (sz <= DATA_PKT_SZ) { 301 nbytes = sz; 302 order = 0x3; 303 } else { 304 nbytes = DATA_PKT_SZ; 305 if (ix == 0) 306 order = 0x1; 307 else 308 order = 0x02; 309 } 310 311 /* 312 * Write command 313 */ 314 cmd = 0xf0; 315 cmd |= order; 316 317 if (wilc_spi_tx(wilc, &cmd, 1)) { 318 dev_err(&spi->dev, 319 "Failed data block cmd write, bus error...\n"); 320 result = -EINVAL; 321 break; 322 } 323 324 /* 325 * Write data 326 */ 327 if (wilc_spi_tx(wilc, &b[ix], nbytes)) { 328 dev_err(&spi->dev, 329 "Failed data block write, bus error...\n"); 330 result = -EINVAL; 331 break; 332 } 333 334 /* 335 * Write Crc 336 */ 337 if (!spi_priv->crc_off) { 338 if (wilc_spi_tx(wilc, crc, 2)) { 339 dev_err(&spi->dev, "Failed data block crc write, bus error...\n"); 340 result = -EINVAL; 341 break; 342 } 343 } 344 345 /* 346 * No need to wait for response 347 */ 348 ix += nbytes; 349 sz -= nbytes; 350 } while (sz); 351 352 return result; 353 } 354 355 /******************************************** 356 * 357 * Spi Internal Read/Write Function 358 * 359 ********************************************/ 360 static u8 wilc_get_crc7(u8 *buffer, u32 len) 361 { 362 return crc7_be(0xfe, buffer, len); 363 } 364 365 static int wilc_spi_single_read(struct wilc *wilc, u8 cmd, u32 adr, void *b, 366 u8 clockless) 367 { 368 struct spi_device *spi = to_spi_device(wilc->dev); 369 struct wilc_spi *spi_priv = wilc->bus_data; 370 u8 wb[32], rb[32]; 371 u8 crc[2]; 372 int cmd_len, resp_len, i; 373 struct wilc_spi_cmd *c; 374 struct wilc_spi_read_rsp_data *r_data; 375 struct wilc_spi_rsp_data *r; 376 377 memset(wb, 0x0, sizeof(wb)); 378 memset(rb, 0x0, sizeof(rb)); 379 c = (struct wilc_spi_cmd *)wb; 380 c->cmd_type = cmd; 381 if (cmd == CMD_SINGLE_READ) { 382 c->u.simple_cmd.addr[0] = adr >> 16; 383 c->u.simple_cmd.addr[1] = adr >> 8; 384 c->u.simple_cmd.addr[2] = adr; 385 } else if (cmd == CMD_INTERNAL_READ) { 386 c->u.simple_cmd.addr[0] = adr >> 8; 387 if (clockless == 1) 388 c->u.simple_cmd.addr[0] |= BIT(7); 389 c->u.simple_cmd.addr[1] = adr; 390 c->u.simple_cmd.addr[2] = 0x0; 391 } else { 392 dev_err(&spi->dev, "cmd [%x] not supported\n", cmd); 393 return -EINVAL; 394 } 395 396 cmd_len = offsetof(struct wilc_spi_cmd, u.simple_cmd.crc); 397 resp_len = sizeof(*r) + sizeof(*r_data) + WILC_SPI_RSP_HDR_EXTRA_DATA; 398 399 if (!spi_priv->crc_off) { 400 c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 401 cmd_len += 1; 402 resp_len += 2; 403 } 404 405 if (cmd_len + resp_len > ARRAY_SIZE(wb)) { 406 dev_err(&spi->dev, 407 "spi buffer size too small (%d) (%d) (%zu)\n", 408 cmd_len, resp_len, ARRAY_SIZE(wb)); 409 return -EINVAL; 410 } 411 412 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) { 413 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); 414 return -EINVAL; 415 } 416 417 r = (struct wilc_spi_rsp_data *)&rb[cmd_len]; 418 if (r->rsp_cmd_type != cmd) { 419 dev_err(&spi->dev, 420 "Failed cmd response, cmd (%02x), resp (%02x)\n", 421 cmd, r->rsp_cmd_type); 422 return -EINVAL; 423 } 424 425 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) { 426 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", 427 r->status); 428 return -EINVAL; 429 } 430 431 for (i = 0; i < WILC_SPI_RSP_HDR_EXTRA_DATA; ++i) 432 if (WILC_GET_RESP_HDR_START(r->data[i]) == 0xf) 433 break; 434 435 if (i >= WILC_SPI_RSP_HDR_EXTRA_DATA) { 436 dev_err(&spi->dev, "Error, data start missing\n"); 437 return -EINVAL; 438 } 439 440 r_data = (struct wilc_spi_read_rsp_data *)&r->data[i]; 441 442 if (b) 443 memcpy(b, r_data->data, 4); 444 445 if (!spi_priv->crc_off) 446 memcpy(crc, r_data->crc, 2); 447 448 return 0; 449 } 450 451 static int wilc_spi_write_cmd(struct wilc *wilc, u8 cmd, u32 adr, u32 data, 452 u8 clockless) 453 { 454 struct spi_device *spi = to_spi_device(wilc->dev); 455 struct wilc_spi *spi_priv = wilc->bus_data; 456 u8 wb[32], rb[32]; 457 int cmd_len, resp_len; 458 struct wilc_spi_cmd *c; 459 struct wilc_spi_rsp_data *r; 460 461 memset(wb, 0x0, sizeof(wb)); 462 memset(rb, 0x0, sizeof(rb)); 463 c = (struct wilc_spi_cmd *)wb; 464 c->cmd_type = cmd; 465 if (cmd == CMD_INTERNAL_WRITE) { 466 c->u.internal_w_cmd.addr[0] = adr >> 8; 467 if (clockless == 1) 468 c->u.internal_w_cmd.addr[0] |= BIT(7); 469 470 c->u.internal_w_cmd.addr[1] = adr; 471 c->u.internal_w_cmd.data = cpu_to_be32(data); 472 cmd_len = offsetof(struct wilc_spi_cmd, u.internal_w_cmd.crc); 473 if (!spi_priv->crc_off) 474 c->u.internal_w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 475 } else if (cmd == CMD_SINGLE_WRITE) { 476 c->u.w_cmd.addr[0] = adr >> 16; 477 c->u.w_cmd.addr[1] = adr >> 8; 478 c->u.w_cmd.addr[2] = adr; 479 c->u.w_cmd.data = cpu_to_be32(data); 480 cmd_len = offsetof(struct wilc_spi_cmd, u.w_cmd.crc); 481 if (!spi_priv->crc_off) 482 c->u.w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 483 } else { 484 dev_err(&spi->dev, "write cmd [%x] not supported\n", cmd); 485 return -EINVAL; 486 } 487 488 if (!spi_priv->crc_off) 489 cmd_len += 1; 490 491 resp_len = sizeof(*r); 492 493 if (cmd_len + resp_len > ARRAY_SIZE(wb)) { 494 dev_err(&spi->dev, 495 "spi buffer size too small (%d) (%d) (%zu)\n", 496 cmd_len, resp_len, ARRAY_SIZE(wb)); 497 return -EINVAL; 498 } 499 500 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) { 501 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); 502 return -EINVAL; 503 } 504 505 r = (struct wilc_spi_rsp_data *)&rb[cmd_len]; 506 if (r->rsp_cmd_type != cmd) { 507 dev_err(&spi->dev, 508 "Failed cmd response, cmd (%02x), resp (%02x)\n", 509 cmd, r->rsp_cmd_type); 510 return -EINVAL; 511 } 512 513 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) { 514 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", 515 r->status); 516 return -EINVAL; 517 } 518 519 return 0; 520 } 521 522 static int wilc_spi_dma_rw(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz) 523 { 524 struct spi_device *spi = to_spi_device(wilc->dev); 525 struct wilc_spi *spi_priv = wilc->bus_data; 526 u8 wb[32], rb[32]; 527 int cmd_len, resp_len; 528 int retry, ix = 0; 529 u8 crc[2]; 530 struct wilc_spi_cmd *c; 531 struct wilc_spi_rsp_data *r; 532 533 memset(wb, 0x0, sizeof(wb)); 534 memset(rb, 0x0, sizeof(rb)); 535 c = (struct wilc_spi_cmd *)wb; 536 c->cmd_type = cmd; 537 if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_READ) { 538 c->u.dma_cmd.addr[0] = adr >> 16; 539 c->u.dma_cmd.addr[1] = adr >> 8; 540 c->u.dma_cmd.addr[2] = adr; 541 c->u.dma_cmd.size[0] = sz >> 8; 542 c->u.dma_cmd.size[1] = sz; 543 cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd.crc); 544 if (!spi_priv->crc_off) 545 c->u.dma_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 546 } else if (cmd == CMD_DMA_EXT_WRITE || cmd == CMD_DMA_EXT_READ) { 547 c->u.dma_cmd_ext.addr[0] = adr >> 16; 548 c->u.dma_cmd_ext.addr[1] = adr >> 8; 549 c->u.dma_cmd_ext.addr[2] = adr; 550 c->u.dma_cmd_ext.size[0] = sz >> 16; 551 c->u.dma_cmd_ext.size[1] = sz >> 8; 552 c->u.dma_cmd_ext.size[2] = sz; 553 cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd_ext.crc); 554 if (!spi_priv->crc_off) 555 c->u.dma_cmd_ext.crc[0] = wilc_get_crc7(wb, cmd_len); 556 } else { 557 dev_err(&spi->dev, "dma read write cmd [%x] not supported\n", 558 cmd); 559 return -EINVAL; 560 } 561 if (!spi_priv->crc_off) 562 cmd_len += 1; 563 564 resp_len = sizeof(*r); 565 566 if (cmd_len + resp_len > ARRAY_SIZE(wb)) { 567 dev_err(&spi->dev, "spi buffer size too small (%d)(%d) (%zu)\n", 568 cmd_len, resp_len, ARRAY_SIZE(wb)); 569 return -EINVAL; 570 } 571 572 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) { 573 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); 574 return -EINVAL; 575 } 576 577 r = (struct wilc_spi_rsp_data *)&rb[cmd_len]; 578 if (r->rsp_cmd_type != cmd) { 579 dev_err(&spi->dev, 580 "Failed cmd response, cmd (%02x), resp (%02x)\n", 581 cmd, r->rsp_cmd_type); 582 return -EINVAL; 583 } 584 585 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) { 586 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", 587 r->status); 588 return -EINVAL; 589 } 590 591 if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_EXT_WRITE) 592 return 0; 593 594 while (sz > 0) { 595 int nbytes; 596 u8 rsp; 597 598 if (sz <= DATA_PKT_SZ) 599 nbytes = sz; 600 else 601 nbytes = DATA_PKT_SZ; 602 603 /* 604 * Data Response header 605 */ 606 retry = 100; 607 do { 608 if (wilc_spi_rx(wilc, &rsp, 1)) { 609 dev_err(&spi->dev, 610 "Failed resp read, bus err\n"); 611 return -EINVAL; 612 } 613 if (WILC_GET_RESP_HDR_START(rsp) == 0xf) 614 break; 615 } while (retry--); 616 617 /* 618 * Read bytes 619 */ 620 if (wilc_spi_rx(wilc, &b[ix], nbytes)) { 621 dev_err(&spi->dev, 622 "Failed block read, bus err\n"); 623 return -EINVAL; 624 } 625 626 /* 627 * Read Crc 628 */ 629 if (!spi_priv->crc_off && wilc_spi_rx(wilc, crc, 2)) { 630 dev_err(&spi->dev, 631 "Failed block crc read, bus err\n"); 632 return -EINVAL; 633 } 634 635 ix += nbytes; 636 sz -= nbytes; 637 } 638 return 0; 639 } 640 641 static int wilc_spi_read_reg(struct wilc *wilc, u32 addr, u32 *data) 642 { 643 struct spi_device *spi = to_spi_device(wilc->dev); 644 int result; 645 u8 cmd = CMD_SINGLE_READ; 646 u8 clockless = 0; 647 648 if (addr < WILC_SPI_CLOCKLESS_ADDR_LIMIT) { 649 /* Clockless register */ 650 cmd = CMD_INTERNAL_READ; 651 clockless = 1; 652 } 653 654 result = wilc_spi_single_read(wilc, cmd, addr, data, clockless); 655 if (result) { 656 dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr); 657 return result; 658 } 659 660 le32_to_cpus(data); 661 662 return 0; 663 } 664 665 static int wilc_spi_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size) 666 { 667 struct spi_device *spi = to_spi_device(wilc->dev); 668 int result; 669 670 if (size <= 4) 671 return -EINVAL; 672 673 result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_READ, addr, buf, size); 674 if (result) { 675 dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr); 676 return result; 677 } 678 679 return 0; 680 } 681 682 static int spi_internal_write(struct wilc *wilc, u32 adr, u32 dat) 683 { 684 struct spi_device *spi = to_spi_device(wilc->dev); 685 int result; 686 687 result = wilc_spi_write_cmd(wilc, CMD_INTERNAL_WRITE, adr, dat, 0); 688 if (result) { 689 dev_err(&spi->dev, "Failed internal write cmd...\n"); 690 return result; 691 } 692 693 return 0; 694 } 695 696 static int spi_internal_read(struct wilc *wilc, u32 adr, u32 *data) 697 { 698 struct spi_device *spi = to_spi_device(wilc->dev); 699 int result; 700 701 result = wilc_spi_single_read(wilc, CMD_INTERNAL_READ, adr, data, 0); 702 if (result) { 703 dev_err(&spi->dev, "Failed internal read cmd...\n"); 704 return result; 705 } 706 707 le32_to_cpus(data); 708 709 return 0; 710 } 711 712 /******************************************** 713 * 714 * Spi interfaces 715 * 716 ********************************************/ 717 718 static int wilc_spi_write_reg(struct wilc *wilc, u32 addr, u32 data) 719 { 720 struct spi_device *spi = to_spi_device(wilc->dev); 721 int result; 722 u8 cmd = CMD_SINGLE_WRITE; 723 u8 clockless = 0; 724 725 if (addr < WILC_SPI_CLOCKLESS_ADDR_LIMIT) { 726 /* Clockless register */ 727 cmd = CMD_INTERNAL_WRITE; 728 clockless = 1; 729 } 730 731 result = wilc_spi_write_cmd(wilc, cmd, addr, data, clockless); 732 if (result) { 733 dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr); 734 return result; 735 } 736 737 return 0; 738 } 739 740 static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size) 741 { 742 struct spi_device *spi = to_spi_device(wilc->dev); 743 int result; 744 745 /* 746 * has to be greated than 4 747 */ 748 if (size <= 4) 749 return -EINVAL; 750 751 result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_WRITE, addr, NULL, size); 752 if (result) { 753 dev_err(&spi->dev, 754 "Failed cmd, write block (%08x)...\n", addr); 755 return result; 756 } 757 758 /* 759 * Data 760 */ 761 result = spi_data_write(wilc, buf, size); 762 if (result) { 763 dev_err(&spi->dev, "Failed block data write...\n"); 764 return result; 765 } 766 767 return 0; 768 } 769 770 /******************************************** 771 * 772 * Bus interfaces 773 * 774 ********************************************/ 775 776 static int wilc_spi_deinit(struct wilc *wilc) 777 { 778 /* 779 * TODO: 780 */ 781 return 0; 782 } 783 784 static int wilc_spi_init(struct wilc *wilc, bool resume) 785 { 786 struct spi_device *spi = to_spi_device(wilc->dev); 787 struct wilc_spi *spi_priv = wilc->bus_data; 788 u32 reg; 789 u32 chipid; 790 static int isinit; 791 int ret; 792 793 if (isinit) { 794 ret = wilc_spi_read_reg(wilc, WILC_CHIPID, &chipid); 795 if (ret) 796 dev_err(&spi->dev, "Fail cmd read chip id...\n"); 797 798 return ret; 799 } 800 801 /* 802 * configure protocol 803 */ 804 805 /* 806 * TODO: We can remove the CRC trials if there is a definite 807 * way to reset 808 */ 809 /* the SPI to it's initial value. */ 810 ret = spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®); 811 if (ret) { 812 /* 813 * Read failed. Try with CRC off. This might happen when module 814 * is removed but chip isn't reset 815 */ 816 spi_priv->crc_off = 1; 817 dev_err(&spi->dev, 818 "Failed read with CRC on, retrying with CRC off\n"); 819 ret = spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®); 820 if (ret) { 821 /* 822 * Read failed with both CRC on and off, 823 * something went bad 824 */ 825 dev_err(&spi->dev, "Failed internal read protocol\n"); 826 return ret; 827 } 828 } 829 if (spi_priv->crc_off == 0) { 830 reg &= ~0xc; /* disable crc checking */ 831 reg &= ~0x70; 832 reg |= (0x5 << 4); 833 ret = spi_internal_write(wilc, WILC_SPI_PROTOCOL_OFFSET, reg); 834 if (ret) { 835 dev_err(&spi->dev, 836 "[wilc spi %d]: Failed internal write reg\n", 837 __LINE__); 838 return ret; 839 } 840 spi_priv->crc_off = 1; 841 } 842 843 /* 844 * make sure can read back chip id correctly 845 */ 846 ret = wilc_spi_read_reg(wilc, WILC_CHIPID, &chipid); 847 if (ret) { 848 dev_err(&spi->dev, "Fail cmd read chip id...\n"); 849 return ret; 850 } 851 852 isinit = 1; 853 854 return 0; 855 } 856 857 static int wilc_spi_read_size(struct wilc *wilc, u32 *size) 858 { 859 int ret; 860 861 ret = spi_internal_read(wilc, 862 WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, size); 863 *size = FIELD_GET(IRQ_DMA_WD_CNT_MASK, *size); 864 865 return ret; 866 } 867 868 static int wilc_spi_read_int(struct wilc *wilc, u32 *int_status) 869 { 870 return spi_internal_read(wilc, WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, 871 int_status); 872 } 873 874 static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val) 875 { 876 int ret; 877 int retry = SPI_ENABLE_VMM_RETRY_LIMIT; 878 u32 check; 879 880 while (retry) { 881 ret = spi_internal_write(wilc, 882 WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE, 883 val); 884 if (ret) 885 break; 886 887 ret = spi_internal_read(wilc, 888 WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE, 889 &check); 890 if (ret || ((check & EN_VMM) == (val & EN_VMM))) 891 break; 892 893 retry--; 894 } 895 return ret; 896 } 897 898 static int wilc_spi_sync_ext(struct wilc *wilc, int nint) 899 { 900 struct spi_device *spi = to_spi_device(wilc->dev); 901 u32 reg; 902 int ret, i; 903 904 if (nint > MAX_NUM_INT) { 905 dev_err(&spi->dev, "Too many interrupts (%d)...\n", nint); 906 return -EINVAL; 907 } 908 909 /* 910 * interrupt pin mux select 911 */ 912 ret = wilc_spi_read_reg(wilc, WILC_PIN_MUX_0, ®); 913 if (ret) { 914 dev_err(&spi->dev, "Failed read reg (%08x)...\n", 915 WILC_PIN_MUX_0); 916 return ret; 917 } 918 reg |= BIT(8); 919 ret = wilc_spi_write_reg(wilc, WILC_PIN_MUX_0, reg); 920 if (ret) { 921 dev_err(&spi->dev, "Failed write reg (%08x)...\n", 922 WILC_PIN_MUX_0); 923 return ret; 924 } 925 926 /* 927 * interrupt enable 928 */ 929 ret = wilc_spi_read_reg(wilc, WILC_INTR_ENABLE, ®); 930 if (ret) { 931 dev_err(&spi->dev, "Failed read reg (%08x)...\n", 932 WILC_INTR_ENABLE); 933 return ret; 934 } 935 936 for (i = 0; (i < 5) && (nint > 0); i++, nint--) 937 reg |= (BIT((27 + i))); 938 939 ret = wilc_spi_write_reg(wilc, WILC_INTR_ENABLE, reg); 940 if (ret) { 941 dev_err(&spi->dev, "Failed write reg (%08x)...\n", 942 WILC_INTR_ENABLE); 943 return ret; 944 } 945 if (nint) { 946 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, ®); 947 if (ret) { 948 dev_err(&spi->dev, "Failed read reg (%08x)...\n", 949 WILC_INTR2_ENABLE); 950 return ret; 951 } 952 953 for (i = 0; (i < 3) && (nint > 0); i++, nint--) 954 reg |= BIT(i); 955 956 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, ®); 957 if (ret) { 958 dev_err(&spi->dev, "Failed write reg (%08x)...\n", 959 WILC_INTR2_ENABLE); 960 return ret; 961 } 962 } 963 964 return 0; 965 } 966 967 /* Global spi HIF function table */ 968 static const struct wilc_hif_func wilc_hif_spi = { 969 .hif_init = wilc_spi_init, 970 .hif_deinit = wilc_spi_deinit, 971 .hif_read_reg = wilc_spi_read_reg, 972 .hif_write_reg = wilc_spi_write_reg, 973 .hif_block_rx = wilc_spi_read, 974 .hif_block_tx = wilc_spi_write, 975 .hif_read_int = wilc_spi_read_int, 976 .hif_clear_int_ext = wilc_spi_clear_int_ext, 977 .hif_read_size = wilc_spi_read_size, 978 .hif_block_tx_ext = wilc_spi_write, 979 .hif_block_rx_ext = wilc_spi_read, 980 .hif_sync_ext = wilc_spi_sync_ext, 981 }; 982