1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries. 4 * All rights reserved. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/spi/spi.h> 9 #include <linux/crc7.h> 10 #include <linux/crc-itu-t.h> 11 #include <linux/gpio/consumer.h> 12 13 #include "netdev.h" 14 #include "cfg80211.h" 15 16 #define SPI_MODALIAS "wilc1000_spi" 17 18 static bool enable_crc7; /* protect SPI commands with CRC7 */ 19 module_param(enable_crc7, bool, 0644); 20 MODULE_PARM_DESC(enable_crc7, 21 "Enable CRC7 checksum to protect command transfers\n" 22 "\t\t\tagainst corruption during the SPI transfer.\n" 23 "\t\t\tCommand transfers are short and the CPU-cycle cost\n" 24 "\t\t\tof enabling this is small."); 25 26 static bool enable_crc16; /* protect SPI data with CRC16 */ 27 module_param(enable_crc16, bool, 0644); 28 MODULE_PARM_DESC(enable_crc16, 29 "Enable CRC16 checksum to protect data transfers\n" 30 "\t\t\tagainst corruption during the SPI transfer.\n" 31 "\t\t\tData transfers can be large and the CPU-cycle cost\n" 32 "\t\t\tof enabling this may be substantial."); 33 34 /* 35 * For CMD_SINGLE_READ and CMD_INTERNAL_READ, WILC may insert one or 36 * more zero bytes between the command response and the DATA Start tag 37 * (0xf3). This behavior appears to be undocumented in "ATWILC1000 38 * USER GUIDE" (https://tinyurl.com/4hhshdts) but we have observed 1-4 39 * zero bytes when the SPI bus operates at 48MHz and none when it 40 * operates at 1MHz. 41 */ 42 #define WILC_SPI_RSP_HDR_EXTRA_DATA 8 43 44 struct wilc_spi { 45 bool isinit; /* true if wilc_spi_init was successful */ 46 bool probing_crc; /* true if we're probing chip's CRC config */ 47 bool crc7_enabled; /* true if crc7 is currently enabled */ 48 bool crc16_enabled; /* true if crc16 is currently enabled */ 49 struct wilc_gpios { 50 struct gpio_desc *enable; /* ENABLE GPIO or NULL */ 51 struct gpio_desc *reset; /* RESET GPIO or NULL */ 52 } gpios; 53 }; 54 55 static const struct wilc_hif_func wilc_hif_spi; 56 57 static int wilc_spi_reset(struct wilc *wilc); 58 static int wilc_spi_configure_bus_protocol(struct wilc *wilc); 59 static int wilc_validate_chipid(struct wilc *wilc); 60 61 /******************************************** 62 * 63 * Spi protocol Function 64 * 65 ********************************************/ 66 67 #define CMD_DMA_WRITE 0xc1 68 #define CMD_DMA_READ 0xc2 69 #define CMD_INTERNAL_WRITE 0xc3 70 #define CMD_INTERNAL_READ 0xc4 71 #define CMD_TERMINATE 0xc5 72 #define CMD_REPEAT 0xc6 73 #define CMD_DMA_EXT_WRITE 0xc7 74 #define CMD_DMA_EXT_READ 0xc8 75 #define CMD_SINGLE_WRITE 0xc9 76 #define CMD_SINGLE_READ 0xca 77 #define CMD_RESET 0xcf 78 79 #define SPI_RETRY_MAX_LIMIT 10 80 #define SPI_ENABLE_VMM_RETRY_LIMIT 2 81 82 /* SPI response fields (section 11.1.2 in ATWILC1000 User Guide): */ 83 #define RSP_START_FIELD GENMASK(7, 4) 84 #define RSP_TYPE_FIELD GENMASK(3, 0) 85 86 /* SPI response values for the response fields: */ 87 #define RSP_START_TAG 0xc 88 #define RSP_TYPE_FIRST_PACKET 0x1 89 #define RSP_TYPE_INNER_PACKET 0x2 90 #define RSP_TYPE_LAST_PACKET 0x3 91 #define RSP_STATE_NO_ERROR 0x00 92 93 #define PROTOCOL_REG_PKT_SZ_MASK GENMASK(6, 4) 94 #define PROTOCOL_REG_CRC16_MASK GENMASK(3, 3) 95 #define PROTOCOL_REG_CRC7_MASK GENMASK(2, 2) 96 97 /* 98 * The SPI data packet size may be any integer power of two in the 99 * range from 256 to 8192 bytes. 100 */ 101 #define DATA_PKT_LOG_SZ_MIN 8 /* 256 B */ 102 #define DATA_PKT_LOG_SZ_MAX 13 /* 8 KiB */ 103 104 /* 105 * Select the data packet size (log2 of number of bytes): Use the 106 * maximum data packet size. We only retransmit complete packets, so 107 * there is no benefit from using smaller data packets. 108 */ 109 #define DATA_PKT_LOG_SZ DATA_PKT_LOG_SZ_MAX 110 #define DATA_PKT_SZ (1 << DATA_PKT_LOG_SZ) 111 112 #define WILC_SPI_COMMAND_STAT_SUCCESS 0 113 #define WILC_GET_RESP_HDR_START(h) (((h) >> 4) & 0xf) 114 115 struct wilc_spi_cmd { 116 u8 cmd_type; 117 union { 118 struct { 119 u8 addr[3]; 120 u8 crc[]; 121 } __packed simple_cmd; 122 struct { 123 u8 addr[3]; 124 u8 size[2]; 125 u8 crc[]; 126 } __packed dma_cmd; 127 struct { 128 u8 addr[3]; 129 u8 size[3]; 130 u8 crc[]; 131 } __packed dma_cmd_ext; 132 struct { 133 u8 addr[2]; 134 __be32 data; 135 u8 crc[]; 136 } __packed internal_w_cmd; 137 struct { 138 u8 addr[3]; 139 __be32 data; 140 u8 crc[]; 141 } __packed w_cmd; 142 } u; 143 } __packed; 144 145 struct wilc_spi_read_rsp_data { 146 u8 header; 147 u8 data[4]; 148 u8 crc[]; 149 } __packed; 150 151 struct wilc_spi_rsp_data { 152 u8 rsp_cmd_type; 153 u8 status; 154 u8 data[]; 155 } __packed; 156 157 struct wilc_spi_special_cmd_rsp { 158 u8 skip_byte; 159 u8 rsp_cmd_type; 160 u8 status; 161 } __packed; 162 163 static int wilc_parse_gpios(struct wilc *wilc) 164 { 165 struct spi_device *spi = to_spi_device(wilc->dev); 166 struct wilc_spi *spi_priv = wilc->bus_data; 167 struct wilc_gpios *gpios = &spi_priv->gpios; 168 169 /* get ENABLE pin and deassert it (if it is defined): */ 170 gpios->enable = devm_gpiod_get_optional(&spi->dev, 171 "enable", GPIOD_OUT_LOW); 172 /* get RESET pin and assert it (if it is defined): */ 173 if (gpios->enable) { 174 /* if enable pin exists, reset must exist as well */ 175 gpios->reset = devm_gpiod_get(&spi->dev, 176 "reset", GPIOD_OUT_HIGH); 177 if (IS_ERR(gpios->reset)) { 178 dev_err(&spi->dev, "missing reset gpio.\n"); 179 return PTR_ERR(gpios->reset); 180 } 181 } else { 182 gpios->reset = devm_gpiod_get_optional(&spi->dev, 183 "reset", GPIOD_OUT_HIGH); 184 } 185 return 0; 186 } 187 188 static void wilc_wlan_power(struct wilc *wilc, bool on) 189 { 190 struct wilc_spi *spi_priv = wilc->bus_data; 191 struct wilc_gpios *gpios = &spi_priv->gpios; 192 193 if (on) { 194 /* assert ENABLE: */ 195 gpiod_set_value(gpios->enable, 1); 196 mdelay(5); 197 /* deassert RESET: */ 198 gpiod_set_value(gpios->reset, 0); 199 } else { 200 /* assert RESET: */ 201 gpiod_set_value(gpios->reset, 1); 202 /* deassert ENABLE: */ 203 gpiod_set_value(gpios->enable, 0); 204 } 205 } 206 207 static int wilc_bus_probe(struct spi_device *spi) 208 { 209 struct wilc_spi *spi_priv; 210 struct wilc_vif *vif; 211 struct wilc *wilc; 212 int ret; 213 214 spi_priv = kzalloc(sizeof(*spi_priv), GFP_KERNEL); 215 if (!spi_priv) 216 return -ENOMEM; 217 218 ret = wilc_cfg80211_init(&wilc, &spi->dev, WILC_HIF_SPI, &wilc_hif_spi); 219 if (ret) 220 goto free; 221 222 spi_set_drvdata(spi, wilc); 223 wilc->dev = &spi->dev; 224 wilc->bus_data = spi_priv; 225 wilc->dev_irq_num = spi->irq; 226 227 ret = wilc_parse_gpios(wilc); 228 if (ret < 0) 229 goto netdev_cleanup; 230 231 wilc->rtc_clk = devm_clk_get_optional(&spi->dev, "rtc"); 232 if (IS_ERR(wilc->rtc_clk)) { 233 ret = PTR_ERR(wilc->rtc_clk); 234 goto netdev_cleanup; 235 } 236 clk_prepare_enable(wilc->rtc_clk); 237 238 dev_info(&spi->dev, "Selected CRC config: crc7=%s, crc16=%s\n", 239 enable_crc7 ? "on" : "off", enable_crc16 ? "on" : "off"); 240 241 /* we need power to configure the bus protocol and to read the chip id: */ 242 243 wilc_wlan_power(wilc, true); 244 245 ret = wilc_spi_configure_bus_protocol(wilc); 246 if (ret) 247 goto power_down; 248 249 ret = wilc_validate_chipid(wilc); 250 if (ret) 251 goto power_down; 252 253 ret = wilc_load_mac_from_nv(wilc); 254 if (ret) { 255 pr_err("Can not retrieve MAC address from chip\n"); 256 goto power_down; 257 } 258 259 wilc_wlan_power(wilc, false); 260 vif = wilc_netdev_ifc_init(wilc, "wlan%d", WILC_STATION_MODE, 261 NL80211_IFTYPE_STATION, false); 262 if (IS_ERR(vif)) { 263 ret = PTR_ERR(vif); 264 goto power_down; 265 } 266 return 0; 267 268 power_down: 269 clk_disable_unprepare(wilc->rtc_clk); 270 wilc_wlan_power(wilc, false); 271 netdev_cleanup: 272 wilc_netdev_cleanup(wilc); 273 free: 274 kfree(spi_priv); 275 return ret; 276 } 277 278 static void wilc_bus_remove(struct spi_device *spi) 279 { 280 struct wilc *wilc = spi_get_drvdata(spi); 281 struct wilc_spi *spi_priv = wilc->bus_data; 282 283 clk_disable_unprepare(wilc->rtc_clk); 284 wilc_netdev_cleanup(wilc); 285 kfree(spi_priv); 286 } 287 288 static const struct of_device_id wilc_of_match[] = { 289 { .compatible = "microchip,wilc1000", }, 290 { /* sentinel */ } 291 }; 292 MODULE_DEVICE_TABLE(of, wilc_of_match); 293 294 static const struct spi_device_id wilc_spi_id[] = { 295 { "wilc1000", 0 }, 296 { /* sentinel */ } 297 }; 298 MODULE_DEVICE_TABLE(spi, wilc_spi_id); 299 300 static struct spi_driver wilc_spi_driver = { 301 .driver = { 302 .name = SPI_MODALIAS, 303 .of_match_table = wilc_of_match, 304 }, 305 .id_table = wilc_spi_id, 306 .probe = wilc_bus_probe, 307 .remove = wilc_bus_remove, 308 }; 309 module_spi_driver(wilc_spi_driver); 310 MODULE_DESCRIPTION("Atmel WILC1000 SPI wireless driver"); 311 MODULE_LICENSE("GPL"); 312 313 static int wilc_spi_tx(struct wilc *wilc, u8 *b, u32 len) 314 { 315 struct spi_device *spi = to_spi_device(wilc->dev); 316 int ret; 317 struct spi_message msg; 318 319 if (len > 0 && b) { 320 struct spi_transfer tr = { 321 .tx_buf = b, 322 .len = len, 323 .delay = { 324 .value = 0, 325 .unit = SPI_DELAY_UNIT_USECS 326 }, 327 }; 328 char *r_buffer = kzalloc(len, GFP_KERNEL); 329 330 if (!r_buffer) 331 return -ENOMEM; 332 333 tr.rx_buf = r_buffer; 334 dev_dbg(&spi->dev, "Request writing %d bytes\n", len); 335 336 memset(&msg, 0, sizeof(msg)); 337 spi_message_init(&msg); 338 spi_message_add_tail(&tr, &msg); 339 340 ret = spi_sync(spi, &msg); 341 if (ret < 0) 342 dev_err(&spi->dev, "SPI transaction failed\n"); 343 344 kfree(r_buffer); 345 } else { 346 dev_err(&spi->dev, 347 "can't write data with the following length: %d\n", 348 len); 349 ret = -EINVAL; 350 } 351 352 return ret; 353 } 354 355 static int wilc_spi_rx(struct wilc *wilc, u8 *rb, u32 rlen) 356 { 357 struct spi_device *spi = to_spi_device(wilc->dev); 358 int ret; 359 360 if (rlen > 0) { 361 struct spi_message msg; 362 struct spi_transfer tr = { 363 .rx_buf = rb, 364 .len = rlen, 365 .delay = { 366 .value = 0, 367 .unit = SPI_DELAY_UNIT_USECS 368 }, 369 370 }; 371 char *t_buffer = kzalloc(rlen, GFP_KERNEL); 372 373 if (!t_buffer) 374 return -ENOMEM; 375 376 tr.tx_buf = t_buffer; 377 378 memset(&msg, 0, sizeof(msg)); 379 spi_message_init(&msg); 380 spi_message_add_tail(&tr, &msg); 381 382 ret = spi_sync(spi, &msg); 383 if (ret < 0) 384 dev_err(&spi->dev, "SPI transaction failed\n"); 385 kfree(t_buffer); 386 } else { 387 dev_err(&spi->dev, 388 "can't read data with the following length: %u\n", 389 rlen); 390 ret = -EINVAL; 391 } 392 393 return ret; 394 } 395 396 static int wilc_spi_tx_rx(struct wilc *wilc, u8 *wb, u8 *rb, u32 rlen) 397 { 398 struct spi_device *spi = to_spi_device(wilc->dev); 399 int ret; 400 401 if (rlen > 0) { 402 struct spi_message msg; 403 struct spi_transfer tr = { 404 .rx_buf = rb, 405 .tx_buf = wb, 406 .len = rlen, 407 .bits_per_word = 8, 408 .delay = { 409 .value = 0, 410 .unit = SPI_DELAY_UNIT_USECS 411 }, 412 413 }; 414 415 memset(&msg, 0, sizeof(msg)); 416 spi_message_init(&msg); 417 spi_message_add_tail(&tr, &msg); 418 ret = spi_sync(spi, &msg); 419 if (ret < 0) 420 dev_err(&spi->dev, "SPI transaction failed\n"); 421 } else { 422 dev_err(&spi->dev, 423 "can't read data with the following length: %u\n", 424 rlen); 425 ret = -EINVAL; 426 } 427 428 return ret; 429 } 430 431 static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz) 432 { 433 struct spi_device *spi = to_spi_device(wilc->dev); 434 struct wilc_spi *spi_priv = wilc->bus_data; 435 int ix, nbytes; 436 int result = 0; 437 u8 cmd, order, crc[2]; 438 u16 crc_calc; 439 440 /* 441 * Data 442 */ 443 ix = 0; 444 do { 445 if (sz <= DATA_PKT_SZ) { 446 nbytes = sz; 447 order = 0x3; 448 } else { 449 nbytes = DATA_PKT_SZ; 450 if (ix == 0) 451 order = 0x1; 452 else 453 order = 0x02; 454 } 455 456 /* 457 * Write command 458 */ 459 cmd = 0xf0; 460 cmd |= order; 461 462 if (wilc_spi_tx(wilc, &cmd, 1)) { 463 dev_err(&spi->dev, 464 "Failed data block cmd write, bus error...\n"); 465 result = -EINVAL; 466 break; 467 } 468 469 /* 470 * Write data 471 */ 472 if (wilc_spi_tx(wilc, &b[ix], nbytes)) { 473 dev_err(&spi->dev, 474 "Failed data block write, bus error...\n"); 475 result = -EINVAL; 476 break; 477 } 478 479 /* 480 * Write CRC 481 */ 482 if (spi_priv->crc16_enabled) { 483 crc_calc = crc_itu_t(0xffff, &b[ix], nbytes); 484 crc[0] = crc_calc >> 8; 485 crc[1] = crc_calc; 486 if (wilc_spi_tx(wilc, crc, 2)) { 487 dev_err(&spi->dev, "Failed data block crc write, bus error...\n"); 488 result = -EINVAL; 489 break; 490 } 491 } 492 493 /* 494 * No need to wait for response 495 */ 496 ix += nbytes; 497 sz -= nbytes; 498 } while (sz); 499 500 return result; 501 } 502 503 /******************************************** 504 * 505 * Spi Internal Read/Write Function 506 * 507 ********************************************/ 508 static u8 wilc_get_crc7(u8 *buffer, u32 len) 509 { 510 return crc7_be(0xfe, buffer, len) | 0x01; 511 } 512 513 static int wilc_spi_single_read(struct wilc *wilc, u8 cmd, u32 adr, void *b, 514 u8 clockless) 515 { 516 struct spi_device *spi = to_spi_device(wilc->dev); 517 struct wilc_spi *spi_priv = wilc->bus_data; 518 u8 wb[32], rb[32]; 519 int cmd_len, resp_len, i; 520 u16 crc_calc, crc_recv; 521 struct wilc_spi_cmd *c; 522 struct wilc_spi_rsp_data *r; 523 struct wilc_spi_read_rsp_data *r_data; 524 525 memset(wb, 0x0, sizeof(wb)); 526 memset(rb, 0x0, sizeof(rb)); 527 c = (struct wilc_spi_cmd *)wb; 528 c->cmd_type = cmd; 529 if (cmd == CMD_SINGLE_READ) { 530 c->u.simple_cmd.addr[0] = adr >> 16; 531 c->u.simple_cmd.addr[1] = adr >> 8; 532 c->u.simple_cmd.addr[2] = adr; 533 } else if (cmd == CMD_INTERNAL_READ) { 534 c->u.simple_cmd.addr[0] = adr >> 8; 535 if (clockless == 1) 536 c->u.simple_cmd.addr[0] |= BIT(7); 537 c->u.simple_cmd.addr[1] = adr; 538 c->u.simple_cmd.addr[2] = 0x0; 539 } else { 540 dev_err(&spi->dev, "cmd [%x] not supported\n", cmd); 541 return -EINVAL; 542 } 543 544 cmd_len = offsetof(struct wilc_spi_cmd, u.simple_cmd.crc); 545 resp_len = sizeof(*r) + sizeof(*r_data) + WILC_SPI_RSP_HDR_EXTRA_DATA; 546 547 if (spi_priv->crc7_enabled) { 548 c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 549 cmd_len += 1; 550 resp_len += 2; 551 } 552 553 if (cmd_len + resp_len > ARRAY_SIZE(wb)) { 554 dev_err(&spi->dev, 555 "spi buffer size too small (%d) (%d) (%zu)\n", 556 cmd_len, resp_len, ARRAY_SIZE(wb)); 557 return -EINVAL; 558 } 559 560 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) { 561 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); 562 return -EINVAL; 563 } 564 565 r = (struct wilc_spi_rsp_data *)&rb[cmd_len]; 566 if (r->rsp_cmd_type != cmd && !clockless) { 567 if (!spi_priv->probing_crc) 568 dev_err(&spi->dev, 569 "Failed cmd, cmd (%02x), resp (%02x)\n", 570 cmd, r->rsp_cmd_type); 571 return -EINVAL; 572 } 573 574 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS && !clockless) { 575 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", 576 r->status); 577 return -EINVAL; 578 } 579 580 for (i = 0; i < WILC_SPI_RSP_HDR_EXTRA_DATA; ++i) 581 if (WILC_GET_RESP_HDR_START(r->data[i]) == 0xf) 582 break; 583 584 if (i >= WILC_SPI_RSP_HDR_EXTRA_DATA) { 585 dev_err(&spi->dev, "Error, data start missing\n"); 586 return -EINVAL; 587 } 588 589 r_data = (struct wilc_spi_read_rsp_data *)&r->data[i]; 590 591 if (b) 592 memcpy(b, r_data->data, 4); 593 594 if (!clockless && spi_priv->crc16_enabled) { 595 crc_recv = (r_data->crc[0] << 8) | r_data->crc[1]; 596 crc_calc = crc_itu_t(0xffff, r_data->data, 4); 597 if (crc_recv != crc_calc) { 598 dev_err(&spi->dev, "%s: bad CRC 0x%04x " 599 "(calculated 0x%04x)\n", __func__, 600 crc_recv, crc_calc); 601 return -EINVAL; 602 } 603 } 604 605 return 0; 606 } 607 608 static int wilc_spi_write_cmd(struct wilc *wilc, u8 cmd, u32 adr, u32 data, 609 u8 clockless) 610 { 611 struct spi_device *spi = to_spi_device(wilc->dev); 612 struct wilc_spi *spi_priv = wilc->bus_data; 613 u8 wb[32], rb[32]; 614 int cmd_len, resp_len; 615 struct wilc_spi_cmd *c; 616 struct wilc_spi_rsp_data *r; 617 618 memset(wb, 0x0, sizeof(wb)); 619 memset(rb, 0x0, sizeof(rb)); 620 c = (struct wilc_spi_cmd *)wb; 621 c->cmd_type = cmd; 622 if (cmd == CMD_INTERNAL_WRITE) { 623 c->u.internal_w_cmd.addr[0] = adr >> 8; 624 if (clockless == 1) 625 c->u.internal_w_cmd.addr[0] |= BIT(7); 626 627 c->u.internal_w_cmd.addr[1] = adr; 628 c->u.internal_w_cmd.data = cpu_to_be32(data); 629 cmd_len = offsetof(struct wilc_spi_cmd, u.internal_w_cmd.crc); 630 if (spi_priv->crc7_enabled) 631 c->u.internal_w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 632 } else if (cmd == CMD_SINGLE_WRITE) { 633 c->u.w_cmd.addr[0] = adr >> 16; 634 c->u.w_cmd.addr[1] = adr >> 8; 635 c->u.w_cmd.addr[2] = adr; 636 c->u.w_cmd.data = cpu_to_be32(data); 637 cmd_len = offsetof(struct wilc_spi_cmd, u.w_cmd.crc); 638 if (spi_priv->crc7_enabled) 639 c->u.w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 640 } else { 641 dev_err(&spi->dev, "write cmd [%x] not supported\n", cmd); 642 return -EINVAL; 643 } 644 645 if (spi_priv->crc7_enabled) 646 cmd_len += 1; 647 648 resp_len = sizeof(*r); 649 650 if (cmd_len + resp_len > ARRAY_SIZE(wb)) { 651 dev_err(&spi->dev, 652 "spi buffer size too small (%d) (%d) (%zu)\n", 653 cmd_len, resp_len, ARRAY_SIZE(wb)); 654 return -EINVAL; 655 } 656 657 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) { 658 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); 659 return -EINVAL; 660 } 661 662 r = (struct wilc_spi_rsp_data *)&rb[cmd_len]; 663 /* 664 * Clockless registers operations might return unexptected responses, 665 * even if successful. 666 */ 667 if (r->rsp_cmd_type != cmd && !clockless) { 668 dev_err(&spi->dev, 669 "Failed cmd response, cmd (%02x), resp (%02x)\n", 670 cmd, r->rsp_cmd_type); 671 return -EINVAL; 672 } 673 674 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS && !clockless) { 675 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", 676 r->status); 677 return -EINVAL; 678 } 679 680 return 0; 681 } 682 683 static int wilc_spi_dma_rw(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz) 684 { 685 struct spi_device *spi = to_spi_device(wilc->dev); 686 struct wilc_spi *spi_priv = wilc->bus_data; 687 u16 crc_recv, crc_calc; 688 u8 wb[32], rb[32]; 689 int cmd_len, resp_len; 690 int retry, ix = 0; 691 u8 crc[2]; 692 struct wilc_spi_cmd *c; 693 struct wilc_spi_rsp_data *r; 694 695 memset(wb, 0x0, sizeof(wb)); 696 memset(rb, 0x0, sizeof(rb)); 697 c = (struct wilc_spi_cmd *)wb; 698 c->cmd_type = cmd; 699 if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_READ) { 700 c->u.dma_cmd.addr[0] = adr >> 16; 701 c->u.dma_cmd.addr[1] = adr >> 8; 702 c->u.dma_cmd.addr[2] = adr; 703 c->u.dma_cmd.size[0] = sz >> 8; 704 c->u.dma_cmd.size[1] = sz; 705 cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd.crc); 706 if (spi_priv->crc7_enabled) 707 c->u.dma_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 708 } else if (cmd == CMD_DMA_EXT_WRITE || cmd == CMD_DMA_EXT_READ) { 709 c->u.dma_cmd_ext.addr[0] = adr >> 16; 710 c->u.dma_cmd_ext.addr[1] = adr >> 8; 711 c->u.dma_cmd_ext.addr[2] = adr; 712 c->u.dma_cmd_ext.size[0] = sz >> 16; 713 c->u.dma_cmd_ext.size[1] = sz >> 8; 714 c->u.dma_cmd_ext.size[2] = sz; 715 cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd_ext.crc); 716 if (spi_priv->crc7_enabled) 717 c->u.dma_cmd_ext.crc[0] = wilc_get_crc7(wb, cmd_len); 718 } else { 719 dev_err(&spi->dev, "dma read write cmd [%x] not supported\n", 720 cmd); 721 return -EINVAL; 722 } 723 if (spi_priv->crc7_enabled) 724 cmd_len += 1; 725 726 resp_len = sizeof(*r); 727 728 if (cmd_len + resp_len > ARRAY_SIZE(wb)) { 729 dev_err(&spi->dev, "spi buffer size too small (%d)(%d) (%zu)\n", 730 cmd_len, resp_len, ARRAY_SIZE(wb)); 731 return -EINVAL; 732 } 733 734 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) { 735 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); 736 return -EINVAL; 737 } 738 739 r = (struct wilc_spi_rsp_data *)&rb[cmd_len]; 740 if (r->rsp_cmd_type != cmd) { 741 dev_err(&spi->dev, 742 "Failed cmd response, cmd (%02x), resp (%02x)\n", 743 cmd, r->rsp_cmd_type); 744 return -EINVAL; 745 } 746 747 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) { 748 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", 749 r->status); 750 return -EINVAL; 751 } 752 753 if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_EXT_WRITE) 754 return 0; 755 756 while (sz > 0) { 757 int nbytes; 758 u8 rsp; 759 760 nbytes = min_t(u32, sz, DATA_PKT_SZ); 761 762 /* 763 * Data Response header 764 */ 765 retry = 100; 766 do { 767 if (wilc_spi_rx(wilc, &rsp, 1)) { 768 dev_err(&spi->dev, 769 "Failed resp read, bus err\n"); 770 return -EINVAL; 771 } 772 if (WILC_GET_RESP_HDR_START(rsp) == 0xf) 773 break; 774 } while (retry--); 775 776 /* 777 * Read bytes 778 */ 779 if (wilc_spi_rx(wilc, &b[ix], nbytes)) { 780 dev_err(&spi->dev, 781 "Failed block read, bus err\n"); 782 return -EINVAL; 783 } 784 785 /* 786 * Read CRC 787 */ 788 if (spi_priv->crc16_enabled) { 789 if (wilc_spi_rx(wilc, crc, 2)) { 790 dev_err(&spi->dev, 791 "Failed block CRC read, bus err\n"); 792 return -EINVAL; 793 } 794 crc_recv = (crc[0] << 8) | crc[1]; 795 crc_calc = crc_itu_t(0xffff, &b[ix], nbytes); 796 if (crc_recv != crc_calc) { 797 dev_err(&spi->dev, "%s: bad CRC 0x%04x " 798 "(calculated 0x%04x)\n", __func__, 799 crc_recv, crc_calc); 800 return -EINVAL; 801 } 802 } 803 804 ix += nbytes; 805 sz -= nbytes; 806 } 807 return 0; 808 } 809 810 static int wilc_spi_special_cmd(struct wilc *wilc, u8 cmd) 811 { 812 struct spi_device *spi = to_spi_device(wilc->dev); 813 struct wilc_spi *spi_priv = wilc->bus_data; 814 u8 wb[32], rb[32]; 815 int cmd_len, resp_len = 0; 816 struct wilc_spi_cmd *c; 817 struct wilc_spi_special_cmd_rsp *r; 818 819 if (cmd != CMD_TERMINATE && cmd != CMD_REPEAT && cmd != CMD_RESET) 820 return -EINVAL; 821 822 memset(wb, 0x0, sizeof(wb)); 823 memset(rb, 0x0, sizeof(rb)); 824 c = (struct wilc_spi_cmd *)wb; 825 c->cmd_type = cmd; 826 827 if (cmd == CMD_RESET) 828 memset(c->u.simple_cmd.addr, 0xFF, 3); 829 830 cmd_len = offsetof(struct wilc_spi_cmd, u.simple_cmd.crc); 831 resp_len = sizeof(*r); 832 833 if (spi_priv->crc7_enabled) { 834 c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 835 cmd_len += 1; 836 } 837 if (cmd_len + resp_len > ARRAY_SIZE(wb)) { 838 dev_err(&spi->dev, "spi buffer size too small (%d) (%d) (%zu)\n", 839 cmd_len, resp_len, ARRAY_SIZE(wb)); 840 return -EINVAL; 841 } 842 843 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) { 844 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); 845 return -EINVAL; 846 } 847 848 r = (struct wilc_spi_special_cmd_rsp *)&rb[cmd_len]; 849 if (r->rsp_cmd_type != cmd) { 850 if (!spi_priv->probing_crc) 851 dev_err(&spi->dev, 852 "Failed cmd response, cmd (%02x), resp (%02x)\n", 853 cmd, r->rsp_cmd_type); 854 return -EINVAL; 855 } 856 857 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) { 858 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", 859 r->status); 860 return -EINVAL; 861 } 862 return 0; 863 } 864 865 static void wilc_spi_reset_cmd_sequence(struct wilc *wl, u8 attempt, u32 addr) 866 { 867 struct spi_device *spi = to_spi_device(wl->dev); 868 struct wilc_spi *spi_priv = wl->bus_data; 869 870 if (!spi_priv->probing_crc) 871 dev_err(&spi->dev, "Reset and retry %d %x\n", attempt, addr); 872 873 usleep_range(1000, 1100); 874 wilc_spi_reset(wl); 875 usleep_range(1000, 1100); 876 } 877 878 static int wilc_spi_read_reg(struct wilc *wilc, u32 addr, u32 *data) 879 { 880 struct spi_device *spi = to_spi_device(wilc->dev); 881 int result; 882 u8 cmd = CMD_SINGLE_READ; 883 u8 clockless = 0; 884 u8 i; 885 886 if (addr <= WILC_SPI_CLOCKLESS_ADDR_LIMIT) { 887 /* Clockless register */ 888 cmd = CMD_INTERNAL_READ; 889 clockless = 1; 890 } 891 892 for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) { 893 result = wilc_spi_single_read(wilc, cmd, addr, data, clockless); 894 if (!result) { 895 le32_to_cpus(data); 896 return 0; 897 } 898 899 /* retry is not applicable for clockless registers */ 900 if (clockless) 901 break; 902 903 dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr); 904 wilc_spi_reset_cmd_sequence(wilc, i, addr); 905 } 906 907 return result; 908 } 909 910 static int wilc_spi_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size) 911 { 912 struct spi_device *spi = to_spi_device(wilc->dev); 913 int result; 914 u8 i; 915 916 if (size <= 4) 917 return -EINVAL; 918 919 for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) { 920 result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_READ, addr, 921 buf, size); 922 if (!result) 923 return 0; 924 925 dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr); 926 927 wilc_spi_reset_cmd_sequence(wilc, i, addr); 928 } 929 930 return result; 931 } 932 933 static int spi_internal_write(struct wilc *wilc, u32 adr, u32 dat) 934 { 935 struct spi_device *spi = to_spi_device(wilc->dev); 936 int result; 937 u8 i; 938 939 for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) { 940 result = wilc_spi_write_cmd(wilc, CMD_INTERNAL_WRITE, adr, 941 dat, 0); 942 if (!result) 943 return 0; 944 dev_err(&spi->dev, "Failed internal write cmd...\n"); 945 946 wilc_spi_reset_cmd_sequence(wilc, i, adr); 947 } 948 949 return result; 950 } 951 952 static int spi_internal_read(struct wilc *wilc, u32 adr, u32 *data) 953 { 954 struct spi_device *spi = to_spi_device(wilc->dev); 955 struct wilc_spi *spi_priv = wilc->bus_data; 956 int result; 957 u8 i; 958 959 for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) { 960 result = wilc_spi_single_read(wilc, CMD_INTERNAL_READ, adr, 961 data, 0); 962 if (!result) { 963 le32_to_cpus(data); 964 return 0; 965 } 966 if (!spi_priv->probing_crc) 967 dev_err(&spi->dev, "Failed internal read cmd...\n"); 968 969 wilc_spi_reset_cmd_sequence(wilc, i, adr); 970 } 971 972 return result; 973 } 974 975 /******************************************** 976 * 977 * Spi interfaces 978 * 979 ********************************************/ 980 981 static int wilc_spi_write_reg(struct wilc *wilc, u32 addr, u32 data) 982 { 983 struct spi_device *spi = to_spi_device(wilc->dev); 984 int result; 985 u8 cmd = CMD_SINGLE_WRITE; 986 u8 clockless = 0; 987 u8 i; 988 989 if (addr <= WILC_SPI_CLOCKLESS_ADDR_LIMIT) { 990 /* Clockless register */ 991 cmd = CMD_INTERNAL_WRITE; 992 clockless = 1; 993 } 994 995 for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) { 996 result = wilc_spi_write_cmd(wilc, cmd, addr, data, clockless); 997 if (!result) 998 return 0; 999 1000 dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr); 1001 1002 if (clockless) 1003 break; 1004 1005 wilc_spi_reset_cmd_sequence(wilc, i, addr); 1006 } 1007 return result; 1008 } 1009 1010 static int spi_data_rsp(struct wilc *wilc, u8 cmd) 1011 { 1012 struct spi_device *spi = to_spi_device(wilc->dev); 1013 int result, i; 1014 u8 rsp[4]; 1015 1016 /* 1017 * The response to data packets is two bytes long. For 1018 * efficiency's sake, wilc_spi_write() wisely ignores the 1019 * responses for all packets but the final one. The downside 1020 * of that optimization is that when the final data packet is 1021 * short, we may receive (part of) the response to the 1022 * second-to-last packet before the one for the final packet. 1023 * To handle this, we always read 4 bytes and then search for 1024 * the last byte that contains the "Response Start" code (0xc 1025 * in the top 4 bits). We then know that this byte is the 1026 * first response byte of the final data packet. 1027 */ 1028 result = wilc_spi_rx(wilc, rsp, sizeof(rsp)); 1029 if (result) { 1030 dev_err(&spi->dev, "Failed bus error...\n"); 1031 return result; 1032 } 1033 1034 for (i = sizeof(rsp) - 2; i >= 0; --i) 1035 if (FIELD_GET(RSP_START_FIELD, rsp[i]) == RSP_START_TAG) 1036 break; 1037 1038 if (i < 0) { 1039 dev_err(&spi->dev, 1040 "Data packet response missing (%02x %02x %02x %02x)\n", 1041 rsp[0], rsp[1], rsp[2], rsp[3]); 1042 return -1; 1043 } 1044 1045 /* rsp[i] is the last response start byte */ 1046 1047 if (FIELD_GET(RSP_TYPE_FIELD, rsp[i]) != RSP_TYPE_LAST_PACKET 1048 || rsp[i + 1] != RSP_STATE_NO_ERROR) { 1049 dev_err(&spi->dev, "Data response error (%02x %02x)\n", 1050 rsp[i], rsp[i + 1]); 1051 return -1; 1052 } 1053 return 0; 1054 } 1055 1056 static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size) 1057 { 1058 struct spi_device *spi = to_spi_device(wilc->dev); 1059 int result; 1060 u8 i; 1061 1062 /* 1063 * has to be greated than 4 1064 */ 1065 if (size <= 4) 1066 return -EINVAL; 1067 1068 for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) { 1069 result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_WRITE, addr, 1070 NULL, size); 1071 if (result) { 1072 dev_err(&spi->dev, 1073 "Failed cmd, write block (%08x)...\n", addr); 1074 wilc_spi_reset_cmd_sequence(wilc, i, addr); 1075 continue; 1076 } 1077 1078 /* 1079 * Data 1080 */ 1081 result = spi_data_write(wilc, buf, size); 1082 if (result) { 1083 dev_err(&spi->dev, "Failed block data write...\n"); 1084 wilc_spi_reset_cmd_sequence(wilc, i, addr); 1085 continue; 1086 } 1087 1088 /* 1089 * Data response 1090 */ 1091 result = spi_data_rsp(wilc, CMD_DMA_EXT_WRITE); 1092 if (result) { 1093 dev_err(&spi->dev, "Failed block data rsp...\n"); 1094 wilc_spi_reset_cmd_sequence(wilc, i, addr); 1095 continue; 1096 } 1097 break; 1098 } 1099 return result; 1100 } 1101 1102 /******************************************** 1103 * 1104 * Bus interfaces 1105 * 1106 ********************************************/ 1107 1108 static int wilc_spi_reset(struct wilc *wilc) 1109 { 1110 struct spi_device *spi = to_spi_device(wilc->dev); 1111 struct wilc_spi *spi_priv = wilc->bus_data; 1112 int result; 1113 1114 result = wilc_spi_special_cmd(wilc, CMD_RESET); 1115 if (result && !spi_priv->probing_crc) 1116 dev_err(&spi->dev, "Failed cmd reset\n"); 1117 1118 return result; 1119 } 1120 1121 static bool wilc_spi_is_init(struct wilc *wilc) 1122 { 1123 struct wilc_spi *spi_priv = wilc->bus_data; 1124 1125 return spi_priv->isinit; 1126 } 1127 1128 static int wilc_spi_deinit(struct wilc *wilc) 1129 { 1130 struct wilc_spi *spi_priv = wilc->bus_data; 1131 1132 spi_priv->isinit = false; 1133 wilc_wlan_power(wilc, false); 1134 return 0; 1135 } 1136 1137 static int wilc_spi_init(struct wilc *wilc, bool resume) 1138 { 1139 struct wilc_spi *spi_priv = wilc->bus_data; 1140 int ret; 1141 1142 if (spi_priv->isinit) { 1143 /* Confirm we can read chipid register without error: */ 1144 if (wilc_validate_chipid(wilc) == 0) 1145 return 0; 1146 } 1147 1148 wilc_wlan_power(wilc, true); 1149 1150 ret = wilc_spi_configure_bus_protocol(wilc); 1151 if (ret) { 1152 wilc_wlan_power(wilc, false); 1153 return ret; 1154 } 1155 1156 spi_priv->isinit = true; 1157 1158 return 0; 1159 } 1160 1161 static int wilc_spi_configure_bus_protocol(struct wilc *wilc) 1162 { 1163 struct spi_device *spi = to_spi_device(wilc->dev); 1164 struct wilc_spi *spi_priv = wilc->bus_data; 1165 u32 reg; 1166 int ret, i; 1167 1168 /* 1169 * Infer the CRC settings that are currently in effect. This 1170 * is necessary because we can't be sure that the chip has 1171 * been RESET (e.g, after module unload and reload). 1172 */ 1173 spi_priv->probing_crc = true; 1174 spi_priv->crc7_enabled = enable_crc7; 1175 spi_priv->crc16_enabled = false; /* don't check CRC16 during probing */ 1176 for (i = 0; i < 2; ++i) { 1177 ret = spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®); 1178 if (ret == 0) 1179 break; 1180 spi_priv->crc7_enabled = !enable_crc7; 1181 } 1182 if (ret) { 1183 dev_err(&spi->dev, "Failed with CRC7 on and off.\n"); 1184 return ret; 1185 } 1186 1187 /* set up the desired CRC configuration: */ 1188 reg &= ~(PROTOCOL_REG_CRC7_MASK | PROTOCOL_REG_CRC16_MASK); 1189 if (enable_crc7) 1190 reg |= PROTOCOL_REG_CRC7_MASK; 1191 if (enable_crc16) 1192 reg |= PROTOCOL_REG_CRC16_MASK; 1193 1194 /* set up the data packet size: */ 1195 BUILD_BUG_ON(DATA_PKT_LOG_SZ < DATA_PKT_LOG_SZ_MIN 1196 || DATA_PKT_LOG_SZ > DATA_PKT_LOG_SZ_MAX); 1197 reg &= ~PROTOCOL_REG_PKT_SZ_MASK; 1198 reg |= FIELD_PREP(PROTOCOL_REG_PKT_SZ_MASK, 1199 DATA_PKT_LOG_SZ - DATA_PKT_LOG_SZ_MIN); 1200 1201 /* establish the new setup: */ 1202 ret = spi_internal_write(wilc, WILC_SPI_PROTOCOL_OFFSET, reg); 1203 if (ret) { 1204 dev_err(&spi->dev, 1205 "[wilc spi %d]: Failed internal write reg\n", 1206 __LINE__); 1207 return ret; 1208 } 1209 /* update our state to match new protocol settings: */ 1210 spi_priv->crc7_enabled = enable_crc7; 1211 spi_priv->crc16_enabled = enable_crc16; 1212 1213 /* re-read to make sure new settings are in effect: */ 1214 spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®); 1215 1216 spi_priv->probing_crc = false; 1217 1218 return 0; 1219 } 1220 1221 static int wilc_validate_chipid(struct wilc *wilc) 1222 { 1223 struct spi_device *spi = to_spi_device(wilc->dev); 1224 u32 chipid; 1225 int ret; 1226 1227 /* 1228 * make sure can read chip id without protocol error 1229 */ 1230 ret = wilc_spi_read_reg(wilc, WILC_CHIPID, &chipid); 1231 if (ret) { 1232 dev_err(&spi->dev, "Fail cmd read chip id...\n"); 1233 return ret; 1234 } 1235 if (!is_wilc1000(chipid)) { 1236 dev_err(&spi->dev, "Unknown chip id 0x%x\n", chipid); 1237 return -ENODEV; 1238 } 1239 return 0; 1240 } 1241 1242 static int wilc_spi_read_size(struct wilc *wilc, u32 *size) 1243 { 1244 int ret; 1245 1246 ret = spi_internal_read(wilc, 1247 WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, size); 1248 *size = FIELD_GET(IRQ_DMA_WD_CNT_MASK, *size); 1249 1250 return ret; 1251 } 1252 1253 static int wilc_spi_read_int(struct wilc *wilc, u32 *int_status) 1254 { 1255 return spi_internal_read(wilc, WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, 1256 int_status); 1257 } 1258 1259 static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val) 1260 { 1261 int ret; 1262 int retry = SPI_ENABLE_VMM_RETRY_LIMIT; 1263 u32 check; 1264 1265 while (retry) { 1266 ret = spi_internal_write(wilc, 1267 WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE, 1268 val); 1269 if (ret) 1270 break; 1271 1272 ret = spi_internal_read(wilc, 1273 WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE, 1274 &check); 1275 if (ret || ((check & EN_VMM) == (val & EN_VMM))) 1276 break; 1277 1278 retry--; 1279 } 1280 return ret; 1281 } 1282 1283 static int wilc_spi_sync_ext(struct wilc *wilc, int nint) 1284 { 1285 struct spi_device *spi = to_spi_device(wilc->dev); 1286 u32 reg; 1287 int ret, i; 1288 1289 if (nint > MAX_NUM_INT) { 1290 dev_err(&spi->dev, "Too many interrupts (%d)...\n", nint); 1291 return -EINVAL; 1292 } 1293 1294 /* 1295 * interrupt pin mux select 1296 */ 1297 ret = wilc_spi_read_reg(wilc, WILC_PIN_MUX_0, ®); 1298 if (ret) { 1299 dev_err(&spi->dev, "Failed read reg (%08x)...\n", 1300 WILC_PIN_MUX_0); 1301 return ret; 1302 } 1303 reg |= BIT(8); 1304 ret = wilc_spi_write_reg(wilc, WILC_PIN_MUX_0, reg); 1305 if (ret) { 1306 dev_err(&spi->dev, "Failed write reg (%08x)...\n", 1307 WILC_PIN_MUX_0); 1308 return ret; 1309 } 1310 1311 /* 1312 * interrupt enable 1313 */ 1314 ret = wilc_spi_read_reg(wilc, WILC_INTR_ENABLE, ®); 1315 if (ret) { 1316 dev_err(&spi->dev, "Failed read reg (%08x)...\n", 1317 WILC_INTR_ENABLE); 1318 return ret; 1319 } 1320 1321 for (i = 0; (i < 5) && (nint > 0); i++, nint--) 1322 reg |= (BIT((27 + i))); 1323 1324 ret = wilc_spi_write_reg(wilc, WILC_INTR_ENABLE, reg); 1325 if (ret) { 1326 dev_err(&spi->dev, "Failed write reg (%08x)...\n", 1327 WILC_INTR_ENABLE); 1328 return ret; 1329 } 1330 if (nint) { 1331 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, ®); 1332 if (ret) { 1333 dev_err(&spi->dev, "Failed read reg (%08x)...\n", 1334 WILC_INTR2_ENABLE); 1335 return ret; 1336 } 1337 1338 for (i = 0; (i < 3) && (nint > 0); i++, nint--) 1339 reg |= BIT(i); 1340 1341 ret = wilc_spi_write_reg(wilc, WILC_INTR2_ENABLE, reg); 1342 if (ret) { 1343 dev_err(&spi->dev, "Failed write reg (%08x)...\n", 1344 WILC_INTR2_ENABLE); 1345 return ret; 1346 } 1347 } 1348 1349 return 0; 1350 } 1351 1352 /* Global spi HIF function table */ 1353 static const struct wilc_hif_func wilc_hif_spi = { 1354 .hif_init = wilc_spi_init, 1355 .hif_deinit = wilc_spi_deinit, 1356 .hif_read_reg = wilc_spi_read_reg, 1357 .hif_write_reg = wilc_spi_write_reg, 1358 .hif_block_rx = wilc_spi_read, 1359 .hif_block_tx = wilc_spi_write, 1360 .hif_read_int = wilc_spi_read_int, 1361 .hif_clear_int_ext = wilc_spi_clear_int_ext, 1362 .hif_read_size = wilc_spi_read_size, 1363 .hif_block_tx_ext = wilc_spi_write, 1364 .hif_block_rx_ext = wilc_spi_read, 1365 .hif_sync_ext = wilc_spi_sync_ext, 1366 .hif_reset = wilc_spi_reset, 1367 .hif_is_init = wilc_spi_is_init, 1368 }; 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