1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries. 4 * All rights reserved. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/spi/spi.h> 9 #include <linux/crc7.h> 10 #include <linux/crc-itu-t.h> 11 #include <linux/gpio/consumer.h> 12 13 #include "netdev.h" 14 #include "cfg80211.h" 15 16 #define SPI_MODALIAS "wilc1000_spi" 17 18 static bool enable_crc7; /* protect SPI commands with CRC7 */ 19 module_param(enable_crc7, bool, 0644); 20 MODULE_PARM_DESC(enable_crc7, 21 "Enable CRC7 checksum to protect command transfers\n" 22 "\t\t\tagainst corruption during the SPI transfer.\n" 23 "\t\t\tCommand transfers are short and the CPU-cycle cost\n" 24 "\t\t\tof enabling this is small."); 25 26 static bool enable_crc16; /* protect SPI data with CRC16 */ 27 module_param(enable_crc16, bool, 0644); 28 MODULE_PARM_DESC(enable_crc16, 29 "Enable CRC16 checksum to protect data transfers\n" 30 "\t\t\tagainst corruption during the SPI transfer.\n" 31 "\t\t\tData transfers can be large and the CPU-cycle cost\n" 32 "\t\t\tof enabling this may be substantial."); 33 34 /* 35 * For CMD_SINGLE_READ and CMD_INTERNAL_READ, WILC may insert one or 36 * more zero bytes between the command response and the DATA Start tag 37 * (0xf3). This behavior appears to be undocumented in "ATWILC1000 38 * USER GUIDE" (https://tinyurl.com/4hhshdts) but we have observed 1-4 39 * zero bytes when the SPI bus operates at 48MHz and none when it 40 * operates at 1MHz. 41 */ 42 #define WILC_SPI_RSP_HDR_EXTRA_DATA 8 43 44 struct wilc_spi { 45 bool isinit; /* true if SPI protocol has been configured */ 46 bool probing_crc; /* true if we're probing chip's CRC config */ 47 bool crc7_enabled; /* true if crc7 is currently enabled */ 48 bool crc16_enabled; /* true if crc16 is currently enabled */ 49 struct wilc_gpios { 50 struct gpio_desc *enable; /* ENABLE GPIO or NULL */ 51 struct gpio_desc *reset; /* RESET GPIO or NULL */ 52 } gpios; 53 }; 54 55 static const struct wilc_hif_func wilc_hif_spi; 56 57 static int wilc_spi_reset(struct wilc *wilc); 58 59 /******************************************** 60 * 61 * Spi protocol Function 62 * 63 ********************************************/ 64 65 #define CMD_DMA_WRITE 0xc1 66 #define CMD_DMA_READ 0xc2 67 #define CMD_INTERNAL_WRITE 0xc3 68 #define CMD_INTERNAL_READ 0xc4 69 #define CMD_TERMINATE 0xc5 70 #define CMD_REPEAT 0xc6 71 #define CMD_DMA_EXT_WRITE 0xc7 72 #define CMD_DMA_EXT_READ 0xc8 73 #define CMD_SINGLE_WRITE 0xc9 74 #define CMD_SINGLE_READ 0xca 75 #define CMD_RESET 0xcf 76 77 #define SPI_RETRY_MAX_LIMIT 10 78 #define SPI_ENABLE_VMM_RETRY_LIMIT 2 79 80 /* SPI response fields (section 11.1.2 in ATWILC1000 User Guide): */ 81 #define RSP_START_FIELD GENMASK(7, 4) 82 #define RSP_TYPE_FIELD GENMASK(3, 0) 83 84 /* SPI response values for the response fields: */ 85 #define RSP_START_TAG 0xc 86 #define RSP_TYPE_FIRST_PACKET 0x1 87 #define RSP_TYPE_INNER_PACKET 0x2 88 #define RSP_TYPE_LAST_PACKET 0x3 89 #define RSP_STATE_NO_ERROR 0x00 90 91 #define PROTOCOL_REG_PKT_SZ_MASK GENMASK(6, 4) 92 #define PROTOCOL_REG_CRC16_MASK GENMASK(3, 3) 93 #define PROTOCOL_REG_CRC7_MASK GENMASK(2, 2) 94 95 /* 96 * The SPI data packet size may be any integer power of two in the 97 * range from 256 to 8192 bytes. 98 */ 99 #define DATA_PKT_LOG_SZ_MIN 8 /* 256 B */ 100 #define DATA_PKT_LOG_SZ_MAX 13 /* 8 KiB */ 101 102 /* 103 * Select the data packet size (log2 of number of bytes): Use the 104 * maximum data packet size. We only retransmit complete packets, so 105 * there is no benefit from using smaller data packets. 106 */ 107 #define DATA_PKT_LOG_SZ DATA_PKT_LOG_SZ_MAX 108 #define DATA_PKT_SZ (1 << DATA_PKT_LOG_SZ) 109 110 #define WILC_SPI_COMMAND_STAT_SUCCESS 0 111 #define WILC_GET_RESP_HDR_START(h) (((h) >> 4) & 0xf) 112 113 struct wilc_spi_cmd { 114 u8 cmd_type; 115 union { 116 struct { 117 u8 addr[3]; 118 u8 crc[]; 119 } __packed simple_cmd; 120 struct { 121 u8 addr[3]; 122 u8 size[2]; 123 u8 crc[]; 124 } __packed dma_cmd; 125 struct { 126 u8 addr[3]; 127 u8 size[3]; 128 u8 crc[]; 129 } __packed dma_cmd_ext; 130 struct { 131 u8 addr[2]; 132 __be32 data; 133 u8 crc[]; 134 } __packed internal_w_cmd; 135 struct { 136 u8 addr[3]; 137 __be32 data; 138 u8 crc[]; 139 } __packed w_cmd; 140 } u; 141 } __packed; 142 143 struct wilc_spi_read_rsp_data { 144 u8 header; 145 u8 data[4]; 146 u8 crc[]; 147 } __packed; 148 149 struct wilc_spi_rsp_data { 150 u8 rsp_cmd_type; 151 u8 status; 152 u8 data[]; 153 } __packed; 154 155 struct wilc_spi_special_cmd_rsp { 156 u8 skip_byte; 157 u8 rsp_cmd_type; 158 u8 status; 159 } __packed; 160 161 static int wilc_parse_gpios(struct wilc *wilc) 162 { 163 struct spi_device *spi = to_spi_device(wilc->dev); 164 struct wilc_spi *spi_priv = wilc->bus_data; 165 struct wilc_gpios *gpios = &spi_priv->gpios; 166 167 /* get ENABLE pin and deassert it (if it is defined): */ 168 gpios->enable = devm_gpiod_get_optional(&spi->dev, 169 "enable", GPIOD_OUT_LOW); 170 /* get RESET pin and assert it (if it is defined): */ 171 if (gpios->enable) { 172 /* if enable pin exists, reset must exist as well */ 173 gpios->reset = devm_gpiod_get(&spi->dev, 174 "reset", GPIOD_OUT_HIGH); 175 if (IS_ERR(gpios->reset)) { 176 dev_err(&spi->dev, "missing reset gpio.\n"); 177 return PTR_ERR(gpios->reset); 178 } 179 } else { 180 gpios->reset = devm_gpiod_get_optional(&spi->dev, 181 "reset", GPIOD_OUT_HIGH); 182 } 183 return 0; 184 } 185 186 static void wilc_wlan_power(struct wilc *wilc, bool on) 187 { 188 struct wilc_spi *spi_priv = wilc->bus_data; 189 struct wilc_gpios *gpios = &spi_priv->gpios; 190 191 if (on) { 192 /* assert ENABLE: */ 193 gpiod_set_value(gpios->enable, 1); 194 mdelay(5); 195 /* assert RESET: */ 196 gpiod_set_value(gpios->reset, 1); 197 } else { 198 /* deassert RESET: */ 199 gpiod_set_value(gpios->reset, 0); 200 /* deassert ENABLE: */ 201 gpiod_set_value(gpios->enable, 0); 202 } 203 } 204 205 static int wilc_bus_probe(struct spi_device *spi) 206 { 207 int ret; 208 struct wilc *wilc; 209 struct wilc_spi *spi_priv; 210 211 spi_priv = kzalloc(sizeof(*spi_priv), GFP_KERNEL); 212 if (!spi_priv) 213 return -ENOMEM; 214 215 ret = wilc_cfg80211_init(&wilc, &spi->dev, WILC_HIF_SPI, &wilc_hif_spi); 216 if (ret) 217 goto free; 218 219 spi_set_drvdata(spi, wilc); 220 wilc->dev = &spi->dev; 221 wilc->bus_data = spi_priv; 222 wilc->dev_irq_num = spi->irq; 223 224 ret = wilc_parse_gpios(wilc); 225 if (ret < 0) 226 goto netdev_cleanup; 227 228 wilc->rtc_clk = devm_clk_get_optional(&spi->dev, "rtc"); 229 if (IS_ERR(wilc->rtc_clk)) { 230 ret = PTR_ERR(wilc->rtc_clk); 231 goto netdev_cleanup; 232 } 233 clk_prepare_enable(wilc->rtc_clk); 234 235 return 0; 236 237 netdev_cleanup: 238 wilc_netdev_cleanup(wilc); 239 free: 240 kfree(spi_priv); 241 return ret; 242 } 243 244 static void wilc_bus_remove(struct spi_device *spi) 245 { 246 struct wilc *wilc = spi_get_drvdata(spi); 247 struct wilc_spi *spi_priv = wilc->bus_data; 248 249 clk_disable_unprepare(wilc->rtc_clk); 250 wilc_netdev_cleanup(wilc); 251 kfree(spi_priv); 252 } 253 254 static const struct of_device_id wilc_of_match[] = { 255 { .compatible = "microchip,wilc1000", }, 256 { /* sentinel */ } 257 }; 258 MODULE_DEVICE_TABLE(of, wilc_of_match); 259 260 static const struct spi_device_id wilc_spi_id[] = { 261 { "wilc1000", 0 }, 262 { /* sentinel */ } 263 }; 264 MODULE_DEVICE_TABLE(spi, wilc_spi_id); 265 266 static struct spi_driver wilc_spi_driver = { 267 .driver = { 268 .name = SPI_MODALIAS, 269 .of_match_table = wilc_of_match, 270 }, 271 .id_table = wilc_spi_id, 272 .probe = wilc_bus_probe, 273 .remove = wilc_bus_remove, 274 }; 275 module_spi_driver(wilc_spi_driver); 276 MODULE_DESCRIPTION("Atmel WILC1000 SPI wireless driver"); 277 MODULE_LICENSE("GPL"); 278 279 static int wilc_spi_tx(struct wilc *wilc, u8 *b, u32 len) 280 { 281 struct spi_device *spi = to_spi_device(wilc->dev); 282 int ret; 283 struct spi_message msg; 284 285 if (len > 0 && b) { 286 struct spi_transfer tr = { 287 .tx_buf = b, 288 .len = len, 289 .delay = { 290 .value = 0, 291 .unit = SPI_DELAY_UNIT_USECS 292 }, 293 }; 294 char *r_buffer = kzalloc(len, GFP_KERNEL); 295 296 if (!r_buffer) 297 return -ENOMEM; 298 299 tr.rx_buf = r_buffer; 300 dev_dbg(&spi->dev, "Request writing %d bytes\n", len); 301 302 memset(&msg, 0, sizeof(msg)); 303 spi_message_init(&msg); 304 msg.spi = spi; 305 spi_message_add_tail(&tr, &msg); 306 307 ret = spi_sync(spi, &msg); 308 if (ret < 0) 309 dev_err(&spi->dev, "SPI transaction failed\n"); 310 311 kfree(r_buffer); 312 } else { 313 dev_err(&spi->dev, 314 "can't write data with the following length: %d\n", 315 len); 316 ret = -EINVAL; 317 } 318 319 return ret; 320 } 321 322 static int wilc_spi_rx(struct wilc *wilc, u8 *rb, u32 rlen) 323 { 324 struct spi_device *spi = to_spi_device(wilc->dev); 325 int ret; 326 327 if (rlen > 0) { 328 struct spi_message msg; 329 struct spi_transfer tr = { 330 .rx_buf = rb, 331 .len = rlen, 332 .delay = { 333 .value = 0, 334 .unit = SPI_DELAY_UNIT_USECS 335 }, 336 337 }; 338 char *t_buffer = kzalloc(rlen, GFP_KERNEL); 339 340 if (!t_buffer) 341 return -ENOMEM; 342 343 tr.tx_buf = t_buffer; 344 345 memset(&msg, 0, sizeof(msg)); 346 spi_message_init(&msg); 347 msg.spi = spi; 348 spi_message_add_tail(&tr, &msg); 349 350 ret = spi_sync(spi, &msg); 351 if (ret < 0) 352 dev_err(&spi->dev, "SPI transaction failed\n"); 353 kfree(t_buffer); 354 } else { 355 dev_err(&spi->dev, 356 "can't read data with the following length: %u\n", 357 rlen); 358 ret = -EINVAL; 359 } 360 361 return ret; 362 } 363 364 static int wilc_spi_tx_rx(struct wilc *wilc, u8 *wb, u8 *rb, u32 rlen) 365 { 366 struct spi_device *spi = to_spi_device(wilc->dev); 367 int ret; 368 369 if (rlen > 0) { 370 struct spi_message msg; 371 struct spi_transfer tr = { 372 .rx_buf = rb, 373 .tx_buf = wb, 374 .len = rlen, 375 .bits_per_word = 8, 376 .delay = { 377 .value = 0, 378 .unit = SPI_DELAY_UNIT_USECS 379 }, 380 381 }; 382 383 memset(&msg, 0, sizeof(msg)); 384 spi_message_init(&msg); 385 msg.spi = spi; 386 387 spi_message_add_tail(&tr, &msg); 388 ret = spi_sync(spi, &msg); 389 if (ret < 0) 390 dev_err(&spi->dev, "SPI transaction failed\n"); 391 } else { 392 dev_err(&spi->dev, 393 "can't read data with the following length: %u\n", 394 rlen); 395 ret = -EINVAL; 396 } 397 398 return ret; 399 } 400 401 static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz) 402 { 403 struct spi_device *spi = to_spi_device(wilc->dev); 404 struct wilc_spi *spi_priv = wilc->bus_data; 405 int ix, nbytes; 406 int result = 0; 407 u8 cmd, order, crc[2]; 408 u16 crc_calc; 409 410 /* 411 * Data 412 */ 413 ix = 0; 414 do { 415 if (sz <= DATA_PKT_SZ) { 416 nbytes = sz; 417 order = 0x3; 418 } else { 419 nbytes = DATA_PKT_SZ; 420 if (ix == 0) 421 order = 0x1; 422 else 423 order = 0x02; 424 } 425 426 /* 427 * Write command 428 */ 429 cmd = 0xf0; 430 cmd |= order; 431 432 if (wilc_spi_tx(wilc, &cmd, 1)) { 433 dev_err(&spi->dev, 434 "Failed data block cmd write, bus error...\n"); 435 result = -EINVAL; 436 break; 437 } 438 439 /* 440 * Write data 441 */ 442 if (wilc_spi_tx(wilc, &b[ix], nbytes)) { 443 dev_err(&spi->dev, 444 "Failed data block write, bus error...\n"); 445 result = -EINVAL; 446 break; 447 } 448 449 /* 450 * Write CRC 451 */ 452 if (spi_priv->crc16_enabled) { 453 crc_calc = crc_itu_t(0xffff, &b[ix], nbytes); 454 crc[0] = crc_calc >> 8; 455 crc[1] = crc_calc; 456 if (wilc_spi_tx(wilc, crc, 2)) { 457 dev_err(&spi->dev, "Failed data block crc write, bus error...\n"); 458 result = -EINVAL; 459 break; 460 } 461 } 462 463 /* 464 * No need to wait for response 465 */ 466 ix += nbytes; 467 sz -= nbytes; 468 } while (sz); 469 470 return result; 471 } 472 473 /******************************************** 474 * 475 * Spi Internal Read/Write Function 476 * 477 ********************************************/ 478 static u8 wilc_get_crc7(u8 *buffer, u32 len) 479 { 480 return crc7_be(0xfe, buffer, len); 481 } 482 483 static int wilc_spi_single_read(struct wilc *wilc, u8 cmd, u32 adr, void *b, 484 u8 clockless) 485 { 486 struct spi_device *spi = to_spi_device(wilc->dev); 487 struct wilc_spi *spi_priv = wilc->bus_data; 488 u8 wb[32], rb[32]; 489 int cmd_len, resp_len, i; 490 u16 crc_calc, crc_recv; 491 struct wilc_spi_cmd *c; 492 struct wilc_spi_rsp_data *r; 493 struct wilc_spi_read_rsp_data *r_data; 494 495 memset(wb, 0x0, sizeof(wb)); 496 memset(rb, 0x0, sizeof(rb)); 497 c = (struct wilc_spi_cmd *)wb; 498 c->cmd_type = cmd; 499 if (cmd == CMD_SINGLE_READ) { 500 c->u.simple_cmd.addr[0] = adr >> 16; 501 c->u.simple_cmd.addr[1] = adr >> 8; 502 c->u.simple_cmd.addr[2] = adr; 503 } else if (cmd == CMD_INTERNAL_READ) { 504 c->u.simple_cmd.addr[0] = adr >> 8; 505 if (clockless == 1) 506 c->u.simple_cmd.addr[0] |= BIT(7); 507 c->u.simple_cmd.addr[1] = adr; 508 c->u.simple_cmd.addr[2] = 0x0; 509 } else { 510 dev_err(&spi->dev, "cmd [%x] not supported\n", cmd); 511 return -EINVAL; 512 } 513 514 cmd_len = offsetof(struct wilc_spi_cmd, u.simple_cmd.crc); 515 resp_len = sizeof(*r) + sizeof(*r_data) + WILC_SPI_RSP_HDR_EXTRA_DATA; 516 517 if (spi_priv->crc7_enabled) { 518 c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 519 cmd_len += 1; 520 resp_len += 2; 521 } 522 523 if (cmd_len + resp_len > ARRAY_SIZE(wb)) { 524 dev_err(&spi->dev, 525 "spi buffer size too small (%d) (%d) (%zu)\n", 526 cmd_len, resp_len, ARRAY_SIZE(wb)); 527 return -EINVAL; 528 } 529 530 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) { 531 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); 532 return -EINVAL; 533 } 534 535 r = (struct wilc_spi_rsp_data *)&rb[cmd_len]; 536 if (r->rsp_cmd_type != cmd && !clockless) { 537 if (!spi_priv->probing_crc) 538 dev_err(&spi->dev, 539 "Failed cmd, cmd (%02x), resp (%02x)\n", 540 cmd, r->rsp_cmd_type); 541 return -EINVAL; 542 } 543 544 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS && !clockless) { 545 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", 546 r->status); 547 return -EINVAL; 548 } 549 550 for (i = 0; i < WILC_SPI_RSP_HDR_EXTRA_DATA; ++i) 551 if (WILC_GET_RESP_HDR_START(r->data[i]) == 0xf) 552 break; 553 554 if (i >= WILC_SPI_RSP_HDR_EXTRA_DATA) { 555 dev_err(&spi->dev, "Error, data start missing\n"); 556 return -EINVAL; 557 } 558 559 r_data = (struct wilc_spi_read_rsp_data *)&r->data[i]; 560 561 if (b) 562 memcpy(b, r_data->data, 4); 563 564 if (!clockless && spi_priv->crc16_enabled) { 565 crc_recv = (r_data->crc[0] << 8) | r_data->crc[1]; 566 crc_calc = crc_itu_t(0xffff, r_data->data, 4); 567 if (crc_recv != crc_calc) { 568 dev_err(&spi->dev, "%s: bad CRC 0x%04x " 569 "(calculated 0x%04x)\n", __func__, 570 crc_recv, crc_calc); 571 return -EINVAL; 572 } 573 } 574 575 return 0; 576 } 577 578 static int wilc_spi_write_cmd(struct wilc *wilc, u8 cmd, u32 adr, u32 data, 579 u8 clockless) 580 { 581 struct spi_device *spi = to_spi_device(wilc->dev); 582 struct wilc_spi *spi_priv = wilc->bus_data; 583 u8 wb[32], rb[32]; 584 int cmd_len, resp_len; 585 struct wilc_spi_cmd *c; 586 struct wilc_spi_rsp_data *r; 587 588 memset(wb, 0x0, sizeof(wb)); 589 memset(rb, 0x0, sizeof(rb)); 590 c = (struct wilc_spi_cmd *)wb; 591 c->cmd_type = cmd; 592 if (cmd == CMD_INTERNAL_WRITE) { 593 c->u.internal_w_cmd.addr[0] = adr >> 8; 594 if (clockless == 1) 595 c->u.internal_w_cmd.addr[0] |= BIT(7); 596 597 c->u.internal_w_cmd.addr[1] = adr; 598 c->u.internal_w_cmd.data = cpu_to_be32(data); 599 cmd_len = offsetof(struct wilc_spi_cmd, u.internal_w_cmd.crc); 600 if (spi_priv->crc7_enabled) 601 c->u.internal_w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 602 } else if (cmd == CMD_SINGLE_WRITE) { 603 c->u.w_cmd.addr[0] = adr >> 16; 604 c->u.w_cmd.addr[1] = adr >> 8; 605 c->u.w_cmd.addr[2] = adr; 606 c->u.w_cmd.data = cpu_to_be32(data); 607 cmd_len = offsetof(struct wilc_spi_cmd, u.w_cmd.crc); 608 if (spi_priv->crc7_enabled) 609 c->u.w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 610 } else { 611 dev_err(&spi->dev, "write cmd [%x] not supported\n", cmd); 612 return -EINVAL; 613 } 614 615 if (spi_priv->crc7_enabled) 616 cmd_len += 1; 617 618 resp_len = sizeof(*r); 619 620 if (cmd_len + resp_len > ARRAY_SIZE(wb)) { 621 dev_err(&spi->dev, 622 "spi buffer size too small (%d) (%d) (%zu)\n", 623 cmd_len, resp_len, ARRAY_SIZE(wb)); 624 return -EINVAL; 625 } 626 627 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) { 628 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); 629 return -EINVAL; 630 } 631 632 r = (struct wilc_spi_rsp_data *)&rb[cmd_len]; 633 /* 634 * Clockless registers operations might return unexptected responses, 635 * even if successful. 636 */ 637 if (r->rsp_cmd_type != cmd && !clockless) { 638 dev_err(&spi->dev, 639 "Failed cmd response, cmd (%02x), resp (%02x)\n", 640 cmd, r->rsp_cmd_type); 641 return -EINVAL; 642 } 643 644 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS && !clockless) { 645 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", 646 r->status); 647 return -EINVAL; 648 } 649 650 return 0; 651 } 652 653 static int wilc_spi_dma_rw(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz) 654 { 655 struct spi_device *spi = to_spi_device(wilc->dev); 656 struct wilc_spi *spi_priv = wilc->bus_data; 657 u16 crc_recv, crc_calc; 658 u8 wb[32], rb[32]; 659 int cmd_len, resp_len; 660 int retry, ix = 0; 661 u8 crc[2]; 662 struct wilc_spi_cmd *c; 663 struct wilc_spi_rsp_data *r; 664 665 memset(wb, 0x0, sizeof(wb)); 666 memset(rb, 0x0, sizeof(rb)); 667 c = (struct wilc_spi_cmd *)wb; 668 c->cmd_type = cmd; 669 if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_READ) { 670 c->u.dma_cmd.addr[0] = adr >> 16; 671 c->u.dma_cmd.addr[1] = adr >> 8; 672 c->u.dma_cmd.addr[2] = adr; 673 c->u.dma_cmd.size[0] = sz >> 8; 674 c->u.dma_cmd.size[1] = sz; 675 cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd.crc); 676 if (spi_priv->crc7_enabled) 677 c->u.dma_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 678 } else if (cmd == CMD_DMA_EXT_WRITE || cmd == CMD_DMA_EXT_READ) { 679 c->u.dma_cmd_ext.addr[0] = adr >> 16; 680 c->u.dma_cmd_ext.addr[1] = adr >> 8; 681 c->u.dma_cmd_ext.addr[2] = adr; 682 c->u.dma_cmd_ext.size[0] = sz >> 16; 683 c->u.dma_cmd_ext.size[1] = sz >> 8; 684 c->u.dma_cmd_ext.size[2] = sz; 685 cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd_ext.crc); 686 if (spi_priv->crc7_enabled) 687 c->u.dma_cmd_ext.crc[0] = wilc_get_crc7(wb, cmd_len); 688 } else { 689 dev_err(&spi->dev, "dma read write cmd [%x] not supported\n", 690 cmd); 691 return -EINVAL; 692 } 693 if (spi_priv->crc7_enabled) 694 cmd_len += 1; 695 696 resp_len = sizeof(*r); 697 698 if (cmd_len + resp_len > ARRAY_SIZE(wb)) { 699 dev_err(&spi->dev, "spi buffer size too small (%d)(%d) (%zu)\n", 700 cmd_len, resp_len, ARRAY_SIZE(wb)); 701 return -EINVAL; 702 } 703 704 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) { 705 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); 706 return -EINVAL; 707 } 708 709 r = (struct wilc_spi_rsp_data *)&rb[cmd_len]; 710 if (r->rsp_cmd_type != cmd) { 711 dev_err(&spi->dev, 712 "Failed cmd response, cmd (%02x), resp (%02x)\n", 713 cmd, r->rsp_cmd_type); 714 return -EINVAL; 715 } 716 717 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) { 718 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", 719 r->status); 720 return -EINVAL; 721 } 722 723 if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_EXT_WRITE) 724 return 0; 725 726 while (sz > 0) { 727 int nbytes; 728 u8 rsp; 729 730 nbytes = min_t(u32, sz, DATA_PKT_SZ); 731 732 /* 733 * Data Response header 734 */ 735 retry = 100; 736 do { 737 if (wilc_spi_rx(wilc, &rsp, 1)) { 738 dev_err(&spi->dev, 739 "Failed resp read, bus err\n"); 740 return -EINVAL; 741 } 742 if (WILC_GET_RESP_HDR_START(rsp) == 0xf) 743 break; 744 } while (retry--); 745 746 /* 747 * Read bytes 748 */ 749 if (wilc_spi_rx(wilc, &b[ix], nbytes)) { 750 dev_err(&spi->dev, 751 "Failed block read, bus err\n"); 752 return -EINVAL; 753 } 754 755 /* 756 * Read CRC 757 */ 758 if (spi_priv->crc16_enabled) { 759 if (wilc_spi_rx(wilc, crc, 2)) { 760 dev_err(&spi->dev, 761 "Failed block CRC read, bus err\n"); 762 return -EINVAL; 763 } 764 crc_recv = (crc[0] << 8) | crc[1]; 765 crc_calc = crc_itu_t(0xffff, &b[ix], nbytes); 766 if (crc_recv != crc_calc) { 767 dev_err(&spi->dev, "%s: bad CRC 0x%04x " 768 "(calculated 0x%04x)\n", __func__, 769 crc_recv, crc_calc); 770 return -EINVAL; 771 } 772 } 773 774 ix += nbytes; 775 sz -= nbytes; 776 } 777 return 0; 778 } 779 780 static int wilc_spi_special_cmd(struct wilc *wilc, u8 cmd) 781 { 782 struct spi_device *spi = to_spi_device(wilc->dev); 783 struct wilc_spi *spi_priv = wilc->bus_data; 784 u8 wb[32], rb[32]; 785 int cmd_len, resp_len = 0; 786 struct wilc_spi_cmd *c; 787 struct wilc_spi_special_cmd_rsp *r; 788 789 if (cmd != CMD_TERMINATE && cmd != CMD_REPEAT && cmd != CMD_RESET) 790 return -EINVAL; 791 792 memset(wb, 0x0, sizeof(wb)); 793 memset(rb, 0x0, sizeof(rb)); 794 c = (struct wilc_spi_cmd *)wb; 795 c->cmd_type = cmd; 796 797 if (cmd == CMD_RESET) 798 memset(c->u.simple_cmd.addr, 0xFF, 3); 799 800 cmd_len = offsetof(struct wilc_spi_cmd, u.simple_cmd.crc); 801 resp_len = sizeof(*r); 802 803 if (spi_priv->crc7_enabled) { 804 c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 805 cmd_len += 1; 806 } 807 if (cmd_len + resp_len > ARRAY_SIZE(wb)) { 808 dev_err(&spi->dev, "spi buffer size too small (%d) (%d) (%zu)\n", 809 cmd_len, resp_len, ARRAY_SIZE(wb)); 810 return -EINVAL; 811 } 812 813 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) { 814 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); 815 return -EINVAL; 816 } 817 818 r = (struct wilc_spi_special_cmd_rsp *)&rb[cmd_len]; 819 if (r->rsp_cmd_type != cmd) { 820 if (!spi_priv->probing_crc) 821 dev_err(&spi->dev, 822 "Failed cmd response, cmd (%02x), resp (%02x)\n", 823 cmd, r->rsp_cmd_type); 824 return -EINVAL; 825 } 826 827 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) { 828 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", 829 r->status); 830 return -EINVAL; 831 } 832 return 0; 833 } 834 835 static void wilc_spi_reset_cmd_sequence(struct wilc *wl, u8 attempt, u32 addr) 836 { 837 struct spi_device *spi = to_spi_device(wl->dev); 838 struct wilc_spi *spi_priv = wl->bus_data; 839 840 if (!spi_priv->probing_crc) 841 dev_err(&spi->dev, "Reset and retry %d %x\n", attempt, addr); 842 843 usleep_range(1000, 1100); 844 wilc_spi_reset(wl); 845 usleep_range(1000, 1100); 846 } 847 848 static int wilc_spi_read_reg(struct wilc *wilc, u32 addr, u32 *data) 849 { 850 struct spi_device *spi = to_spi_device(wilc->dev); 851 int result; 852 u8 cmd = CMD_SINGLE_READ; 853 u8 clockless = 0; 854 u8 i; 855 856 if (addr <= WILC_SPI_CLOCKLESS_ADDR_LIMIT) { 857 /* Clockless register */ 858 cmd = CMD_INTERNAL_READ; 859 clockless = 1; 860 } 861 862 for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) { 863 result = wilc_spi_single_read(wilc, cmd, addr, data, clockless); 864 if (!result) { 865 le32_to_cpus(data); 866 return 0; 867 } 868 869 /* retry is not applicable for clockless registers */ 870 if (clockless) 871 break; 872 873 dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr); 874 wilc_spi_reset_cmd_sequence(wilc, i, addr); 875 } 876 877 return result; 878 } 879 880 static int wilc_spi_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size) 881 { 882 struct spi_device *spi = to_spi_device(wilc->dev); 883 int result; 884 u8 i; 885 886 if (size <= 4) 887 return -EINVAL; 888 889 for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) { 890 result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_READ, addr, 891 buf, size); 892 if (!result) 893 return 0; 894 895 dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr); 896 897 wilc_spi_reset_cmd_sequence(wilc, i, addr); 898 } 899 900 return result; 901 } 902 903 static int spi_internal_write(struct wilc *wilc, u32 adr, u32 dat) 904 { 905 struct spi_device *spi = to_spi_device(wilc->dev); 906 int result; 907 u8 i; 908 909 for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) { 910 result = wilc_spi_write_cmd(wilc, CMD_INTERNAL_WRITE, adr, 911 dat, 0); 912 if (!result) 913 return 0; 914 dev_err(&spi->dev, "Failed internal write cmd...\n"); 915 916 wilc_spi_reset_cmd_sequence(wilc, i, adr); 917 } 918 919 return result; 920 } 921 922 static int spi_internal_read(struct wilc *wilc, u32 adr, u32 *data) 923 { 924 struct spi_device *spi = to_spi_device(wilc->dev); 925 struct wilc_spi *spi_priv = wilc->bus_data; 926 int result; 927 u8 i; 928 929 for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) { 930 result = wilc_spi_single_read(wilc, CMD_INTERNAL_READ, adr, 931 data, 0); 932 if (!result) { 933 le32_to_cpus(data); 934 return 0; 935 } 936 if (!spi_priv->probing_crc) 937 dev_err(&spi->dev, "Failed internal read cmd...\n"); 938 939 wilc_spi_reset_cmd_sequence(wilc, i, adr); 940 } 941 942 return result; 943 } 944 945 /******************************************** 946 * 947 * Spi interfaces 948 * 949 ********************************************/ 950 951 static int wilc_spi_write_reg(struct wilc *wilc, u32 addr, u32 data) 952 { 953 struct spi_device *spi = to_spi_device(wilc->dev); 954 int result; 955 u8 cmd = CMD_SINGLE_WRITE; 956 u8 clockless = 0; 957 u8 i; 958 959 if (addr <= WILC_SPI_CLOCKLESS_ADDR_LIMIT) { 960 /* Clockless register */ 961 cmd = CMD_INTERNAL_WRITE; 962 clockless = 1; 963 } 964 965 for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) { 966 result = wilc_spi_write_cmd(wilc, cmd, addr, data, clockless); 967 if (!result) 968 return 0; 969 970 dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr); 971 972 if (clockless) 973 break; 974 975 wilc_spi_reset_cmd_sequence(wilc, i, addr); 976 } 977 return result; 978 } 979 980 static int spi_data_rsp(struct wilc *wilc, u8 cmd) 981 { 982 struct spi_device *spi = to_spi_device(wilc->dev); 983 int result, i; 984 u8 rsp[4]; 985 986 /* 987 * The response to data packets is two bytes long. For 988 * efficiency's sake, wilc_spi_write() wisely ignores the 989 * responses for all packets but the final one. The downside 990 * of that optimization is that when the final data packet is 991 * short, we may receive (part of) the response to the 992 * second-to-last packet before the one for the final packet. 993 * To handle this, we always read 4 bytes and then search for 994 * the last byte that contains the "Response Start" code (0xc 995 * in the top 4 bits). We then know that this byte is the 996 * first response byte of the final data packet. 997 */ 998 result = wilc_spi_rx(wilc, rsp, sizeof(rsp)); 999 if (result) { 1000 dev_err(&spi->dev, "Failed bus error...\n"); 1001 return result; 1002 } 1003 1004 for (i = sizeof(rsp) - 2; i >= 0; --i) 1005 if (FIELD_GET(RSP_START_FIELD, rsp[i]) == RSP_START_TAG) 1006 break; 1007 1008 if (i < 0) { 1009 dev_err(&spi->dev, 1010 "Data packet response missing (%02x %02x %02x %02x)\n", 1011 rsp[0], rsp[1], rsp[2], rsp[3]); 1012 return -1; 1013 } 1014 1015 /* rsp[i] is the last response start byte */ 1016 1017 if (FIELD_GET(RSP_TYPE_FIELD, rsp[i]) != RSP_TYPE_LAST_PACKET 1018 || rsp[i + 1] != RSP_STATE_NO_ERROR) { 1019 dev_err(&spi->dev, "Data response error (%02x %02x)\n", 1020 rsp[i], rsp[i + 1]); 1021 return -1; 1022 } 1023 return 0; 1024 } 1025 1026 static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size) 1027 { 1028 struct spi_device *spi = to_spi_device(wilc->dev); 1029 int result; 1030 u8 i; 1031 1032 /* 1033 * has to be greated than 4 1034 */ 1035 if (size <= 4) 1036 return -EINVAL; 1037 1038 for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) { 1039 result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_WRITE, addr, 1040 NULL, size); 1041 if (result) { 1042 dev_err(&spi->dev, 1043 "Failed cmd, write block (%08x)...\n", addr); 1044 wilc_spi_reset_cmd_sequence(wilc, i, addr); 1045 continue; 1046 } 1047 1048 /* 1049 * Data 1050 */ 1051 result = spi_data_write(wilc, buf, size); 1052 if (result) { 1053 dev_err(&spi->dev, "Failed block data write...\n"); 1054 wilc_spi_reset_cmd_sequence(wilc, i, addr); 1055 continue; 1056 } 1057 1058 /* 1059 * Data response 1060 */ 1061 result = spi_data_rsp(wilc, CMD_DMA_EXT_WRITE); 1062 if (result) { 1063 dev_err(&spi->dev, "Failed block data rsp...\n"); 1064 wilc_spi_reset_cmd_sequence(wilc, i, addr); 1065 continue; 1066 } 1067 break; 1068 } 1069 return result; 1070 } 1071 1072 /******************************************** 1073 * 1074 * Bus interfaces 1075 * 1076 ********************************************/ 1077 1078 static int wilc_spi_reset(struct wilc *wilc) 1079 { 1080 struct spi_device *spi = to_spi_device(wilc->dev); 1081 struct wilc_spi *spi_priv = wilc->bus_data; 1082 int result; 1083 1084 result = wilc_spi_special_cmd(wilc, CMD_RESET); 1085 if (result && !spi_priv->probing_crc) 1086 dev_err(&spi->dev, "Failed cmd reset\n"); 1087 1088 return result; 1089 } 1090 1091 static bool wilc_spi_is_init(struct wilc *wilc) 1092 { 1093 struct wilc_spi *spi_priv = wilc->bus_data; 1094 1095 return spi_priv->isinit; 1096 } 1097 1098 static int wilc_spi_deinit(struct wilc *wilc) 1099 { 1100 struct wilc_spi *spi_priv = wilc->bus_data; 1101 1102 spi_priv->isinit = false; 1103 wilc_wlan_power(wilc, false); 1104 return 0; 1105 } 1106 1107 static int wilc_spi_init(struct wilc *wilc, bool resume) 1108 { 1109 struct spi_device *spi = to_spi_device(wilc->dev); 1110 struct wilc_spi *spi_priv = wilc->bus_data; 1111 u32 reg; 1112 u32 chipid; 1113 int ret, i; 1114 1115 if (spi_priv->isinit) { 1116 /* Confirm we can read chipid register without error: */ 1117 ret = wilc_spi_read_reg(wilc, WILC_CHIPID, &chipid); 1118 if (ret == 0) 1119 return 0; 1120 1121 dev_err(&spi->dev, "Fail cmd read chip id...\n"); 1122 } 1123 1124 wilc_wlan_power(wilc, true); 1125 1126 /* 1127 * configure protocol 1128 */ 1129 1130 /* 1131 * Infer the CRC settings that are currently in effect. This 1132 * is necessary because we can't be sure that the chip has 1133 * been RESET (e.g, after module unload and reload). 1134 */ 1135 spi_priv->probing_crc = true; 1136 spi_priv->crc7_enabled = enable_crc7; 1137 spi_priv->crc16_enabled = false; /* don't check CRC16 during probing */ 1138 for (i = 0; i < 2; ++i) { 1139 ret = spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®); 1140 if (ret == 0) 1141 break; 1142 spi_priv->crc7_enabled = !enable_crc7; 1143 } 1144 if (ret) { 1145 dev_err(&spi->dev, "Failed with CRC7 on and off.\n"); 1146 return ret; 1147 } 1148 1149 /* set up the desired CRC configuration: */ 1150 reg &= ~(PROTOCOL_REG_CRC7_MASK | PROTOCOL_REG_CRC16_MASK); 1151 if (enable_crc7) 1152 reg |= PROTOCOL_REG_CRC7_MASK; 1153 if (enable_crc16) 1154 reg |= PROTOCOL_REG_CRC16_MASK; 1155 1156 /* set up the data packet size: */ 1157 BUILD_BUG_ON(DATA_PKT_LOG_SZ < DATA_PKT_LOG_SZ_MIN 1158 || DATA_PKT_LOG_SZ > DATA_PKT_LOG_SZ_MAX); 1159 reg &= ~PROTOCOL_REG_PKT_SZ_MASK; 1160 reg |= FIELD_PREP(PROTOCOL_REG_PKT_SZ_MASK, 1161 DATA_PKT_LOG_SZ - DATA_PKT_LOG_SZ_MIN); 1162 1163 /* establish the new setup: */ 1164 ret = spi_internal_write(wilc, WILC_SPI_PROTOCOL_OFFSET, reg); 1165 if (ret) { 1166 dev_err(&spi->dev, 1167 "[wilc spi %d]: Failed internal write reg\n", 1168 __LINE__); 1169 return ret; 1170 } 1171 /* update our state to match new protocol settings: */ 1172 spi_priv->crc7_enabled = enable_crc7; 1173 spi_priv->crc16_enabled = enable_crc16; 1174 1175 /* re-read to make sure new settings are in effect: */ 1176 spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®); 1177 1178 spi_priv->probing_crc = false; 1179 1180 /* 1181 * make sure can read chip id without protocol error 1182 */ 1183 ret = wilc_spi_read_reg(wilc, WILC_CHIPID, &chipid); 1184 if (ret) { 1185 dev_err(&spi->dev, "Fail cmd read chip id...\n"); 1186 return ret; 1187 } 1188 1189 spi_priv->isinit = true; 1190 1191 return 0; 1192 } 1193 1194 static int wilc_spi_read_size(struct wilc *wilc, u32 *size) 1195 { 1196 int ret; 1197 1198 ret = spi_internal_read(wilc, 1199 WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, size); 1200 *size = FIELD_GET(IRQ_DMA_WD_CNT_MASK, *size); 1201 1202 return ret; 1203 } 1204 1205 static int wilc_spi_read_int(struct wilc *wilc, u32 *int_status) 1206 { 1207 return spi_internal_read(wilc, WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, 1208 int_status); 1209 } 1210 1211 static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val) 1212 { 1213 int ret; 1214 int retry = SPI_ENABLE_VMM_RETRY_LIMIT; 1215 u32 check; 1216 1217 while (retry) { 1218 ret = spi_internal_write(wilc, 1219 WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE, 1220 val); 1221 if (ret) 1222 break; 1223 1224 ret = spi_internal_read(wilc, 1225 WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE, 1226 &check); 1227 if (ret || ((check & EN_VMM) == (val & EN_VMM))) 1228 break; 1229 1230 retry--; 1231 } 1232 return ret; 1233 } 1234 1235 static int wilc_spi_sync_ext(struct wilc *wilc, int nint) 1236 { 1237 struct spi_device *spi = to_spi_device(wilc->dev); 1238 u32 reg; 1239 int ret, i; 1240 1241 if (nint > MAX_NUM_INT) { 1242 dev_err(&spi->dev, "Too many interrupts (%d)...\n", nint); 1243 return -EINVAL; 1244 } 1245 1246 /* 1247 * interrupt pin mux select 1248 */ 1249 ret = wilc_spi_read_reg(wilc, WILC_PIN_MUX_0, ®); 1250 if (ret) { 1251 dev_err(&spi->dev, "Failed read reg (%08x)...\n", 1252 WILC_PIN_MUX_0); 1253 return ret; 1254 } 1255 reg |= BIT(8); 1256 ret = wilc_spi_write_reg(wilc, WILC_PIN_MUX_0, reg); 1257 if (ret) { 1258 dev_err(&spi->dev, "Failed write reg (%08x)...\n", 1259 WILC_PIN_MUX_0); 1260 return ret; 1261 } 1262 1263 /* 1264 * interrupt enable 1265 */ 1266 ret = wilc_spi_read_reg(wilc, WILC_INTR_ENABLE, ®); 1267 if (ret) { 1268 dev_err(&spi->dev, "Failed read reg (%08x)...\n", 1269 WILC_INTR_ENABLE); 1270 return ret; 1271 } 1272 1273 for (i = 0; (i < 5) && (nint > 0); i++, nint--) 1274 reg |= (BIT((27 + i))); 1275 1276 ret = wilc_spi_write_reg(wilc, WILC_INTR_ENABLE, reg); 1277 if (ret) { 1278 dev_err(&spi->dev, "Failed write reg (%08x)...\n", 1279 WILC_INTR_ENABLE); 1280 return ret; 1281 } 1282 if (nint) { 1283 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, ®); 1284 if (ret) { 1285 dev_err(&spi->dev, "Failed read reg (%08x)...\n", 1286 WILC_INTR2_ENABLE); 1287 return ret; 1288 } 1289 1290 for (i = 0; (i < 3) && (nint > 0); i++, nint--) 1291 reg |= BIT(i); 1292 1293 ret = wilc_spi_write_reg(wilc, WILC_INTR2_ENABLE, reg); 1294 if (ret) { 1295 dev_err(&spi->dev, "Failed write reg (%08x)...\n", 1296 WILC_INTR2_ENABLE); 1297 return ret; 1298 } 1299 } 1300 1301 return 0; 1302 } 1303 1304 /* Global spi HIF function table */ 1305 static const struct wilc_hif_func wilc_hif_spi = { 1306 .hif_init = wilc_spi_init, 1307 .hif_deinit = wilc_spi_deinit, 1308 .hif_read_reg = wilc_spi_read_reg, 1309 .hif_write_reg = wilc_spi_write_reg, 1310 .hif_block_rx = wilc_spi_read, 1311 .hif_block_tx = wilc_spi_write, 1312 .hif_read_int = wilc_spi_read_int, 1313 .hif_clear_int_ext = wilc_spi_clear_int_ext, 1314 .hif_read_size = wilc_spi_read_size, 1315 .hif_block_tx_ext = wilc_spi_write, 1316 .hif_block_rx_ext = wilc_spi_read, 1317 .hif_sync_ext = wilc_spi_sync_ext, 1318 .hif_reset = wilc_spi_reset, 1319 .hif_is_init = wilc_spi_is_init, 1320 }; 1321