1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries. 4 * All rights reserved. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/spi/spi.h> 9 #include <linux/crc7.h> 10 11 #include "netdev.h" 12 #include "cfg80211.h" 13 14 struct wilc_spi { 15 int crc_off; 16 }; 17 18 static const struct wilc_hif_func wilc_hif_spi; 19 20 /******************************************** 21 * 22 * Spi protocol Function 23 * 24 ********************************************/ 25 26 #define CMD_DMA_WRITE 0xc1 27 #define CMD_DMA_READ 0xc2 28 #define CMD_INTERNAL_WRITE 0xc3 29 #define CMD_INTERNAL_READ 0xc4 30 #define CMD_TERMINATE 0xc5 31 #define CMD_REPEAT 0xc6 32 #define CMD_DMA_EXT_WRITE 0xc7 33 #define CMD_DMA_EXT_READ 0xc8 34 #define CMD_SINGLE_WRITE 0xc9 35 #define CMD_SINGLE_READ 0xca 36 #define CMD_RESET 0xcf 37 38 #define SPI_ENABLE_VMM_RETRY_LIMIT 2 39 #define DATA_PKT_SZ_256 256 40 #define DATA_PKT_SZ_512 512 41 #define DATA_PKT_SZ_1K 1024 42 #define DATA_PKT_SZ_4K (4 * 1024) 43 #define DATA_PKT_SZ_8K (8 * 1024) 44 #define DATA_PKT_SZ DATA_PKT_SZ_8K 45 46 #define USE_SPI_DMA 0 47 48 #define WILC_SPI_COMMAND_STAT_SUCCESS 0 49 #define WILC_GET_RESP_HDR_START(h) (((h) >> 4) & 0xf) 50 51 struct wilc_spi_cmd { 52 u8 cmd_type; 53 union { 54 struct { 55 u8 addr[3]; 56 u8 crc[]; 57 } __packed simple_cmd; 58 struct { 59 u8 addr[3]; 60 u8 size[2]; 61 u8 crc[]; 62 } __packed dma_cmd; 63 struct { 64 u8 addr[3]; 65 u8 size[3]; 66 u8 crc[]; 67 } __packed dma_cmd_ext; 68 struct { 69 u8 addr[2]; 70 __be32 data; 71 u8 crc[]; 72 } __packed internal_w_cmd; 73 struct { 74 u8 addr[3]; 75 __be32 data; 76 u8 crc[]; 77 } __packed w_cmd; 78 } u; 79 } __packed; 80 81 struct wilc_spi_read_rsp_data { 82 u8 rsp_cmd_type; 83 u8 status; 84 u8 resp_header; 85 u8 resp_data[4]; 86 u8 crc[]; 87 } __packed; 88 89 struct wilc_spi_rsp_data { 90 u8 rsp_cmd_type; 91 u8 status; 92 } __packed; 93 94 static int wilc_bus_probe(struct spi_device *spi) 95 { 96 int ret; 97 struct wilc *wilc; 98 struct wilc_spi *spi_priv; 99 100 spi_priv = kzalloc(sizeof(*spi_priv), GFP_KERNEL); 101 if (!spi_priv) 102 return -ENOMEM; 103 104 ret = wilc_cfg80211_init(&wilc, &spi->dev, WILC_HIF_SPI, &wilc_hif_spi); 105 if (ret) { 106 kfree(spi_priv); 107 return ret; 108 } 109 110 spi_set_drvdata(spi, wilc); 111 wilc->dev = &spi->dev; 112 wilc->bus_data = spi_priv; 113 wilc->dev_irq_num = spi->irq; 114 115 wilc->rtc_clk = devm_clk_get(&spi->dev, "rtc_clk"); 116 if (PTR_ERR_OR_ZERO(wilc->rtc_clk) == -EPROBE_DEFER) { 117 kfree(spi_priv); 118 return -EPROBE_DEFER; 119 } else if (!IS_ERR(wilc->rtc_clk)) 120 clk_prepare_enable(wilc->rtc_clk); 121 122 return 0; 123 } 124 125 static int wilc_bus_remove(struct spi_device *spi) 126 { 127 struct wilc *wilc = spi_get_drvdata(spi); 128 129 if (!IS_ERR(wilc->rtc_clk)) 130 clk_disable_unprepare(wilc->rtc_clk); 131 132 wilc_netdev_cleanup(wilc); 133 return 0; 134 } 135 136 static const struct of_device_id wilc_of_match[] = { 137 { .compatible = "microchip,wilc1000", }, 138 { /* sentinel */ } 139 }; 140 MODULE_DEVICE_TABLE(of, wilc_of_match); 141 142 static struct spi_driver wilc_spi_driver = { 143 .driver = { 144 .name = MODALIAS, 145 .of_match_table = wilc_of_match, 146 }, 147 .probe = wilc_bus_probe, 148 .remove = wilc_bus_remove, 149 }; 150 module_spi_driver(wilc_spi_driver); 151 MODULE_LICENSE("GPL"); 152 153 static int wilc_spi_tx(struct wilc *wilc, u8 *b, u32 len) 154 { 155 struct spi_device *spi = to_spi_device(wilc->dev); 156 int ret; 157 struct spi_message msg; 158 159 if (len > 0 && b) { 160 struct spi_transfer tr = { 161 .tx_buf = b, 162 .len = len, 163 .delay = { 164 .value = 0, 165 .unit = SPI_DELAY_UNIT_USECS 166 }, 167 }; 168 char *r_buffer = kzalloc(len, GFP_KERNEL); 169 170 if (!r_buffer) 171 return -ENOMEM; 172 173 tr.rx_buf = r_buffer; 174 dev_dbg(&spi->dev, "Request writing %d bytes\n", len); 175 176 memset(&msg, 0, sizeof(msg)); 177 spi_message_init(&msg); 178 msg.spi = spi; 179 msg.is_dma_mapped = USE_SPI_DMA; 180 spi_message_add_tail(&tr, &msg); 181 182 ret = spi_sync(spi, &msg); 183 if (ret < 0) 184 dev_err(&spi->dev, "SPI transaction failed\n"); 185 186 kfree(r_buffer); 187 } else { 188 dev_err(&spi->dev, 189 "can't write data with the following length: %d\n", 190 len); 191 ret = -EINVAL; 192 } 193 194 return ret; 195 } 196 197 static int wilc_spi_rx(struct wilc *wilc, u8 *rb, u32 rlen) 198 { 199 struct spi_device *spi = to_spi_device(wilc->dev); 200 int ret; 201 202 if (rlen > 0) { 203 struct spi_message msg; 204 struct spi_transfer tr = { 205 .rx_buf = rb, 206 .len = rlen, 207 .delay = { 208 .value = 0, 209 .unit = SPI_DELAY_UNIT_USECS 210 }, 211 212 }; 213 char *t_buffer = kzalloc(rlen, GFP_KERNEL); 214 215 if (!t_buffer) 216 return -ENOMEM; 217 218 tr.tx_buf = t_buffer; 219 220 memset(&msg, 0, sizeof(msg)); 221 spi_message_init(&msg); 222 msg.spi = spi; 223 msg.is_dma_mapped = USE_SPI_DMA; 224 spi_message_add_tail(&tr, &msg); 225 226 ret = spi_sync(spi, &msg); 227 if (ret < 0) 228 dev_err(&spi->dev, "SPI transaction failed\n"); 229 kfree(t_buffer); 230 } else { 231 dev_err(&spi->dev, 232 "can't read data with the following length: %u\n", 233 rlen); 234 ret = -EINVAL; 235 } 236 237 return ret; 238 } 239 240 static int wilc_spi_tx_rx(struct wilc *wilc, u8 *wb, u8 *rb, u32 rlen) 241 { 242 struct spi_device *spi = to_spi_device(wilc->dev); 243 int ret; 244 245 if (rlen > 0) { 246 struct spi_message msg; 247 struct spi_transfer tr = { 248 .rx_buf = rb, 249 .tx_buf = wb, 250 .len = rlen, 251 .bits_per_word = 8, 252 .delay = { 253 .value = 0, 254 .unit = SPI_DELAY_UNIT_USECS 255 }, 256 257 }; 258 259 memset(&msg, 0, sizeof(msg)); 260 spi_message_init(&msg); 261 msg.spi = spi; 262 msg.is_dma_mapped = USE_SPI_DMA; 263 264 spi_message_add_tail(&tr, &msg); 265 ret = spi_sync(spi, &msg); 266 if (ret < 0) 267 dev_err(&spi->dev, "SPI transaction failed\n"); 268 } else { 269 dev_err(&spi->dev, 270 "can't read data with the following length: %u\n", 271 rlen); 272 ret = -EINVAL; 273 } 274 275 return ret; 276 } 277 278 static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz) 279 { 280 struct spi_device *spi = to_spi_device(wilc->dev); 281 struct wilc_spi *spi_priv = wilc->bus_data; 282 int ix, nbytes; 283 int result = 0; 284 u8 cmd, order, crc[2] = {0}; 285 286 /* 287 * Data 288 */ 289 ix = 0; 290 do { 291 if (sz <= DATA_PKT_SZ) { 292 nbytes = sz; 293 order = 0x3; 294 } else { 295 nbytes = DATA_PKT_SZ; 296 if (ix == 0) 297 order = 0x1; 298 else 299 order = 0x02; 300 } 301 302 /* 303 * Write command 304 */ 305 cmd = 0xf0; 306 cmd |= order; 307 308 if (wilc_spi_tx(wilc, &cmd, 1)) { 309 dev_err(&spi->dev, 310 "Failed data block cmd write, bus error...\n"); 311 result = -EINVAL; 312 break; 313 } 314 315 /* 316 * Write data 317 */ 318 if (wilc_spi_tx(wilc, &b[ix], nbytes)) { 319 dev_err(&spi->dev, 320 "Failed data block write, bus error...\n"); 321 result = -EINVAL; 322 break; 323 } 324 325 /* 326 * Write Crc 327 */ 328 if (!spi_priv->crc_off) { 329 if (wilc_spi_tx(wilc, crc, 2)) { 330 dev_err(&spi->dev, "Failed data block crc write, bus error...\n"); 331 result = -EINVAL; 332 break; 333 } 334 } 335 336 /* 337 * No need to wait for response 338 */ 339 ix += nbytes; 340 sz -= nbytes; 341 } while (sz); 342 343 return result; 344 } 345 346 /******************************************** 347 * 348 * Spi Internal Read/Write Function 349 * 350 ********************************************/ 351 static u8 wilc_get_crc7(u8 *buffer, u32 len) 352 { 353 return crc7_be(0xfe, buffer, len); 354 } 355 356 static int wilc_spi_single_read(struct wilc *wilc, u8 cmd, u32 adr, void *b, 357 u8 clockless) 358 { 359 struct spi_device *spi = to_spi_device(wilc->dev); 360 struct wilc_spi *spi_priv = wilc->bus_data; 361 u8 wb[32], rb[32]; 362 int cmd_len, resp_len; 363 u8 crc[2]; 364 struct wilc_spi_cmd *c; 365 struct wilc_spi_read_rsp_data *r; 366 367 memset(wb, 0x0, sizeof(wb)); 368 memset(rb, 0x0, sizeof(rb)); 369 c = (struct wilc_spi_cmd *)wb; 370 c->cmd_type = cmd; 371 if (cmd == CMD_SINGLE_READ) { 372 c->u.simple_cmd.addr[0] = adr >> 16; 373 c->u.simple_cmd.addr[1] = adr >> 8; 374 c->u.simple_cmd.addr[2] = adr; 375 } else if (cmd == CMD_INTERNAL_READ) { 376 c->u.simple_cmd.addr[0] = adr >> 8; 377 if (clockless == 1) 378 c->u.simple_cmd.addr[0] |= BIT(7); 379 c->u.simple_cmd.addr[1] = adr; 380 c->u.simple_cmd.addr[2] = 0x0; 381 } else { 382 dev_err(&spi->dev, "cmd [%x] not supported\n", cmd); 383 return -EINVAL; 384 } 385 386 cmd_len = offsetof(struct wilc_spi_cmd, u.simple_cmd.crc); 387 resp_len = sizeof(*r); 388 if (!spi_priv->crc_off) { 389 c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 390 cmd_len += 1; 391 resp_len += 2; 392 } 393 394 if (cmd_len + resp_len > ARRAY_SIZE(wb)) { 395 dev_err(&spi->dev, 396 "spi buffer size too small (%d) (%d) (%zu)\n", 397 cmd_len, resp_len, ARRAY_SIZE(wb)); 398 return -EINVAL; 399 } 400 401 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) { 402 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); 403 return -EINVAL; 404 } 405 406 r = (struct wilc_spi_read_rsp_data *)&rb[cmd_len]; 407 if (r->rsp_cmd_type != cmd) { 408 dev_err(&spi->dev, 409 "Failed cmd response, cmd (%02x), resp (%02x)\n", 410 cmd, r->rsp_cmd_type); 411 return -EINVAL; 412 } 413 414 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) { 415 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", 416 r->status); 417 return -EINVAL; 418 } 419 420 if (WILC_GET_RESP_HDR_START(r->resp_header) != 0xf) { 421 dev_err(&spi->dev, "Error, data read response (%02x)\n", 422 r->resp_header); 423 return -EINVAL; 424 } 425 426 if (b) 427 memcpy(b, r->resp_data, 4); 428 429 if (!spi_priv->crc_off) 430 memcpy(crc, r->crc, 2); 431 432 return 0; 433 } 434 435 static int wilc_spi_write_cmd(struct wilc *wilc, u8 cmd, u32 adr, u32 data, 436 u8 clockless) 437 { 438 struct spi_device *spi = to_spi_device(wilc->dev); 439 struct wilc_spi *spi_priv = wilc->bus_data; 440 u8 wb[32], rb[32]; 441 int cmd_len, resp_len; 442 struct wilc_spi_cmd *c; 443 struct wilc_spi_rsp_data *r; 444 445 memset(wb, 0x0, sizeof(wb)); 446 memset(rb, 0x0, sizeof(rb)); 447 c = (struct wilc_spi_cmd *)wb; 448 c->cmd_type = cmd; 449 if (cmd == CMD_INTERNAL_WRITE) { 450 c->u.internal_w_cmd.addr[0] = adr >> 8; 451 if (clockless == 1) 452 c->u.internal_w_cmd.addr[0] |= BIT(7); 453 454 c->u.internal_w_cmd.addr[1] = adr; 455 c->u.internal_w_cmd.data = cpu_to_be32(data); 456 cmd_len = offsetof(struct wilc_spi_cmd, u.internal_w_cmd.crc); 457 if (!spi_priv->crc_off) 458 c->u.internal_w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 459 } else if (cmd == CMD_SINGLE_WRITE) { 460 c->u.w_cmd.addr[0] = adr >> 16; 461 c->u.w_cmd.addr[1] = adr >> 8; 462 c->u.w_cmd.addr[2] = adr; 463 c->u.w_cmd.data = cpu_to_be32(data); 464 cmd_len = offsetof(struct wilc_spi_cmd, u.w_cmd.crc); 465 if (!spi_priv->crc_off) 466 c->u.w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 467 } else { 468 dev_err(&spi->dev, "write cmd [%x] not supported\n", cmd); 469 return -EINVAL; 470 } 471 472 if (!spi_priv->crc_off) 473 cmd_len += 1; 474 475 resp_len = sizeof(*r); 476 477 if (cmd_len + resp_len > ARRAY_SIZE(wb)) { 478 dev_err(&spi->dev, 479 "spi buffer size too small (%d) (%d) (%zu)\n", 480 cmd_len, resp_len, ARRAY_SIZE(wb)); 481 return -EINVAL; 482 } 483 484 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) { 485 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); 486 return -EINVAL; 487 } 488 489 r = (struct wilc_spi_rsp_data *)&rb[cmd_len]; 490 if (r->rsp_cmd_type != cmd) { 491 dev_err(&spi->dev, 492 "Failed cmd response, cmd (%02x), resp (%02x)\n", 493 cmd, r->rsp_cmd_type); 494 return -EINVAL; 495 } 496 497 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) { 498 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", 499 r->status); 500 return -EINVAL; 501 } 502 503 return 0; 504 } 505 506 static int wilc_spi_dma_rw(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz) 507 { 508 struct spi_device *spi = to_spi_device(wilc->dev); 509 struct wilc_spi *spi_priv = wilc->bus_data; 510 u8 wb[32], rb[32]; 511 int cmd_len, resp_len; 512 int retry, ix = 0; 513 u8 crc[2]; 514 struct wilc_spi_cmd *c; 515 struct wilc_spi_rsp_data *r; 516 517 memset(wb, 0x0, sizeof(wb)); 518 memset(rb, 0x0, sizeof(rb)); 519 c = (struct wilc_spi_cmd *)wb; 520 c->cmd_type = cmd; 521 if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_READ) { 522 c->u.dma_cmd.addr[0] = adr >> 16; 523 c->u.dma_cmd.addr[1] = adr >> 8; 524 c->u.dma_cmd.addr[2] = adr; 525 c->u.dma_cmd.size[0] = sz >> 8; 526 c->u.dma_cmd.size[1] = sz; 527 cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd.crc); 528 if (!spi_priv->crc_off) 529 c->u.dma_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 530 } else if (cmd == CMD_DMA_EXT_WRITE || cmd == CMD_DMA_EXT_READ) { 531 c->u.dma_cmd_ext.addr[0] = adr >> 16; 532 c->u.dma_cmd_ext.addr[1] = adr >> 8; 533 c->u.dma_cmd_ext.addr[2] = adr; 534 c->u.dma_cmd_ext.size[0] = sz >> 16; 535 c->u.dma_cmd_ext.size[1] = sz >> 8; 536 c->u.dma_cmd_ext.size[2] = sz; 537 cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd_ext.crc); 538 if (!spi_priv->crc_off) 539 c->u.dma_cmd_ext.crc[0] = wilc_get_crc7(wb, cmd_len); 540 } else { 541 dev_err(&spi->dev, "dma read write cmd [%x] not supported\n", 542 cmd); 543 return -EINVAL; 544 } 545 if (!spi_priv->crc_off) 546 cmd_len += 1; 547 548 resp_len = sizeof(*r); 549 550 if (cmd_len + resp_len > ARRAY_SIZE(wb)) { 551 dev_err(&spi->dev, "spi buffer size too small (%d)(%d) (%zu)\n", 552 cmd_len, resp_len, ARRAY_SIZE(wb)); 553 return -EINVAL; 554 } 555 556 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) { 557 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); 558 return -EINVAL; 559 } 560 561 r = (struct wilc_spi_rsp_data *)&rb[cmd_len]; 562 if (r->rsp_cmd_type != cmd) { 563 dev_err(&spi->dev, 564 "Failed cmd response, cmd (%02x), resp (%02x)\n", 565 cmd, r->rsp_cmd_type); 566 return -EINVAL; 567 } 568 569 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) { 570 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", 571 r->status); 572 return -EINVAL; 573 } 574 575 if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_EXT_WRITE) 576 return 0; 577 578 while (sz > 0) { 579 int nbytes; 580 u8 rsp; 581 582 if (sz <= DATA_PKT_SZ) 583 nbytes = sz; 584 else 585 nbytes = DATA_PKT_SZ; 586 587 /* 588 * Data Response header 589 */ 590 retry = 100; 591 do { 592 if (wilc_spi_rx(wilc, &rsp, 1)) { 593 dev_err(&spi->dev, 594 "Failed resp read, bus err\n"); 595 return -EINVAL; 596 } 597 if (WILC_GET_RESP_HDR_START(rsp) == 0xf) 598 break; 599 } while (retry--); 600 601 /* 602 * Read bytes 603 */ 604 if (wilc_spi_rx(wilc, &b[ix], nbytes)) { 605 dev_err(&spi->dev, 606 "Failed block read, bus err\n"); 607 return -EINVAL; 608 } 609 610 /* 611 * Read Crc 612 */ 613 if (!spi_priv->crc_off && wilc_spi_rx(wilc, crc, 2)) { 614 dev_err(&spi->dev, 615 "Failed block crc read, bus err\n"); 616 return -EINVAL; 617 } 618 619 ix += nbytes; 620 sz -= nbytes; 621 } 622 return 0; 623 } 624 625 static int wilc_spi_read_reg(struct wilc *wilc, u32 addr, u32 *data) 626 { 627 struct spi_device *spi = to_spi_device(wilc->dev); 628 int result; 629 u8 cmd = CMD_SINGLE_READ; 630 u8 clockless = 0; 631 632 if (addr < WILC_SPI_CLOCKLESS_ADDR_LIMIT) { 633 /* Clockless register */ 634 cmd = CMD_INTERNAL_READ; 635 clockless = 1; 636 } 637 638 result = wilc_spi_single_read(wilc, cmd, addr, data, clockless); 639 if (result) { 640 dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr); 641 return result; 642 } 643 644 le32_to_cpus(data); 645 646 return 0; 647 } 648 649 static int wilc_spi_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size) 650 { 651 struct spi_device *spi = to_spi_device(wilc->dev); 652 int result; 653 654 if (size <= 4) 655 return -EINVAL; 656 657 result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_READ, addr, buf, size); 658 if (result) { 659 dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr); 660 return result; 661 } 662 663 return 0; 664 } 665 666 static int spi_internal_write(struct wilc *wilc, u32 adr, u32 dat) 667 { 668 struct spi_device *spi = to_spi_device(wilc->dev); 669 int result; 670 671 result = wilc_spi_write_cmd(wilc, CMD_INTERNAL_WRITE, adr, dat, 0); 672 if (result) { 673 dev_err(&spi->dev, "Failed internal write cmd...\n"); 674 return result; 675 } 676 677 return 0; 678 } 679 680 static int spi_internal_read(struct wilc *wilc, u32 adr, u32 *data) 681 { 682 struct spi_device *spi = to_spi_device(wilc->dev); 683 int result; 684 685 result = wilc_spi_single_read(wilc, CMD_INTERNAL_READ, adr, data, 0); 686 if (result) { 687 dev_err(&spi->dev, "Failed internal read cmd...\n"); 688 return result; 689 } 690 691 le32_to_cpus(data); 692 693 return 0; 694 } 695 696 /******************************************** 697 * 698 * Spi interfaces 699 * 700 ********************************************/ 701 702 static int wilc_spi_write_reg(struct wilc *wilc, u32 addr, u32 data) 703 { 704 struct spi_device *spi = to_spi_device(wilc->dev); 705 int result; 706 u8 cmd = CMD_SINGLE_WRITE; 707 u8 clockless = 0; 708 709 if (addr < WILC_SPI_CLOCKLESS_ADDR_LIMIT) { 710 /* Clockless register */ 711 cmd = CMD_INTERNAL_WRITE; 712 clockless = 1; 713 } 714 715 result = wilc_spi_write_cmd(wilc, cmd, addr, data, clockless); 716 if (result) { 717 dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr); 718 return result; 719 } 720 721 return 0; 722 } 723 724 static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size) 725 { 726 struct spi_device *spi = to_spi_device(wilc->dev); 727 int result; 728 729 /* 730 * has to be greated than 4 731 */ 732 if (size <= 4) 733 return -EINVAL; 734 735 result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_WRITE, addr, NULL, size); 736 if (result) { 737 dev_err(&spi->dev, 738 "Failed cmd, write block (%08x)...\n", addr); 739 return result; 740 } 741 742 /* 743 * Data 744 */ 745 result = spi_data_write(wilc, buf, size); 746 if (result) { 747 dev_err(&spi->dev, "Failed block data write...\n"); 748 return result; 749 } 750 751 return 0; 752 } 753 754 /******************************************** 755 * 756 * Bus interfaces 757 * 758 ********************************************/ 759 760 static int wilc_spi_deinit(struct wilc *wilc) 761 { 762 /* 763 * TODO: 764 */ 765 return 0; 766 } 767 768 static int wilc_spi_init(struct wilc *wilc, bool resume) 769 { 770 struct spi_device *spi = to_spi_device(wilc->dev); 771 struct wilc_spi *spi_priv = wilc->bus_data; 772 u32 reg; 773 u32 chipid; 774 static int isinit; 775 int ret; 776 777 if (isinit) { 778 ret = wilc_spi_read_reg(wilc, WILC_CHIPID, &chipid); 779 if (ret) 780 dev_err(&spi->dev, "Fail cmd read chip id...\n"); 781 782 return ret; 783 } 784 785 /* 786 * configure protocol 787 */ 788 789 /* 790 * TODO: We can remove the CRC trials if there is a definite 791 * way to reset 792 */ 793 /* the SPI to it's initial value. */ 794 ret = spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®); 795 if (ret) { 796 /* 797 * Read failed. Try with CRC off. This might happen when module 798 * is removed but chip isn't reset 799 */ 800 spi_priv->crc_off = 1; 801 dev_err(&spi->dev, 802 "Failed read with CRC on, retrying with CRC off\n"); 803 ret = spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®); 804 if (ret) { 805 /* 806 * Read failed with both CRC on and off, 807 * something went bad 808 */ 809 dev_err(&spi->dev, "Failed internal read protocol\n"); 810 return ret; 811 } 812 } 813 if (spi_priv->crc_off == 0) { 814 reg &= ~0xc; /* disable crc checking */ 815 reg &= ~0x70; 816 reg |= (0x5 << 4); 817 ret = spi_internal_write(wilc, WILC_SPI_PROTOCOL_OFFSET, reg); 818 if (ret) { 819 dev_err(&spi->dev, 820 "[wilc spi %d]: Failed internal write reg\n", 821 __LINE__); 822 return ret; 823 } 824 spi_priv->crc_off = 1; 825 } 826 827 /* 828 * make sure can read back chip id correctly 829 */ 830 ret = wilc_spi_read_reg(wilc, WILC_CHIPID, &chipid); 831 if (ret) { 832 dev_err(&spi->dev, "Fail cmd read chip id...\n"); 833 return ret; 834 } 835 836 isinit = 1; 837 838 return 0; 839 } 840 841 static int wilc_spi_read_size(struct wilc *wilc, u32 *size) 842 { 843 int ret; 844 845 ret = spi_internal_read(wilc, 846 WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, size); 847 *size = FIELD_GET(IRQ_DMA_WD_CNT_MASK, *size); 848 849 return ret; 850 } 851 852 static int wilc_spi_read_int(struct wilc *wilc, u32 *int_status) 853 { 854 return spi_internal_read(wilc, WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, 855 int_status); 856 } 857 858 static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val) 859 { 860 int ret; 861 int retry = SPI_ENABLE_VMM_RETRY_LIMIT; 862 u32 check; 863 864 while (retry) { 865 ret = spi_internal_write(wilc, 866 WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE, 867 val); 868 if (ret) 869 break; 870 871 ret = spi_internal_read(wilc, 872 WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE, 873 &check); 874 if (ret || ((check & EN_VMM) == (val & EN_VMM))) 875 break; 876 877 retry--; 878 } 879 return ret; 880 } 881 882 static int wilc_spi_sync_ext(struct wilc *wilc, int nint) 883 { 884 struct spi_device *spi = to_spi_device(wilc->dev); 885 u32 reg; 886 int ret, i; 887 888 if (nint > MAX_NUM_INT) { 889 dev_err(&spi->dev, "Too many interrupts (%d)...\n", nint); 890 return -EINVAL; 891 } 892 893 /* 894 * interrupt pin mux select 895 */ 896 ret = wilc_spi_read_reg(wilc, WILC_PIN_MUX_0, ®); 897 if (ret) { 898 dev_err(&spi->dev, "Failed read reg (%08x)...\n", 899 WILC_PIN_MUX_0); 900 return ret; 901 } 902 reg |= BIT(8); 903 ret = wilc_spi_write_reg(wilc, WILC_PIN_MUX_0, reg); 904 if (ret) { 905 dev_err(&spi->dev, "Failed write reg (%08x)...\n", 906 WILC_PIN_MUX_0); 907 return ret; 908 } 909 910 /* 911 * interrupt enable 912 */ 913 ret = wilc_spi_read_reg(wilc, WILC_INTR_ENABLE, ®); 914 if (ret) { 915 dev_err(&spi->dev, "Failed read reg (%08x)...\n", 916 WILC_INTR_ENABLE); 917 return ret; 918 } 919 920 for (i = 0; (i < 5) && (nint > 0); i++, nint--) 921 reg |= (BIT((27 + i))); 922 923 ret = wilc_spi_write_reg(wilc, WILC_INTR_ENABLE, reg); 924 if (ret) { 925 dev_err(&spi->dev, "Failed write reg (%08x)...\n", 926 WILC_INTR_ENABLE); 927 return ret; 928 } 929 if (nint) { 930 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, ®); 931 if (ret) { 932 dev_err(&spi->dev, "Failed read reg (%08x)...\n", 933 WILC_INTR2_ENABLE); 934 return ret; 935 } 936 937 for (i = 0; (i < 3) && (nint > 0); i++, nint--) 938 reg |= BIT(i); 939 940 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, ®); 941 if (ret) { 942 dev_err(&spi->dev, "Failed write reg (%08x)...\n", 943 WILC_INTR2_ENABLE); 944 return ret; 945 } 946 } 947 948 return 0; 949 } 950 951 /* Global spi HIF function table */ 952 static const struct wilc_hif_func wilc_hif_spi = { 953 .hif_init = wilc_spi_init, 954 .hif_deinit = wilc_spi_deinit, 955 .hif_read_reg = wilc_spi_read_reg, 956 .hif_write_reg = wilc_spi_write_reg, 957 .hif_block_rx = wilc_spi_read, 958 .hif_block_tx = wilc_spi_write, 959 .hif_read_int = wilc_spi_read_int, 960 .hif_clear_int_ext = wilc_spi_clear_int_ext, 961 .hif_read_size = wilc_spi_read_size, 962 .hif_block_tx_ext = wilc_spi_write, 963 .hif_block_rx_ext = wilc_spi_read, 964 .hif_sync_ext = wilc_spi_sync_ext, 965 }; 966