1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries. 4 * All rights reserved. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/spi/spi.h> 9 #include <linux/crc7.h> 10 #include <linux/crc-itu-t.h> 11 #include <linux/gpio/consumer.h> 12 13 #include "netdev.h" 14 #include "cfg80211.h" 15 16 #define SPI_MODALIAS "wilc1000_spi" 17 18 static bool enable_crc7; /* protect SPI commands with CRC7 */ 19 module_param(enable_crc7, bool, 0644); 20 MODULE_PARM_DESC(enable_crc7, 21 "Enable CRC7 checksum to protect command transfers\n" 22 "\t\t\tagainst corruption during the SPI transfer.\n" 23 "\t\t\tCommand transfers are short and the CPU-cycle cost\n" 24 "\t\t\tof enabling this is small."); 25 26 static bool enable_crc16; /* protect SPI data with CRC16 */ 27 module_param(enable_crc16, bool, 0644); 28 MODULE_PARM_DESC(enable_crc16, 29 "Enable CRC16 checksum to protect data transfers\n" 30 "\t\t\tagainst corruption during the SPI transfer.\n" 31 "\t\t\tData transfers can be large and the CPU-cycle cost\n" 32 "\t\t\tof enabling this may be substantial."); 33 34 /* 35 * For CMD_SINGLE_READ and CMD_INTERNAL_READ, WILC may insert one or 36 * more zero bytes between the command response and the DATA Start tag 37 * (0xf3). This behavior appears to be undocumented in "ATWILC1000 38 * USER GUIDE" (https://tinyurl.com/4hhshdts) but we have observed 1-4 39 * zero bytes when the SPI bus operates at 48MHz and none when it 40 * operates at 1MHz. 41 */ 42 #define WILC_SPI_RSP_HDR_EXTRA_DATA 8 43 44 struct wilc_spi { 45 bool isinit; /* true if SPI protocol has been configured */ 46 bool probing_crc; /* true if we're probing chip's CRC config */ 47 bool crc7_enabled; /* true if crc7 is currently enabled */ 48 bool crc16_enabled; /* true if crc16 is currently enabled */ 49 struct wilc_gpios { 50 struct gpio_desc *enable; /* ENABLE GPIO or NULL */ 51 struct gpio_desc *reset; /* RESET GPIO or NULL */ 52 } gpios; 53 }; 54 55 static const struct wilc_hif_func wilc_hif_spi; 56 57 static int wilc_spi_reset(struct wilc *wilc); 58 59 /******************************************** 60 * 61 * Spi protocol Function 62 * 63 ********************************************/ 64 65 #define CMD_DMA_WRITE 0xc1 66 #define CMD_DMA_READ 0xc2 67 #define CMD_INTERNAL_WRITE 0xc3 68 #define CMD_INTERNAL_READ 0xc4 69 #define CMD_TERMINATE 0xc5 70 #define CMD_REPEAT 0xc6 71 #define CMD_DMA_EXT_WRITE 0xc7 72 #define CMD_DMA_EXT_READ 0xc8 73 #define CMD_SINGLE_WRITE 0xc9 74 #define CMD_SINGLE_READ 0xca 75 #define CMD_RESET 0xcf 76 77 #define SPI_ENABLE_VMM_RETRY_LIMIT 2 78 79 /* SPI response fields (section 11.1.2 in ATWILC1000 User Guide): */ 80 #define RSP_START_FIELD GENMASK(7, 4) 81 #define RSP_TYPE_FIELD GENMASK(3, 0) 82 83 /* SPI response values for the response fields: */ 84 #define RSP_START_TAG 0xc 85 #define RSP_TYPE_FIRST_PACKET 0x1 86 #define RSP_TYPE_INNER_PACKET 0x2 87 #define RSP_TYPE_LAST_PACKET 0x3 88 #define RSP_STATE_NO_ERROR 0x00 89 90 #define PROTOCOL_REG_PKT_SZ_MASK GENMASK(6, 4) 91 #define PROTOCOL_REG_CRC16_MASK GENMASK(3, 3) 92 #define PROTOCOL_REG_CRC7_MASK GENMASK(2, 2) 93 94 /* 95 * The SPI data packet size may be any integer power of two in the 96 * range from 256 to 8192 bytes. 97 */ 98 #define DATA_PKT_LOG_SZ_MIN 8 /* 256 B */ 99 #define DATA_PKT_LOG_SZ_MAX 13 /* 8 KiB */ 100 101 /* 102 * Select the data packet size (log2 of number of bytes): Use the 103 * maximum data packet size. We only retransmit complete packets, so 104 * there is no benefit from using smaller data packets. 105 */ 106 #define DATA_PKT_LOG_SZ DATA_PKT_LOG_SZ_MAX 107 #define DATA_PKT_SZ (1 << DATA_PKT_LOG_SZ) 108 109 #define WILC_SPI_COMMAND_STAT_SUCCESS 0 110 #define WILC_GET_RESP_HDR_START(h) (((h) >> 4) & 0xf) 111 112 struct wilc_spi_cmd { 113 u8 cmd_type; 114 union { 115 struct { 116 u8 addr[3]; 117 u8 crc[]; 118 } __packed simple_cmd; 119 struct { 120 u8 addr[3]; 121 u8 size[2]; 122 u8 crc[]; 123 } __packed dma_cmd; 124 struct { 125 u8 addr[3]; 126 u8 size[3]; 127 u8 crc[]; 128 } __packed dma_cmd_ext; 129 struct { 130 u8 addr[2]; 131 __be32 data; 132 u8 crc[]; 133 } __packed internal_w_cmd; 134 struct { 135 u8 addr[3]; 136 __be32 data; 137 u8 crc[]; 138 } __packed w_cmd; 139 } u; 140 } __packed; 141 142 struct wilc_spi_read_rsp_data { 143 u8 header; 144 u8 data[4]; 145 u8 crc[]; 146 } __packed; 147 148 struct wilc_spi_rsp_data { 149 u8 rsp_cmd_type; 150 u8 status; 151 u8 data[]; 152 } __packed; 153 154 struct wilc_spi_special_cmd_rsp { 155 u8 skip_byte; 156 u8 rsp_cmd_type; 157 u8 status; 158 } __packed; 159 160 static int wilc_parse_gpios(struct wilc *wilc) 161 { 162 struct spi_device *spi = to_spi_device(wilc->dev); 163 struct wilc_spi *spi_priv = wilc->bus_data; 164 struct wilc_gpios *gpios = &spi_priv->gpios; 165 166 /* get ENABLE pin and deassert it (if it is defined): */ 167 gpios->enable = devm_gpiod_get_optional(&spi->dev, 168 "enable", GPIOD_OUT_LOW); 169 /* get RESET pin and assert it (if it is defined): */ 170 if (gpios->enable) { 171 /* if enable pin exists, reset must exist as well */ 172 gpios->reset = devm_gpiod_get(&spi->dev, 173 "reset", GPIOD_OUT_HIGH); 174 if (IS_ERR(gpios->reset)) { 175 dev_err(&spi->dev, "missing reset gpio.\n"); 176 return PTR_ERR(gpios->reset); 177 } 178 } else { 179 gpios->reset = devm_gpiod_get_optional(&spi->dev, 180 "reset", GPIOD_OUT_HIGH); 181 } 182 return 0; 183 } 184 185 static void wilc_wlan_power(struct wilc *wilc, bool on) 186 { 187 struct wilc_spi *spi_priv = wilc->bus_data; 188 struct wilc_gpios *gpios = &spi_priv->gpios; 189 190 if (on) { 191 /* assert ENABLE: */ 192 gpiod_set_value(gpios->enable, 1); 193 mdelay(5); 194 /* deassert RESET: */ 195 gpiod_set_value(gpios->reset, 0); 196 } else { 197 /* assert RESET: */ 198 gpiod_set_value(gpios->reset, 1); 199 /* deassert ENABLE: */ 200 gpiod_set_value(gpios->enable, 0); 201 } 202 } 203 204 static int wilc_bus_probe(struct spi_device *spi) 205 { 206 int ret; 207 struct wilc *wilc; 208 struct wilc_spi *spi_priv; 209 210 spi_priv = kzalloc(sizeof(*spi_priv), GFP_KERNEL); 211 if (!spi_priv) 212 return -ENOMEM; 213 214 ret = wilc_cfg80211_init(&wilc, &spi->dev, WILC_HIF_SPI, &wilc_hif_spi); 215 if (ret) 216 goto free; 217 218 spi_set_drvdata(spi, wilc); 219 wilc->dev = &spi->dev; 220 wilc->bus_data = spi_priv; 221 wilc->dev_irq_num = spi->irq; 222 223 ret = wilc_parse_gpios(wilc); 224 if (ret < 0) 225 goto netdev_cleanup; 226 227 wilc->rtc_clk = devm_clk_get_optional(&spi->dev, "rtc"); 228 if (IS_ERR(wilc->rtc_clk)) { 229 ret = PTR_ERR(wilc->rtc_clk); 230 goto netdev_cleanup; 231 } 232 clk_prepare_enable(wilc->rtc_clk); 233 234 return 0; 235 236 netdev_cleanup: 237 wilc_netdev_cleanup(wilc); 238 free: 239 kfree(spi_priv); 240 return ret; 241 } 242 243 static int wilc_bus_remove(struct spi_device *spi) 244 { 245 struct wilc *wilc = spi_get_drvdata(spi); 246 struct wilc_spi *spi_priv = wilc->bus_data; 247 248 clk_disable_unprepare(wilc->rtc_clk); 249 wilc_netdev_cleanup(wilc); 250 kfree(spi_priv); 251 252 return 0; 253 } 254 255 static const struct of_device_id wilc_of_match[] = { 256 { .compatible = "microchip,wilc1000", }, 257 { /* sentinel */ } 258 }; 259 MODULE_DEVICE_TABLE(of, wilc_of_match); 260 261 static const struct spi_device_id wilc_spi_id[] = { 262 { "wilc1000", 0 }, 263 { /* sentinel */ } 264 }; 265 MODULE_DEVICE_TABLE(spi, wilc_spi_id); 266 267 static struct spi_driver wilc_spi_driver = { 268 .driver = { 269 .name = SPI_MODALIAS, 270 .of_match_table = wilc_of_match, 271 }, 272 .id_table = wilc_spi_id, 273 .probe = wilc_bus_probe, 274 .remove = wilc_bus_remove, 275 }; 276 module_spi_driver(wilc_spi_driver); 277 MODULE_LICENSE("GPL"); 278 279 static int wilc_spi_tx(struct wilc *wilc, u8 *b, u32 len) 280 { 281 struct spi_device *spi = to_spi_device(wilc->dev); 282 int ret; 283 struct spi_message msg; 284 285 if (len > 0 && b) { 286 struct spi_transfer tr = { 287 .tx_buf = b, 288 .len = len, 289 .delay = { 290 .value = 0, 291 .unit = SPI_DELAY_UNIT_USECS 292 }, 293 }; 294 char *r_buffer = kzalloc(len, GFP_KERNEL); 295 296 if (!r_buffer) 297 return -ENOMEM; 298 299 tr.rx_buf = r_buffer; 300 dev_dbg(&spi->dev, "Request writing %d bytes\n", len); 301 302 memset(&msg, 0, sizeof(msg)); 303 spi_message_init(&msg); 304 msg.spi = spi; 305 spi_message_add_tail(&tr, &msg); 306 307 ret = spi_sync(spi, &msg); 308 if (ret < 0) 309 dev_err(&spi->dev, "SPI transaction failed\n"); 310 311 kfree(r_buffer); 312 } else { 313 dev_err(&spi->dev, 314 "can't write data with the following length: %d\n", 315 len); 316 ret = -EINVAL; 317 } 318 319 return ret; 320 } 321 322 static int wilc_spi_rx(struct wilc *wilc, u8 *rb, u32 rlen) 323 { 324 struct spi_device *spi = to_spi_device(wilc->dev); 325 int ret; 326 327 if (rlen > 0) { 328 struct spi_message msg; 329 struct spi_transfer tr = { 330 .rx_buf = rb, 331 .len = rlen, 332 .delay = { 333 .value = 0, 334 .unit = SPI_DELAY_UNIT_USECS 335 }, 336 337 }; 338 char *t_buffer = kzalloc(rlen, GFP_KERNEL); 339 340 if (!t_buffer) 341 return -ENOMEM; 342 343 tr.tx_buf = t_buffer; 344 345 memset(&msg, 0, sizeof(msg)); 346 spi_message_init(&msg); 347 msg.spi = spi; 348 spi_message_add_tail(&tr, &msg); 349 350 ret = spi_sync(spi, &msg); 351 if (ret < 0) 352 dev_err(&spi->dev, "SPI transaction failed\n"); 353 kfree(t_buffer); 354 } else { 355 dev_err(&spi->dev, 356 "can't read data with the following length: %u\n", 357 rlen); 358 ret = -EINVAL; 359 } 360 361 return ret; 362 } 363 364 static int wilc_spi_tx_rx(struct wilc *wilc, u8 *wb, u8 *rb, u32 rlen) 365 { 366 struct spi_device *spi = to_spi_device(wilc->dev); 367 int ret; 368 369 if (rlen > 0) { 370 struct spi_message msg; 371 struct spi_transfer tr = { 372 .rx_buf = rb, 373 .tx_buf = wb, 374 .len = rlen, 375 .bits_per_word = 8, 376 .delay = { 377 .value = 0, 378 .unit = SPI_DELAY_UNIT_USECS 379 }, 380 381 }; 382 383 memset(&msg, 0, sizeof(msg)); 384 spi_message_init(&msg); 385 msg.spi = spi; 386 387 spi_message_add_tail(&tr, &msg); 388 ret = spi_sync(spi, &msg); 389 if (ret < 0) 390 dev_err(&spi->dev, "SPI transaction failed\n"); 391 } else { 392 dev_err(&spi->dev, 393 "can't read data with the following length: %u\n", 394 rlen); 395 ret = -EINVAL; 396 } 397 398 return ret; 399 } 400 401 static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz) 402 { 403 struct spi_device *spi = to_spi_device(wilc->dev); 404 struct wilc_spi *spi_priv = wilc->bus_data; 405 int ix, nbytes; 406 int result = 0; 407 u8 cmd, order, crc[2]; 408 u16 crc_calc; 409 410 /* 411 * Data 412 */ 413 ix = 0; 414 do { 415 if (sz <= DATA_PKT_SZ) { 416 nbytes = sz; 417 order = 0x3; 418 } else { 419 nbytes = DATA_PKT_SZ; 420 if (ix == 0) 421 order = 0x1; 422 else 423 order = 0x02; 424 } 425 426 /* 427 * Write command 428 */ 429 cmd = 0xf0; 430 cmd |= order; 431 432 if (wilc_spi_tx(wilc, &cmd, 1)) { 433 dev_err(&spi->dev, 434 "Failed data block cmd write, bus error...\n"); 435 result = -EINVAL; 436 break; 437 } 438 439 /* 440 * Write data 441 */ 442 if (wilc_spi_tx(wilc, &b[ix], nbytes)) { 443 dev_err(&spi->dev, 444 "Failed data block write, bus error...\n"); 445 result = -EINVAL; 446 break; 447 } 448 449 /* 450 * Write CRC 451 */ 452 if (spi_priv->crc16_enabled) { 453 crc_calc = crc_itu_t(0xffff, &b[ix], nbytes); 454 crc[0] = crc_calc >> 8; 455 crc[1] = crc_calc; 456 if (wilc_spi_tx(wilc, crc, 2)) { 457 dev_err(&spi->dev, "Failed data block crc write, bus error...\n"); 458 result = -EINVAL; 459 break; 460 } 461 } 462 463 /* 464 * No need to wait for response 465 */ 466 ix += nbytes; 467 sz -= nbytes; 468 } while (sz); 469 470 return result; 471 } 472 473 /******************************************** 474 * 475 * Spi Internal Read/Write Function 476 * 477 ********************************************/ 478 static u8 wilc_get_crc7(u8 *buffer, u32 len) 479 { 480 return crc7_be(0xfe, buffer, len); 481 } 482 483 static int wilc_spi_single_read(struct wilc *wilc, u8 cmd, u32 adr, void *b, 484 u8 clockless) 485 { 486 struct spi_device *spi = to_spi_device(wilc->dev); 487 struct wilc_spi *spi_priv = wilc->bus_data; 488 u8 wb[32], rb[32]; 489 int cmd_len, resp_len, i; 490 u16 crc_calc, crc_recv; 491 struct wilc_spi_cmd *c; 492 struct wilc_spi_rsp_data *r; 493 struct wilc_spi_read_rsp_data *r_data; 494 495 memset(wb, 0x0, sizeof(wb)); 496 memset(rb, 0x0, sizeof(rb)); 497 c = (struct wilc_spi_cmd *)wb; 498 c->cmd_type = cmd; 499 if (cmd == CMD_SINGLE_READ) { 500 c->u.simple_cmd.addr[0] = adr >> 16; 501 c->u.simple_cmd.addr[1] = adr >> 8; 502 c->u.simple_cmd.addr[2] = adr; 503 } else if (cmd == CMD_INTERNAL_READ) { 504 c->u.simple_cmd.addr[0] = adr >> 8; 505 if (clockless == 1) 506 c->u.simple_cmd.addr[0] |= BIT(7); 507 c->u.simple_cmd.addr[1] = adr; 508 c->u.simple_cmd.addr[2] = 0x0; 509 } else { 510 dev_err(&spi->dev, "cmd [%x] not supported\n", cmd); 511 return -EINVAL; 512 } 513 514 cmd_len = offsetof(struct wilc_spi_cmd, u.simple_cmd.crc); 515 resp_len = sizeof(*r) + sizeof(*r_data) + WILC_SPI_RSP_HDR_EXTRA_DATA; 516 517 if (spi_priv->crc7_enabled) { 518 c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 519 cmd_len += 1; 520 resp_len += 2; 521 } 522 523 if (cmd_len + resp_len > ARRAY_SIZE(wb)) { 524 dev_err(&spi->dev, 525 "spi buffer size too small (%d) (%d) (%zu)\n", 526 cmd_len, resp_len, ARRAY_SIZE(wb)); 527 return -EINVAL; 528 } 529 530 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) { 531 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); 532 return -EINVAL; 533 } 534 535 r = (struct wilc_spi_rsp_data *)&rb[cmd_len]; 536 if (r->rsp_cmd_type != cmd && !clockless) { 537 if (!spi_priv->probing_crc) 538 dev_err(&spi->dev, 539 "Failed cmd, cmd (%02x), resp (%02x)\n", 540 cmd, r->rsp_cmd_type); 541 return -EINVAL; 542 } 543 544 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS && !clockless) { 545 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", 546 r->status); 547 return -EINVAL; 548 } 549 550 for (i = 0; i < WILC_SPI_RSP_HDR_EXTRA_DATA; ++i) 551 if (WILC_GET_RESP_HDR_START(r->data[i]) == 0xf) 552 break; 553 554 if (i >= WILC_SPI_RSP_HDR_EXTRA_DATA) { 555 dev_err(&spi->dev, "Error, data start missing\n"); 556 return -EINVAL; 557 } 558 559 r_data = (struct wilc_spi_read_rsp_data *)&r->data[i]; 560 561 if (b) 562 memcpy(b, r_data->data, 4); 563 564 if (!clockless && spi_priv->crc16_enabled) { 565 crc_recv = (r_data->crc[0] << 8) | r_data->crc[1]; 566 crc_calc = crc_itu_t(0xffff, r_data->data, 4); 567 if (crc_recv != crc_calc) { 568 dev_err(&spi->dev, "%s: bad CRC 0x%04x " 569 "(calculated 0x%04x)\n", __func__, 570 crc_recv, crc_calc); 571 return -EINVAL; 572 } 573 } 574 575 return 0; 576 } 577 578 static int wilc_spi_write_cmd(struct wilc *wilc, u8 cmd, u32 adr, u32 data, 579 u8 clockless) 580 { 581 struct spi_device *spi = to_spi_device(wilc->dev); 582 struct wilc_spi *spi_priv = wilc->bus_data; 583 u8 wb[32], rb[32]; 584 int cmd_len, resp_len; 585 struct wilc_spi_cmd *c; 586 struct wilc_spi_rsp_data *r; 587 588 memset(wb, 0x0, sizeof(wb)); 589 memset(rb, 0x0, sizeof(rb)); 590 c = (struct wilc_spi_cmd *)wb; 591 c->cmd_type = cmd; 592 if (cmd == CMD_INTERNAL_WRITE) { 593 c->u.internal_w_cmd.addr[0] = adr >> 8; 594 if (clockless == 1) 595 c->u.internal_w_cmd.addr[0] |= BIT(7); 596 597 c->u.internal_w_cmd.addr[1] = adr; 598 c->u.internal_w_cmd.data = cpu_to_be32(data); 599 cmd_len = offsetof(struct wilc_spi_cmd, u.internal_w_cmd.crc); 600 if (spi_priv->crc7_enabled) 601 c->u.internal_w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 602 } else if (cmd == CMD_SINGLE_WRITE) { 603 c->u.w_cmd.addr[0] = adr >> 16; 604 c->u.w_cmd.addr[1] = adr >> 8; 605 c->u.w_cmd.addr[2] = adr; 606 c->u.w_cmd.data = cpu_to_be32(data); 607 cmd_len = offsetof(struct wilc_spi_cmd, u.w_cmd.crc); 608 if (spi_priv->crc7_enabled) 609 c->u.w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 610 } else { 611 dev_err(&spi->dev, "write cmd [%x] not supported\n", cmd); 612 return -EINVAL; 613 } 614 615 if (spi_priv->crc7_enabled) 616 cmd_len += 1; 617 618 resp_len = sizeof(*r); 619 620 if (cmd_len + resp_len > ARRAY_SIZE(wb)) { 621 dev_err(&spi->dev, 622 "spi buffer size too small (%d) (%d) (%zu)\n", 623 cmd_len, resp_len, ARRAY_SIZE(wb)); 624 return -EINVAL; 625 } 626 627 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) { 628 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); 629 return -EINVAL; 630 } 631 632 r = (struct wilc_spi_rsp_data *)&rb[cmd_len]; 633 /* 634 * Clockless registers operations might return unexptected responses, 635 * even if successful. 636 */ 637 if (r->rsp_cmd_type != cmd && !clockless) { 638 dev_err(&spi->dev, 639 "Failed cmd response, cmd (%02x), resp (%02x)\n", 640 cmd, r->rsp_cmd_type); 641 return -EINVAL; 642 } 643 644 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS && !clockless) { 645 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", 646 r->status); 647 return -EINVAL; 648 } 649 650 return 0; 651 } 652 653 static int wilc_spi_dma_rw(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz) 654 { 655 struct spi_device *spi = to_spi_device(wilc->dev); 656 struct wilc_spi *spi_priv = wilc->bus_data; 657 u16 crc_recv, crc_calc; 658 u8 wb[32], rb[32]; 659 int cmd_len, resp_len; 660 int retry, ix = 0; 661 u8 crc[2]; 662 struct wilc_spi_cmd *c; 663 struct wilc_spi_rsp_data *r; 664 665 memset(wb, 0x0, sizeof(wb)); 666 memset(rb, 0x0, sizeof(rb)); 667 c = (struct wilc_spi_cmd *)wb; 668 c->cmd_type = cmd; 669 if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_READ) { 670 c->u.dma_cmd.addr[0] = adr >> 16; 671 c->u.dma_cmd.addr[1] = adr >> 8; 672 c->u.dma_cmd.addr[2] = adr; 673 c->u.dma_cmd.size[0] = sz >> 8; 674 c->u.dma_cmd.size[1] = sz; 675 cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd.crc); 676 if (spi_priv->crc7_enabled) 677 c->u.dma_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 678 } else if (cmd == CMD_DMA_EXT_WRITE || cmd == CMD_DMA_EXT_READ) { 679 c->u.dma_cmd_ext.addr[0] = adr >> 16; 680 c->u.dma_cmd_ext.addr[1] = adr >> 8; 681 c->u.dma_cmd_ext.addr[2] = adr; 682 c->u.dma_cmd_ext.size[0] = sz >> 16; 683 c->u.dma_cmd_ext.size[1] = sz >> 8; 684 c->u.dma_cmd_ext.size[2] = sz; 685 cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd_ext.crc); 686 if (spi_priv->crc7_enabled) 687 c->u.dma_cmd_ext.crc[0] = wilc_get_crc7(wb, cmd_len); 688 } else { 689 dev_err(&spi->dev, "dma read write cmd [%x] not supported\n", 690 cmd); 691 return -EINVAL; 692 } 693 if (spi_priv->crc7_enabled) 694 cmd_len += 1; 695 696 resp_len = sizeof(*r); 697 698 if (cmd_len + resp_len > ARRAY_SIZE(wb)) { 699 dev_err(&spi->dev, "spi buffer size too small (%d)(%d) (%zu)\n", 700 cmd_len, resp_len, ARRAY_SIZE(wb)); 701 return -EINVAL; 702 } 703 704 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) { 705 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); 706 return -EINVAL; 707 } 708 709 r = (struct wilc_spi_rsp_data *)&rb[cmd_len]; 710 if (r->rsp_cmd_type != cmd) { 711 dev_err(&spi->dev, 712 "Failed cmd response, cmd (%02x), resp (%02x)\n", 713 cmd, r->rsp_cmd_type); 714 return -EINVAL; 715 } 716 717 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) { 718 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", 719 r->status); 720 return -EINVAL; 721 } 722 723 if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_EXT_WRITE) 724 return 0; 725 726 while (sz > 0) { 727 int nbytes; 728 u8 rsp; 729 730 if (sz <= DATA_PKT_SZ) 731 nbytes = sz; 732 else 733 nbytes = DATA_PKT_SZ; 734 735 /* 736 * Data Response header 737 */ 738 retry = 100; 739 do { 740 if (wilc_spi_rx(wilc, &rsp, 1)) { 741 dev_err(&spi->dev, 742 "Failed resp read, bus err\n"); 743 return -EINVAL; 744 } 745 if (WILC_GET_RESP_HDR_START(rsp) == 0xf) 746 break; 747 } while (retry--); 748 749 /* 750 * Read bytes 751 */ 752 if (wilc_spi_rx(wilc, &b[ix], nbytes)) { 753 dev_err(&spi->dev, 754 "Failed block read, bus err\n"); 755 return -EINVAL; 756 } 757 758 /* 759 * Read CRC 760 */ 761 if (spi_priv->crc16_enabled) { 762 if (wilc_spi_rx(wilc, crc, 2)) { 763 dev_err(&spi->dev, 764 "Failed block CRC read, bus err\n"); 765 return -EINVAL; 766 } 767 crc_recv = (crc[0] << 8) | crc[1]; 768 crc_calc = crc_itu_t(0xffff, &b[ix], nbytes); 769 if (crc_recv != crc_calc) { 770 dev_err(&spi->dev, "%s: bad CRC 0x%04x " 771 "(calculated 0x%04x)\n", __func__, 772 crc_recv, crc_calc); 773 return -EINVAL; 774 } 775 } 776 777 ix += nbytes; 778 sz -= nbytes; 779 } 780 return 0; 781 } 782 783 static int wilc_spi_special_cmd(struct wilc *wilc, u8 cmd) 784 { 785 struct spi_device *spi = to_spi_device(wilc->dev); 786 struct wilc_spi *spi_priv = wilc->bus_data; 787 u8 wb[32], rb[32]; 788 int cmd_len, resp_len = 0; 789 struct wilc_spi_cmd *c; 790 struct wilc_spi_special_cmd_rsp *r; 791 792 if (cmd != CMD_TERMINATE && cmd != CMD_REPEAT && cmd != CMD_RESET) 793 return -EINVAL; 794 795 memset(wb, 0x0, sizeof(wb)); 796 memset(rb, 0x0, sizeof(rb)); 797 c = (struct wilc_spi_cmd *)wb; 798 c->cmd_type = cmd; 799 800 if (cmd == CMD_RESET) 801 memset(c->u.simple_cmd.addr, 0xFF, 3); 802 803 cmd_len = offsetof(struct wilc_spi_cmd, u.simple_cmd.crc); 804 resp_len = sizeof(*r); 805 806 if (spi_priv->crc7_enabled) { 807 c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 808 cmd_len += 1; 809 } 810 if (cmd_len + resp_len > ARRAY_SIZE(wb)) { 811 dev_err(&spi->dev, "spi buffer size too small (%d) (%d) (%zu)\n", 812 cmd_len, resp_len, ARRAY_SIZE(wb)); 813 return -EINVAL; 814 } 815 816 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) { 817 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); 818 return -EINVAL; 819 } 820 821 r = (struct wilc_spi_special_cmd_rsp *)&rb[cmd_len]; 822 if (r->rsp_cmd_type != cmd) { 823 if (!spi_priv->probing_crc) 824 dev_err(&spi->dev, 825 "Failed cmd response, cmd (%02x), resp (%02x)\n", 826 cmd, r->rsp_cmd_type); 827 return -EINVAL; 828 } 829 830 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) { 831 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", 832 r->status); 833 return -EINVAL; 834 } 835 return 0; 836 } 837 838 static int wilc_spi_read_reg(struct wilc *wilc, u32 addr, u32 *data) 839 { 840 struct spi_device *spi = to_spi_device(wilc->dev); 841 int result; 842 u8 cmd = CMD_SINGLE_READ; 843 u8 clockless = 0; 844 845 if (addr < WILC_SPI_CLOCKLESS_ADDR_LIMIT) { 846 /* Clockless register */ 847 cmd = CMD_INTERNAL_READ; 848 clockless = 1; 849 } 850 851 result = wilc_spi_single_read(wilc, cmd, addr, data, clockless); 852 if (result) { 853 dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr); 854 return result; 855 } 856 857 le32_to_cpus(data); 858 859 return 0; 860 } 861 862 static int wilc_spi_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size) 863 { 864 struct spi_device *spi = to_spi_device(wilc->dev); 865 int result; 866 867 if (size <= 4) 868 return -EINVAL; 869 870 result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_READ, addr, buf, size); 871 if (result) { 872 dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr); 873 return result; 874 } 875 876 return 0; 877 } 878 879 static int spi_internal_write(struct wilc *wilc, u32 adr, u32 dat) 880 { 881 struct spi_device *spi = to_spi_device(wilc->dev); 882 int result; 883 884 result = wilc_spi_write_cmd(wilc, CMD_INTERNAL_WRITE, adr, dat, 0); 885 if (result) { 886 dev_err(&spi->dev, "Failed internal write cmd...\n"); 887 return result; 888 } 889 890 return 0; 891 } 892 893 static int spi_internal_read(struct wilc *wilc, u32 adr, u32 *data) 894 { 895 struct spi_device *spi = to_spi_device(wilc->dev); 896 struct wilc_spi *spi_priv = wilc->bus_data; 897 int result; 898 899 result = wilc_spi_single_read(wilc, CMD_INTERNAL_READ, adr, data, 0); 900 if (result) { 901 if (!spi_priv->probing_crc) 902 dev_err(&spi->dev, "Failed internal read cmd...\n"); 903 return result; 904 } 905 906 le32_to_cpus(data); 907 908 return 0; 909 } 910 911 /******************************************** 912 * 913 * Spi interfaces 914 * 915 ********************************************/ 916 917 static int wilc_spi_write_reg(struct wilc *wilc, u32 addr, u32 data) 918 { 919 struct spi_device *spi = to_spi_device(wilc->dev); 920 int result; 921 u8 cmd = CMD_SINGLE_WRITE; 922 u8 clockless = 0; 923 924 if (addr < WILC_SPI_CLOCKLESS_ADDR_LIMIT) { 925 /* Clockless register */ 926 cmd = CMD_INTERNAL_WRITE; 927 clockless = 1; 928 } 929 930 result = wilc_spi_write_cmd(wilc, cmd, addr, data, clockless); 931 if (result) { 932 dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr); 933 return result; 934 } 935 936 return 0; 937 } 938 939 static int spi_data_rsp(struct wilc *wilc, u8 cmd) 940 { 941 struct spi_device *spi = to_spi_device(wilc->dev); 942 int result, i; 943 u8 rsp[4]; 944 945 /* 946 * The response to data packets is two bytes long. For 947 * efficiency's sake, wilc_spi_write() wisely ignores the 948 * responses for all packets but the final one. The downside 949 * of that optimization is that when the final data packet is 950 * short, we may receive (part of) the response to the 951 * second-to-last packet before the one for the final packet. 952 * To handle this, we always read 4 bytes and then search for 953 * the last byte that contains the "Response Start" code (0xc 954 * in the top 4 bits). We then know that this byte is the 955 * first response byte of the final data packet. 956 */ 957 result = wilc_spi_rx(wilc, rsp, sizeof(rsp)); 958 if (result) { 959 dev_err(&spi->dev, "Failed bus error...\n"); 960 return result; 961 } 962 963 for (i = sizeof(rsp) - 2; i >= 0; --i) 964 if (FIELD_GET(RSP_START_FIELD, rsp[i]) == RSP_START_TAG) 965 break; 966 967 if (i < 0) { 968 dev_err(&spi->dev, 969 "Data packet response missing (%02x %02x %02x %02x)\n", 970 rsp[0], rsp[1], rsp[2], rsp[3]); 971 return -1; 972 } 973 974 /* rsp[i] is the last response start byte */ 975 976 if (FIELD_GET(RSP_TYPE_FIELD, rsp[i]) != RSP_TYPE_LAST_PACKET 977 || rsp[i + 1] != RSP_STATE_NO_ERROR) { 978 dev_err(&spi->dev, "Data response error (%02x %02x)\n", 979 rsp[i], rsp[i + 1]); 980 return -1; 981 } 982 return 0; 983 } 984 985 static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size) 986 { 987 struct spi_device *spi = to_spi_device(wilc->dev); 988 int result; 989 990 /* 991 * has to be greated than 4 992 */ 993 if (size <= 4) 994 return -EINVAL; 995 996 result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_WRITE, addr, NULL, size); 997 if (result) { 998 dev_err(&spi->dev, 999 "Failed cmd, write block (%08x)...\n", addr); 1000 return result; 1001 } 1002 1003 /* 1004 * Data 1005 */ 1006 result = spi_data_write(wilc, buf, size); 1007 if (result) { 1008 dev_err(&spi->dev, "Failed block data write...\n"); 1009 return result; 1010 } 1011 1012 /* 1013 * Data response 1014 */ 1015 return spi_data_rsp(wilc, CMD_DMA_EXT_WRITE); 1016 } 1017 1018 /******************************************** 1019 * 1020 * Bus interfaces 1021 * 1022 ********************************************/ 1023 1024 static int wilc_spi_reset(struct wilc *wilc) 1025 { 1026 struct spi_device *spi = to_spi_device(wilc->dev); 1027 struct wilc_spi *spi_priv = wilc->bus_data; 1028 int result; 1029 1030 result = wilc_spi_special_cmd(wilc, CMD_RESET); 1031 if (result && !spi_priv->probing_crc) 1032 dev_err(&spi->dev, "Failed cmd reset\n"); 1033 1034 return result; 1035 } 1036 1037 static int wilc_spi_deinit(struct wilc *wilc) 1038 { 1039 struct wilc_spi *spi_priv = wilc->bus_data; 1040 1041 spi_priv->isinit = false; 1042 wilc_wlan_power(wilc, false); 1043 return 0; 1044 } 1045 1046 static int wilc_spi_init(struct wilc *wilc, bool resume) 1047 { 1048 struct spi_device *spi = to_spi_device(wilc->dev); 1049 struct wilc_spi *spi_priv = wilc->bus_data; 1050 u32 reg; 1051 u32 chipid; 1052 int ret, i; 1053 1054 if (spi_priv->isinit) { 1055 /* Confirm we can read chipid register without error: */ 1056 ret = wilc_spi_read_reg(wilc, WILC_CHIPID, &chipid); 1057 if (ret == 0) 1058 return 0; 1059 1060 dev_err(&spi->dev, "Fail cmd read chip id...\n"); 1061 } 1062 1063 wilc_wlan_power(wilc, true); 1064 1065 /* 1066 * configure protocol 1067 */ 1068 1069 /* 1070 * Infer the CRC settings that are currently in effect. This 1071 * is necessary because we can't be sure that the chip has 1072 * been RESET (e.g, after module unload and reload). 1073 */ 1074 spi_priv->probing_crc = true; 1075 spi_priv->crc7_enabled = enable_crc7; 1076 spi_priv->crc16_enabled = false; /* don't check CRC16 during probing */ 1077 for (i = 0; i < 2; ++i) { 1078 ret = spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®); 1079 if (ret == 0) 1080 break; 1081 spi_priv->crc7_enabled = !enable_crc7; 1082 } 1083 if (ret) { 1084 dev_err(&spi->dev, "Failed with CRC7 on and off.\n"); 1085 return ret; 1086 } 1087 1088 /* set up the desired CRC configuration: */ 1089 reg &= ~(PROTOCOL_REG_CRC7_MASK | PROTOCOL_REG_CRC16_MASK); 1090 if (enable_crc7) 1091 reg |= PROTOCOL_REG_CRC7_MASK; 1092 if (enable_crc16) 1093 reg |= PROTOCOL_REG_CRC16_MASK; 1094 1095 /* set up the data packet size: */ 1096 BUILD_BUG_ON(DATA_PKT_LOG_SZ < DATA_PKT_LOG_SZ_MIN 1097 || DATA_PKT_LOG_SZ > DATA_PKT_LOG_SZ_MAX); 1098 reg &= ~PROTOCOL_REG_PKT_SZ_MASK; 1099 reg |= FIELD_PREP(PROTOCOL_REG_PKT_SZ_MASK, 1100 DATA_PKT_LOG_SZ - DATA_PKT_LOG_SZ_MIN); 1101 1102 /* establish the new setup: */ 1103 ret = spi_internal_write(wilc, WILC_SPI_PROTOCOL_OFFSET, reg); 1104 if (ret) { 1105 dev_err(&spi->dev, 1106 "[wilc spi %d]: Failed internal write reg\n", 1107 __LINE__); 1108 return ret; 1109 } 1110 /* update our state to match new protocol settings: */ 1111 spi_priv->crc7_enabled = enable_crc7; 1112 spi_priv->crc16_enabled = enable_crc16; 1113 1114 /* re-read to make sure new settings are in effect: */ 1115 spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®); 1116 1117 spi_priv->probing_crc = false; 1118 1119 /* 1120 * make sure can read chip id without protocol error 1121 */ 1122 ret = wilc_spi_read_reg(wilc, WILC_CHIPID, &chipid); 1123 if (ret) { 1124 dev_err(&spi->dev, "Fail cmd read chip id...\n"); 1125 return ret; 1126 } 1127 1128 spi_priv->isinit = true; 1129 1130 return 0; 1131 } 1132 1133 static int wilc_spi_read_size(struct wilc *wilc, u32 *size) 1134 { 1135 int ret; 1136 1137 ret = spi_internal_read(wilc, 1138 WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, size); 1139 *size = FIELD_GET(IRQ_DMA_WD_CNT_MASK, *size); 1140 1141 return ret; 1142 } 1143 1144 static int wilc_spi_read_int(struct wilc *wilc, u32 *int_status) 1145 { 1146 return spi_internal_read(wilc, WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, 1147 int_status); 1148 } 1149 1150 static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val) 1151 { 1152 int ret; 1153 int retry = SPI_ENABLE_VMM_RETRY_LIMIT; 1154 u32 check; 1155 1156 while (retry) { 1157 ret = spi_internal_write(wilc, 1158 WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE, 1159 val); 1160 if (ret) 1161 break; 1162 1163 ret = spi_internal_read(wilc, 1164 WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE, 1165 &check); 1166 if (ret || ((check & EN_VMM) == (val & EN_VMM))) 1167 break; 1168 1169 retry--; 1170 } 1171 return ret; 1172 } 1173 1174 static int wilc_spi_sync_ext(struct wilc *wilc, int nint) 1175 { 1176 struct spi_device *spi = to_spi_device(wilc->dev); 1177 u32 reg; 1178 int ret, i; 1179 1180 if (nint > MAX_NUM_INT) { 1181 dev_err(&spi->dev, "Too many interrupts (%d)...\n", nint); 1182 return -EINVAL; 1183 } 1184 1185 /* 1186 * interrupt pin mux select 1187 */ 1188 ret = wilc_spi_read_reg(wilc, WILC_PIN_MUX_0, ®); 1189 if (ret) { 1190 dev_err(&spi->dev, "Failed read reg (%08x)...\n", 1191 WILC_PIN_MUX_0); 1192 return ret; 1193 } 1194 reg |= BIT(8); 1195 ret = wilc_spi_write_reg(wilc, WILC_PIN_MUX_0, reg); 1196 if (ret) { 1197 dev_err(&spi->dev, "Failed write reg (%08x)...\n", 1198 WILC_PIN_MUX_0); 1199 return ret; 1200 } 1201 1202 /* 1203 * interrupt enable 1204 */ 1205 ret = wilc_spi_read_reg(wilc, WILC_INTR_ENABLE, ®); 1206 if (ret) { 1207 dev_err(&spi->dev, "Failed read reg (%08x)...\n", 1208 WILC_INTR_ENABLE); 1209 return ret; 1210 } 1211 1212 for (i = 0; (i < 5) && (nint > 0); i++, nint--) 1213 reg |= (BIT((27 + i))); 1214 1215 ret = wilc_spi_write_reg(wilc, WILC_INTR_ENABLE, reg); 1216 if (ret) { 1217 dev_err(&spi->dev, "Failed write reg (%08x)...\n", 1218 WILC_INTR_ENABLE); 1219 return ret; 1220 } 1221 if (nint) { 1222 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, ®); 1223 if (ret) { 1224 dev_err(&spi->dev, "Failed read reg (%08x)...\n", 1225 WILC_INTR2_ENABLE); 1226 return ret; 1227 } 1228 1229 for (i = 0; (i < 3) && (nint > 0); i++, nint--) 1230 reg |= BIT(i); 1231 1232 ret = wilc_spi_write_reg(wilc, WILC_INTR2_ENABLE, reg); 1233 if (ret) { 1234 dev_err(&spi->dev, "Failed write reg (%08x)...\n", 1235 WILC_INTR2_ENABLE); 1236 return ret; 1237 } 1238 } 1239 1240 return 0; 1241 } 1242 1243 /* Global spi HIF function table */ 1244 static const struct wilc_hif_func wilc_hif_spi = { 1245 .hif_init = wilc_spi_init, 1246 .hif_deinit = wilc_spi_deinit, 1247 .hif_read_reg = wilc_spi_read_reg, 1248 .hif_write_reg = wilc_spi_write_reg, 1249 .hif_block_rx = wilc_spi_read, 1250 .hif_block_tx = wilc_spi_write, 1251 .hif_read_int = wilc_spi_read_int, 1252 .hif_clear_int_ext = wilc_spi_clear_int_ext, 1253 .hif_read_size = wilc_spi_read_size, 1254 .hif_block_tx_ext = wilc_spi_write, 1255 .hif_block_rx_ext = wilc_spi_read, 1256 .hif_sync_ext = wilc_spi_sync_ext, 1257 .hif_reset = wilc_spi_reset, 1258 }; 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