1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries. 4 * All rights reserved. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/mmc/sdio_func.h> 9 #include <linux/mmc/sdio_ids.h> 10 #include <linux/mmc/host.h> 11 #include <linux/mmc/sdio.h> 12 #include <linux/of_irq.h> 13 14 #include "netdev.h" 15 #include "cfg80211.h" 16 17 #define SDIO_MODALIAS "wilc1000_sdio" 18 19 static const struct sdio_device_id wilc_sdio_ids[] = { 20 { SDIO_DEVICE(SDIO_VENDOR_ID_MICROCHIP_WILC, SDIO_DEVICE_ID_MICROCHIP_WILC1000) }, 21 { }, 22 }; 23 MODULE_DEVICE_TABLE(sdio, wilc_sdio_ids); 24 25 #define WILC_SDIO_BLOCK_SIZE 512 26 27 static int wilc_sdio_init(struct wilc *wilc, bool resume); 28 static int wilc_sdio_deinit(struct wilc *wilc); 29 30 struct wilc_sdio { 31 bool irq_gpio; 32 u32 block_size; 33 bool isinit; 34 u8 *cmd53_buf; 35 }; 36 37 struct sdio_cmd52 { 38 u32 read_write: 1; 39 u32 function: 3; 40 u32 raw: 1; 41 u32 address: 17; 42 u32 data: 8; 43 }; 44 45 struct sdio_cmd53 { 46 u32 read_write: 1; 47 u32 function: 3; 48 u32 block_mode: 1; 49 u32 increment: 1; 50 u32 address: 17; 51 u32 count: 9; 52 u8 *buffer; 53 u32 block_size; 54 bool use_global_buf; 55 }; 56 57 static const struct wilc_hif_func wilc_hif_sdio; 58 59 static void wilc_sdio_interrupt(struct sdio_func *func) 60 { 61 sdio_release_host(func); 62 wilc_handle_isr(sdio_get_drvdata(func)); 63 sdio_claim_host(func); 64 } 65 66 static int wilc_sdio_cmd52(struct wilc *wilc, struct sdio_cmd52 *cmd) 67 { 68 struct sdio_func *func = container_of(wilc->dev, struct sdio_func, dev); 69 int ret; 70 u8 data; 71 72 sdio_claim_host(func); 73 74 func->num = cmd->function; 75 if (cmd->read_write) { /* write */ 76 if (cmd->raw) { 77 sdio_writeb(func, cmd->data, cmd->address, &ret); 78 data = sdio_readb(func, cmd->address, &ret); 79 cmd->data = data; 80 } else { 81 sdio_writeb(func, cmd->data, cmd->address, &ret); 82 } 83 } else { /* read */ 84 data = sdio_readb(func, cmd->address, &ret); 85 cmd->data = data; 86 } 87 88 sdio_release_host(func); 89 90 if (ret) 91 dev_err(&func->dev, "%s..failed, err(%d)\n", __func__, ret); 92 return ret; 93 } 94 95 static int wilc_sdio_cmd53(struct wilc *wilc, struct sdio_cmd53 *cmd) 96 { 97 struct sdio_func *func = container_of(wilc->dev, struct sdio_func, dev); 98 int size, ret; 99 struct wilc_sdio *sdio_priv = wilc->bus_data; 100 u8 *buf = cmd->buffer; 101 102 sdio_claim_host(func); 103 104 func->num = cmd->function; 105 func->cur_blksize = cmd->block_size; 106 if (cmd->block_mode) 107 size = cmd->count * cmd->block_size; 108 else 109 size = cmd->count; 110 111 if (cmd->use_global_buf) { 112 if (size > sizeof(u32)) { 113 ret = -EINVAL; 114 goto out; 115 } 116 buf = sdio_priv->cmd53_buf; 117 } 118 119 if (cmd->read_write) { /* write */ 120 if (cmd->use_global_buf) 121 memcpy(buf, cmd->buffer, size); 122 123 ret = sdio_memcpy_toio(func, cmd->address, buf, size); 124 } else { /* read */ 125 ret = sdio_memcpy_fromio(func, buf, cmd->address, size); 126 127 if (cmd->use_global_buf) 128 memcpy(cmd->buffer, buf, size); 129 } 130 out: 131 sdio_release_host(func); 132 133 if (ret) 134 dev_err(&func->dev, "%s..failed, err(%d)\n", __func__, ret); 135 136 return ret; 137 } 138 139 static int wilc_sdio_probe(struct sdio_func *func, 140 const struct sdio_device_id *id) 141 { 142 struct wilc_sdio *sdio_priv; 143 struct wilc_vif *vif; 144 struct wilc *wilc; 145 int ret; 146 147 148 sdio_priv = kzalloc(sizeof(*sdio_priv), GFP_KERNEL); 149 if (!sdio_priv) 150 return -ENOMEM; 151 152 sdio_priv->cmd53_buf = kzalloc(sizeof(u32), GFP_KERNEL); 153 if (!sdio_priv->cmd53_buf) { 154 ret = -ENOMEM; 155 goto free; 156 } 157 158 ret = wilc_cfg80211_init(&wilc, &func->dev, WILC_HIF_SDIO, 159 &wilc_hif_sdio); 160 if (ret) 161 goto free; 162 163 if (IS_ENABLED(CONFIG_WILC1000_HW_OOB_INTR)) { 164 struct device_node *np = func->card->dev.of_node; 165 int irq_num = of_irq_get(np, 0); 166 167 if (irq_num > 0) { 168 wilc->dev_irq_num = irq_num; 169 sdio_priv->irq_gpio = true; 170 } 171 } 172 173 sdio_set_drvdata(func, wilc); 174 wilc->bus_data = sdio_priv; 175 wilc->dev = &func->dev; 176 177 wilc->rtc_clk = devm_clk_get_optional(&func->card->dev, "rtc"); 178 if (IS_ERR(wilc->rtc_clk)) { 179 ret = PTR_ERR(wilc->rtc_clk); 180 goto dispose_irq; 181 } 182 clk_prepare_enable(wilc->rtc_clk); 183 184 wilc_sdio_init(wilc, false); 185 186 ret = wilc_load_mac_from_nv(wilc); 187 if (ret) { 188 pr_err("Can not retrieve MAC address from chip\n"); 189 goto clk_disable_unprepare; 190 } 191 192 wilc_sdio_deinit(wilc); 193 194 vif = wilc_netdev_ifc_init(wilc, "wlan%d", WILC_STATION_MODE, 195 NL80211_IFTYPE_STATION, false); 196 if (IS_ERR(vif)) { 197 ret = PTR_ERR(vif); 198 goto clk_disable_unprepare; 199 } 200 201 dev_info(&func->dev, "Driver Initializing success\n"); 202 return 0; 203 204 clk_disable_unprepare: 205 clk_disable_unprepare(wilc->rtc_clk); 206 dispose_irq: 207 irq_dispose_mapping(wilc->dev_irq_num); 208 wilc_netdev_cleanup(wilc); 209 free: 210 kfree(sdio_priv->cmd53_buf); 211 kfree(sdio_priv); 212 return ret; 213 } 214 215 static void wilc_sdio_remove(struct sdio_func *func) 216 { 217 struct wilc *wilc = sdio_get_drvdata(func); 218 struct wilc_sdio *sdio_priv = wilc->bus_data; 219 220 clk_disable_unprepare(wilc->rtc_clk); 221 wilc_netdev_cleanup(wilc); 222 kfree(sdio_priv->cmd53_buf); 223 kfree(sdio_priv); 224 } 225 226 static int wilc_sdio_reset(struct wilc *wilc) 227 { 228 struct sdio_cmd52 cmd; 229 int ret; 230 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 231 232 cmd.read_write = 1; 233 cmd.function = 0; 234 cmd.raw = 0; 235 cmd.address = SDIO_CCCR_ABORT; 236 cmd.data = WILC_SDIO_CCCR_ABORT_RESET; 237 ret = wilc_sdio_cmd52(wilc, &cmd); 238 if (ret) { 239 dev_err(&func->dev, "Fail cmd 52, reset cmd ...\n"); 240 return ret; 241 } 242 return 0; 243 } 244 245 static bool wilc_sdio_is_init(struct wilc *wilc) 246 { 247 struct wilc_sdio *sdio_priv = wilc->bus_data; 248 249 return sdio_priv->isinit; 250 } 251 252 static int wilc_sdio_suspend(struct device *dev) 253 { 254 struct sdio_func *func = dev_to_sdio_func(dev); 255 struct wilc *wilc = sdio_get_drvdata(func); 256 int ret; 257 258 dev_info(dev, "sdio suspend\n"); 259 chip_wakeup(wilc); 260 261 if (!IS_ERR(wilc->rtc_clk)) 262 clk_disable_unprepare(wilc->rtc_clk); 263 264 if (wilc->suspend_event) { 265 host_sleep_notify(wilc); 266 chip_allow_sleep(wilc); 267 } 268 269 ret = wilc_sdio_reset(wilc); 270 if (ret) { 271 dev_err(&func->dev, "Fail reset sdio\n"); 272 return ret; 273 } 274 sdio_claim_host(func); 275 276 return 0; 277 } 278 279 static int wilc_sdio_enable_interrupt(struct wilc *dev) 280 { 281 struct sdio_func *func = container_of(dev->dev, struct sdio_func, dev); 282 int ret = 0; 283 284 sdio_claim_host(func); 285 ret = sdio_claim_irq(func, wilc_sdio_interrupt); 286 sdio_release_host(func); 287 288 if (ret < 0) { 289 dev_err(&func->dev, "can't claim sdio_irq, err(%d)\n", ret); 290 ret = -EIO; 291 } 292 return ret; 293 } 294 295 static void wilc_sdio_disable_interrupt(struct wilc *dev) 296 { 297 struct sdio_func *func = container_of(dev->dev, struct sdio_func, dev); 298 int ret; 299 300 sdio_claim_host(func); 301 ret = sdio_release_irq(func); 302 if (ret < 0) 303 dev_err(&func->dev, "can't release sdio_irq, err(%d)\n", ret); 304 sdio_release_host(func); 305 } 306 307 /******************************************** 308 * 309 * Function 0 310 * 311 ********************************************/ 312 313 static int wilc_sdio_set_func0_csa_address(struct wilc *wilc, u32 adr) 314 { 315 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 316 struct sdio_cmd52 cmd; 317 int ret; 318 319 /** 320 * Review: BIG ENDIAN 321 **/ 322 cmd.read_write = 1; 323 cmd.function = 0; 324 cmd.raw = 0; 325 cmd.address = WILC_SDIO_FBR_CSA_REG; 326 cmd.data = (u8)adr; 327 ret = wilc_sdio_cmd52(wilc, &cmd); 328 if (ret) { 329 dev_err(&func->dev, "Failed cmd52, set %04x data...\n", 330 cmd.address); 331 return ret; 332 } 333 334 cmd.address = WILC_SDIO_FBR_CSA_REG + 1; 335 cmd.data = (u8)(adr >> 8); 336 ret = wilc_sdio_cmd52(wilc, &cmd); 337 if (ret) { 338 dev_err(&func->dev, "Failed cmd52, set %04x data...\n", 339 cmd.address); 340 return ret; 341 } 342 343 cmd.address = WILC_SDIO_FBR_CSA_REG + 2; 344 cmd.data = (u8)(adr >> 16); 345 ret = wilc_sdio_cmd52(wilc, &cmd); 346 if (ret) { 347 dev_err(&func->dev, "Failed cmd52, set %04x data...\n", 348 cmd.address); 349 return ret; 350 } 351 352 return 0; 353 } 354 355 static int wilc_sdio_set_block_size(struct wilc *wilc, u8 func_num, 356 u32 block_size) 357 { 358 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 359 struct sdio_cmd52 cmd; 360 int ret; 361 362 cmd.read_write = 1; 363 cmd.function = 0; 364 cmd.raw = 0; 365 cmd.address = SDIO_FBR_BASE(func_num) + SDIO_CCCR_BLKSIZE; 366 cmd.data = (u8)block_size; 367 ret = wilc_sdio_cmd52(wilc, &cmd); 368 if (ret) { 369 dev_err(&func->dev, "Failed cmd52, set %04x data...\n", 370 cmd.address); 371 return ret; 372 } 373 374 cmd.address = SDIO_FBR_BASE(func_num) + SDIO_CCCR_BLKSIZE + 1; 375 cmd.data = (u8)(block_size >> 8); 376 ret = wilc_sdio_cmd52(wilc, &cmd); 377 if (ret) { 378 dev_err(&func->dev, "Failed cmd52, set %04x data...\n", 379 cmd.address); 380 return ret; 381 } 382 383 return 0; 384 } 385 386 /******************************************** 387 * 388 * Sdio interfaces 389 * 390 ********************************************/ 391 static int wilc_sdio_write_reg(struct wilc *wilc, u32 addr, u32 data) 392 { 393 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 394 struct wilc_sdio *sdio_priv = wilc->bus_data; 395 int ret; 396 397 cpu_to_le32s(&data); 398 399 if (addr >= 0xf0 && addr <= 0xff) { /* only vendor specific registers */ 400 struct sdio_cmd52 cmd; 401 402 cmd.read_write = 1; 403 cmd.function = 0; 404 cmd.raw = 0; 405 cmd.address = addr; 406 cmd.data = data; 407 ret = wilc_sdio_cmd52(wilc, &cmd); 408 if (ret) 409 dev_err(&func->dev, 410 "Failed cmd 52, read reg (%08x) ...\n", addr); 411 } else { 412 struct sdio_cmd53 cmd; 413 414 /** 415 * set the AHB address 416 **/ 417 ret = wilc_sdio_set_func0_csa_address(wilc, addr); 418 if (ret) 419 return ret; 420 421 cmd.read_write = 1; 422 cmd.function = 0; 423 cmd.address = WILC_SDIO_FBR_DATA_REG; 424 cmd.block_mode = 0; 425 cmd.increment = 1; 426 cmd.count = sizeof(u32); 427 cmd.buffer = (u8 *)&data; 428 cmd.use_global_buf = true; 429 cmd.block_size = sdio_priv->block_size; 430 ret = wilc_sdio_cmd53(wilc, &cmd); 431 if (ret) 432 dev_err(&func->dev, 433 "Failed cmd53, write reg (%08x)...\n", addr); 434 } 435 436 return ret; 437 } 438 439 static int wilc_sdio_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size) 440 { 441 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 442 struct wilc_sdio *sdio_priv = wilc->bus_data; 443 u32 block_size = sdio_priv->block_size; 444 struct sdio_cmd53 cmd; 445 int nblk, nleft, ret; 446 447 cmd.read_write = 1; 448 if (addr > 0) { 449 /** 450 * func 0 access 451 **/ 452 cmd.function = 0; 453 cmd.address = WILC_SDIO_FBR_DATA_REG; 454 } else { 455 /** 456 * func 1 access 457 **/ 458 cmd.function = 1; 459 cmd.address = WILC_SDIO_F1_DATA_REG; 460 } 461 462 size = ALIGN(size, 4); 463 nblk = size / block_size; 464 nleft = size % block_size; 465 466 cmd.use_global_buf = false; 467 if (nblk > 0) { 468 cmd.block_mode = 1; 469 cmd.increment = 1; 470 cmd.count = nblk; 471 cmd.buffer = buf; 472 cmd.block_size = block_size; 473 if (addr > 0) { 474 ret = wilc_sdio_set_func0_csa_address(wilc, addr); 475 if (ret) 476 return ret; 477 } 478 ret = wilc_sdio_cmd53(wilc, &cmd); 479 if (ret) { 480 dev_err(&func->dev, 481 "Failed cmd53 [%x], block send...\n", addr); 482 return ret; 483 } 484 if (addr > 0) 485 addr += nblk * block_size; 486 buf += nblk * block_size; 487 } 488 489 if (nleft > 0) { 490 cmd.block_mode = 0; 491 cmd.increment = 1; 492 cmd.count = nleft; 493 cmd.buffer = buf; 494 495 cmd.block_size = block_size; 496 497 if (addr > 0) { 498 ret = wilc_sdio_set_func0_csa_address(wilc, addr); 499 if (ret) 500 return ret; 501 } 502 ret = wilc_sdio_cmd53(wilc, &cmd); 503 if (ret) { 504 dev_err(&func->dev, 505 "Failed cmd53 [%x], bytes send...\n", addr); 506 return ret; 507 } 508 } 509 510 return 0; 511 } 512 513 static int wilc_sdio_read_reg(struct wilc *wilc, u32 addr, u32 *data) 514 { 515 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 516 struct wilc_sdio *sdio_priv = wilc->bus_data; 517 int ret; 518 519 if (addr >= 0xf0 && addr <= 0xff) { /* only vendor specific registers */ 520 struct sdio_cmd52 cmd; 521 522 cmd.read_write = 0; 523 cmd.function = 0; 524 cmd.raw = 0; 525 cmd.address = addr; 526 ret = wilc_sdio_cmd52(wilc, &cmd); 527 if (ret) { 528 dev_err(&func->dev, 529 "Failed cmd 52, read reg (%08x) ...\n", addr); 530 return ret; 531 } 532 *data = cmd.data; 533 } else { 534 struct sdio_cmd53 cmd; 535 536 ret = wilc_sdio_set_func0_csa_address(wilc, addr); 537 if (ret) 538 return ret; 539 540 cmd.read_write = 0; 541 cmd.function = 0; 542 cmd.address = WILC_SDIO_FBR_DATA_REG; 543 cmd.block_mode = 0; 544 cmd.increment = 1; 545 cmd.count = sizeof(u32); 546 cmd.buffer = (u8 *)data; 547 cmd.use_global_buf = true; 548 549 cmd.block_size = sdio_priv->block_size; 550 ret = wilc_sdio_cmd53(wilc, &cmd); 551 if (ret) { 552 dev_err(&func->dev, 553 "Failed cmd53, read reg (%08x)...\n", addr); 554 return ret; 555 } 556 } 557 558 le32_to_cpus(data); 559 return 0; 560 } 561 562 static int wilc_sdio_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size) 563 { 564 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 565 struct wilc_sdio *sdio_priv = wilc->bus_data; 566 u32 block_size = sdio_priv->block_size; 567 struct sdio_cmd53 cmd; 568 int nblk, nleft, ret; 569 570 cmd.read_write = 0; 571 if (addr > 0) { 572 /** 573 * func 0 access 574 **/ 575 cmd.function = 0; 576 cmd.address = WILC_SDIO_FBR_DATA_REG; 577 } else { 578 /** 579 * func 1 access 580 **/ 581 cmd.function = 1; 582 cmd.address = WILC_SDIO_F1_DATA_REG; 583 } 584 585 size = ALIGN(size, 4); 586 nblk = size / block_size; 587 nleft = size % block_size; 588 589 cmd.use_global_buf = false; 590 if (nblk > 0) { 591 cmd.block_mode = 1; 592 cmd.increment = 1; 593 cmd.count = nblk; 594 cmd.buffer = buf; 595 cmd.block_size = block_size; 596 if (addr > 0) { 597 ret = wilc_sdio_set_func0_csa_address(wilc, addr); 598 if (ret) 599 return ret; 600 } 601 ret = wilc_sdio_cmd53(wilc, &cmd); 602 if (ret) { 603 dev_err(&func->dev, 604 "Failed cmd53 [%x], block read...\n", addr); 605 return ret; 606 } 607 if (addr > 0) 608 addr += nblk * block_size; 609 buf += nblk * block_size; 610 } /* if (nblk > 0) */ 611 612 if (nleft > 0) { 613 cmd.block_mode = 0; 614 cmd.increment = 1; 615 cmd.count = nleft; 616 cmd.buffer = buf; 617 618 cmd.block_size = block_size; 619 620 if (addr > 0) { 621 ret = wilc_sdio_set_func0_csa_address(wilc, addr); 622 if (ret) 623 return ret; 624 } 625 ret = wilc_sdio_cmd53(wilc, &cmd); 626 if (ret) { 627 dev_err(&func->dev, 628 "Failed cmd53 [%x], bytes read...\n", addr); 629 return ret; 630 } 631 } 632 633 return 0; 634 } 635 636 /******************************************** 637 * 638 * Bus interfaces 639 * 640 ********************************************/ 641 642 static int wilc_sdio_deinit(struct wilc *wilc) 643 { 644 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 645 struct wilc_sdio *sdio_priv = wilc->bus_data; 646 struct sdio_cmd52 cmd; 647 int ret; 648 649 cmd.read_write = 1; 650 cmd.function = 0; 651 cmd.raw = 1; 652 653 /* Disable all functions interrupts */ 654 cmd.address = SDIO_CCCR_IENx; 655 cmd.data = 0; 656 ret = wilc_sdio_cmd52(wilc, &cmd); 657 if (ret) { 658 dev_err(&func->dev, "Failed to disable functions interrupts\n"); 659 return ret; 660 } 661 662 /* Disable all functions */ 663 cmd.address = SDIO_CCCR_IOEx; 664 cmd.data = 0; 665 ret = wilc_sdio_cmd52(wilc, &cmd); 666 if (ret) { 667 dev_err(&func->dev, 668 "Failed to reset all functions\n"); 669 return ret; 670 } 671 672 /* Disable CSA */ 673 cmd.read_write = 0; 674 cmd.address = SDIO_FBR_BASE(1); 675 ret = wilc_sdio_cmd52(wilc, &cmd); 676 if (ret) { 677 dev_err(&func->dev, 678 "Failed to read CSA for function 1\n"); 679 return ret; 680 } 681 cmd.read_write = 1; 682 cmd.address = SDIO_FBR_BASE(1); 683 cmd.data &= ~SDIO_FBR_ENABLE_CSA; 684 ret = wilc_sdio_cmd52(wilc, &cmd); 685 if (ret) { 686 dev_err(&func->dev, 687 "Failed to disable CSA for function 1\n"); 688 return ret; 689 } 690 691 sdio_priv->isinit = false; 692 return 0; 693 } 694 695 static int wilc_sdio_init(struct wilc *wilc, bool resume) 696 { 697 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 698 struct wilc_sdio *sdio_priv = wilc->bus_data; 699 struct sdio_cmd52 cmd; 700 int loop, ret; 701 u32 chipid; 702 703 /** 704 * function 0 csa enable 705 **/ 706 cmd.read_write = 1; 707 cmd.function = 0; 708 cmd.raw = 1; 709 cmd.address = SDIO_FBR_BASE(1); 710 cmd.data = SDIO_FBR_ENABLE_CSA; 711 ret = wilc_sdio_cmd52(wilc, &cmd); 712 if (ret) { 713 dev_err(&func->dev, "Fail cmd 52, enable csa...\n"); 714 return ret; 715 } 716 717 /** 718 * function 0 block size 719 **/ 720 ret = wilc_sdio_set_block_size(wilc, 0, WILC_SDIO_BLOCK_SIZE); 721 if (ret) { 722 dev_err(&func->dev, "Fail cmd 52, set func 0 block size...\n"); 723 return ret; 724 } 725 sdio_priv->block_size = WILC_SDIO_BLOCK_SIZE; 726 727 /** 728 * enable func1 IO 729 **/ 730 cmd.read_write = 1; 731 cmd.function = 0; 732 cmd.raw = 1; 733 cmd.address = SDIO_CCCR_IOEx; 734 cmd.data = WILC_SDIO_CCCR_IO_EN_FUNC1; 735 ret = wilc_sdio_cmd52(wilc, &cmd); 736 if (ret) { 737 dev_err(&func->dev, 738 "Fail cmd 52, set IOE register...\n"); 739 return ret; 740 } 741 742 /** 743 * make sure func 1 is up 744 **/ 745 cmd.read_write = 0; 746 cmd.function = 0; 747 cmd.raw = 0; 748 cmd.address = SDIO_CCCR_IORx; 749 loop = 3; 750 do { 751 cmd.data = 0; 752 ret = wilc_sdio_cmd52(wilc, &cmd); 753 if (ret) { 754 dev_err(&func->dev, 755 "Fail cmd 52, get IOR register...\n"); 756 return ret; 757 } 758 if (cmd.data == WILC_SDIO_CCCR_IO_EN_FUNC1) 759 break; 760 } while (loop--); 761 762 if (loop <= 0) { 763 dev_err(&func->dev, "Fail func 1 is not ready...\n"); 764 return -EINVAL; 765 } 766 767 /** 768 * func 1 is ready, set func 1 block size 769 **/ 770 ret = wilc_sdio_set_block_size(wilc, 1, WILC_SDIO_BLOCK_SIZE); 771 if (ret) { 772 dev_err(&func->dev, "Fail set func 1 block size...\n"); 773 return ret; 774 } 775 776 /** 777 * func 1 interrupt enable 778 **/ 779 cmd.read_write = 1; 780 cmd.function = 0; 781 cmd.raw = 1; 782 cmd.address = SDIO_CCCR_IENx; 783 cmd.data = WILC_SDIO_CCCR_IEN_MASTER | WILC_SDIO_CCCR_IEN_FUNC1; 784 ret = wilc_sdio_cmd52(wilc, &cmd); 785 if (ret) { 786 dev_err(&func->dev, "Fail cmd 52, set IEN register...\n"); 787 return ret; 788 } 789 790 /** 791 * make sure can read back chip id correctly 792 **/ 793 if (!resume) { 794 ret = wilc_sdio_read_reg(wilc, WILC_CHIPID, &chipid); 795 if (ret) { 796 dev_err(&func->dev, "Fail cmd read chip id...\n"); 797 return ret; 798 } 799 dev_err(&func->dev, "chipid (%08x)\n", chipid); 800 } 801 802 sdio_priv->isinit = true; 803 return 0; 804 } 805 806 static int wilc_sdio_read_size(struct wilc *wilc, u32 *size) 807 { 808 u32 tmp; 809 struct sdio_cmd52 cmd; 810 811 /** 812 * Read DMA count in words 813 **/ 814 cmd.read_write = 0; 815 cmd.function = 0; 816 cmd.raw = 0; 817 cmd.address = WILC_SDIO_INTERRUPT_DATA_SZ_REG; 818 cmd.data = 0; 819 wilc_sdio_cmd52(wilc, &cmd); 820 tmp = cmd.data; 821 822 cmd.address = WILC_SDIO_INTERRUPT_DATA_SZ_REG + 1; 823 cmd.data = 0; 824 wilc_sdio_cmd52(wilc, &cmd); 825 tmp |= (cmd.data << 8); 826 827 *size = tmp; 828 return 0; 829 } 830 831 static int wilc_sdio_read_int(struct wilc *wilc, u32 *int_status) 832 { 833 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 834 struct wilc_sdio *sdio_priv = wilc->bus_data; 835 u32 tmp; 836 u8 irq_flags; 837 struct sdio_cmd52 cmd; 838 839 wilc_sdio_read_size(wilc, &tmp); 840 841 /** 842 * Read IRQ flags 843 **/ 844 if (!sdio_priv->irq_gpio) { 845 cmd.function = 1; 846 cmd.address = WILC_SDIO_EXT_IRQ_FLAG_REG; 847 } else { 848 cmd.function = 0; 849 cmd.address = WILC_SDIO_IRQ_FLAG_REG; 850 } 851 cmd.raw = 0; 852 cmd.read_write = 0; 853 cmd.data = 0; 854 wilc_sdio_cmd52(wilc, &cmd); 855 irq_flags = cmd.data; 856 tmp |= FIELD_PREP(IRG_FLAGS_MASK, cmd.data); 857 858 if (FIELD_GET(UNHANDLED_IRQ_MASK, irq_flags)) 859 dev_err(&func->dev, "Unexpected interrupt (1) int=%lx\n", 860 FIELD_GET(UNHANDLED_IRQ_MASK, irq_flags)); 861 862 *int_status = tmp; 863 864 return 0; 865 } 866 867 static int wilc_sdio_clear_int_ext(struct wilc *wilc, u32 val) 868 { 869 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 870 struct wilc_sdio *sdio_priv = wilc->bus_data; 871 int ret; 872 u32 reg = 0; 873 874 if (sdio_priv->irq_gpio) 875 reg = val & (BIT(MAX_NUM_INT) - 1); 876 877 /* select VMM table 0 */ 878 if (val & SEL_VMM_TBL0) 879 reg |= BIT(5); 880 /* select VMM table 1 */ 881 if (val & SEL_VMM_TBL1) 882 reg |= BIT(6); 883 /* enable VMM */ 884 if (val & EN_VMM) 885 reg |= BIT(7); 886 if (reg) { 887 struct sdio_cmd52 cmd; 888 889 cmd.read_write = 1; 890 cmd.function = 0; 891 cmd.raw = 0; 892 cmd.address = WILC_SDIO_IRQ_CLEAR_FLAG_REG; 893 cmd.data = reg; 894 895 ret = wilc_sdio_cmd52(wilc, &cmd); 896 if (ret) { 897 dev_err(&func->dev, 898 "Failed cmd52, set (%02x) data (%d) ...\n", 899 cmd.address, __LINE__); 900 return ret; 901 } 902 } 903 return 0; 904 } 905 906 static int wilc_sdio_sync_ext(struct wilc *wilc, int nint) 907 { 908 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 909 struct wilc_sdio *sdio_priv = wilc->bus_data; 910 u32 reg; 911 912 if (nint > MAX_NUM_INT) { 913 dev_err(&func->dev, "Too many interrupts (%d)...\n", nint); 914 return -EINVAL; 915 } 916 917 /** 918 * Disable power sequencer 919 **/ 920 if (wilc_sdio_read_reg(wilc, WILC_MISC, ®)) { 921 dev_err(&func->dev, "Failed read misc reg...\n"); 922 return -EINVAL; 923 } 924 925 reg &= ~BIT(8); 926 if (wilc_sdio_write_reg(wilc, WILC_MISC, reg)) { 927 dev_err(&func->dev, "Failed write misc reg...\n"); 928 return -EINVAL; 929 } 930 931 if (sdio_priv->irq_gpio) { 932 u32 reg; 933 int ret, i; 934 935 /** 936 * interrupt pin mux select 937 **/ 938 ret = wilc_sdio_read_reg(wilc, WILC_PIN_MUX_0, ®); 939 if (ret) { 940 dev_err(&func->dev, "Failed read reg (%08x)...\n", 941 WILC_PIN_MUX_0); 942 return ret; 943 } 944 reg |= BIT(8); 945 ret = wilc_sdio_write_reg(wilc, WILC_PIN_MUX_0, reg); 946 if (ret) { 947 dev_err(&func->dev, "Failed write reg (%08x)...\n", 948 WILC_PIN_MUX_0); 949 return ret; 950 } 951 952 /** 953 * interrupt enable 954 **/ 955 ret = wilc_sdio_read_reg(wilc, WILC_INTR_ENABLE, ®); 956 if (ret) { 957 dev_err(&func->dev, "Failed read reg (%08x)...\n", 958 WILC_INTR_ENABLE); 959 return ret; 960 } 961 962 for (i = 0; (i < 5) && (nint > 0); i++, nint--) 963 reg |= BIT((27 + i)); 964 ret = wilc_sdio_write_reg(wilc, WILC_INTR_ENABLE, reg); 965 if (ret) { 966 dev_err(&func->dev, "Failed write reg (%08x)...\n", 967 WILC_INTR_ENABLE); 968 return ret; 969 } 970 if (nint) { 971 ret = wilc_sdio_read_reg(wilc, WILC_INTR2_ENABLE, ®); 972 if (ret) { 973 dev_err(&func->dev, 974 "Failed read reg (%08x)...\n", 975 WILC_INTR2_ENABLE); 976 return ret; 977 } 978 979 for (i = 0; (i < 3) && (nint > 0); i++, nint--) 980 reg |= BIT(i); 981 982 ret = wilc_sdio_write_reg(wilc, WILC_INTR2_ENABLE, reg); 983 if (ret) { 984 dev_err(&func->dev, 985 "Failed write reg (%08x)...\n", 986 WILC_INTR2_ENABLE); 987 return ret; 988 } 989 } 990 } 991 return 0; 992 } 993 994 /* Global sdio HIF function table */ 995 static const struct wilc_hif_func wilc_hif_sdio = { 996 .hif_init = wilc_sdio_init, 997 .hif_deinit = wilc_sdio_deinit, 998 .hif_read_reg = wilc_sdio_read_reg, 999 .hif_write_reg = wilc_sdio_write_reg, 1000 .hif_block_rx = wilc_sdio_read, 1001 .hif_block_tx = wilc_sdio_write, 1002 .hif_read_int = wilc_sdio_read_int, 1003 .hif_clear_int_ext = wilc_sdio_clear_int_ext, 1004 .hif_read_size = wilc_sdio_read_size, 1005 .hif_block_tx_ext = wilc_sdio_write, 1006 .hif_block_rx_ext = wilc_sdio_read, 1007 .hif_sync_ext = wilc_sdio_sync_ext, 1008 .enable_interrupt = wilc_sdio_enable_interrupt, 1009 .disable_interrupt = wilc_sdio_disable_interrupt, 1010 .hif_reset = wilc_sdio_reset, 1011 .hif_is_init = wilc_sdio_is_init, 1012 }; 1013 1014 static int wilc_sdio_resume(struct device *dev) 1015 { 1016 struct sdio_func *func = dev_to_sdio_func(dev); 1017 struct wilc *wilc = sdio_get_drvdata(func); 1018 1019 dev_info(dev, "sdio resume\n"); 1020 sdio_release_host(func); 1021 chip_wakeup(wilc); 1022 wilc_sdio_init(wilc, true); 1023 1024 if (wilc->suspend_event) 1025 host_wakeup_notify(wilc); 1026 1027 chip_allow_sleep(wilc); 1028 1029 return 0; 1030 } 1031 1032 static const struct of_device_id wilc_of_match[] = { 1033 { .compatible = "microchip,wilc1000", }, 1034 { /* sentinel */ } 1035 }; 1036 MODULE_DEVICE_TABLE(of, wilc_of_match); 1037 1038 static const struct dev_pm_ops wilc_sdio_pm_ops = { 1039 .suspend = wilc_sdio_suspend, 1040 .resume = wilc_sdio_resume, 1041 }; 1042 1043 static struct sdio_driver wilc_sdio_driver = { 1044 .name = SDIO_MODALIAS, 1045 .id_table = wilc_sdio_ids, 1046 .probe = wilc_sdio_probe, 1047 .remove = wilc_sdio_remove, 1048 .drv = { 1049 .pm = &wilc_sdio_pm_ops, 1050 .of_match_table = wilc_of_match, 1051 } 1052 }; 1053 module_sdio_driver(wilc_sdio_driver); 1054 1055 MODULE_DESCRIPTION("Atmel WILC1000 SDIO wireless driver"); 1056 MODULE_LICENSE("GPL"); 1057