1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries. 4 * All rights reserved. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/mmc/sdio_func.h> 9 #include <linux/mmc/sdio_ids.h> 10 #include <linux/mmc/host.h> 11 #include <linux/mmc/sdio.h> 12 #include <linux/of_irq.h> 13 14 #include "netdev.h" 15 #include "cfg80211.h" 16 17 #define SDIO_MODALIAS "wilc1000_sdio" 18 19 static const struct sdio_device_id wilc_sdio_ids[] = { 20 { SDIO_DEVICE(SDIO_VENDOR_ID_MICROCHIP_WILC, SDIO_DEVICE_ID_MICROCHIP_WILC1000) }, 21 { }, 22 }; 23 MODULE_DEVICE_TABLE(sdio, wilc_sdio_ids); 24 25 #define WILC_SDIO_BLOCK_SIZE 512 26 27 struct wilc_sdio { 28 bool irq_gpio; 29 u32 block_size; 30 bool isinit; 31 int has_thrpt_enh3; 32 u8 *cmd53_buf; 33 }; 34 35 struct sdio_cmd52 { 36 u32 read_write: 1; 37 u32 function: 3; 38 u32 raw: 1; 39 u32 address: 17; 40 u32 data: 8; 41 }; 42 43 struct sdio_cmd53 { 44 u32 read_write: 1; 45 u32 function: 3; 46 u32 block_mode: 1; 47 u32 increment: 1; 48 u32 address: 17; 49 u32 count: 9; 50 u8 *buffer; 51 u32 block_size; 52 bool use_global_buf; 53 }; 54 55 static const struct wilc_hif_func wilc_hif_sdio; 56 57 static void wilc_sdio_interrupt(struct sdio_func *func) 58 { 59 sdio_release_host(func); 60 wilc_handle_isr(sdio_get_drvdata(func)); 61 sdio_claim_host(func); 62 } 63 64 static int wilc_sdio_cmd52(struct wilc *wilc, struct sdio_cmd52 *cmd) 65 { 66 struct sdio_func *func = container_of(wilc->dev, struct sdio_func, dev); 67 int ret; 68 u8 data; 69 70 sdio_claim_host(func); 71 72 func->num = cmd->function; 73 if (cmd->read_write) { /* write */ 74 if (cmd->raw) { 75 sdio_writeb(func, cmd->data, cmd->address, &ret); 76 data = sdio_readb(func, cmd->address, &ret); 77 cmd->data = data; 78 } else { 79 sdio_writeb(func, cmd->data, cmd->address, &ret); 80 } 81 } else { /* read */ 82 data = sdio_readb(func, cmd->address, &ret); 83 cmd->data = data; 84 } 85 86 sdio_release_host(func); 87 88 if (ret) 89 dev_err(&func->dev, "%s..failed, err(%d)\n", __func__, ret); 90 return ret; 91 } 92 93 static int wilc_sdio_cmd53(struct wilc *wilc, struct sdio_cmd53 *cmd) 94 { 95 struct sdio_func *func = container_of(wilc->dev, struct sdio_func, dev); 96 int size, ret; 97 struct wilc_sdio *sdio_priv = wilc->bus_data; 98 u8 *buf = cmd->buffer; 99 100 sdio_claim_host(func); 101 102 func->num = cmd->function; 103 func->cur_blksize = cmd->block_size; 104 if (cmd->block_mode) 105 size = cmd->count * cmd->block_size; 106 else 107 size = cmd->count; 108 109 if (cmd->use_global_buf) { 110 if (size > sizeof(u32)) 111 return -EINVAL; 112 113 buf = sdio_priv->cmd53_buf; 114 } 115 116 if (cmd->read_write) { /* write */ 117 if (cmd->use_global_buf) 118 memcpy(buf, cmd->buffer, size); 119 120 ret = sdio_memcpy_toio(func, cmd->address, buf, size); 121 } else { /* read */ 122 ret = sdio_memcpy_fromio(func, buf, cmd->address, size); 123 124 if (cmd->use_global_buf) 125 memcpy(cmd->buffer, buf, size); 126 } 127 128 sdio_release_host(func); 129 130 if (ret) 131 dev_err(&func->dev, "%s..failed, err(%d)\n", __func__, ret); 132 133 return ret; 134 } 135 136 static int wilc_sdio_probe(struct sdio_func *func, 137 const struct sdio_device_id *id) 138 { 139 struct wilc *wilc; 140 int ret; 141 struct wilc_sdio *sdio_priv; 142 143 sdio_priv = kzalloc(sizeof(*sdio_priv), GFP_KERNEL); 144 if (!sdio_priv) 145 return -ENOMEM; 146 147 sdio_priv->cmd53_buf = kzalloc(sizeof(u32), GFP_KERNEL); 148 if (!sdio_priv->cmd53_buf) { 149 ret = -ENOMEM; 150 goto free; 151 } 152 153 ret = wilc_cfg80211_init(&wilc, &func->dev, WILC_HIF_SDIO, 154 &wilc_hif_sdio); 155 if (ret) 156 goto free; 157 158 if (IS_ENABLED(CONFIG_WILC1000_HW_OOB_INTR)) { 159 struct device_node *np = func->card->dev.of_node; 160 int irq_num = of_irq_get(np, 0); 161 162 if (irq_num > 0) { 163 wilc->dev_irq_num = irq_num; 164 sdio_priv->irq_gpio = true; 165 } 166 } 167 168 sdio_set_drvdata(func, wilc); 169 wilc->bus_data = sdio_priv; 170 wilc->dev = &func->dev; 171 172 wilc->rtc_clk = devm_clk_get_optional(&func->card->dev, "rtc"); 173 if (IS_ERR(wilc->rtc_clk)) { 174 ret = PTR_ERR(wilc->rtc_clk); 175 goto dispose_irq; 176 } 177 clk_prepare_enable(wilc->rtc_clk); 178 179 dev_info(&func->dev, "Driver Initializing success\n"); 180 return 0; 181 182 dispose_irq: 183 irq_dispose_mapping(wilc->dev_irq_num); 184 wilc_netdev_cleanup(wilc); 185 free: 186 kfree(sdio_priv->cmd53_buf); 187 kfree(sdio_priv); 188 return ret; 189 } 190 191 static void wilc_sdio_remove(struct sdio_func *func) 192 { 193 struct wilc *wilc = sdio_get_drvdata(func); 194 struct wilc_sdio *sdio_priv = wilc->bus_data; 195 196 clk_disable_unprepare(wilc->rtc_clk); 197 wilc_netdev_cleanup(wilc); 198 kfree(sdio_priv->cmd53_buf); 199 kfree(sdio_priv); 200 } 201 202 static int wilc_sdio_reset(struct wilc *wilc) 203 { 204 struct sdio_cmd52 cmd; 205 int ret; 206 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 207 208 cmd.read_write = 1; 209 cmd.function = 0; 210 cmd.raw = 0; 211 cmd.address = SDIO_CCCR_ABORT; 212 cmd.data = WILC_SDIO_CCCR_ABORT_RESET; 213 ret = wilc_sdio_cmd52(wilc, &cmd); 214 if (ret) { 215 dev_err(&func->dev, "Fail cmd 52, reset cmd ...\n"); 216 return ret; 217 } 218 return 0; 219 } 220 221 static bool wilc_sdio_is_init(struct wilc *wilc) 222 { 223 struct wilc_sdio *sdio_priv = wilc->bus_data; 224 225 return sdio_priv->isinit; 226 } 227 228 static int wilc_sdio_suspend(struct device *dev) 229 { 230 struct sdio_func *func = dev_to_sdio_func(dev); 231 struct wilc *wilc = sdio_get_drvdata(func); 232 int ret; 233 234 dev_info(dev, "sdio suspend\n"); 235 chip_wakeup(wilc); 236 237 if (!IS_ERR(wilc->rtc_clk)) 238 clk_disable_unprepare(wilc->rtc_clk); 239 240 if (wilc->suspend_event) { 241 host_sleep_notify(wilc); 242 chip_allow_sleep(wilc); 243 } 244 245 ret = wilc_sdio_reset(wilc); 246 if (ret) { 247 dev_err(&func->dev, "Fail reset sdio\n"); 248 return ret; 249 } 250 sdio_claim_host(func); 251 252 return 0; 253 } 254 255 static int wilc_sdio_enable_interrupt(struct wilc *dev) 256 { 257 struct sdio_func *func = container_of(dev->dev, struct sdio_func, dev); 258 int ret = 0; 259 260 sdio_claim_host(func); 261 ret = sdio_claim_irq(func, wilc_sdio_interrupt); 262 sdio_release_host(func); 263 264 if (ret < 0) { 265 dev_err(&func->dev, "can't claim sdio_irq, err(%d)\n", ret); 266 ret = -EIO; 267 } 268 return ret; 269 } 270 271 static void wilc_sdio_disable_interrupt(struct wilc *dev) 272 { 273 struct sdio_func *func = container_of(dev->dev, struct sdio_func, dev); 274 int ret; 275 276 sdio_claim_host(func); 277 ret = sdio_release_irq(func); 278 if (ret < 0) 279 dev_err(&func->dev, "can't release sdio_irq, err(%d)\n", ret); 280 sdio_release_host(func); 281 } 282 283 /******************************************** 284 * 285 * Function 0 286 * 287 ********************************************/ 288 289 static int wilc_sdio_set_func0_csa_address(struct wilc *wilc, u32 adr) 290 { 291 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 292 struct sdio_cmd52 cmd; 293 int ret; 294 295 /** 296 * Review: BIG ENDIAN 297 **/ 298 cmd.read_write = 1; 299 cmd.function = 0; 300 cmd.raw = 0; 301 cmd.address = WILC_SDIO_FBR_CSA_REG; 302 cmd.data = (u8)adr; 303 ret = wilc_sdio_cmd52(wilc, &cmd); 304 if (ret) { 305 dev_err(&func->dev, "Failed cmd52, set %04x data...\n", 306 cmd.address); 307 return ret; 308 } 309 310 cmd.address = WILC_SDIO_FBR_CSA_REG + 1; 311 cmd.data = (u8)(adr >> 8); 312 ret = wilc_sdio_cmd52(wilc, &cmd); 313 if (ret) { 314 dev_err(&func->dev, "Failed cmd52, set %04x data...\n", 315 cmd.address); 316 return ret; 317 } 318 319 cmd.address = WILC_SDIO_FBR_CSA_REG + 2; 320 cmd.data = (u8)(adr >> 16); 321 ret = wilc_sdio_cmd52(wilc, &cmd); 322 if (ret) { 323 dev_err(&func->dev, "Failed cmd52, set %04x data...\n", 324 cmd.address); 325 return ret; 326 } 327 328 return 0; 329 } 330 331 static int wilc_sdio_set_block_size(struct wilc *wilc, u8 func_num, 332 u32 block_size) 333 { 334 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 335 struct sdio_cmd52 cmd; 336 int ret; 337 338 cmd.read_write = 1; 339 cmd.function = 0; 340 cmd.raw = 0; 341 cmd.address = SDIO_FBR_BASE(func_num) + SDIO_CCCR_BLKSIZE; 342 cmd.data = (u8)block_size; 343 ret = wilc_sdio_cmd52(wilc, &cmd); 344 if (ret) { 345 dev_err(&func->dev, "Failed cmd52, set %04x data...\n", 346 cmd.address); 347 return ret; 348 } 349 350 cmd.address = SDIO_FBR_BASE(func_num) + SDIO_CCCR_BLKSIZE + 1; 351 cmd.data = (u8)(block_size >> 8); 352 ret = wilc_sdio_cmd52(wilc, &cmd); 353 if (ret) { 354 dev_err(&func->dev, "Failed cmd52, set %04x data...\n", 355 cmd.address); 356 return ret; 357 } 358 359 return 0; 360 } 361 362 /******************************************** 363 * 364 * Sdio interfaces 365 * 366 ********************************************/ 367 static int wilc_sdio_write_reg(struct wilc *wilc, u32 addr, u32 data) 368 { 369 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 370 struct wilc_sdio *sdio_priv = wilc->bus_data; 371 int ret; 372 373 cpu_to_le32s(&data); 374 375 if (addr >= 0xf0 && addr <= 0xff) { /* only vendor specific registers */ 376 struct sdio_cmd52 cmd; 377 378 cmd.read_write = 1; 379 cmd.function = 0; 380 cmd.raw = 0; 381 cmd.address = addr; 382 cmd.data = data; 383 ret = wilc_sdio_cmd52(wilc, &cmd); 384 if (ret) 385 dev_err(&func->dev, 386 "Failed cmd 52, read reg (%08x) ...\n", addr); 387 } else { 388 struct sdio_cmd53 cmd; 389 390 /** 391 * set the AHB address 392 **/ 393 ret = wilc_sdio_set_func0_csa_address(wilc, addr); 394 if (ret) 395 return ret; 396 397 cmd.read_write = 1; 398 cmd.function = 0; 399 cmd.address = WILC_SDIO_FBR_DATA_REG; 400 cmd.block_mode = 0; 401 cmd.increment = 1; 402 cmd.count = sizeof(u32); 403 cmd.buffer = (u8 *)&data; 404 cmd.use_global_buf = true; 405 cmd.block_size = sdio_priv->block_size; 406 ret = wilc_sdio_cmd53(wilc, &cmd); 407 if (ret) 408 dev_err(&func->dev, 409 "Failed cmd53, write reg (%08x)...\n", addr); 410 } 411 412 return ret; 413 } 414 415 static int wilc_sdio_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size) 416 { 417 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 418 struct wilc_sdio *sdio_priv = wilc->bus_data; 419 u32 block_size = sdio_priv->block_size; 420 struct sdio_cmd53 cmd; 421 int nblk, nleft, ret; 422 423 cmd.read_write = 1; 424 if (addr > 0) { 425 /** 426 * func 0 access 427 **/ 428 cmd.function = 0; 429 cmd.address = WILC_SDIO_FBR_DATA_REG; 430 } else { 431 /** 432 * func 1 access 433 **/ 434 cmd.function = 1; 435 cmd.address = WILC_SDIO_F1_DATA_REG; 436 } 437 438 size = ALIGN(size, 4); 439 nblk = size / block_size; 440 nleft = size % block_size; 441 442 cmd.use_global_buf = false; 443 if (nblk > 0) { 444 cmd.block_mode = 1; 445 cmd.increment = 1; 446 cmd.count = nblk; 447 cmd.buffer = buf; 448 cmd.block_size = block_size; 449 if (addr > 0) { 450 ret = wilc_sdio_set_func0_csa_address(wilc, addr); 451 if (ret) 452 return ret; 453 } 454 ret = wilc_sdio_cmd53(wilc, &cmd); 455 if (ret) { 456 dev_err(&func->dev, 457 "Failed cmd53 [%x], block send...\n", addr); 458 return ret; 459 } 460 if (addr > 0) 461 addr += nblk * block_size; 462 buf += nblk * block_size; 463 } 464 465 if (nleft > 0) { 466 cmd.block_mode = 0; 467 cmd.increment = 1; 468 cmd.count = nleft; 469 cmd.buffer = buf; 470 471 cmd.block_size = block_size; 472 473 if (addr > 0) { 474 ret = wilc_sdio_set_func0_csa_address(wilc, addr); 475 if (ret) 476 return ret; 477 } 478 ret = wilc_sdio_cmd53(wilc, &cmd); 479 if (ret) { 480 dev_err(&func->dev, 481 "Failed cmd53 [%x], bytes send...\n", addr); 482 return ret; 483 } 484 } 485 486 return 0; 487 } 488 489 static int wilc_sdio_read_reg(struct wilc *wilc, u32 addr, u32 *data) 490 { 491 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 492 struct wilc_sdio *sdio_priv = wilc->bus_data; 493 int ret; 494 495 if (addr >= 0xf0 && addr <= 0xff) { /* only vendor specific registers */ 496 struct sdio_cmd52 cmd; 497 498 cmd.read_write = 0; 499 cmd.function = 0; 500 cmd.raw = 0; 501 cmd.address = addr; 502 ret = wilc_sdio_cmd52(wilc, &cmd); 503 if (ret) { 504 dev_err(&func->dev, 505 "Failed cmd 52, read reg (%08x) ...\n", addr); 506 return ret; 507 } 508 *data = cmd.data; 509 } else { 510 struct sdio_cmd53 cmd; 511 512 ret = wilc_sdio_set_func0_csa_address(wilc, addr); 513 if (ret) 514 return ret; 515 516 cmd.read_write = 0; 517 cmd.function = 0; 518 cmd.address = WILC_SDIO_FBR_DATA_REG; 519 cmd.block_mode = 0; 520 cmd.increment = 1; 521 cmd.count = sizeof(u32); 522 cmd.buffer = (u8 *)data; 523 cmd.use_global_buf = true; 524 525 cmd.block_size = sdio_priv->block_size; 526 ret = wilc_sdio_cmd53(wilc, &cmd); 527 if (ret) { 528 dev_err(&func->dev, 529 "Failed cmd53, read reg (%08x)...\n", addr); 530 return ret; 531 } 532 } 533 534 le32_to_cpus(data); 535 return 0; 536 } 537 538 static int wilc_sdio_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size) 539 { 540 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 541 struct wilc_sdio *sdio_priv = wilc->bus_data; 542 u32 block_size = sdio_priv->block_size; 543 struct sdio_cmd53 cmd; 544 int nblk, nleft, ret; 545 546 cmd.read_write = 0; 547 if (addr > 0) { 548 /** 549 * func 0 access 550 **/ 551 cmd.function = 0; 552 cmd.address = WILC_SDIO_FBR_DATA_REG; 553 } else { 554 /** 555 * func 1 access 556 **/ 557 cmd.function = 1; 558 cmd.address = WILC_SDIO_F1_DATA_REG; 559 } 560 561 size = ALIGN(size, 4); 562 nblk = size / block_size; 563 nleft = size % block_size; 564 565 cmd.use_global_buf = false; 566 if (nblk > 0) { 567 cmd.block_mode = 1; 568 cmd.increment = 1; 569 cmd.count = nblk; 570 cmd.buffer = buf; 571 cmd.block_size = block_size; 572 if (addr > 0) { 573 ret = wilc_sdio_set_func0_csa_address(wilc, addr); 574 if (ret) 575 return ret; 576 } 577 ret = wilc_sdio_cmd53(wilc, &cmd); 578 if (ret) { 579 dev_err(&func->dev, 580 "Failed cmd53 [%x], block read...\n", addr); 581 return ret; 582 } 583 if (addr > 0) 584 addr += nblk * block_size; 585 buf += nblk * block_size; 586 } /* if (nblk > 0) */ 587 588 if (nleft > 0) { 589 cmd.block_mode = 0; 590 cmd.increment = 1; 591 cmd.count = nleft; 592 cmd.buffer = buf; 593 594 cmd.block_size = block_size; 595 596 if (addr > 0) { 597 ret = wilc_sdio_set_func0_csa_address(wilc, addr); 598 if (ret) 599 return ret; 600 } 601 ret = wilc_sdio_cmd53(wilc, &cmd); 602 if (ret) { 603 dev_err(&func->dev, 604 "Failed cmd53 [%x], bytes read...\n", addr); 605 return ret; 606 } 607 } 608 609 return 0; 610 } 611 612 /******************************************** 613 * 614 * Bus interfaces 615 * 616 ********************************************/ 617 618 static int wilc_sdio_deinit(struct wilc *wilc) 619 { 620 struct wilc_sdio *sdio_priv = wilc->bus_data; 621 622 sdio_priv->isinit = false; 623 return 0; 624 } 625 626 static int wilc_sdio_init(struct wilc *wilc, bool resume) 627 { 628 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 629 struct wilc_sdio *sdio_priv = wilc->bus_data; 630 struct sdio_cmd52 cmd; 631 int loop, ret; 632 u32 chipid; 633 634 /** 635 * function 0 csa enable 636 **/ 637 cmd.read_write = 1; 638 cmd.function = 0; 639 cmd.raw = 1; 640 cmd.address = SDIO_FBR_BASE(1); 641 cmd.data = SDIO_FBR_ENABLE_CSA; 642 ret = wilc_sdio_cmd52(wilc, &cmd); 643 if (ret) { 644 dev_err(&func->dev, "Fail cmd 52, enable csa...\n"); 645 return ret; 646 } 647 648 /** 649 * function 0 block size 650 **/ 651 ret = wilc_sdio_set_block_size(wilc, 0, WILC_SDIO_BLOCK_SIZE); 652 if (ret) { 653 dev_err(&func->dev, "Fail cmd 52, set func 0 block size...\n"); 654 return ret; 655 } 656 sdio_priv->block_size = WILC_SDIO_BLOCK_SIZE; 657 658 /** 659 * enable func1 IO 660 **/ 661 cmd.read_write = 1; 662 cmd.function = 0; 663 cmd.raw = 1; 664 cmd.address = SDIO_CCCR_IOEx; 665 cmd.data = WILC_SDIO_CCCR_IO_EN_FUNC1; 666 ret = wilc_sdio_cmd52(wilc, &cmd); 667 if (ret) { 668 dev_err(&func->dev, 669 "Fail cmd 52, set IOE register...\n"); 670 return ret; 671 } 672 673 /** 674 * make sure func 1 is up 675 **/ 676 cmd.read_write = 0; 677 cmd.function = 0; 678 cmd.raw = 0; 679 cmd.address = SDIO_CCCR_IORx; 680 loop = 3; 681 do { 682 cmd.data = 0; 683 ret = wilc_sdio_cmd52(wilc, &cmd); 684 if (ret) { 685 dev_err(&func->dev, 686 "Fail cmd 52, get IOR register...\n"); 687 return ret; 688 } 689 if (cmd.data == WILC_SDIO_CCCR_IO_EN_FUNC1) 690 break; 691 } while (loop--); 692 693 if (loop <= 0) { 694 dev_err(&func->dev, "Fail func 1 is not ready...\n"); 695 return -EINVAL; 696 } 697 698 /** 699 * func 1 is ready, set func 1 block size 700 **/ 701 ret = wilc_sdio_set_block_size(wilc, 1, WILC_SDIO_BLOCK_SIZE); 702 if (ret) { 703 dev_err(&func->dev, "Fail set func 1 block size...\n"); 704 return ret; 705 } 706 707 /** 708 * func 1 interrupt enable 709 **/ 710 cmd.read_write = 1; 711 cmd.function = 0; 712 cmd.raw = 1; 713 cmd.address = SDIO_CCCR_IENx; 714 cmd.data = WILC_SDIO_CCCR_IEN_MASTER | WILC_SDIO_CCCR_IEN_FUNC1; 715 ret = wilc_sdio_cmd52(wilc, &cmd); 716 if (ret) { 717 dev_err(&func->dev, "Fail cmd 52, set IEN register...\n"); 718 return ret; 719 } 720 721 /** 722 * make sure can read back chip id correctly 723 **/ 724 if (!resume) { 725 int rev; 726 727 ret = wilc_sdio_read_reg(wilc, WILC_CHIPID, &chipid); 728 if (ret) { 729 dev_err(&func->dev, "Fail cmd read chip id...\n"); 730 return ret; 731 } 732 dev_err(&func->dev, "chipid (%08x)\n", chipid); 733 rev = FIELD_GET(WILC_CHIP_REV_FIELD, chipid); 734 if (rev > FIELD_GET(WILC_CHIP_REV_FIELD, WILC_1000_BASE_ID_2A)) 735 sdio_priv->has_thrpt_enh3 = 1; 736 else 737 sdio_priv->has_thrpt_enh3 = 0; 738 dev_info(&func->dev, "has_thrpt_enh3 = %d...\n", 739 sdio_priv->has_thrpt_enh3); 740 } 741 742 sdio_priv->isinit = true; 743 return 0; 744 } 745 746 static int wilc_sdio_read_size(struct wilc *wilc, u32 *size) 747 { 748 u32 tmp; 749 struct sdio_cmd52 cmd; 750 751 /** 752 * Read DMA count in words 753 **/ 754 cmd.read_write = 0; 755 cmd.function = 0; 756 cmd.raw = 0; 757 cmd.address = WILC_SDIO_INTERRUPT_DATA_SZ_REG; 758 cmd.data = 0; 759 wilc_sdio_cmd52(wilc, &cmd); 760 tmp = cmd.data; 761 762 cmd.address = WILC_SDIO_INTERRUPT_DATA_SZ_REG + 1; 763 cmd.data = 0; 764 wilc_sdio_cmd52(wilc, &cmd); 765 tmp |= (cmd.data << 8); 766 767 *size = tmp; 768 return 0; 769 } 770 771 static int wilc_sdio_read_int(struct wilc *wilc, u32 *int_status) 772 { 773 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 774 struct wilc_sdio *sdio_priv = wilc->bus_data; 775 u32 tmp; 776 u8 irq_flags; 777 struct sdio_cmd52 cmd; 778 779 wilc_sdio_read_size(wilc, &tmp); 780 781 /** 782 * Read IRQ flags 783 **/ 784 if (!sdio_priv->irq_gpio) { 785 cmd.function = 1; 786 cmd.address = WILC_SDIO_EXT_IRQ_FLAG_REG; 787 } else { 788 cmd.function = 0; 789 cmd.address = WILC_SDIO_IRQ_FLAG_REG; 790 } 791 cmd.raw = 0; 792 cmd.read_write = 0; 793 cmd.data = 0; 794 wilc_sdio_cmd52(wilc, &cmd); 795 irq_flags = cmd.data; 796 tmp |= FIELD_PREP(IRG_FLAGS_MASK, cmd.data); 797 798 if (FIELD_GET(UNHANDLED_IRQ_MASK, irq_flags)) 799 dev_err(&func->dev, "Unexpected interrupt (1) int=%lx\n", 800 FIELD_GET(UNHANDLED_IRQ_MASK, irq_flags)); 801 802 *int_status = tmp; 803 804 return 0; 805 } 806 807 static int wilc_sdio_clear_int_ext(struct wilc *wilc, u32 val) 808 { 809 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 810 struct wilc_sdio *sdio_priv = wilc->bus_data; 811 int ret; 812 int vmm_ctl; 813 814 if (sdio_priv->has_thrpt_enh3) { 815 u32 reg = 0; 816 817 if (sdio_priv->irq_gpio) 818 reg = val & (BIT(MAX_NUM_INT) - 1); 819 820 /* select VMM table 0 */ 821 if (val & SEL_VMM_TBL0) 822 reg |= BIT(5); 823 /* select VMM table 1 */ 824 if (val & SEL_VMM_TBL1) 825 reg |= BIT(6); 826 /* enable VMM */ 827 if (val & EN_VMM) 828 reg |= BIT(7); 829 if (reg) { 830 struct sdio_cmd52 cmd; 831 832 cmd.read_write = 1; 833 cmd.function = 0; 834 cmd.raw = 0; 835 cmd.address = WILC_SDIO_IRQ_CLEAR_FLAG_REG; 836 cmd.data = reg; 837 838 ret = wilc_sdio_cmd52(wilc, &cmd); 839 if (ret) { 840 dev_err(&func->dev, 841 "Failed cmd52, set (%02x) data (%d) ...\n", 842 cmd.address, __LINE__); 843 return ret; 844 } 845 } 846 return 0; 847 } 848 if (sdio_priv->irq_gpio) { 849 /* has_thrpt_enh2 uses register 0xf8 to clear interrupts. */ 850 /* 851 * Cannot clear multiple interrupts. 852 * Must clear each interrupt individually. 853 */ 854 u32 flags; 855 int i; 856 857 flags = val & (BIT(MAX_NUM_INT) - 1); 858 for (i = 0; i < NUM_INT_EXT && flags; i++) { 859 if (flags & BIT(i)) { 860 struct sdio_cmd52 cmd; 861 862 cmd.read_write = 1; 863 cmd.function = 0; 864 cmd.raw = 0; 865 cmd.address = WILC_SDIO_IRQ_CLEAR_FLAG_REG; 866 cmd.data = BIT(i); 867 868 ret = wilc_sdio_cmd52(wilc, &cmd); 869 if (ret) { 870 dev_err(&func->dev, 871 "Failed cmd52, set (%02x) data (%d) ...\n", 872 cmd.address, __LINE__); 873 return ret; 874 } 875 flags &= ~BIT(i); 876 } 877 } 878 879 for (i = NUM_INT_EXT; i < MAX_NUM_INT && flags; i++) { 880 if (flags & BIT(i)) { 881 dev_err(&func->dev, 882 "Unexpected interrupt cleared %d...\n", 883 i); 884 flags &= ~BIT(i); 885 } 886 } 887 } 888 889 vmm_ctl = 0; 890 /* select VMM table 0 */ 891 if (val & SEL_VMM_TBL0) 892 vmm_ctl |= BIT(0); 893 /* select VMM table 1 */ 894 if (val & SEL_VMM_TBL1) 895 vmm_ctl |= BIT(1); 896 /* enable VMM */ 897 if (val & EN_VMM) 898 vmm_ctl |= BIT(2); 899 900 if (vmm_ctl) { 901 struct sdio_cmd52 cmd; 902 903 cmd.read_write = 1; 904 cmd.function = 0; 905 cmd.raw = 0; 906 cmd.address = WILC_SDIO_VMM_TBL_CTRL_REG; 907 cmd.data = vmm_ctl; 908 ret = wilc_sdio_cmd52(wilc, &cmd); 909 if (ret) { 910 dev_err(&func->dev, 911 "Failed cmd52, set (%02x) data (%d) ...\n", 912 cmd.address, __LINE__); 913 return ret; 914 } 915 } 916 return 0; 917 } 918 919 static int wilc_sdio_sync_ext(struct wilc *wilc, int nint) 920 { 921 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 922 struct wilc_sdio *sdio_priv = wilc->bus_data; 923 u32 reg; 924 925 if (nint > MAX_NUM_INT) { 926 dev_err(&func->dev, "Too many interrupts (%d)...\n", nint); 927 return -EINVAL; 928 } 929 930 /** 931 * Disable power sequencer 932 **/ 933 if (wilc_sdio_read_reg(wilc, WILC_MISC, ®)) { 934 dev_err(&func->dev, "Failed read misc reg...\n"); 935 return -EINVAL; 936 } 937 938 reg &= ~BIT(8); 939 if (wilc_sdio_write_reg(wilc, WILC_MISC, reg)) { 940 dev_err(&func->dev, "Failed write misc reg...\n"); 941 return -EINVAL; 942 } 943 944 if (sdio_priv->irq_gpio) { 945 u32 reg; 946 int ret, i; 947 948 /** 949 * interrupt pin mux select 950 **/ 951 ret = wilc_sdio_read_reg(wilc, WILC_PIN_MUX_0, ®); 952 if (ret) { 953 dev_err(&func->dev, "Failed read reg (%08x)...\n", 954 WILC_PIN_MUX_0); 955 return ret; 956 } 957 reg |= BIT(8); 958 ret = wilc_sdio_write_reg(wilc, WILC_PIN_MUX_0, reg); 959 if (ret) { 960 dev_err(&func->dev, "Failed write reg (%08x)...\n", 961 WILC_PIN_MUX_0); 962 return ret; 963 } 964 965 /** 966 * interrupt enable 967 **/ 968 ret = wilc_sdio_read_reg(wilc, WILC_INTR_ENABLE, ®); 969 if (ret) { 970 dev_err(&func->dev, "Failed read reg (%08x)...\n", 971 WILC_INTR_ENABLE); 972 return ret; 973 } 974 975 for (i = 0; (i < 5) && (nint > 0); i++, nint--) 976 reg |= BIT((27 + i)); 977 ret = wilc_sdio_write_reg(wilc, WILC_INTR_ENABLE, reg); 978 if (ret) { 979 dev_err(&func->dev, "Failed write reg (%08x)...\n", 980 WILC_INTR_ENABLE); 981 return ret; 982 } 983 if (nint) { 984 ret = wilc_sdio_read_reg(wilc, WILC_INTR2_ENABLE, ®); 985 if (ret) { 986 dev_err(&func->dev, 987 "Failed read reg (%08x)...\n", 988 WILC_INTR2_ENABLE); 989 return ret; 990 } 991 992 for (i = 0; (i < 3) && (nint > 0); i++, nint--) 993 reg |= BIT(i); 994 995 ret = wilc_sdio_write_reg(wilc, WILC_INTR2_ENABLE, reg); 996 if (ret) { 997 dev_err(&func->dev, 998 "Failed write reg (%08x)...\n", 999 WILC_INTR2_ENABLE); 1000 return ret; 1001 } 1002 } 1003 } 1004 return 0; 1005 } 1006 1007 /* Global sdio HIF function table */ 1008 static const struct wilc_hif_func wilc_hif_sdio = { 1009 .hif_init = wilc_sdio_init, 1010 .hif_deinit = wilc_sdio_deinit, 1011 .hif_read_reg = wilc_sdio_read_reg, 1012 .hif_write_reg = wilc_sdio_write_reg, 1013 .hif_block_rx = wilc_sdio_read, 1014 .hif_block_tx = wilc_sdio_write, 1015 .hif_read_int = wilc_sdio_read_int, 1016 .hif_clear_int_ext = wilc_sdio_clear_int_ext, 1017 .hif_read_size = wilc_sdio_read_size, 1018 .hif_block_tx_ext = wilc_sdio_write, 1019 .hif_block_rx_ext = wilc_sdio_read, 1020 .hif_sync_ext = wilc_sdio_sync_ext, 1021 .enable_interrupt = wilc_sdio_enable_interrupt, 1022 .disable_interrupt = wilc_sdio_disable_interrupt, 1023 .hif_reset = wilc_sdio_reset, 1024 .hif_is_init = wilc_sdio_is_init, 1025 }; 1026 1027 static int wilc_sdio_resume(struct device *dev) 1028 { 1029 struct sdio_func *func = dev_to_sdio_func(dev); 1030 struct wilc *wilc = sdio_get_drvdata(func); 1031 1032 dev_info(dev, "sdio resume\n"); 1033 sdio_release_host(func); 1034 chip_wakeup(wilc); 1035 wilc_sdio_init(wilc, true); 1036 1037 if (wilc->suspend_event) 1038 host_wakeup_notify(wilc); 1039 1040 chip_allow_sleep(wilc); 1041 1042 return 0; 1043 } 1044 1045 static const struct of_device_id wilc_of_match[] = { 1046 { .compatible = "microchip,wilc1000", }, 1047 { /* sentinel */ } 1048 }; 1049 MODULE_DEVICE_TABLE(of, wilc_of_match); 1050 1051 static const struct dev_pm_ops wilc_sdio_pm_ops = { 1052 .suspend = wilc_sdio_suspend, 1053 .resume = wilc_sdio_resume, 1054 }; 1055 1056 static struct sdio_driver wilc_sdio_driver = { 1057 .name = SDIO_MODALIAS, 1058 .id_table = wilc_sdio_ids, 1059 .probe = wilc_sdio_probe, 1060 .remove = wilc_sdio_remove, 1061 .drv = { 1062 .pm = &wilc_sdio_pm_ops, 1063 .of_match_table = wilc_of_match, 1064 } 1065 }; 1066 module_driver(wilc_sdio_driver, 1067 sdio_register_driver, 1068 sdio_unregister_driver); 1069 MODULE_LICENSE("GPL"); 1070