1 /* 2 * (c) Copyright 2002-2010, Ralink Technology, Inc. 3 * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org> 4 * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 8 * as published by the Free Software Foundation 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include "mt7601u.h" 17 #include "eeprom.h" 18 #include "trace.h" 19 #include "mcu.h" 20 21 #include "initvals.h" 22 23 static void 24 mt7601u_set_wlan_state(struct mt7601u_dev *dev, u32 val, bool enable) 25 { 26 int i; 27 28 /* Note: we don't turn off WLAN_CLK because that makes the device 29 * not respond properly on the probe path. 30 * In case anyone (PSM?) wants to use this function we can 31 * bring the clock stuff back and fixup the probe path. 32 */ 33 34 if (enable) 35 val |= (MT_WLAN_FUN_CTRL_WLAN_EN | 36 MT_WLAN_FUN_CTRL_WLAN_CLK_EN); 37 else 38 val &= ~(MT_WLAN_FUN_CTRL_WLAN_EN); 39 40 mt7601u_wr(dev, MT_WLAN_FUN_CTRL, val); 41 udelay(20); 42 43 if (enable) { 44 set_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state); 45 } else { 46 clear_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state); 47 return; 48 } 49 50 for (i = 200; i; i--) { 51 val = mt7601u_rr(dev, MT_CMB_CTRL); 52 53 if (val & MT_CMB_CTRL_XTAL_RDY && val & MT_CMB_CTRL_PLL_LD) 54 break; 55 56 udelay(20); 57 } 58 59 /* Note: vendor driver tries to disable/enable wlan here and retry 60 * but the code which does it is so buggy it must have never 61 * triggered, so don't bother. 62 */ 63 if (!i) 64 dev_err(dev->dev, "Error: PLL and XTAL check failed!\n"); 65 } 66 67 static void mt7601u_chip_onoff(struct mt7601u_dev *dev, bool enable, bool reset) 68 { 69 u32 val; 70 71 mutex_lock(&dev->hw_atomic_mutex); 72 73 val = mt7601u_rr(dev, MT_WLAN_FUN_CTRL); 74 75 if (reset) { 76 val |= MT_WLAN_FUN_CTRL_GPIO_OUT_EN; 77 val &= ~MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL; 78 79 if (val & MT_WLAN_FUN_CTRL_WLAN_EN) { 80 val |= (MT_WLAN_FUN_CTRL_WLAN_RESET | 81 MT_WLAN_FUN_CTRL_WLAN_RESET_RF); 82 mt7601u_wr(dev, MT_WLAN_FUN_CTRL, val); 83 udelay(20); 84 85 val &= ~(MT_WLAN_FUN_CTRL_WLAN_RESET | 86 MT_WLAN_FUN_CTRL_WLAN_RESET_RF); 87 } 88 } 89 90 mt7601u_wr(dev, MT_WLAN_FUN_CTRL, val); 91 udelay(20); 92 93 mt7601u_set_wlan_state(dev, val, enable); 94 95 mutex_unlock(&dev->hw_atomic_mutex); 96 } 97 98 static void mt7601u_reset_csr_bbp(struct mt7601u_dev *dev) 99 { 100 mt7601u_wr(dev, MT_MAC_SYS_CTRL, (MT_MAC_SYS_CTRL_RESET_CSR | 101 MT_MAC_SYS_CTRL_RESET_BBP)); 102 mt7601u_wr(dev, MT_USB_DMA_CFG, 0); 103 msleep(1); 104 mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0); 105 } 106 107 static void mt7601u_init_usb_dma(struct mt7601u_dev *dev) 108 { 109 u32 val; 110 111 val = MT76_SET(MT_USB_DMA_CFG_RX_BULK_AGG_TOUT, MT_USB_AGGR_TIMEOUT) | 112 MT76_SET(MT_USB_DMA_CFG_RX_BULK_AGG_LMT, MT_USB_AGGR_SIZE_LIMIT) | 113 MT_USB_DMA_CFG_RX_BULK_EN | 114 MT_USB_DMA_CFG_TX_BULK_EN; 115 if (dev->in_max_packet == 512) 116 val |= MT_USB_DMA_CFG_RX_BULK_AGG_EN; 117 mt7601u_wr(dev, MT_USB_DMA_CFG, val); 118 119 val |= MT_USB_DMA_CFG_UDMA_RX_WL_DROP; 120 mt7601u_wr(dev, MT_USB_DMA_CFG, val); 121 val &= ~MT_USB_DMA_CFG_UDMA_RX_WL_DROP; 122 mt7601u_wr(dev, MT_USB_DMA_CFG, val); 123 } 124 125 static int mt7601u_init_bbp(struct mt7601u_dev *dev) 126 { 127 int ret; 128 129 ret = mt7601u_wait_bbp_ready(dev); 130 if (ret) 131 return ret; 132 133 ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, bbp_common_vals, 134 ARRAY_SIZE(bbp_common_vals)); 135 if (ret) 136 return ret; 137 138 return mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, bbp_chip_vals, 139 ARRAY_SIZE(bbp_chip_vals)); 140 } 141 142 static void 143 mt76_init_beacon_offsets(struct mt7601u_dev *dev) 144 { 145 u16 base = MT_BEACON_BASE; 146 u32 regs[4] = {}; 147 int i; 148 149 for (i = 0; i < 16; i++) { 150 u16 addr = dev->beacon_offsets[i]; 151 152 regs[i / 4] |= ((addr - base) / 64) << (8 * (i % 4)); 153 } 154 155 for (i = 0; i < 4; i++) 156 mt7601u_wr(dev, MT_BCN_OFFSET(i), regs[i]); 157 } 158 159 static int mt7601u_write_mac_initvals(struct mt7601u_dev *dev) 160 { 161 int ret; 162 163 ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_WLAN, mac_common_vals, 164 ARRAY_SIZE(mac_common_vals)); 165 if (ret) 166 return ret; 167 ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_WLAN, 168 mac_chip_vals, ARRAY_SIZE(mac_chip_vals)); 169 if (ret) 170 return ret; 171 172 mt76_init_beacon_offsets(dev); 173 174 mt7601u_wr(dev, MT_AUX_CLK_CFG, 0); 175 176 return 0; 177 } 178 179 static int mt7601u_init_wcid_mem(struct mt7601u_dev *dev) 180 { 181 u32 *vals; 182 int i, ret; 183 184 vals = kmalloc(sizeof(*vals) * N_WCIDS * 2, GFP_KERNEL); 185 if (!vals) 186 return -ENOMEM; 187 188 for (i = 0; i < N_WCIDS; i++) { 189 vals[i * 2] = 0xffffffff; 190 vals[i * 2 + 1] = 0x00ffffff; 191 } 192 193 ret = mt7601u_burst_write_regs(dev, MT_WCID_ADDR_BASE, 194 vals, N_WCIDS * 2); 195 kfree(vals); 196 197 return ret; 198 } 199 200 static int mt7601u_init_key_mem(struct mt7601u_dev *dev) 201 { 202 u32 vals[4] = {}; 203 204 return mt7601u_burst_write_regs(dev, MT_SKEY_MODE_BASE_0, 205 vals, ARRAY_SIZE(vals)); 206 } 207 208 static int mt7601u_init_wcid_attr_mem(struct mt7601u_dev *dev) 209 { 210 u32 *vals; 211 int i, ret; 212 213 vals = kmalloc(sizeof(*vals) * N_WCIDS * 2, GFP_KERNEL); 214 if (!vals) 215 return -ENOMEM; 216 217 for (i = 0; i < N_WCIDS * 2; i++) 218 vals[i] = 1; 219 220 ret = mt7601u_burst_write_regs(dev, MT_WCID_ATTR_BASE, 221 vals, N_WCIDS * 2); 222 kfree(vals); 223 224 return ret; 225 } 226 227 static void mt7601u_reset_counters(struct mt7601u_dev *dev) 228 { 229 mt7601u_rr(dev, MT_RX_STA_CNT0); 230 mt7601u_rr(dev, MT_RX_STA_CNT1); 231 mt7601u_rr(dev, MT_RX_STA_CNT2); 232 mt7601u_rr(dev, MT_TX_STA_CNT0); 233 mt7601u_rr(dev, MT_TX_STA_CNT1); 234 mt7601u_rr(dev, MT_TX_STA_CNT2); 235 } 236 237 int mt7601u_mac_start(struct mt7601u_dev *dev) 238 { 239 mt7601u_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX); 240 241 if (!mt76_poll(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_DMA_BUSY | 242 MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 200000)) 243 return -ETIMEDOUT; 244 245 dev->rxfilter = MT_RX_FILTR_CFG_CRC_ERR | 246 MT_RX_FILTR_CFG_PHY_ERR | MT_RX_FILTR_CFG_PROMISC | 247 MT_RX_FILTR_CFG_VER_ERR | MT_RX_FILTR_CFG_DUP | 248 MT_RX_FILTR_CFG_CFACK | MT_RX_FILTR_CFG_CFEND | 249 MT_RX_FILTR_CFG_ACK | MT_RX_FILTR_CFG_CTS | 250 MT_RX_FILTR_CFG_RTS | MT_RX_FILTR_CFG_PSPOLL | 251 MT_RX_FILTR_CFG_BA | MT_RX_FILTR_CFG_CTRL_RSV; 252 mt7601u_wr(dev, MT_RX_FILTR_CFG, dev->rxfilter); 253 254 mt7601u_wr(dev, MT_MAC_SYS_CTRL, 255 MT_MAC_SYS_CTRL_ENABLE_TX | MT_MAC_SYS_CTRL_ENABLE_RX); 256 257 if (!mt76_poll(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_DMA_BUSY | 258 MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 50)) 259 return -ETIMEDOUT; 260 261 return 0; 262 } 263 264 static void mt7601u_mac_stop_hw(struct mt7601u_dev *dev) 265 { 266 int i, ok; 267 268 if (test_bit(MT7601U_STATE_REMOVED, &dev->state)) 269 return; 270 271 mt76_clear(dev, MT_BEACON_TIME_CFG, MT_BEACON_TIME_CFG_TIMER_EN | 272 MT_BEACON_TIME_CFG_SYNC_MODE | MT_BEACON_TIME_CFG_TBTT_EN | 273 MT_BEACON_TIME_CFG_BEACON_TX); 274 275 if (!mt76_poll(dev, MT_USB_DMA_CFG, MT_USB_DMA_CFG_TX_BUSY, 0, 1000)) 276 dev_warn(dev->dev, "Warning: TX DMA did not stop!\n"); 277 278 /* Page count on TxQ */ 279 i = 200; 280 while (i-- && ((mt76_rr(dev, 0x0438) & 0xffffffff) || 281 (mt76_rr(dev, 0x0a30) & 0x000000ff) || 282 (mt76_rr(dev, 0x0a34) & 0x00ff00ff))) 283 msleep(10); 284 285 if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_TX, 0, 1000)) 286 dev_warn(dev->dev, "Warning: MAC TX did not stop!\n"); 287 288 mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_RX | 289 MT_MAC_SYS_CTRL_ENABLE_TX); 290 291 /* Page count on RxQ */ 292 ok = 0; 293 i = 200; 294 while (i--) { 295 if ((mt76_rr(dev, 0x0430) & 0x00ff0000) || 296 (mt76_rr(dev, 0x0a30) & 0xffffffff) || 297 (mt76_rr(dev, 0x0a34) & 0xffffffff)) 298 ok++; 299 if (ok > 6) 300 break; 301 302 msleep(1); 303 } 304 305 if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_RX, 0, 1000)) 306 dev_warn(dev->dev, "Warning: MAC RX did not stop!\n"); 307 308 if (!mt76_poll(dev, MT_USB_DMA_CFG, MT_USB_DMA_CFG_RX_BUSY, 0, 1000)) 309 dev_warn(dev->dev, "Warning: RX DMA did not stop!\n"); 310 } 311 312 void mt7601u_mac_stop(struct mt7601u_dev *dev) 313 { 314 mt7601u_mac_stop_hw(dev); 315 flush_delayed_work(&dev->stat_work); 316 cancel_delayed_work_sync(&dev->stat_work); 317 } 318 319 static void mt7601u_stop_hardware(struct mt7601u_dev *dev) 320 { 321 mt7601u_chip_onoff(dev, false, false); 322 } 323 324 int mt7601u_init_hardware(struct mt7601u_dev *dev) 325 { 326 static const u16 beacon_offsets[16] = { 327 /* 512 byte per beacon */ 328 0xc000, 0xc200, 0xc400, 0xc600, 329 0xc800, 0xca00, 0xcc00, 0xce00, 330 0xd000, 0xd200, 0xd400, 0xd600, 331 0xd800, 0xda00, 0xdc00, 0xde00 332 }; 333 int ret; 334 335 dev->beacon_offsets = beacon_offsets; 336 337 mt7601u_chip_onoff(dev, true, false); 338 339 ret = mt7601u_wait_asic_ready(dev); 340 if (ret) 341 goto err; 342 ret = mt7601u_mcu_init(dev); 343 if (ret) 344 goto err; 345 346 if (!mt76_poll_msec(dev, MT_WPDMA_GLO_CFG, 347 MT_WPDMA_GLO_CFG_TX_DMA_BUSY | 348 MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 100)) { 349 ret = -EIO; 350 goto err; 351 } 352 353 /* Wait for ASIC ready after FW load. */ 354 ret = mt7601u_wait_asic_ready(dev); 355 if (ret) 356 goto err; 357 358 mt7601u_reset_csr_bbp(dev); 359 mt7601u_init_usb_dma(dev); 360 361 ret = mt7601u_mcu_cmd_init(dev); 362 if (ret) 363 goto err; 364 ret = mt7601u_dma_init(dev); 365 if (ret) 366 goto err_mcu; 367 ret = mt7601u_write_mac_initvals(dev); 368 if (ret) 369 goto err_rx; 370 371 if (!mt76_poll_msec(dev, MT_MAC_STATUS, 372 MT_MAC_STATUS_TX | MT_MAC_STATUS_RX, 0, 100)) { 373 ret = -EIO; 374 goto err_rx; 375 } 376 377 ret = mt7601u_init_bbp(dev); 378 if (ret) 379 goto err_rx; 380 ret = mt7601u_init_wcid_mem(dev); 381 if (ret) 382 goto err_rx; 383 ret = mt7601u_init_key_mem(dev); 384 if (ret) 385 goto err_rx; 386 ret = mt7601u_init_wcid_attr_mem(dev); 387 if (ret) 388 goto err_rx; 389 390 mt76_clear(dev, MT_BEACON_TIME_CFG, (MT_BEACON_TIME_CFG_TIMER_EN | 391 MT_BEACON_TIME_CFG_SYNC_MODE | 392 MT_BEACON_TIME_CFG_TBTT_EN | 393 MT_BEACON_TIME_CFG_BEACON_TX)); 394 395 mt7601u_reset_counters(dev); 396 397 mt7601u_rmw(dev, MT_US_CYC_CFG, MT_US_CYC_CNT, 0x1e); 398 399 mt7601u_wr(dev, MT_TXOP_CTRL_CFG, MT76_SET(MT_TXOP_TRUN_EN, 0x3f) | 400 MT76_SET(MT_TXOP_EXT_CCA_DLY, 0x58)); 401 402 ret = mt7601u_eeprom_init(dev); 403 if (ret) 404 goto err_rx; 405 406 ret = mt7601u_phy_init(dev); 407 if (ret) 408 goto err_rx; 409 410 mt7601u_set_rx_path(dev, 0); 411 mt7601u_set_tx_dac(dev, 0); 412 413 mt7601u_mac_set_ctrlch(dev, false); 414 mt7601u_bbp_set_ctrlch(dev, false); 415 mt7601u_bbp_set_bw(dev, MT_BW_20); 416 417 return 0; 418 419 err_rx: 420 mt7601u_dma_cleanup(dev); 421 err_mcu: 422 mt7601u_mcu_cmd_deinit(dev); 423 err: 424 mt7601u_chip_onoff(dev, false, false); 425 return ret; 426 } 427 428 void mt7601u_cleanup(struct mt7601u_dev *dev) 429 { 430 if (!test_and_clear_bit(MT7601U_STATE_INITIALIZED, &dev->state)) 431 return; 432 433 mt7601u_stop_hardware(dev); 434 mt7601u_dma_cleanup(dev); 435 mt7601u_mcu_cmd_deinit(dev); 436 } 437 438 struct mt7601u_dev *mt7601u_alloc_device(struct device *pdev) 439 { 440 struct ieee80211_hw *hw; 441 struct mt7601u_dev *dev; 442 443 hw = ieee80211_alloc_hw(sizeof(*dev), &mt7601u_ops); 444 if (!hw) 445 return NULL; 446 447 dev = hw->priv; 448 dev->dev = pdev; 449 dev->hw = hw; 450 mutex_init(&dev->vendor_req_mutex); 451 mutex_init(&dev->reg_atomic_mutex); 452 mutex_init(&dev->hw_atomic_mutex); 453 mutex_init(&dev->mutex); 454 spin_lock_init(&dev->tx_lock); 455 spin_lock_init(&dev->rx_lock); 456 spin_lock_init(&dev->lock); 457 spin_lock_init(&dev->mac_lock); 458 spin_lock_init(&dev->con_mon_lock); 459 atomic_set(&dev->avg_ampdu_len, 1); 460 skb_queue_head_init(&dev->tx_skb_done); 461 462 dev->stat_wq = alloc_workqueue("mt7601u", WQ_UNBOUND, 0); 463 if (!dev->stat_wq) { 464 ieee80211_free_hw(hw); 465 return NULL; 466 } 467 468 return dev; 469 } 470 471 #define CHAN2G(_idx, _freq) { \ 472 .band = IEEE80211_BAND_2GHZ, \ 473 .center_freq = (_freq), \ 474 .hw_value = (_idx), \ 475 .max_power = 30, \ 476 } 477 478 static const struct ieee80211_channel mt76_channels_2ghz[] = { 479 CHAN2G(1, 2412), 480 CHAN2G(2, 2417), 481 CHAN2G(3, 2422), 482 CHAN2G(4, 2427), 483 CHAN2G(5, 2432), 484 CHAN2G(6, 2437), 485 CHAN2G(7, 2442), 486 CHAN2G(8, 2447), 487 CHAN2G(9, 2452), 488 CHAN2G(10, 2457), 489 CHAN2G(11, 2462), 490 CHAN2G(12, 2467), 491 CHAN2G(13, 2472), 492 CHAN2G(14, 2484), 493 }; 494 495 #define CCK_RATE(_idx, _rate) { \ 496 .bitrate = _rate, \ 497 .flags = IEEE80211_RATE_SHORT_PREAMBLE, \ 498 .hw_value = (MT_PHY_TYPE_CCK << 8) | _idx, \ 499 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (8 + _idx), \ 500 } 501 502 #define OFDM_RATE(_idx, _rate) { \ 503 .bitrate = _rate, \ 504 .hw_value = (MT_PHY_TYPE_OFDM << 8) | _idx, \ 505 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | _idx, \ 506 } 507 508 static struct ieee80211_rate mt76_rates[] = { 509 CCK_RATE(0, 10), 510 CCK_RATE(1, 20), 511 CCK_RATE(2, 55), 512 CCK_RATE(3, 110), 513 OFDM_RATE(0, 60), 514 OFDM_RATE(1, 90), 515 OFDM_RATE(2, 120), 516 OFDM_RATE(3, 180), 517 OFDM_RATE(4, 240), 518 OFDM_RATE(5, 360), 519 OFDM_RATE(6, 480), 520 OFDM_RATE(7, 540), 521 }; 522 523 static int 524 mt76_init_sband(struct mt7601u_dev *dev, struct ieee80211_supported_band *sband, 525 const struct ieee80211_channel *chan, int n_chan, 526 struct ieee80211_rate *rates, int n_rates) 527 { 528 struct ieee80211_sta_ht_cap *ht_cap; 529 void *chanlist; 530 int size; 531 532 size = n_chan * sizeof(*chan); 533 chanlist = devm_kmemdup(dev->dev, chan, size, GFP_KERNEL); 534 if (!chanlist) 535 return -ENOMEM; 536 537 sband->channels = chanlist; 538 sband->n_channels = n_chan; 539 sband->bitrates = rates; 540 sband->n_bitrates = n_rates; 541 542 ht_cap = &sband->ht_cap; 543 ht_cap->ht_supported = true; 544 ht_cap->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 545 IEEE80211_HT_CAP_GRN_FLD | 546 IEEE80211_HT_CAP_SGI_20 | 547 IEEE80211_HT_CAP_SGI_40 | 548 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 549 550 ht_cap->mcs.rx_mask[0] = 0xff; 551 ht_cap->mcs.rx_mask[4] = 0x1; 552 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 553 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 554 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_2; 555 556 dev->chandef.chan = &sband->channels[0]; 557 558 return 0; 559 } 560 561 static int 562 mt76_init_sband_2g(struct mt7601u_dev *dev) 563 { 564 dev->sband_2g = devm_kzalloc(dev->dev, sizeof(*dev->sband_2g), 565 GFP_KERNEL); 566 dev->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = dev->sband_2g; 567 568 WARN_ON(dev->ee->reg.start - 1 + dev->ee->reg.num > 569 ARRAY_SIZE(mt76_channels_2ghz)); 570 571 return mt76_init_sband(dev, dev->sband_2g, 572 &mt76_channels_2ghz[dev->ee->reg.start - 1], 573 dev->ee->reg.num, 574 mt76_rates, ARRAY_SIZE(mt76_rates)); 575 } 576 577 int mt7601u_register_device(struct mt7601u_dev *dev) 578 { 579 struct ieee80211_hw *hw = dev->hw; 580 struct wiphy *wiphy = hw->wiphy; 581 int ret; 582 583 /* Reserve WCID 0 for mcast - thanks to this APs WCID will go to 584 * entry no. 1 like it does in the vendor driver. 585 */ 586 dev->wcid_mask[0] |= 1; 587 588 /* init fake wcid for monitor interfaces */ 589 dev->mon_wcid = devm_kmalloc(dev->dev, sizeof(*dev->mon_wcid), 590 GFP_KERNEL); 591 if (!dev->mon_wcid) 592 return -ENOMEM; 593 dev->mon_wcid->idx = 0xff; 594 dev->mon_wcid->hw_key_idx = -1; 595 596 SET_IEEE80211_DEV(hw, dev->dev); 597 598 hw->queues = 4; 599 ieee80211_hw_set(hw, SIGNAL_DBM); 600 ieee80211_hw_set(hw, PS_NULLFUNC_STACK); 601 ieee80211_hw_set(hw, SUPPORTS_HT_CCK_RATES); 602 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 603 ieee80211_hw_set(hw, SUPPORTS_RC_TABLE); 604 hw->max_rates = 1; 605 hw->max_report_rates = 7; 606 hw->max_rate_tries = 1; 607 608 hw->sta_data_size = sizeof(struct mt76_sta); 609 hw->vif_data_size = sizeof(struct mt76_vif); 610 611 SET_IEEE80211_PERM_ADDR(hw, dev->macaddr); 612 613 wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR; 614 wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); 615 616 ret = mt76_init_sband_2g(dev); 617 if (ret) 618 return ret; 619 620 INIT_DELAYED_WORK(&dev->mac_work, mt7601u_mac_work); 621 INIT_DELAYED_WORK(&dev->stat_work, mt7601u_tx_stat); 622 623 ret = ieee80211_register_hw(hw); 624 if (ret) 625 return ret; 626 627 mt7601u_init_debugfs(dev); 628 629 return 0; 630 } 631