xref: /linux/drivers/net/wireless/mediatek/mt7601u/core.c (revision 75bf465f0bc33e9b776a46d6a1b9b990f5fb7c37)
1*1802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2c869f77dSJakub Kicinski /*
3c869f77dSJakub Kicinski  * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
4c869f77dSJakub Kicinski  * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
5c869f77dSJakub Kicinski  */
6c869f77dSJakub Kicinski 
7c869f77dSJakub Kicinski #include "mt7601u.h"
8c869f77dSJakub Kicinski 
mt7601u_wait_asic_ready(struct mt7601u_dev * dev)9c869f77dSJakub Kicinski int mt7601u_wait_asic_ready(struct mt7601u_dev *dev)
10c869f77dSJakub Kicinski {
11c869f77dSJakub Kicinski 	int i = 100;
12c869f77dSJakub Kicinski 	u32 val;
13c869f77dSJakub Kicinski 
14c869f77dSJakub Kicinski 	do {
15c869f77dSJakub Kicinski 		if (test_bit(MT7601U_STATE_REMOVED, &dev->state))
16c869f77dSJakub Kicinski 			return -EIO;
17c869f77dSJakub Kicinski 
18c869f77dSJakub Kicinski 		val = mt7601u_rr(dev, MT_MAC_CSR0);
19c869f77dSJakub Kicinski 		if (val && ~val)
20c869f77dSJakub Kicinski 			return 0;
21c869f77dSJakub Kicinski 
22c869f77dSJakub Kicinski 		udelay(10);
23c869f77dSJakub Kicinski 	} while (i--);
24c869f77dSJakub Kicinski 
25c869f77dSJakub Kicinski 	return -EIO;
26c869f77dSJakub Kicinski }
27c869f77dSJakub Kicinski 
mt76_poll(struct mt7601u_dev * dev,u32 offset,u32 mask,u32 val,int timeout)28c869f77dSJakub Kicinski bool mt76_poll(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val,
29c869f77dSJakub Kicinski 	       int timeout)
30c869f77dSJakub Kicinski {
31c869f77dSJakub Kicinski 	u32 cur;
32c869f77dSJakub Kicinski 
33c869f77dSJakub Kicinski 	timeout /= 10;
34c869f77dSJakub Kicinski 	do {
35c869f77dSJakub Kicinski 		if (test_bit(MT7601U_STATE_REMOVED, &dev->state))
36c869f77dSJakub Kicinski 			return false;
37c869f77dSJakub Kicinski 
38c869f77dSJakub Kicinski 		cur = mt7601u_rr(dev, offset) & mask;
39c869f77dSJakub Kicinski 		if (cur == val)
40c869f77dSJakub Kicinski 			return true;
41c869f77dSJakub Kicinski 
42c869f77dSJakub Kicinski 		udelay(10);
43c869f77dSJakub Kicinski 	} while (timeout-- > 0);
44c869f77dSJakub Kicinski 
45c869f77dSJakub Kicinski 	dev_err(dev->dev, "Error: Time out with reg %08x\n", offset);
46c869f77dSJakub Kicinski 
47c869f77dSJakub Kicinski 	return false;
48c869f77dSJakub Kicinski }
49c869f77dSJakub Kicinski 
mt76_poll_msec(struct mt7601u_dev * dev,u32 offset,u32 mask,u32 val,int timeout)50c869f77dSJakub Kicinski bool mt76_poll_msec(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val,
51c869f77dSJakub Kicinski 		    int timeout)
52c869f77dSJakub Kicinski {
53c869f77dSJakub Kicinski 	u32 cur;
54c869f77dSJakub Kicinski 
55c869f77dSJakub Kicinski 	timeout /= 10;
56c869f77dSJakub Kicinski 	do {
57c869f77dSJakub Kicinski 		if (test_bit(MT7601U_STATE_REMOVED, &dev->state))
58c869f77dSJakub Kicinski 			return false;
59c869f77dSJakub Kicinski 
60c869f77dSJakub Kicinski 		cur = mt7601u_rr(dev, offset) & mask;
61c869f77dSJakub Kicinski 		if (cur == val)
62c869f77dSJakub Kicinski 			return true;
63c869f77dSJakub Kicinski 
64c869f77dSJakub Kicinski 		msleep(10);
65c869f77dSJakub Kicinski 	} while (timeout-- > 0);
66c869f77dSJakub Kicinski 
67c869f77dSJakub Kicinski 	dev_err(dev->dev, "Error: Time out with reg %08x\n", offset);
68c869f77dSJakub Kicinski 
69c869f77dSJakub Kicinski 	return false;
70c869f77dSJakub Kicinski }
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