1 /* 2 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "mt76.h" 18 19 static struct mt76_txwi_cache * 20 mt76_alloc_txwi(struct mt76_dev *dev) 21 { 22 struct mt76_txwi_cache *t; 23 dma_addr_t addr; 24 int size; 25 26 size = (sizeof(*t) + L1_CACHE_BYTES - 1) & ~(L1_CACHE_BYTES - 1); 27 t = devm_kzalloc(dev->dev, size, GFP_ATOMIC); 28 if (!t) 29 return NULL; 30 31 addr = dma_map_single(dev->dev, &t->txwi, sizeof(t->txwi), 32 DMA_TO_DEVICE); 33 t->dma_addr = addr; 34 35 return t; 36 } 37 38 static struct mt76_txwi_cache * 39 __mt76_get_txwi(struct mt76_dev *dev) 40 { 41 struct mt76_txwi_cache *t = NULL; 42 43 spin_lock_bh(&dev->lock); 44 if (!list_empty(&dev->txwi_cache)) { 45 t = list_first_entry(&dev->txwi_cache, struct mt76_txwi_cache, 46 list); 47 list_del(&t->list); 48 } 49 spin_unlock_bh(&dev->lock); 50 51 return t; 52 } 53 54 struct mt76_txwi_cache * 55 mt76_get_txwi(struct mt76_dev *dev) 56 { 57 struct mt76_txwi_cache *t = __mt76_get_txwi(dev); 58 59 if (t) 60 return t; 61 62 return mt76_alloc_txwi(dev); 63 } 64 65 void 66 mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t) 67 { 68 if (!t) 69 return; 70 71 spin_lock_bh(&dev->lock); 72 list_add(&t->list, &dev->txwi_cache); 73 spin_unlock_bh(&dev->lock); 74 } 75 76 void mt76_tx_free(struct mt76_dev *dev) 77 { 78 struct mt76_txwi_cache *t; 79 80 while ((t = __mt76_get_txwi(dev)) != NULL) 81 dma_unmap_single(dev->dev, t->dma_addr, sizeof(t->txwi), 82 DMA_TO_DEVICE); 83 } 84 85 static int 86 mt76_txq_get_qid(struct ieee80211_txq *txq) 87 { 88 if (!txq->sta) 89 return MT_TXQ_BE; 90 91 return txq->ac; 92 } 93 94 static void 95 mt76_check_agg_ssn(struct mt76_txq *mtxq, struct sk_buff *skb) 96 { 97 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 98 99 if (!ieee80211_is_data_qos(hdr->frame_control)) 100 return; 101 102 mtxq->agg_ssn = le16_to_cpu(hdr->seq_ctrl) + 0x10; 103 } 104 105 void 106 mt76_tx(struct mt76_dev *dev, struct ieee80211_sta *sta, 107 struct mt76_wcid *wcid, struct sk_buff *skb) 108 { 109 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 110 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 111 struct mt76_queue *q; 112 int qid = skb_get_queue_mapping(skb); 113 114 if (WARN_ON(qid >= MT_TXQ_PSD)) { 115 qid = MT_TXQ_BE; 116 skb_set_queue_mapping(skb, qid); 117 } 118 119 if (!wcid->tx_rate_set) 120 ieee80211_get_tx_rates(info->control.vif, sta, skb, 121 info->control.rates, 1); 122 123 if (sta && ieee80211_is_data_qos(hdr->frame_control)) { 124 struct ieee80211_txq *txq; 125 struct mt76_txq *mtxq; 126 u8 tid; 127 128 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 129 txq = sta->txq[tid]; 130 mtxq = (struct mt76_txq *) txq->drv_priv; 131 132 if (mtxq->aggr) 133 mt76_check_agg_ssn(mtxq, skb); 134 } 135 136 q = &dev->q_tx[qid]; 137 138 spin_lock_bh(&q->lock); 139 dev->queue_ops->tx_queue_skb(dev, q, skb, wcid, sta); 140 dev->queue_ops->kick(dev, q); 141 142 if (q->queued > q->ndesc - 8) 143 ieee80211_stop_queue(dev->hw, skb_get_queue_mapping(skb)); 144 spin_unlock_bh(&q->lock); 145 } 146 EXPORT_SYMBOL_GPL(mt76_tx); 147 148 static struct sk_buff * 149 mt76_txq_dequeue(struct mt76_dev *dev, struct mt76_txq *mtxq, bool ps) 150 { 151 struct ieee80211_txq *txq = mtxq_to_txq(mtxq); 152 struct sk_buff *skb; 153 154 skb = skb_dequeue(&mtxq->retry_q); 155 if (skb) { 156 u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 157 158 if (ps && skb_queue_empty(&mtxq->retry_q)) 159 ieee80211_sta_set_buffered(txq->sta, tid, false); 160 161 return skb; 162 } 163 164 skb = ieee80211_tx_dequeue(dev->hw, txq); 165 if (!skb) 166 return NULL; 167 168 return skb; 169 } 170 171 static void 172 mt76_queue_ps_skb(struct mt76_dev *dev, struct ieee80211_sta *sta, 173 struct sk_buff *skb, bool last) 174 { 175 struct mt76_wcid *wcid = (struct mt76_wcid *) sta->drv_priv; 176 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 177 struct mt76_queue *hwq = &dev->q_tx[MT_TXQ_PSD]; 178 179 info->control.flags |= IEEE80211_TX_CTRL_PS_RESPONSE; 180 if (last) 181 info->flags |= IEEE80211_TX_STATUS_EOSP; 182 183 mt76_skb_set_moredata(skb, !last); 184 dev->queue_ops->tx_queue_skb(dev, hwq, skb, wcid, sta); 185 } 186 187 void 188 mt76_release_buffered_frames(struct ieee80211_hw *hw, struct ieee80211_sta *sta, 189 u16 tids, int nframes, 190 enum ieee80211_frame_release_type reason, 191 bool more_data) 192 { 193 struct mt76_dev *dev = hw->priv; 194 struct sk_buff *last_skb = NULL; 195 struct mt76_queue *hwq = &dev->q_tx[MT_TXQ_PSD]; 196 int i; 197 198 spin_lock_bh(&hwq->lock); 199 for (i = 0; tids && nframes; i++, tids >>= 1) { 200 struct ieee80211_txq *txq = sta->txq[i]; 201 struct mt76_txq *mtxq = (struct mt76_txq *) txq->drv_priv; 202 struct sk_buff *skb; 203 204 if (!(tids & 1)) 205 continue; 206 207 do { 208 skb = mt76_txq_dequeue(dev, mtxq, true); 209 if (!skb) 210 break; 211 212 if (mtxq->aggr) 213 mt76_check_agg_ssn(mtxq, skb); 214 215 nframes--; 216 if (last_skb) 217 mt76_queue_ps_skb(dev, sta, last_skb, false); 218 219 last_skb = skb; 220 } while (nframes); 221 } 222 223 if (last_skb) { 224 mt76_queue_ps_skb(dev, sta, last_skb, true); 225 dev->queue_ops->kick(dev, hwq); 226 } 227 spin_unlock_bh(&hwq->lock); 228 } 229 EXPORT_SYMBOL_GPL(mt76_release_buffered_frames); 230 231 static int 232 mt76_txq_send_burst(struct mt76_dev *dev, struct mt76_queue *hwq, 233 struct mt76_txq *mtxq, bool *empty) 234 { 235 struct ieee80211_txq *txq = mtxq_to_txq(mtxq); 236 struct ieee80211_tx_info *info; 237 struct mt76_wcid *wcid = mtxq->wcid; 238 struct sk_buff *skb; 239 int n_frames = 1, limit; 240 struct ieee80211_tx_rate tx_rate; 241 bool ampdu; 242 bool probe; 243 int idx; 244 245 skb = mt76_txq_dequeue(dev, mtxq, false); 246 if (!skb) { 247 *empty = true; 248 return 0; 249 } 250 251 info = IEEE80211_SKB_CB(skb); 252 if (!wcid->tx_rate_set) 253 ieee80211_get_tx_rates(txq->vif, txq->sta, skb, 254 info->control.rates, 1); 255 tx_rate = info->control.rates[0]; 256 257 probe = (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE); 258 ampdu = IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU; 259 limit = ampdu ? 16 : 3; 260 261 if (ampdu) 262 mt76_check_agg_ssn(mtxq, skb); 263 264 idx = dev->queue_ops->tx_queue_skb(dev, hwq, skb, wcid, txq->sta); 265 266 if (idx < 0) 267 return idx; 268 269 do { 270 bool cur_ampdu; 271 272 if (probe) 273 break; 274 275 if (test_bit(MT76_OFFCHANNEL, &dev->state) || 276 test_bit(MT76_RESET, &dev->state)) 277 return -EBUSY; 278 279 skb = mt76_txq_dequeue(dev, mtxq, false); 280 if (!skb) { 281 *empty = true; 282 break; 283 } 284 285 info = IEEE80211_SKB_CB(skb); 286 cur_ampdu = info->flags & IEEE80211_TX_CTL_AMPDU; 287 288 if (ampdu != cur_ampdu || 289 (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) { 290 skb_queue_tail(&mtxq->retry_q, skb); 291 break; 292 } 293 294 info->control.rates[0] = tx_rate; 295 296 if (cur_ampdu) 297 mt76_check_agg_ssn(mtxq, skb); 298 299 idx = dev->queue_ops->tx_queue_skb(dev, hwq, skb, wcid, 300 txq->sta); 301 if (idx < 0) 302 return idx; 303 304 n_frames++; 305 } while (n_frames < limit); 306 307 if (!probe) { 308 hwq->swq_queued++; 309 hwq->entry[idx].schedule = true; 310 } 311 312 dev->queue_ops->kick(dev, hwq); 313 314 return n_frames; 315 } 316 317 static int 318 mt76_txq_schedule_list(struct mt76_dev *dev, struct mt76_queue *hwq) 319 { 320 struct mt76_txq *mtxq, *mtxq_last; 321 int len = 0; 322 323 restart: 324 mtxq_last = list_last_entry(&hwq->swq, struct mt76_txq, list); 325 while (!list_empty(&hwq->swq)) { 326 bool empty = false; 327 int cur; 328 329 if (test_bit(MT76_OFFCHANNEL, &dev->state) || 330 test_bit(MT76_RESET, &dev->state)) 331 return -EBUSY; 332 333 mtxq = list_first_entry(&hwq->swq, struct mt76_txq, list); 334 if (mtxq->send_bar && mtxq->aggr) { 335 struct ieee80211_txq *txq = mtxq_to_txq(mtxq); 336 struct ieee80211_sta *sta = txq->sta; 337 struct ieee80211_vif *vif = txq->vif; 338 u16 agg_ssn = mtxq->agg_ssn; 339 u8 tid = txq->tid; 340 341 mtxq->send_bar = false; 342 spin_unlock_bh(&hwq->lock); 343 ieee80211_send_bar(vif, sta->addr, tid, agg_ssn); 344 spin_lock_bh(&hwq->lock); 345 goto restart; 346 } 347 348 list_del_init(&mtxq->list); 349 350 cur = mt76_txq_send_burst(dev, hwq, mtxq, &empty); 351 if (!empty) 352 list_add_tail(&mtxq->list, &hwq->swq); 353 354 if (cur < 0) 355 return cur; 356 357 len += cur; 358 359 if (mtxq == mtxq_last) 360 break; 361 } 362 363 return len; 364 } 365 366 void mt76_txq_schedule(struct mt76_dev *dev, struct mt76_queue *hwq) 367 { 368 int len; 369 370 rcu_read_lock(); 371 do { 372 if (hwq->swq_queued >= 4 || list_empty(&hwq->swq)) 373 break; 374 375 len = mt76_txq_schedule_list(dev, hwq); 376 } while (len > 0); 377 rcu_read_unlock(); 378 } 379 EXPORT_SYMBOL_GPL(mt76_txq_schedule); 380 381 void mt76_txq_schedule_all(struct mt76_dev *dev) 382 { 383 int i; 384 385 for (i = 0; i <= MT_TXQ_BK; i++) { 386 struct mt76_queue *q = &dev->q_tx[i]; 387 388 spin_lock_bh(&q->lock); 389 mt76_txq_schedule(dev, q); 390 spin_unlock_bh(&q->lock); 391 } 392 } 393 EXPORT_SYMBOL_GPL(mt76_txq_schedule_all); 394 395 void mt76_stop_tx_queues(struct mt76_dev *dev, struct ieee80211_sta *sta, 396 bool send_bar) 397 { 398 int i; 399 400 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) { 401 struct ieee80211_txq *txq = sta->txq[i]; 402 struct mt76_txq *mtxq = (struct mt76_txq *) txq->drv_priv; 403 404 spin_lock_bh(&mtxq->hwq->lock); 405 mtxq->send_bar = mtxq->aggr && send_bar; 406 if (!list_empty(&mtxq->list)) 407 list_del_init(&mtxq->list); 408 spin_unlock_bh(&mtxq->hwq->lock); 409 } 410 } 411 EXPORT_SYMBOL_GPL(mt76_stop_tx_queues); 412 413 void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq) 414 { 415 struct mt76_dev *dev = hw->priv; 416 struct mt76_txq *mtxq = (struct mt76_txq *) txq->drv_priv; 417 struct mt76_queue *hwq = mtxq->hwq; 418 419 spin_lock_bh(&hwq->lock); 420 if (list_empty(&mtxq->list)) 421 list_add_tail(&mtxq->list, &hwq->swq); 422 mt76_txq_schedule(dev, hwq); 423 spin_unlock_bh(&hwq->lock); 424 } 425 EXPORT_SYMBOL_GPL(mt76_wake_tx_queue); 426 427 void mt76_txq_remove(struct mt76_dev *dev, struct ieee80211_txq *txq) 428 { 429 struct mt76_txq *mtxq; 430 struct mt76_queue *hwq; 431 struct sk_buff *skb; 432 433 if (!txq) 434 return; 435 436 mtxq = (struct mt76_txq *) txq->drv_priv; 437 hwq = mtxq->hwq; 438 439 spin_lock_bh(&hwq->lock); 440 if (!list_empty(&mtxq->list)) 441 list_del(&mtxq->list); 442 spin_unlock_bh(&hwq->lock); 443 444 while ((skb = skb_dequeue(&mtxq->retry_q)) != NULL) 445 ieee80211_free_txskb(dev->hw, skb); 446 } 447 EXPORT_SYMBOL_GPL(mt76_txq_remove); 448 449 void mt76_txq_init(struct mt76_dev *dev, struct ieee80211_txq *txq) 450 { 451 struct mt76_txq *mtxq = (struct mt76_txq *) txq->drv_priv; 452 453 INIT_LIST_HEAD(&mtxq->list); 454 skb_queue_head_init(&mtxq->retry_q); 455 456 mtxq->hwq = &dev->q_tx[mt76_txq_get_qid(txq)]; 457 } 458 EXPORT_SYMBOL_GPL(mt76_txq_init); 459 460 u8 mt76_ac_to_hwq(u8 ac) 461 { 462 static const u8 wmm_queue_map[] = { 463 [IEEE80211_AC_BE] = 0, 464 [IEEE80211_AC_BK] = 1, 465 [IEEE80211_AC_VI] = 2, 466 [IEEE80211_AC_VO] = 3, 467 }; 468 469 if (WARN_ON(ac >= IEEE80211_NUM_ACS)) 470 return 0; 471 472 return wmm_queue_map[ac]; 473 } 474 EXPORT_SYMBOL_GPL(mt76_ac_to_hwq); 475