1 /* 2 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "mt76.h" 18 19 static struct mt76_txwi_cache * 20 mt76_alloc_txwi(struct mt76_dev *dev) 21 { 22 struct mt76_txwi_cache *t; 23 dma_addr_t addr; 24 int size; 25 26 size = (sizeof(*t) + L1_CACHE_BYTES - 1) & ~(L1_CACHE_BYTES - 1); 27 t = devm_kzalloc(dev->dev, size, GFP_ATOMIC); 28 if (!t) 29 return NULL; 30 31 addr = dma_map_single(dev->dev, &t->txwi, sizeof(t->txwi), 32 DMA_TO_DEVICE); 33 t->dma_addr = addr; 34 35 return t; 36 } 37 38 static struct mt76_txwi_cache * 39 __mt76_get_txwi(struct mt76_dev *dev) 40 { 41 struct mt76_txwi_cache *t = NULL; 42 43 spin_lock_bh(&dev->lock); 44 if (!list_empty(&dev->txwi_cache)) { 45 t = list_first_entry(&dev->txwi_cache, struct mt76_txwi_cache, 46 list); 47 list_del(&t->list); 48 } 49 spin_unlock_bh(&dev->lock); 50 51 return t; 52 } 53 54 struct mt76_txwi_cache * 55 mt76_get_txwi(struct mt76_dev *dev) 56 { 57 struct mt76_txwi_cache *t = __mt76_get_txwi(dev); 58 59 if (t) 60 return t; 61 62 return mt76_alloc_txwi(dev); 63 } 64 65 void 66 mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t) 67 { 68 if (!t) 69 return; 70 71 spin_lock_bh(&dev->lock); 72 list_add(&t->list, &dev->txwi_cache); 73 spin_unlock_bh(&dev->lock); 74 } 75 76 void mt76_tx_free(struct mt76_dev *dev) 77 { 78 struct mt76_txwi_cache *t; 79 80 while ((t = __mt76_get_txwi(dev)) != NULL) 81 dma_unmap_single(dev->dev, t->dma_addr, sizeof(t->txwi), 82 DMA_TO_DEVICE); 83 } 84 85 static int 86 mt76_txq_get_qid(struct ieee80211_txq *txq) 87 { 88 if (!txq->sta) 89 return MT_TXQ_BE; 90 91 return txq->ac; 92 } 93 94 static void 95 mt76_check_agg_ssn(struct mt76_txq *mtxq, struct sk_buff *skb) 96 { 97 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 98 99 if (!ieee80211_is_data_qos(hdr->frame_control) || 100 !ieee80211_is_data_present(hdr->frame_control)) 101 return; 102 103 mtxq->agg_ssn = le16_to_cpu(hdr->seq_ctrl) + 0x10; 104 } 105 106 void 107 mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list) 108 __acquires(&dev->status_list.lock) 109 { 110 __skb_queue_head_init(list); 111 spin_lock_bh(&dev->status_list.lock); 112 __acquire(&dev->status_list.lock); 113 } 114 EXPORT_SYMBOL_GPL(mt76_tx_status_lock); 115 116 void 117 mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list) 118 __releases(&dev->status_list.unlock) 119 { 120 struct sk_buff *skb; 121 122 spin_unlock_bh(&dev->status_list.lock); 123 __release(&dev->status_list.unlock); 124 125 while ((skb = __skb_dequeue(list)) != NULL) 126 ieee80211_tx_status(dev->hw, skb); 127 } 128 EXPORT_SYMBOL_GPL(mt76_tx_status_unlock); 129 130 static void 131 __mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb, u8 flags, 132 struct sk_buff_head *list) 133 { 134 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 135 struct mt76_tx_cb *cb = mt76_tx_skb_cb(skb); 136 u8 done = MT_TX_CB_DMA_DONE | MT_TX_CB_TXS_DONE; 137 138 flags |= cb->flags; 139 cb->flags = flags; 140 141 if ((flags & done) != done) 142 return; 143 144 __skb_unlink(skb, &dev->status_list); 145 146 /* Tx status can be unreliable. if it fails, mark the frame as ACKed */ 147 if (flags & MT_TX_CB_TXS_FAILED) { 148 ieee80211_tx_info_clear_status(info); 149 info->status.rates[0].idx = -1; 150 info->flags |= IEEE80211_TX_STAT_ACK; 151 } 152 153 __skb_queue_tail(list, skb); 154 } 155 156 void 157 mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb, 158 struct sk_buff_head *list) 159 { 160 __mt76_tx_status_skb_done(dev, skb, MT_TX_CB_TXS_DONE, list); 161 } 162 EXPORT_SYMBOL_GPL(mt76_tx_status_skb_done); 163 164 int 165 mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid, 166 struct sk_buff *skb) 167 { 168 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 169 struct mt76_tx_cb *cb = mt76_tx_skb_cb(skb); 170 int pid; 171 172 if (!wcid) 173 return MT_PACKET_ID_NO_ACK; 174 175 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 176 return MT_PACKET_ID_NO_ACK; 177 178 if (!(info->flags & (IEEE80211_TX_CTL_REQ_TX_STATUS | 179 IEEE80211_TX_CTL_RATE_CTRL_PROBE))) 180 return MT_PACKET_ID_NO_SKB; 181 182 spin_lock_bh(&dev->status_list.lock); 183 184 memset(cb, 0, sizeof(*cb)); 185 wcid->packet_id = (wcid->packet_id + 1) & MT_PACKET_ID_MASK; 186 if (wcid->packet_id == MT_PACKET_ID_NO_ACK || 187 wcid->packet_id == MT_PACKET_ID_NO_SKB) 188 wcid->packet_id = MT_PACKET_ID_FIRST; 189 190 pid = wcid->packet_id; 191 cb->wcid = wcid->idx; 192 cb->pktid = pid; 193 cb->jiffies = jiffies; 194 195 __skb_queue_tail(&dev->status_list, skb); 196 spin_unlock_bh(&dev->status_list.lock); 197 198 return pid; 199 } 200 EXPORT_SYMBOL_GPL(mt76_tx_status_skb_add); 201 202 struct sk_buff * 203 mt76_tx_status_skb_get(struct mt76_dev *dev, struct mt76_wcid *wcid, int pktid, 204 struct sk_buff_head *list) 205 { 206 struct sk_buff *skb, *tmp; 207 208 if (pktid == MT_PACKET_ID_NO_ACK) 209 return NULL; 210 211 skb_queue_walk_safe(&dev->status_list, skb, tmp) { 212 struct mt76_tx_cb *cb = mt76_tx_skb_cb(skb); 213 214 if (wcid && cb->wcid != wcid->idx) 215 continue; 216 217 if (cb->pktid == pktid) 218 return skb; 219 220 if (!pktid && 221 !time_after(jiffies, cb->jiffies + MT_TX_STATUS_SKB_TIMEOUT)) 222 continue; 223 224 __mt76_tx_status_skb_done(dev, skb, MT_TX_CB_TXS_FAILED | 225 MT_TX_CB_TXS_DONE, list); 226 } 227 228 return NULL; 229 } 230 EXPORT_SYMBOL_GPL(mt76_tx_status_skb_get); 231 232 void 233 mt76_tx_status_check(struct mt76_dev *dev, struct mt76_wcid *wcid, bool flush) 234 { 235 struct sk_buff_head list; 236 237 mt76_tx_status_lock(dev, &list); 238 mt76_tx_status_skb_get(dev, wcid, flush ? -1 : 0, &list); 239 mt76_tx_status_unlock(dev, &list); 240 } 241 EXPORT_SYMBOL_GPL(mt76_tx_status_check); 242 243 void mt76_tx_complete_skb(struct mt76_dev *dev, struct sk_buff *skb) 244 { 245 struct sk_buff_head list; 246 247 if (!skb->prev) { 248 ieee80211_free_txskb(dev->hw, skb); 249 return; 250 } 251 252 mt76_tx_status_lock(dev, &list); 253 __mt76_tx_status_skb_done(dev, skb, MT_TX_CB_DMA_DONE, &list); 254 mt76_tx_status_unlock(dev, &list); 255 } 256 EXPORT_SYMBOL_GPL(mt76_tx_complete_skb); 257 258 void 259 mt76_tx(struct mt76_dev *dev, struct ieee80211_sta *sta, 260 struct mt76_wcid *wcid, struct sk_buff *skb) 261 { 262 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 263 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 264 struct mt76_queue *q; 265 int qid = skb_get_queue_mapping(skb); 266 267 if (WARN_ON(qid >= MT_TXQ_PSD)) { 268 qid = MT_TXQ_BE; 269 skb_set_queue_mapping(skb, qid); 270 } 271 272 if (!wcid->tx_rate_set) 273 ieee80211_get_tx_rates(info->control.vif, sta, skb, 274 info->control.rates, 1); 275 276 if (sta && ieee80211_is_data_qos(hdr->frame_control)) { 277 struct ieee80211_txq *txq; 278 struct mt76_txq *mtxq; 279 u8 tid; 280 281 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 282 txq = sta->txq[tid]; 283 mtxq = (struct mt76_txq *) txq->drv_priv; 284 285 if (mtxq->aggr) 286 mt76_check_agg_ssn(mtxq, skb); 287 } 288 289 q = &dev->q_tx[qid]; 290 291 spin_lock_bh(&q->lock); 292 dev->queue_ops->tx_queue_skb(dev, q, skb, wcid, sta); 293 dev->queue_ops->kick(dev, q); 294 295 if (q->queued > q->ndesc - 8) 296 ieee80211_stop_queue(dev->hw, skb_get_queue_mapping(skb)); 297 spin_unlock_bh(&q->lock); 298 } 299 EXPORT_SYMBOL_GPL(mt76_tx); 300 301 static struct sk_buff * 302 mt76_txq_dequeue(struct mt76_dev *dev, struct mt76_txq *mtxq, bool ps) 303 { 304 struct ieee80211_txq *txq = mtxq_to_txq(mtxq); 305 struct sk_buff *skb; 306 307 skb = skb_dequeue(&mtxq->retry_q); 308 if (skb) { 309 u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 310 311 if (ps && skb_queue_empty(&mtxq->retry_q)) 312 ieee80211_sta_set_buffered(txq->sta, tid, false); 313 314 return skb; 315 } 316 317 skb = ieee80211_tx_dequeue(dev->hw, txq); 318 if (!skb) 319 return NULL; 320 321 return skb; 322 } 323 324 static void 325 mt76_queue_ps_skb(struct mt76_dev *dev, struct ieee80211_sta *sta, 326 struct sk_buff *skb, bool last) 327 { 328 struct mt76_wcid *wcid = (struct mt76_wcid *) sta->drv_priv; 329 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 330 struct mt76_queue *hwq = &dev->q_tx[MT_TXQ_PSD]; 331 332 info->control.flags |= IEEE80211_TX_CTRL_PS_RESPONSE; 333 if (last) 334 info->flags |= IEEE80211_TX_STATUS_EOSP | 335 IEEE80211_TX_CTL_REQ_TX_STATUS; 336 337 mt76_skb_set_moredata(skb, !last); 338 dev->queue_ops->tx_queue_skb(dev, hwq, skb, wcid, sta); 339 } 340 341 void 342 mt76_release_buffered_frames(struct ieee80211_hw *hw, struct ieee80211_sta *sta, 343 u16 tids, int nframes, 344 enum ieee80211_frame_release_type reason, 345 bool more_data) 346 { 347 struct mt76_dev *dev = hw->priv; 348 struct sk_buff *last_skb = NULL; 349 struct mt76_queue *hwq = &dev->q_tx[MT_TXQ_PSD]; 350 int i; 351 352 spin_lock_bh(&hwq->lock); 353 for (i = 0; tids && nframes; i++, tids >>= 1) { 354 struct ieee80211_txq *txq = sta->txq[i]; 355 struct mt76_txq *mtxq = (struct mt76_txq *) txq->drv_priv; 356 struct sk_buff *skb; 357 358 if (!(tids & 1)) 359 continue; 360 361 do { 362 skb = mt76_txq_dequeue(dev, mtxq, true); 363 if (!skb) 364 break; 365 366 if (mtxq->aggr) 367 mt76_check_agg_ssn(mtxq, skb); 368 369 nframes--; 370 if (last_skb) 371 mt76_queue_ps_skb(dev, sta, last_skb, false); 372 373 last_skb = skb; 374 } while (nframes); 375 } 376 377 if (last_skb) { 378 mt76_queue_ps_skb(dev, sta, last_skb, true); 379 dev->queue_ops->kick(dev, hwq); 380 } 381 spin_unlock_bh(&hwq->lock); 382 } 383 EXPORT_SYMBOL_GPL(mt76_release_buffered_frames); 384 385 static int 386 mt76_txq_send_burst(struct mt76_dev *dev, struct mt76_queue *hwq, 387 struct mt76_txq *mtxq, bool *empty) 388 { 389 struct ieee80211_txq *txq = mtxq_to_txq(mtxq); 390 struct ieee80211_tx_info *info; 391 struct mt76_wcid *wcid = mtxq->wcid; 392 struct sk_buff *skb; 393 int n_frames = 1, limit; 394 struct ieee80211_tx_rate tx_rate; 395 bool ampdu; 396 bool probe; 397 int idx; 398 399 if (test_bit(MT_WCID_FLAG_PS, &wcid->flags)) { 400 *empty = true; 401 return 0; 402 } 403 404 skb = mt76_txq_dequeue(dev, mtxq, false); 405 if (!skb) { 406 *empty = true; 407 return 0; 408 } 409 410 info = IEEE80211_SKB_CB(skb); 411 if (!wcid->tx_rate_set) 412 ieee80211_get_tx_rates(txq->vif, txq->sta, skb, 413 info->control.rates, 1); 414 tx_rate = info->control.rates[0]; 415 416 probe = (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE); 417 ampdu = IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU; 418 limit = ampdu ? 16 : 3; 419 420 if (ampdu) 421 mt76_check_agg_ssn(mtxq, skb); 422 423 idx = dev->queue_ops->tx_queue_skb(dev, hwq, skb, wcid, txq->sta); 424 425 if (idx < 0) 426 return idx; 427 428 do { 429 bool cur_ampdu; 430 431 if (probe) 432 break; 433 434 if (test_bit(MT76_OFFCHANNEL, &dev->state) || 435 test_bit(MT76_RESET, &dev->state)) 436 return -EBUSY; 437 438 skb = mt76_txq_dequeue(dev, mtxq, false); 439 if (!skb) { 440 *empty = true; 441 break; 442 } 443 444 info = IEEE80211_SKB_CB(skb); 445 cur_ampdu = info->flags & IEEE80211_TX_CTL_AMPDU; 446 447 if (ampdu != cur_ampdu || 448 (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) { 449 skb_queue_tail(&mtxq->retry_q, skb); 450 break; 451 } 452 453 info->control.rates[0] = tx_rate; 454 455 if (cur_ampdu) 456 mt76_check_agg_ssn(mtxq, skb); 457 458 idx = dev->queue_ops->tx_queue_skb(dev, hwq, skb, wcid, 459 txq->sta); 460 if (idx < 0) 461 return idx; 462 463 n_frames++; 464 } while (n_frames < limit); 465 466 if (!probe) { 467 hwq->swq_queued++; 468 hwq->entry[idx].schedule = true; 469 } 470 471 dev->queue_ops->kick(dev, hwq); 472 473 return n_frames; 474 } 475 476 static int 477 mt76_txq_schedule_list(struct mt76_dev *dev, struct mt76_queue *hwq) 478 { 479 struct mt76_txq *mtxq, *mtxq_last; 480 int len = 0; 481 482 restart: 483 mtxq_last = list_last_entry(&hwq->swq, struct mt76_txq, list); 484 while (!list_empty(&hwq->swq)) { 485 bool empty = false; 486 int cur; 487 488 if (test_bit(MT76_OFFCHANNEL, &dev->state) || 489 test_bit(MT76_RESET, &dev->state)) 490 return -EBUSY; 491 492 mtxq = list_first_entry(&hwq->swq, struct mt76_txq, list); 493 if (mtxq->send_bar && mtxq->aggr) { 494 struct ieee80211_txq *txq = mtxq_to_txq(mtxq); 495 struct ieee80211_sta *sta = txq->sta; 496 struct ieee80211_vif *vif = txq->vif; 497 u16 agg_ssn = mtxq->agg_ssn; 498 u8 tid = txq->tid; 499 500 mtxq->send_bar = false; 501 spin_unlock_bh(&hwq->lock); 502 ieee80211_send_bar(vif, sta->addr, tid, agg_ssn); 503 spin_lock_bh(&hwq->lock); 504 goto restart; 505 } 506 507 list_del_init(&mtxq->list); 508 509 cur = mt76_txq_send_burst(dev, hwq, mtxq, &empty); 510 if (!empty) 511 list_add_tail(&mtxq->list, &hwq->swq); 512 513 if (cur < 0) 514 return cur; 515 516 len += cur; 517 518 if (mtxq == mtxq_last) 519 break; 520 } 521 522 return len; 523 } 524 525 void mt76_txq_schedule(struct mt76_dev *dev, struct mt76_queue *hwq) 526 { 527 int len; 528 529 rcu_read_lock(); 530 do { 531 if (hwq->swq_queued >= 4 || list_empty(&hwq->swq)) 532 break; 533 534 len = mt76_txq_schedule_list(dev, hwq); 535 } while (len > 0); 536 rcu_read_unlock(); 537 } 538 EXPORT_SYMBOL_GPL(mt76_txq_schedule); 539 540 void mt76_txq_schedule_all(struct mt76_dev *dev) 541 { 542 int i; 543 544 for (i = 0; i <= MT_TXQ_BK; i++) { 545 struct mt76_queue *q = &dev->q_tx[i]; 546 547 spin_lock_bh(&q->lock); 548 mt76_txq_schedule(dev, q); 549 spin_unlock_bh(&q->lock); 550 } 551 } 552 EXPORT_SYMBOL_GPL(mt76_txq_schedule_all); 553 554 void mt76_stop_tx_queues(struct mt76_dev *dev, struct ieee80211_sta *sta, 555 bool send_bar) 556 { 557 int i; 558 559 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) { 560 struct ieee80211_txq *txq = sta->txq[i]; 561 struct mt76_txq *mtxq; 562 563 if (!txq) 564 continue; 565 566 mtxq = (struct mt76_txq *)txq->drv_priv; 567 568 spin_lock_bh(&mtxq->hwq->lock); 569 mtxq->send_bar = mtxq->aggr && send_bar; 570 if (!list_empty(&mtxq->list)) 571 list_del_init(&mtxq->list); 572 spin_unlock_bh(&mtxq->hwq->lock); 573 } 574 } 575 EXPORT_SYMBOL_GPL(mt76_stop_tx_queues); 576 577 void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq) 578 { 579 struct mt76_dev *dev = hw->priv; 580 struct mt76_txq *mtxq = (struct mt76_txq *) txq->drv_priv; 581 struct mt76_queue *hwq = mtxq->hwq; 582 583 spin_lock_bh(&hwq->lock); 584 if (list_empty(&mtxq->list)) 585 list_add_tail(&mtxq->list, &hwq->swq); 586 mt76_txq_schedule(dev, hwq); 587 spin_unlock_bh(&hwq->lock); 588 } 589 EXPORT_SYMBOL_GPL(mt76_wake_tx_queue); 590 591 void mt76_txq_remove(struct mt76_dev *dev, struct ieee80211_txq *txq) 592 { 593 struct mt76_txq *mtxq; 594 struct mt76_queue *hwq; 595 struct sk_buff *skb; 596 597 if (!txq) 598 return; 599 600 mtxq = (struct mt76_txq *) txq->drv_priv; 601 hwq = mtxq->hwq; 602 603 spin_lock_bh(&hwq->lock); 604 if (!list_empty(&mtxq->list)) 605 list_del_init(&mtxq->list); 606 spin_unlock_bh(&hwq->lock); 607 608 while ((skb = skb_dequeue(&mtxq->retry_q)) != NULL) 609 ieee80211_free_txskb(dev->hw, skb); 610 } 611 EXPORT_SYMBOL_GPL(mt76_txq_remove); 612 613 void mt76_txq_init(struct mt76_dev *dev, struct ieee80211_txq *txq) 614 { 615 struct mt76_txq *mtxq = (struct mt76_txq *) txq->drv_priv; 616 617 INIT_LIST_HEAD(&mtxq->list); 618 skb_queue_head_init(&mtxq->retry_q); 619 620 mtxq->hwq = &dev->q_tx[mt76_txq_get_qid(txq)]; 621 } 622 EXPORT_SYMBOL_GPL(mt76_txq_init); 623 624 u8 mt76_ac_to_hwq(u8 ac) 625 { 626 static const u8 wmm_queue_map[] = { 627 [IEEE80211_AC_BE] = 0, 628 [IEEE80211_AC_BK] = 1, 629 [IEEE80211_AC_VI] = 2, 630 [IEEE80211_AC_VO] = 3, 631 }; 632 633 if (WARN_ON(ac >= IEEE80211_NUM_ACS)) 634 return 0; 635 636 return wmm_queue_map[ac]; 637 } 638 EXPORT_SYMBOL_GPL(mt76_ac_to_hwq); 639