1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. 3 * 4 * Author: Felix Fietkau <nbd@nbd.name> 5 * Lorenzo Bianconi <lorenzo@kernel.org> 6 * Sean Wang <sean.wang@mediatek.com> 7 */ 8 9 #include <linux/kernel.h> 10 #include <linux/iopoll.h> 11 #include <linux/module.h> 12 13 #include <linux/mmc/host.h> 14 #include <linux/mmc/sdio_ids.h> 15 #include <linux/mmc/sdio_func.h> 16 17 #include "trace.h" 18 #include "sdio.h" 19 #include "mt76.h" 20 21 static int mt76s_refill_sched_quota(struct mt76_dev *dev, u32 *data) 22 { 23 u32 ple_ac_data_quota[] = { 24 FIELD_GET(TXQ_CNT_L, data[4]), /* VO */ 25 FIELD_GET(TXQ_CNT_H, data[3]), /* VI */ 26 FIELD_GET(TXQ_CNT_L, data[3]), /* BE */ 27 FIELD_GET(TXQ_CNT_H, data[2]), /* BK */ 28 }; 29 u32 pse_ac_data_quota[] = { 30 FIELD_GET(TXQ_CNT_H, data[1]), /* VO */ 31 FIELD_GET(TXQ_CNT_L, data[1]), /* VI */ 32 FIELD_GET(TXQ_CNT_H, data[0]), /* BE */ 33 FIELD_GET(TXQ_CNT_L, data[0]), /* BK */ 34 }; 35 u32 pse_mcu_quota = FIELD_GET(TXQ_CNT_L, data[2]); 36 u32 pse_data_quota = 0, ple_data_quota = 0; 37 struct mt76_sdio *sdio = &dev->sdio; 38 int i; 39 40 for (i = 0; i < ARRAY_SIZE(pse_ac_data_quota); i++) { 41 pse_data_quota += pse_ac_data_quota[i]; 42 ple_data_quota += ple_ac_data_quota[i]; 43 } 44 45 if (!pse_data_quota && !ple_data_quota && !pse_mcu_quota) 46 return 0; 47 48 sdio->sched.pse_mcu_quota += pse_mcu_quota; 49 sdio->sched.pse_data_quota += pse_data_quota; 50 sdio->sched.ple_data_quota += ple_data_quota; 51 52 return pse_data_quota + ple_data_quota + pse_mcu_quota; 53 } 54 55 static struct sk_buff * 56 mt76s_build_rx_skb(void *data, int data_len, int buf_len) 57 { 58 int len = min_t(int, data_len, MT_SKB_HEAD_LEN); 59 struct sk_buff *skb; 60 61 skb = alloc_skb(len, GFP_KERNEL); 62 if (!skb) 63 return NULL; 64 65 skb_put_data(skb, data, len); 66 if (data_len > len) { 67 struct page *page; 68 69 data += len; 70 page = virt_to_head_page(data); 71 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 72 page, data - page_address(page), 73 data_len - len, buf_len); 74 get_page(page); 75 } 76 77 return skb; 78 } 79 80 static int 81 mt76s_rx_run_queue(struct mt76_dev *dev, enum mt76_rxq_id qid, 82 struct mt76s_intr *intr) 83 { 84 struct mt76_queue *q = &dev->q_rx[qid]; 85 struct mt76_sdio *sdio = &dev->sdio; 86 int len = 0, err, i; 87 struct page *page; 88 u8 *buf; 89 90 for (i = 0; i < intr->rx.num[qid]; i++) 91 len += round_up(intr->rx.len[qid][i] + 4, 4); 92 93 if (!len) 94 return 0; 95 96 if (len > sdio->func->cur_blksize) 97 len = roundup(len, sdio->func->cur_blksize); 98 99 page = __dev_alloc_pages(GFP_KERNEL, get_order(len)); 100 if (!page) 101 return -ENOMEM; 102 103 buf = page_address(page); 104 105 sdio_claim_host(sdio->func); 106 err = sdio_readsb(sdio->func, buf, MCR_WRDR(qid), len); 107 sdio_release_host(sdio->func); 108 109 if (err < 0) { 110 dev_err(dev->dev, "sdio read data failed:%d\n", err); 111 put_page(page); 112 return err; 113 } 114 115 for (i = 0; i < intr->rx.num[qid]; i++) { 116 int index = (q->head + i) % q->ndesc; 117 struct mt76_queue_entry *e = &q->entry[index]; 118 __le32 *rxd = (__le32 *)buf; 119 120 /* parse rxd to get the actual packet length */ 121 len = le32_get_bits(rxd[0], GENMASK(15, 0)); 122 e->skb = mt76s_build_rx_skb(buf, len, round_up(len + 4, 4)); 123 if (!e->skb) 124 break; 125 126 buf += round_up(len + 4, 4); 127 if (q->queued + i + 1 == q->ndesc) 128 break; 129 } 130 put_page(page); 131 132 spin_lock_bh(&q->lock); 133 q->head = (q->head + i) % q->ndesc; 134 q->queued += i; 135 spin_unlock_bh(&q->lock); 136 137 return i; 138 } 139 140 static int mt76s_rx_handler(struct mt76_dev *dev) 141 { 142 struct mt76_sdio *sdio = &dev->sdio; 143 struct mt76s_intr intr; 144 int nframes = 0, ret; 145 146 ret = sdio->parse_irq(dev, &intr); 147 if (ret) 148 return ret; 149 150 trace_dev_irq(dev, intr.isr, 0); 151 152 if (intr.isr & WHIER_RX0_DONE_INT_EN) { 153 ret = mt76s_rx_run_queue(dev, 0, &intr); 154 if (ret > 0) { 155 mt76_worker_schedule(&sdio->net_worker); 156 nframes += ret; 157 } 158 } 159 160 if (intr.isr & WHIER_RX1_DONE_INT_EN) { 161 ret = mt76s_rx_run_queue(dev, 1, &intr); 162 if (ret > 0) { 163 mt76_worker_schedule(&sdio->net_worker); 164 nframes += ret; 165 } 166 } 167 168 nframes += !!mt76s_refill_sched_quota(dev, intr.tx.wtqcr); 169 170 return nframes; 171 } 172 173 static int 174 mt76s_tx_pick_quota(struct mt76_sdio *sdio, bool mcu, int buf_sz, 175 int *pse_size, int *ple_size) 176 { 177 int pse_sz; 178 179 pse_sz = DIV_ROUND_UP(buf_sz + sdio->sched.deficit, 180 sdio->sched.pse_page_size); 181 182 if (mcu && sdio->hw_ver == MT76_CONNAC2_SDIO) 183 pse_sz = 1; 184 185 if (mcu) { 186 if (sdio->sched.pse_mcu_quota < *pse_size + pse_sz) 187 return -EBUSY; 188 } else { 189 if (sdio->sched.pse_data_quota < *pse_size + pse_sz || 190 sdio->sched.ple_data_quota < *ple_size + 1) 191 return -EBUSY; 192 193 *ple_size = *ple_size + 1; 194 } 195 *pse_size = *pse_size + pse_sz; 196 197 return 0; 198 } 199 200 static void 201 mt76s_tx_update_quota(struct mt76_sdio *sdio, bool mcu, int pse_size, 202 int ple_size) 203 { 204 if (mcu) { 205 sdio->sched.pse_mcu_quota -= pse_size; 206 } else { 207 sdio->sched.pse_data_quota -= pse_size; 208 sdio->sched.ple_data_quota -= ple_size; 209 } 210 } 211 212 static int __mt76s_xmit_queue(struct mt76_dev *dev, u8 *data, int len) 213 { 214 struct mt76_sdio *sdio = &dev->sdio; 215 int err; 216 217 if (len > sdio->func->cur_blksize) 218 len = roundup(len, sdio->func->cur_blksize); 219 220 sdio_claim_host(sdio->func); 221 err = sdio_writesb(sdio->func, MCR_WTDR1, data, len); 222 sdio_release_host(sdio->func); 223 224 if (err) 225 dev_err(dev->dev, "sdio write failed: %d\n", err); 226 227 return err; 228 } 229 230 static int mt76s_tx_run_queue(struct mt76_dev *dev, struct mt76_queue *q) 231 { 232 int err, nframes = 0, len = 0, pse_sz = 0, ple_sz = 0; 233 bool mcu = q == dev->q_mcu[MT_MCUQ_WM]; 234 struct mt76_sdio *sdio = &dev->sdio; 235 u8 pad; 236 237 while (q->first != q->head) { 238 struct mt76_queue_entry *e = &q->entry[q->first]; 239 struct sk_buff *iter; 240 241 smp_rmb(); 242 243 if (test_bit(MT76_MCU_RESET, &dev->phy.state)) 244 goto next; 245 246 if (!test_bit(MT76_STATE_MCU_RUNNING, &dev->phy.state)) { 247 __skb_put_zero(e->skb, 4); 248 err = __mt76s_xmit_queue(dev, e->skb->data, 249 e->skb->len); 250 if (err) 251 return err; 252 253 goto next; 254 } 255 256 pad = roundup(e->skb->len, 4) - e->skb->len; 257 if (len + e->skb->len + pad + 4 > dev->sdio.xmit_buf_sz) 258 break; 259 260 if (mt76s_tx_pick_quota(sdio, mcu, e->buf_sz, &pse_sz, 261 &ple_sz)) 262 break; 263 264 memcpy(sdio->xmit_buf + len, e->skb->data, skb_headlen(e->skb)); 265 len += skb_headlen(e->skb); 266 nframes++; 267 268 skb_walk_frags(e->skb, iter) { 269 memcpy(sdio->xmit_buf + len, iter->data, iter->len); 270 len += iter->len; 271 nframes++; 272 } 273 274 if (unlikely(pad)) { 275 memset(sdio->xmit_buf + len, 0, pad); 276 len += pad; 277 } 278 next: 279 q->first = (q->first + 1) % q->ndesc; 280 e->done = true; 281 } 282 283 if (nframes) { 284 memset(sdio->xmit_buf + len, 0, 4); 285 err = __mt76s_xmit_queue(dev, sdio->xmit_buf, len + 4); 286 if (err) 287 return err; 288 } 289 mt76s_tx_update_quota(sdio, mcu, pse_sz, ple_sz); 290 291 mt76_worker_schedule(&sdio->status_worker); 292 293 return nframes; 294 } 295 296 void mt76s_txrx_worker(struct mt76_sdio *sdio) 297 { 298 struct mt76_dev *dev = container_of(sdio, struct mt76_dev, sdio); 299 int i, nframes, ret; 300 301 /* disable interrupt */ 302 sdio_claim_host(sdio->func); 303 sdio_writel(sdio->func, WHLPCR_INT_EN_CLR, MCR_WHLPCR, NULL); 304 sdio_release_host(sdio->func); 305 306 do { 307 nframes = 0; 308 309 /* tx */ 310 for (i = 0; i <= MT_TXQ_PSD; i++) { 311 ret = mt76s_tx_run_queue(dev, dev->phy.q_tx[i]); 312 if (ret > 0) 313 nframes += ret; 314 } 315 ret = mt76s_tx_run_queue(dev, dev->q_mcu[MT_MCUQ_WM]); 316 if (ret > 0) 317 nframes += ret; 318 319 /* rx */ 320 ret = mt76s_rx_handler(dev); 321 if (ret > 0) 322 nframes += ret; 323 324 if (test_bit(MT76_MCU_RESET, &dev->phy.state) || 325 test_bit(MT76_STATE_SUSPEND, &dev->phy.state)) { 326 if (!mt76s_txqs_empty(dev)) 327 continue; 328 else 329 wake_up(&sdio->wait); 330 } 331 } while (nframes > 0); 332 333 /* enable interrupt */ 334 sdio_claim_host(sdio->func); 335 sdio_writel(sdio->func, WHLPCR_INT_EN_SET, MCR_WHLPCR, NULL); 336 sdio_release_host(sdio->func); 337 } 338 EXPORT_SYMBOL_GPL(mt76s_txrx_worker); 339 340 void mt76s_sdio_irq(struct sdio_func *func) 341 { 342 struct mt76_dev *dev = sdio_get_drvdata(func); 343 struct mt76_sdio *sdio = &dev->sdio; 344 345 if (!test_bit(MT76_STATE_INITIALIZED, &dev->phy.state) || 346 test_bit(MT76_MCU_RESET, &dev->phy.state)) 347 return; 348 349 sdio_writel(sdio->func, WHLPCR_INT_EN_CLR, MCR_WHLPCR, NULL); 350 mt76_worker_schedule(&sdio->txrx_worker); 351 } 352 EXPORT_SYMBOL_GPL(mt76s_sdio_irq); 353 354 bool mt76s_txqs_empty(struct mt76_dev *dev) 355 { 356 struct mt76_queue *q; 357 int i; 358 359 for (i = 0; i <= MT_TXQ_PSD + 1; i++) { 360 if (i <= MT_TXQ_PSD) 361 q = dev->phy.q_tx[i]; 362 else 363 q = dev->q_mcu[MT_MCUQ_WM]; 364 365 if (q->first != q->head) 366 return false; 367 } 368 369 return true; 370 } 371 EXPORT_SYMBOL_GPL(mt76s_txqs_empty); 372