1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. 3 * 4 * Author: Felix Fietkau <nbd@nbd.name> 5 * Lorenzo Bianconi <lorenzo@kernel.org> 6 * Sean Wang <sean.wang@mediatek.com> 7 */ 8 9 #include <linux/kernel.h> 10 #include <linux/iopoll.h> 11 #include <linux/module.h> 12 13 #include <linux/mmc/host.h> 14 #include <linux/mmc/sdio_ids.h> 15 #include <linux/mmc/sdio_func.h> 16 17 #include "trace.h" 18 #include "sdio.h" 19 #include "mt76.h" 20 21 static int mt76s_refill_sched_quota(struct mt76_dev *dev, u32 *data) 22 { 23 u32 ple_ac_data_quota[] = { 24 FIELD_GET(TXQ_CNT_L, data[4]), /* VO */ 25 FIELD_GET(TXQ_CNT_H, data[3]), /* VI */ 26 FIELD_GET(TXQ_CNT_L, data[3]), /* BE */ 27 FIELD_GET(TXQ_CNT_H, data[2]), /* BK */ 28 }; 29 u32 pse_ac_data_quota[] = { 30 FIELD_GET(TXQ_CNT_H, data[1]), /* VO */ 31 FIELD_GET(TXQ_CNT_L, data[1]), /* VI */ 32 FIELD_GET(TXQ_CNT_H, data[0]), /* BE */ 33 FIELD_GET(TXQ_CNT_L, data[0]), /* BK */ 34 }; 35 u32 pse_mcu_quota = FIELD_GET(TXQ_CNT_L, data[2]); 36 u32 pse_data_quota = 0, ple_data_quota = 0; 37 struct mt76_sdio *sdio = &dev->sdio; 38 int i; 39 40 for (i = 0; i < ARRAY_SIZE(pse_ac_data_quota); i++) { 41 pse_data_quota += pse_ac_data_quota[i]; 42 ple_data_quota += ple_ac_data_quota[i]; 43 } 44 45 if (!pse_data_quota && !ple_data_quota && !pse_mcu_quota) 46 return 0; 47 48 sdio->sched.pse_mcu_quota += pse_mcu_quota; 49 if (sdio->pse_mcu_quota_max && 50 sdio->sched.pse_mcu_quota > sdio->pse_mcu_quota_max) { 51 sdio->sched.pse_mcu_quota = sdio->pse_mcu_quota_max; 52 } 53 sdio->sched.pse_data_quota += pse_data_quota; 54 sdio->sched.ple_data_quota += ple_data_quota; 55 56 return pse_data_quota + ple_data_quota + pse_mcu_quota; 57 } 58 59 static struct sk_buff * 60 mt76s_build_rx_skb(void *data, int data_len, int buf_len) 61 { 62 int len = min_t(int, data_len, MT_SKB_HEAD_LEN); 63 struct sk_buff *skb; 64 65 skb = alloc_skb(len, GFP_KERNEL); 66 if (!skb) 67 return NULL; 68 69 skb_put_data(skb, data, len); 70 if (data_len > len) { 71 struct page *page; 72 73 data += len; 74 page = virt_to_head_page(data); 75 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 76 page, data - page_address(page), 77 data_len - len, buf_len); 78 get_page(page); 79 } 80 81 return skb; 82 } 83 84 static int 85 mt76s_rx_run_queue(struct mt76_dev *dev, enum mt76_rxq_id qid, 86 struct mt76s_intr *intr) 87 { 88 struct mt76_queue *q = &dev->q_rx[qid]; 89 struct mt76_sdio *sdio = &dev->sdio; 90 int len = 0, err, i; 91 struct page *page; 92 u8 *buf, *end; 93 94 for (i = 0; i < intr->rx.num[qid]; i++) 95 len += round_up(intr->rx.len[qid][i] + 4, 4); 96 97 if (!len) 98 return 0; 99 100 if (len > sdio->func->cur_blksize) 101 len = roundup(len, sdio->func->cur_blksize); 102 103 page = __dev_alloc_pages(GFP_KERNEL, get_order(len)); 104 if (!page) 105 return -ENOMEM; 106 107 buf = page_address(page); 108 109 sdio_claim_host(sdio->func); 110 err = sdio_readsb(sdio->func, buf, MCR_WRDR(qid), len); 111 sdio_release_host(sdio->func); 112 113 if (err < 0) { 114 dev_err(dev->dev, "sdio read data failed:%d\n", err); 115 atomic_set(&dev->bus_hung, true); 116 put_page(page); 117 return err; 118 } 119 120 end = buf + len; 121 i = 0; 122 123 while (i < intr->rx.num[qid] && buf < end) { 124 int index = (q->head + i) % q->ndesc; 125 struct mt76_queue_entry *e = &q->entry[index]; 126 __le32 *rxd = (__le32 *)buf; 127 128 /* parse rxd to get the actual packet length */ 129 len = le32_get_bits(rxd[0], GENMASK(15, 0)); 130 131 /* Optimized path for TXS */ 132 if (!dev->drv->rx_check || dev->drv->rx_check(dev, buf, len)) { 133 e->skb = mt76s_build_rx_skb(buf, len, 134 round_up(len + 4, 4)); 135 if (!e->skb) 136 break; 137 138 if (q->queued + i + 1 == q->ndesc) 139 break; 140 i++; 141 } 142 buf += round_up(len + 4, 4); 143 } 144 put_page(page); 145 146 spin_lock_bh(&q->lock); 147 q->head = (q->head + i) % q->ndesc; 148 q->queued += i; 149 spin_unlock_bh(&q->lock); 150 151 return i; 152 } 153 154 static int mt76s_rx_handler(struct mt76_dev *dev) 155 { 156 struct mt76_sdio *sdio = &dev->sdio; 157 struct mt76s_intr intr; 158 int nframes = 0, ret; 159 160 ret = sdio->parse_irq(dev, &intr); 161 if (ret) 162 return ret; 163 164 trace_dev_irq(dev, intr.isr, 0); 165 166 if (intr.isr & WHIER_RX0_DONE_INT_EN) { 167 ret = mt76s_rx_run_queue(dev, 0, &intr); 168 if (ret > 0) { 169 mt76_worker_schedule(&sdio->net_worker); 170 nframes += ret; 171 } 172 } 173 174 if (intr.isr & WHIER_RX1_DONE_INT_EN) { 175 ret = mt76s_rx_run_queue(dev, 1, &intr); 176 if (ret > 0) { 177 mt76_worker_schedule(&sdio->net_worker); 178 nframes += ret; 179 } 180 } 181 182 nframes += !!mt76s_refill_sched_quota(dev, intr.tx.wtqcr); 183 184 return nframes; 185 } 186 187 static int 188 mt76s_tx_pick_quota(struct mt76_sdio *sdio, bool mcu, int buf_sz, 189 int *pse_size, int *ple_size) 190 { 191 int pse_sz; 192 193 pse_sz = DIV_ROUND_UP(buf_sz + sdio->sched.deficit, 194 sdio->sched.pse_page_size); 195 196 if (mcu && sdio->hw_ver == MT76_CONNAC2_SDIO) 197 pse_sz = 1; 198 199 if (mcu) { 200 if (sdio->sched.pse_mcu_quota < *pse_size + pse_sz) 201 return -EBUSY; 202 } else { 203 if (sdio->sched.pse_data_quota < *pse_size + pse_sz || 204 sdio->sched.ple_data_quota < *ple_size + 1) 205 return -EBUSY; 206 207 *ple_size = *ple_size + 1; 208 } 209 *pse_size = *pse_size + pse_sz; 210 211 return 0; 212 } 213 214 static void 215 mt76s_tx_update_quota(struct mt76_sdio *sdio, bool mcu, int pse_size, 216 int ple_size) 217 { 218 if (mcu) { 219 sdio->sched.pse_mcu_quota -= pse_size; 220 } else { 221 sdio->sched.pse_data_quota -= pse_size; 222 sdio->sched.ple_data_quota -= ple_size; 223 } 224 } 225 226 static int __mt76s_xmit_queue(struct mt76_dev *dev, u8 *data, int len) 227 { 228 struct mt76_sdio *sdio = &dev->sdio; 229 int err; 230 231 if (len > sdio->func->cur_blksize) 232 len = roundup(len, sdio->func->cur_blksize); 233 234 sdio_claim_host(sdio->func); 235 err = sdio_writesb(sdio->func, MCR_WTDR1, data, len); 236 sdio_release_host(sdio->func); 237 238 if (err) { 239 dev_err(dev->dev, "sdio write failed: %d\n", err); 240 atomic_set(&dev->bus_hung, true); 241 } 242 return err; 243 } 244 245 static int mt76s_tx_run_queue(struct mt76_dev *dev, struct mt76_queue *q) 246 { 247 int err, nframes = 0, len = 0, pse_sz = 0, ple_sz = 0; 248 bool mcu = q == dev->q_mcu[MT_MCUQ_WM]; 249 struct mt76_sdio *sdio = &dev->sdio; 250 u8 pad; 251 252 while (q->first != q->head) { 253 struct mt76_queue_entry *e = &q->entry[q->first]; 254 struct sk_buff *iter; 255 256 smp_rmb(); 257 258 if (test_bit(MT76_MCU_RESET, &dev->phy.state)) 259 goto next; 260 261 if (!test_bit(MT76_STATE_MCU_RUNNING, &dev->phy.state)) { 262 __skb_put_zero(e->skb, 4); 263 err = __skb_grow(e->skb, roundup(e->skb->len, 264 sdio->func->cur_blksize)); 265 if (err) 266 return err; 267 err = __mt76s_xmit_queue(dev, e->skb->data, 268 e->skb->len); 269 if (err) 270 return err; 271 272 goto next; 273 } 274 275 pad = roundup(e->skb->len, 4) - e->skb->len; 276 if (len + e->skb->len + pad + 4 > dev->sdio.xmit_buf_sz) 277 break; 278 279 if (mt76s_tx_pick_quota(sdio, mcu, e->buf_sz, &pse_sz, 280 &ple_sz)) 281 break; 282 283 memcpy(sdio->xmit_buf + len, e->skb->data, skb_headlen(e->skb)); 284 len += skb_headlen(e->skb); 285 nframes++; 286 287 skb_walk_frags(e->skb, iter) { 288 memcpy(sdio->xmit_buf + len, iter->data, iter->len); 289 len += iter->len; 290 nframes++; 291 } 292 293 if (unlikely(pad)) { 294 memset(sdio->xmit_buf + len, 0, pad); 295 len += pad; 296 } 297 next: 298 q->first = (q->first + 1) % q->ndesc; 299 e->done = true; 300 } 301 302 if (nframes) { 303 memset(sdio->xmit_buf + len, 0, 4); 304 err = __mt76s_xmit_queue(dev, sdio->xmit_buf, len + 4); 305 if (err) 306 return err; 307 } 308 mt76s_tx_update_quota(sdio, mcu, pse_sz, ple_sz); 309 310 mt76_worker_schedule(&sdio->status_worker); 311 312 return nframes; 313 } 314 315 void mt76s_txrx_worker(struct mt76_sdio *sdio) 316 { 317 struct mt76_dev *dev = container_of(sdio, struct mt76_dev, sdio); 318 int i, nframes, ret; 319 320 /* disable interrupt */ 321 sdio_claim_host(sdio->func); 322 sdio_writel(sdio->func, WHLPCR_INT_EN_CLR, MCR_WHLPCR, NULL); 323 sdio_release_host(sdio->func); 324 325 do { 326 nframes = 0; 327 328 /* tx */ 329 for (i = 0; i <= MT_TXQ_PSD; i++) { 330 ret = mt76s_tx_run_queue(dev, dev->phy.q_tx[i]); 331 if (ret > 0) 332 nframes += ret; 333 } 334 ret = mt76s_tx_run_queue(dev, dev->q_mcu[MT_MCUQ_WM]); 335 if (ret > 0) 336 nframes += ret; 337 338 /* rx */ 339 ret = mt76s_rx_handler(dev); 340 if (ret > 0) 341 nframes += ret; 342 343 if (test_bit(MT76_MCU_RESET, &dev->phy.state) || 344 test_bit(MT76_STATE_SUSPEND, &dev->phy.state)) { 345 if (!mt76s_txqs_empty(dev)) 346 continue; 347 else 348 wake_up(&sdio->wait); 349 } 350 } while (nframes > 0); 351 352 /* enable interrupt */ 353 sdio_claim_host(sdio->func); 354 sdio_writel(sdio->func, WHLPCR_INT_EN_SET, MCR_WHLPCR, NULL); 355 sdio_release_host(sdio->func); 356 } 357 EXPORT_SYMBOL_GPL(mt76s_txrx_worker); 358 359 void mt76s_sdio_irq(struct sdio_func *func) 360 { 361 struct mt76_dev *dev = sdio_get_drvdata(func); 362 struct mt76_sdio *sdio = &dev->sdio; 363 364 if (!test_bit(MT76_STATE_INITIALIZED, &dev->phy.state) || 365 test_bit(MT76_MCU_RESET, &dev->phy.state)) 366 return; 367 368 sdio_writel(sdio->func, WHLPCR_INT_EN_CLR, MCR_WHLPCR, NULL); 369 mt76_worker_schedule(&sdio->txrx_worker); 370 } 371 EXPORT_SYMBOL_GPL(mt76s_sdio_irq); 372 373 bool mt76s_txqs_empty(struct mt76_dev *dev) 374 { 375 struct mt76_queue *q; 376 int i; 377 378 for (i = 0; i <= MT_TXQ_PSD + 1; i++) { 379 if (i <= MT_TXQ_PSD) 380 q = dev->phy.q_tx[i]; 381 else 382 q = dev->q_mcu[MT_MCUQ_WM]; 383 384 if (q->first != q->head) 385 return false; 386 } 387 388 return true; 389 } 390 EXPORT_SYMBOL_GPL(mt76s_txqs_empty); 391