1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #ifndef __MT7996_REGS_H 7 #define __MT7996_REGS_H 8 9 struct __map { 10 u32 phys; 11 u32 mapped; 12 u32 size; 13 }; 14 15 struct __base { 16 u32 band_base[__MT_MAX_BAND]; 17 }; 18 19 /* used to differentiate between generations */ 20 struct mt7996_reg_desc { 21 const struct __base *base; 22 const u32 *offs_rev; 23 const struct __map *map; 24 u32 map_size; 25 }; 26 27 enum base_rev { 28 WF_AGG_BASE, 29 WF_ARB_BASE, 30 WF_TMAC_BASE, 31 WF_RMAC_BASE, 32 WF_DMA_BASE, 33 WF_WTBLOFF_BASE, 34 WF_ETBF_BASE, 35 WF_LPON_BASE, 36 WF_MIB_BASE, 37 WF_RATE_BASE, 38 __MT_REG_BASE_MAX, 39 }; 40 41 #define __BASE(_id, _band) (dev->reg.base[(_id)].band_base[(_band)]) 42 43 enum offs_rev { 44 MIB_RVSR0, 45 MIB_RVSR1, 46 MIB_BTSCR5, 47 MIB_BTSCR6, 48 MIB_RSCR1, 49 MIB_RSCR27, 50 MIB_RSCR28, 51 MIB_RSCR29, 52 MIB_RSCR30, 53 MIB_RSCR31, 54 MIB_RSCR33, 55 MIB_RSCR35, 56 MIB_RSCR36, 57 MIB_BSCR0, 58 MIB_BSCR1, 59 MIB_BSCR2, 60 MIB_BSCR3, 61 MIB_BSCR4, 62 MIB_BSCR5, 63 MIB_BSCR6, 64 MIB_BSCR7, 65 MIB_BSCR17, 66 MIB_TRDR1, 67 HIF_REMAP_L1, 68 HIF_REMAP_BASE_L1, 69 HIF_REMAP_L2, 70 HIF_REMAP_BASE_L2, 71 CBTOP1_PHY_END, 72 INFRA_MCU_END, 73 WTBLON_WDUCR, 74 WTBL_UPDATE, 75 WTBL_ITCR, 76 WTBL_ITCR0, 77 WTBL_ITCR1, 78 __MT_OFFS_MAX, 79 }; 80 81 #define __OFFS(id) (dev->reg.offs_rev[(id)]) 82 83 /* RRO TOP */ 84 #define MT_RRO_TOP_BASE 0xA000 85 #define MT_RRO_TOP(ofs) (MT_RRO_TOP_BASE + (ofs)) 86 87 #define MT_RRO_BA_BITMAP_BASE0 MT_RRO_TOP(0x8) 88 #define MT_RRO_BA_BITMAP_BASE1 MT_RRO_TOP(0xC) 89 #define WF_RRO_AXI_MST_CFG MT_RRO_TOP(0xB8) 90 #define WF_RRO_AXI_MST_CFG_DIDX_OK BIT(12) 91 92 #define MT_RRO_ADDR_ARRAY_BASE0 MT_RRO_TOP(0x30) 93 #define MT_RRO_ADDR_ARRAY_BASE1 MT_RRO_TOP(0x34) 94 #define MT_RRO_ADDR_ARRAY_ELEM_ADDR_SEG_MODE BIT(31) 95 96 #define MT_RRO_IND_CMD_SIGNATURE_BASE0 MT_RRO_TOP(0x38) 97 #define MT_RRO_IND_CMD_SIGNATURE_BASE1 MT_RRO_TOP(0x3C) 98 #define MT_RRO_IND_CMD_0_CTRL0 MT_RRO_TOP(0x40) 99 #define MT_RRO_IND_CMD_SIGNATURE_BASE1_EN BIT(31) 100 101 #define MT_RRO_PARTICULAR_CFG0 MT_RRO_TOP(0x5C) 102 #define MT_RRO_PARTICULAR_CFG1 MT_RRO_TOP(0x60) 103 #define MT_RRO_PARTICULAR_CONFG_EN BIT(31) 104 #define MT_RRO_PARTICULAR_SID GENMASK(30, 16) 105 106 #define MT_RRO_BA_BITMAP_BASE_EXT0 MT_RRO_TOP(0x70) 107 #define MT_RRO_BA_BITMAP_BASE_EXT1 MT_RRO_TOP(0x74) 108 #define MT_RRO_HOST_INT_ENA MT_RRO_TOP(0x204) 109 #define MT_RRO_HOST_INT_ENA_HOST_RRO_DONE_ENA BIT(0) 110 111 #define MT_RRO_ADDR_ELEM_SEG_ADDR0 MT_RRO_TOP(0x400) 112 113 #define MT_RRO_3_0_EMU_CONF MT_RRO_TOP(0x600) 114 #define MT_RRO_3_0_EMU_CONF_EN_MASK BIT(11) 115 116 #define MT_RRO_3_1_GLOBAL_CONFIG MT_RRO_TOP(0x604) 117 #define MT_RRO_3_1_GLOBAL_CONFIG_RXDMAD_SEL BIT(6) 118 #define MT_RRO_3_1_GLOBAL_CONFIG_RX_CIDX_RD_EN BIT(3) 119 #define MT_RRO_3_1_GLOBAL_CONFIG_RX_DIDX_WR_EN BIT(2) 120 #define MT_RRO_3_1_GLOBAL_CONFIG_INTERLEAVE_EN BIT(0) 121 122 #define MT_RRO_MSDU_PG_SEG_ADDR0 MT_RRO_TOP(0x620) 123 #define MT_RRO_RX_RING_AP_CIDX_ADDR MT_RRO_TOP(0x6f0) 124 #define MT_RRO_RX_RING_AP_DIDX_ADDR MT_RRO_TOP(0x6f4) 125 126 #define MT_RRO_ACK_SN_CTRL MT_RRO_TOP(0x50) 127 #define MT_RRO_ACK_SN_CTRL_SN_MASK GENMASK(27, 16) 128 #define MT_RRO_ACK_SN_CTRL_SESSION_MASK GENMASK(11, 0) 129 130 #define MT_RRO_DBG_RD_CTRL MT_RRO_TOP(0xe0) 131 #define MT_RRO_DBG_RD_ADDR GENMASK(15, 0) 132 #define MT_RRO_DBG_RD_EXEC BIT(31) 133 134 #define MT_RRO_DBG_RDAT_DW(_n) MT_RRO_TOP(0xf0 + (_n) * 0x4) 135 136 #define MT_MCU_INT_EVENT 0x2108 137 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0) 138 #define MT_MCU_INT_EVENT_DMA_INIT BIT(1) 139 #define MT_MCU_INT_EVENT_RESET_DONE BIT(3) 140 141 /* PLE */ 142 #define MT_PLE_BASE 0x820c0000 143 #define MT_PLE(ofs) (MT_PLE_BASE + (ofs)) 144 145 #define MT_FL_Q_EMPTY MT_PLE(0x360) 146 #define MT_FL_Q0_CTRL MT_PLE(0x3e0) 147 #define MT_FL_Q2_CTRL MT_PLE(0x3e8) 148 #define MT_FL_Q3_CTRL MT_PLE(0x3ec) 149 150 #define MT_PLE_FREEPG_CNT MT_PLE(0x380) 151 #define MT_PLE_FREEPG_HEAD_TAIL MT_PLE(0x384) 152 #define MT_PLE_PG_HIF_GROUP MT_PLE(0x00c) 153 #define MT_PLE_HIF_PG_INFO MT_PLE(0x388) 154 155 #define MT_PLE_AC_QEMPTY(ac, n) MT_PLE(0x600 + 0x80 * (ac) + ((n) << 2)) 156 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2)) 157 158 /* WF MDP TOP */ 159 #define MT_MDP_BASE 0x820cc000 160 #define MT_MDP(ofs) (MT_MDP_BASE + (ofs)) 161 162 #define MT_MDP_DCR2 MT_MDP(0x8e8) 163 #define MT_MDP_DCR2_RX_TRANS_SHORT BIT(2) 164 165 /* TMAC: band 0(0x820e4000), band 1(0x820f4000), band 2(0x830e4000) */ 166 #define MT_WF_TMAC_BASE(_band) __BASE(WF_TMAC_BASE, (_band)) 167 #define MT_WF_TMAC(_band, ofs) (MT_WF_TMAC_BASE(_band) + (ofs)) 168 169 #define MT_TMAC_TCR0(_band) MT_WF_TMAC(_band, 0) 170 #define MT_TMAC_TCR0_TX_BLINK GENMASK(7, 6) 171 172 #define MT_TMAC_CDTR(_band) MT_WF_TMAC(_band, 0x0c8) 173 #define MT_TMAC_ODTR(_band) MT_WF_TMAC(_band, 0x0cc) 174 #define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0) 175 #define MT_TIMEOUT_VAL_CCA GENMASK(31, 16) 176 177 #define MT_TMAC_ICR0(_band) MT_WF_TMAC(_band, 0x014) 178 #define MT_IFS_EIFS_OFDM GENMASK(8, 0) 179 #define MT_IFS_RIFS GENMASK(14, 10) 180 #define MT_IFS_SIFS GENMASK(22, 16) 181 #define MT_IFS_SLOT GENMASK(30, 24) 182 183 #define MT_TMAC_ICR1(_band) MT_WF_TMAC(_band, 0x018) 184 #define MT_IFS_EIFS_CCK GENMASK(8, 0) 185 186 /* WF DMA TOP: band 0(0x820e7000), band 1(0x820f7000), band 2(0x830e7000) */ 187 #define MT_WF_DMA_BASE(_band) __BASE(WF_DMA_BASE, (_band)) 188 #define MT_WF_DMA(_band, ofs) (MT_WF_DMA_BASE(_band) + (ofs)) 189 190 #define MT_DMA_DCR0(_band) MT_WF_DMA(_band, 0x000) 191 #define MT_DMA_DCR0_RXD_G5_EN BIT(23) 192 193 #define MT_DMA_TCRF1(_band) MT_WF_DMA(_band, 0x054) 194 #define MT_DMA_TCRF1_QIDX GENMASK(15, 13) 195 196 /* WTBLOFF TOP: band 0(0x820e9000), band 1(0x820f9000), band 2(0x830e9000) */ 197 #define MT_WTBLOFF_BASE(_band) __BASE(WF_WTBLOFF_BASE, (_band)) 198 #define MT_WTBLOFF(_band, ofs) (MT_WTBLOFF_BASE(_band) + (ofs)) 199 200 #define MT_WTBLOFF_RSCR(_band) MT_WTBLOFF(_band, 0x008) 201 #define MT_WTBLOFF_RSCR_RCPI_MODE GENMASK(31, 30) 202 #define MT_WTBLOFF_RSCR_RCPI_PARAM GENMASK(25, 24) 203 204 #define MT_WTBLOFF_ACR(_band) MT_WTBLOFF(_band, 0x010) 205 #define MT_WTBLOFF_ADM_BACKOFFTIME BIT(29) 206 207 /* ETBF: band 0(0x820ea000), band 1(0x820fa000), band 2(0x830ea000) */ 208 #define MT_WF_ETBF_BASE(_band) __BASE(WF_ETBF_BASE, (_band)) 209 #define MT_WF_ETBF(_band, ofs) (MT_WF_ETBF_BASE(_band) + (ofs)) 210 211 #define MT_ETBF_RX_FB_CONT(_band) MT_WF_ETBF(_band, 0x100) 212 #define MT_ETBF_RX_FB_BW GENMASK(10, 8) 213 #define MT_ETBF_RX_FB_NC GENMASK(7, 4) 214 #define MT_ETBF_RX_FB_NR GENMASK(3, 0) 215 216 /* LPON: band 0(0x820eb000), band 1(0x820fb000), band 2(0x830eb000) */ 217 #define MT_WF_LPON_BASE(_band) __BASE(WF_LPON_BASE, (_band)) 218 #define MT_WF_LPON(_band, ofs) (MT_WF_LPON_BASE(_band) + (ofs)) 219 220 #define MT_LPON_UTTR0(_band) MT_WF_LPON(_band, 0x360) 221 #define MT_LPON_UTTR1(_band) MT_WF_LPON(_band, 0x364) 222 #define MT_LPON_FRCR(_band) MT_WF_LPON(_band, 0x37c) 223 224 #define MT_LPON_TCR(_band, n) MT_WF_LPON(_band, 0x0a8 + (((n) * 4) << 4)) 225 #define MT_LPON_TCR_SW_MODE GENMASK(1, 0) 226 #define MT_LPON_TCR_SW_WRITE BIT(0) 227 #define MT_LPON_TCR_SW_ADJUST BIT(1) 228 #define MT_LPON_TCR_SW_READ GENMASK(1, 0) 229 230 /* MIB: band 0(0x820ed000), band 1(0x820fd000), band 2(0x830ed000)*/ 231 /* These counters are (mostly?) clear-on-read. So, some should not 232 * be read at all in case firmware is already reading them. These 233 * are commented with 'DNR' below. The DNR stats will be read by querying 234 * the firmware API for the appropriate message. For counters the driver 235 * does read, the driver should accumulate the counters. 236 */ 237 #define MT_WF_MIB_BASE(_band) __BASE(WF_MIB_BASE, (_band)) 238 #define MT_WF_MIB(_band, ofs) (MT_WF_MIB_BASE(_band) + (ofs)) 239 240 #define MT_MIB_BSCR0(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR0)) 241 #define MT_MIB_BSCR1(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR1)) 242 #define MT_MIB_BSCR2(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR2)) 243 #define MT_MIB_BSCR3(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR3)) 244 #define MT_MIB_BSCR4(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR4)) 245 #define MT_MIB_BSCR5(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR5)) 246 #define MT_MIB_BSCR6(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR6)) 247 #define MT_MIB_BSCR7(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR7)) 248 #define MT_MIB_BSCR17(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR17)) 249 250 #define MT_MIB_TSCR5(_band) MT_WF_MIB(_band, 0x6c4) 251 #define MT_MIB_TSCR6(_band) MT_WF_MIB(_band, 0x6c8) 252 #define MT_MIB_TSCR7(_band) MT_WF_MIB(_band, 0x6d0) 253 254 #define MT_MIB_RSCR1(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR1)) 255 /* rx mpdu counter, full 32 bits */ 256 #define MT_MIB_RSCR31(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR31)) 257 #define MT_MIB_RSCR33(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR33)) 258 259 #define MT_MIB_SDR6(_band) MT_WF_MIB(_band, 0x020) 260 #define MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK GENMASK(15, 0) 261 262 #define MT_MIB_RVSR0(_band) MT_WF_MIB(_band, __OFFS(MIB_RVSR0)) 263 264 #define MT_MIB_RSCR35(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR35)) 265 #define MT_MIB_RSCR36(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR36)) 266 267 /* tx ampdu cnt, full 32 bits */ 268 #define MT_MIB_TSCR0(_band) MT_WF_MIB(_band, 0x6b0) 269 #define MT_MIB_TSCR2(_band) MT_WF_MIB(_band, 0x6b8) 270 271 /* counts all mpdus in ampdu, regardless of success */ 272 #define MT_MIB_TSCR3(_band) MT_WF_MIB(_band, 0x6bc) 273 274 /* counts all successfully tx'd mpdus in ampdu */ 275 #define MT_MIB_TSCR4(_band) MT_WF_MIB(_band, 0x6c0) 276 277 /* rx ampdu count, 32-bit */ 278 #define MT_MIB_RSCR27(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR27)) 279 280 /* rx ampdu bytes count, 32-bit */ 281 #define MT_MIB_RSCR28(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR28)) 282 283 /* rx ampdu valid subframe count */ 284 #define MT_MIB_RSCR29(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR29)) 285 286 /* rx ampdu valid subframe bytes count, 32bits */ 287 #define MT_MIB_RSCR30(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR30)) 288 289 /* remaining windows protected stats */ 290 #define MT_MIB_SDR27(_band) MT_WF_MIB(_band, 0x080) 291 #define MT_MIB_SDR27_TX_RWP_FAIL_CNT GENMASK(15, 0) 292 293 #define MT_MIB_SDR28(_band) MT_WF_MIB(_band, 0x084) 294 #define MT_MIB_SDR28_TX_RWP_NEED_CNT GENMASK(15, 0) 295 296 #define MT_MIB_RVSR1(_band) MT_WF_MIB(_band, __OFFS(MIB_RVSR1)) 297 298 /* rx blockack count, 32 bits */ 299 #define MT_MIB_TSCR1(_band) MT_WF_MIB(_band, 0x6b4) 300 301 #define MT_MIB_BTSCR0(_band) MT_WF_MIB(_band, 0x5e0) 302 #define MT_MIB_BTSCR5(_band) MT_WF_MIB(_band, __OFFS(MIB_BTSCR5)) 303 #define MT_MIB_BTSCR6(_band) MT_WF_MIB(_band, __OFFS(MIB_BTSCR6)) 304 305 #define MT_MIB_BFTFCR(_band) MT_WF_MIB(_band, 0x5d0) 306 307 #define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(_band, __OFFS(MIB_TRDR1) + ((n) << 2)) 308 #define MT_MIB_ARNG(_band, n) MT_WF_MIB(_band, 0x0b0 + ((n) << 2)) 309 #define MT_MIB_ARNCR_RANGE(val, n) (((val) >> ((n) << 4)) & GENMASK(9, 0)) 310 311 /* UMIB */ 312 #define MT_WF_UMIB_BASE 0x820cd000 313 #define MT_WF_UMIB(ofs) (MT_WF_UMIB_BASE + (ofs)) 314 315 #define MT_UMIB_RPDCR(_band) (MT_WF_UMIB(0x594) + (_band) * 0x164) 316 317 /* WTBLON TOP */ 318 #define MT_WTBLON_TOP_BASE 0x820d4000 319 #define MT_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs)) 320 #define MT_WTBLON_TOP_WDUCR MT_WTBLON_TOP(__OFFS(WTBLON_WDUCR)) 321 #define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(4, 0) 322 323 #define MT_WTBL_UPDATE MT_WTBLON_TOP(__OFFS(WTBL_UPDATE)) 324 #define MT_WTBL_UPDATE_WLAN_IDX GENMASK(11, 0) 325 #define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(14) 326 #define MT_WTBL_UPDATE_BUSY BIT(31) 327 328 #define MT_WTBL_ITCR MT_WTBLON_TOP(__OFFS(WTBL_ITCR)) 329 #define MT_WTBL_ITCR_WR BIT(16) 330 #define MT_WTBL_ITCR_EXEC BIT(31) 331 #define MT_WTBL_ITDR0 MT_WTBLON_TOP(__OFFS(WTBL_ITCR0)) 332 #define MT_WTBL_ITDR1 MT_WTBLON_TOP(__OFFS(WTBL_ITCR1)) 333 #define MT_WTBL_SPE_IDX_SEL BIT(6) 334 335 /* WTBL */ 336 #define MT_WTBL_BASE 0x820d8000 337 #define MT_WTBL_LMAC_ID GENMASK(14, 8) 338 #define MT_WTBL_LMAC_DW GENMASK(7, 2) 339 #define MT_WTBL_LMAC_OFFS(_id, _dw) (MT_WTBL_BASE | \ 340 FIELD_PREP(MT_WTBL_LMAC_ID, _id) | \ 341 FIELD_PREP(MT_WTBL_LMAC_DW, _dw)) 342 343 /* AGG: band 0(0x820e2000), band 1(0x820f2000), band 2(0x830e2000) */ 344 #define MT_WF_AGG_BASE(_band) __BASE(WF_AGG_BASE, (_band)) 345 #define MT_WF_AGG(_band, ofs) (MT_WF_AGG_BASE(_band) + (ofs)) 346 347 #define MT_AGG_ACR4(_band) MT_WF_AGG(_band, 0x3c) 348 #define MT_AGG_ACR_PPDU_TXS2H BIT(1) 349 350 /* ARB: band 0(0x820e3000), band 1(0x820f3000), band 2(0x830e3000) */ 351 #define MT_WF_ARB_BASE(_band) __BASE(WF_ARB_BASE, (_band)) 352 #define MT_WF_ARB(_band, ofs) (MT_WF_ARB_BASE(_band) + (ofs)) 353 354 #define MT_ARB_SCR(_band) MT_WF_ARB(_band, 0x000) 355 #define MT_ARB_SCR_TX_DISABLE BIT(8) 356 #define MT_ARB_SCR_RX_DISABLE BIT(9) 357 358 /* RMAC: band 0(0x820e5000), band 1(0x820f5000), band 2(0x830e5000), */ 359 #define MT_WF_RMAC_BASE(_band) __BASE(WF_RMAC_BASE, (_band)) 360 #define MT_WF_RMAC(_band, ofs) (MT_WF_RMAC_BASE(_band) + (ofs)) 361 362 #define MT_WF_RFCR(_band) MT_WF_RMAC(_band, 0x000) 363 #define MT_WF_RFCR_DROP_STBC_MULTI BIT(0) 364 #define MT_WF_RFCR_DROP_FCSFAIL BIT(1) 365 #define MT_WF_RFCR_DROP_PROBEREQ BIT(4) 366 #define MT_WF_RFCR_DROP_MCAST BIT(5) 367 #define MT_WF_RFCR_DROP_BCAST BIT(6) 368 #define MT_WF_RFCR_DROP_MCAST_FILTERED BIT(7) 369 #define MT_WF_RFCR_DROP_A3_MAC BIT(8) 370 #define MT_WF_RFCR_DROP_A3_BSSID BIT(9) 371 #define MT_WF_RFCR_DROP_A2_BSSID BIT(10) 372 #define MT_WF_RFCR_DROP_OTHER_BEACON BIT(11) 373 #define MT_WF_RFCR_DROP_FRAME_REPORT BIT(12) 374 #define MT_WF_RFCR_DROP_CTL_RSV BIT(13) 375 #define MT_WF_RFCR_DROP_CTS BIT(14) 376 #define MT_WF_RFCR_DROP_RTS BIT(15) 377 #define MT_WF_RFCR_DROP_DUPLICATE BIT(16) 378 #define MT_WF_RFCR_DROP_OTHER_BSS BIT(17) 379 #define MT_WF_RFCR_DROP_OTHER_UC BIT(18) 380 #define MT_WF_RFCR_DROP_OTHER_TIM BIT(19) 381 #define MT_WF_RFCR_DROP_NDPA BIT(20) 382 #define MT_WF_RFCR_DROP_UNWANTED_CTL BIT(21) 383 384 #define MT_WF_RFCR1(_band) MT_WF_RMAC(_band, 0x004) 385 #define MT_WF_RFCR1_DROP_ACK BIT(4) 386 #define MT_WF_RFCR1_DROP_BF_POLL BIT(5) 387 #define MT_WF_RFCR1_DROP_BA BIT(6) 388 #define MT_WF_RFCR1_DROP_CFEND BIT(7) 389 #define MT_WF_RFCR1_DROP_CFACK BIT(8) 390 391 #define MT_WF_RMAC_MIB_AIRTIME0(_band) MT_WF_RMAC(_band, 0x0380) 392 #define MT_WF_RMAC_MIB_RXTIME_CLR BIT(31) 393 #define MT_WF_RMAC_MIB_ED_OFFSET GENMASK(20, 16) 394 #define MT_WF_RMAC_MIB_OBSS_BACKOFF GENMASK(15, 0) 395 396 #define MT_WF_RMAC_MIB_AIRTIME1(_band) MT_WF_RMAC(_band, 0x0384) 397 #define MT_WF_RMAC_MIB_NONQOSD_BACKOFF GENMASK(31, 16) 398 399 #define MT_WF_RMAC_MIB_AIRTIME3(_band) MT_WF_RMAC(_band, 0x038c) 400 #define MT_WF_RMAC_MIB_QOS01_BACKOFF GENMASK(31, 0) 401 402 #define MT_WF_RMAC_MIB_AIRTIME4(_band) MT_WF_RMAC(_band, 0x0390) 403 #define MT_WF_RMAC_MIB_QOS23_BACKOFF GENMASK(31, 0) 404 405 #define MT_WF_RMAC_RSVD0(_band) MT_WF_RMAC(_band, 0x03e0) 406 #define MT_WF_RMAC_RSVD0_EIFS_CLR BIT(21) 407 408 /* RATE: band 0(0x820ee000), band 1(0x820fe000), band 2(0x830ee000) */ 409 #define MT_WF_RATE_BASE(_band) __BASE(WF_RATE_BASE, (_band)) 410 #define MT_WF_RATE(_band, ofs) (MT_WF_RATE_BASE(_band) + (ofs)) 411 412 #define MT_RATE_HRCR0(_band) MT_WF_RATE(_band, 0x050) 413 #define MT_RATE_HRCR0_CFEND_RATE GENMASK(14, 0) 414 415 /* WFDMA0 */ 416 #define MT_WFDMA0_BASE 0xd4000 417 #define MT_WFDMA0(ofs) (MT_WFDMA0_BASE + (ofs)) 418 419 #define MT_WFDMA0_RST MT_WFDMA0(0x100) 420 #define MT_WFDMA0_RST_LOGIC_RST BIT(4) 421 #define MT_WFDMA0_RST_DMASHDL_ALL_RST BIT(5) 422 423 #define MT_WFDMA0_BUSY_ENA MT_WFDMA0(0x13c) 424 #define MT_WFDMA0_BUSY_ENA_TX_FIFO0 BIT(0) 425 #define MT_WFDMA0_BUSY_ENA_TX_FIFO1 BIT(1) 426 #define MT_WFDMA0_BUSY_ENA_RX_FIFO BIT(2) 427 428 #define MT_WFDMA0_RX_INT_PCIE_SEL MT_WFDMA0(0x154) 429 #define MT_WFDMA0_RX_INT_SEL_RING3 BIT(3) 430 #define MT_WFDMA0_RX_INT_SEL_RING5 BIT(5) 431 #define MT_WFDMA0_RX_INT_SEL_RING6 BIT(6) 432 #define MT_WFDMA0_RX_INT_SEL_RING9 BIT(9) 433 434 #define MT_WFDMA0_MCU_HOST_INT_ENA MT_WFDMA0(0x1f4) 435 436 #define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208) 437 #define MT_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0) 438 #define MT_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2) 439 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21) 440 #define MT_WFDMA0_GLO_CFG_EXT_EN BIT(26) 441 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO BIT(27) 442 #define MT_WFDMA0_GLO_CFG_OMIT_TX_INFO BIT(28) 443 444 #define MT_WFDMA0_PAUSE_RX_Q_45_TH MT_WFDMA0(0x268) 445 #define MT_WFDMA0_PAUSE_RX_Q_67_TH MT_WFDMA0(0x26c) 446 #define MT_WFDMA0_PAUSE_RX_Q_89_TH MT_WFDMA0(0x270) 447 #define MT_WFDMA0_PAUSE_RX_Q_RRO_TH MT_WFDMA0(0x27c) 448 449 #define WF_WFDMA0_GLO_CFG_EXT0 MT_WFDMA0(0x2b0) 450 #define WF_WFDMA0_GLO_CFG_EXT0_OUTSTAND_MASK GENMASK(27, 24) 451 #define WF_WFDMA0_GLO_CFG_EXT0_RX_WB_RXD BIT(18) 452 #define WF_WFDMA0_GLO_CFG_EXT0_WED_MERGE_MODE BIT(14) 453 454 #define WF_WFDMA0_GLO_CFG_EXT1 MT_WFDMA0(0x2b4) 455 #define WF_WFDMA0_GLO_CFG_EXT1_CALC_MODE BIT(31) 456 #define WF_WFDMA0_GLO_CFG_EXT1_TX_FCTRL_MODE BIT(28) 457 458 #define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c) 459 #define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0) 460 #define MT_WFDMA0_PRI_DLY_INT_CFG1 MT_WFDMA0(0x2f4) 461 #define MT_WFDMA0_PRI_DLY_INT_CFG2 MT_WFDMA0(0x2f8) 462 463 /* WFDMA1 */ 464 #define MT_WFDMA1_BASE 0xd5000 465 466 /* WFDMA CSR */ 467 #define MT_WFDMA_EXT_CSR_BASE 0xd7000 468 #define MT_WFDMA_EXT_CSR(ofs) (MT_WFDMA_EXT_CSR_BASE + (ofs)) 469 470 #define MT_WFDMA_HOST_CONFIG MT_WFDMA_EXT_CSR(0x30) 471 #define MT_WFDMA_HOST_CONFIG_PDMA_BAND BIT(0) 472 #define MT_WFDMA_HOST_CONFIG_BAND0_PCIE1 BIT(20) 473 #define MT_WFDMA_HOST_CONFIG_BAND1_PCIE1 BIT(21) 474 #define MT_WFDMA_HOST_CONFIG_BAND2_PCIE1 BIT(22) 475 476 #define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR(0x44) 477 #define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY BIT(0) 478 479 #define MT_WFDMA_AXI_R2A_CTRL MT_WFDMA_EXT_CSR(0x500) 480 #define MT_WFDMA_AXI_R2A_CTRL_OUTSTAND_MASK GENMASK(4, 0) 481 482 #define MT_WFDMA_AXI_R2A_CTRL2 MT_WFDMA_EXT_CSR(0x508) 483 #define MT_WFDMA_AXI_R2A_CTRL2_OUTSTAND_MASK GENMASK(31, 28) 484 485 #define MT_PCIE_RECOG_ID 0xd7090 486 #define MT_PCIE_RECOG_ID_MASK GENMASK(30, 0) 487 #define MT_PCIE_RECOG_ID_SEM BIT(31) 488 489 /* WFDMA0 PCIE1 */ 490 #define MT_WFDMA0_PCIE1_BASE 0xd8000 491 #define MT_WFDMA0_PCIE1(ofs) (MT_WFDMA0_PCIE1_BASE + (ofs)) 492 493 #define MT_INT_PCIE1_SOURCE_CSR_EXT MT_WFDMA0_PCIE1(0x118) 494 #define MT_INT_PCIE1_MASK_CSR MT_WFDMA0_PCIE1(0x11c) 495 496 #define MT_WFDMA0_PCIE1_BUSY_ENA MT_WFDMA0_PCIE1(0x13c) 497 #define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 BIT(0) 498 #define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 BIT(1) 499 #define MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO BIT(2) 500 501 /* WFDMA COMMON */ 502 #define __RXQ(q) ((q) + __MT_MCUQ_MAX) 503 #define __TXQ(q) (__RXQ(q) + __MT_RXQ_MAX) 504 505 #define MT_Q_ID(q) (dev->q_id[(q)]) 506 #define MT_Q_BASE(q) ((dev->q_wfdma_mask >> (q)) & 0x1 ? \ 507 MT_WFDMA1_BASE : MT_WFDMA0_BASE) 508 509 #define MT_MCUQ_ID(q) MT_Q_ID(q) 510 #define MT_TXQ_ID(q) MT_Q_ID(__TXQ(q)) 511 #define MT_RXQ_ID(q) MT_Q_ID(__RXQ(q)) 512 513 #define MT_MCUQ_RING_BASE(q) (MT_Q_BASE(q) + 0x300) 514 #define MT_TXQ_RING_BASE(q) (MT_Q_BASE(__TXQ(q)) + 0x300) 515 #define MT_RXQ_RING_BASE(q) (MT_Q_BASE(__RXQ(q)) + 0x500) 516 #define MT_RXQ_RRO_IND_RING_BASE MT_RRO_TOP(0x40) 517 518 #define MT_RXQ_RRO_AP_RING_BASE MT_RRO_TOP(0x650) 519 520 #define MT_MCUQ_EXT_CTRL(q) (MT_Q_BASE(q) + 0x600 + \ 521 MT_MCUQ_ID(q) * 0x4) 522 #define MT_RXQ_EXT_CTRL(q) (MT_Q_BASE(__RXQ(q)) + 0x680 + \ 523 MT_RXQ_ID(q) * 0x4) 524 #define MT_TXQ_EXT_CTRL(q) (MT_Q_BASE(__TXQ(q)) + 0x600 + \ 525 MT_TXQ_ID(q) * 0x4) 526 527 #define MT_INT_SOURCE_CSR MT_WFDMA0(0x200) 528 #define MT_INT_MASK_CSR MT_WFDMA0(0x204) 529 530 #define MT_INT1_SOURCE_CSR MT_WFDMA0_PCIE1(0x200) 531 #define MT_INT1_MASK_CSR MT_WFDMA0_PCIE1(0x204) 532 533 #define MT_INT_RX_DONE_BAND0 BIT(12) 534 #define MT_INT_RX_DONE_BAND1 BIT(13) /* for mt7992 */ 535 #define MT_INT_RX_DONE_BAND2 BIT(13) 536 #define MT_INT_RX_DONE_WM BIT(0) 537 #define MT_INT_RX_DONE_WA BIT(1) 538 #define MT_INT_RX_DONE_WA_MAIN BIT(2) 539 #define MT_INT_RX_DONE_WA_EXT BIT(3) /* for mt7992 */ 540 #define MT_INT_RX_DONE_WA_TRI BIT(3) 541 #define MT_INT_RX_TXFREE_MAIN BIT(17) 542 #define MT_INT_RX_TXFREE_BAND1 BIT(15) 543 #define MT_INT_RX_TXFREE_TRI BIT(15) 544 #define MT_INT_RX_TXFREE_BAND1_EXT BIT(19) /* for mt7992 two PCIE*/ 545 #define MT_INT_RX_TXFREE_BAND0_MT7990 BIT(14) 546 #define MT_INT_RX_TXFREE_BAND1_MT7990 BIT(15) 547 #define MT_INT_RX_DONE_BAND2_EXT BIT(23) 548 #define MT_INT_RX_TXFREE_EXT BIT(26) 549 #define MT_INT_MCU_CMD BIT(29) 550 551 #define MT_INT_RX_DONE_RRO_BAND0 BIT(16) 552 #define MT_INT_RX_DONE_RRO_BAND1 BIT(17) 553 #define MT_INT_RX_DONE_RRO_BAND2 BIT(14) 554 #define MT_INT_RX_DONE_RRO_IND BIT(11) 555 #define MT_INT_RX_DONE_RRO_RXDMAD_C BIT(11) 556 #define MT_INT_RX_DONE_MSDU_PG_BAND0 BIT(18) 557 #define MT_INT_RX_DONE_MSDU_PG_BAND1 BIT(19) 558 #define MT_INT_RX_DONE_MSDU_PG_BAND2 BIT(23) 559 560 #define MT_INT_RX(q) (dev->q_int_mask[__RXQ(q)]) 561 #define MT_INT_TX_MCU(q) (dev->q_int_mask[(q)]) 562 563 #define MT_INT_RX_DONE_MCU (MT_INT_RX(MT_RXQ_MCU) | \ 564 MT_INT_RX(MT_RXQ_MCU_WA)) 565 566 #define MT_INT_BAND0_RX_DONE (MT_INT_RX(MT_RXQ_MAIN) | \ 567 MT_INT_RX(MT_RXQ_MAIN_WA) | \ 568 MT_INT_RX(MT_RXQ_TXFREE_BAND0)) 569 570 #define MT_INT_BAND1_RX_DONE (MT_INT_RX(MT_RXQ_BAND1) | \ 571 MT_INT_RX(MT_RXQ_BAND1_WA) | \ 572 MT_INT_RX(MT_RXQ_MAIN_WA) | \ 573 MT_INT_RX(MT_RXQ_TXFREE_BAND0)) 574 575 #define MT_INT_BAND2_RX_DONE (MT_INT_RX(MT_RXQ_BAND2) | \ 576 MT_INT_RX(MT_RXQ_BAND2_WA) | \ 577 MT_INT_RX(MT_RXQ_MAIN_WA) | \ 578 MT_INT_RX(MT_RXQ_TXFREE_BAND0)) 579 580 #define MT_INT_RRO_RX_DONE (MT_INT_RX(MT_RXQ_RRO_BAND0) | \ 581 MT_INT_RX(MT_RXQ_RRO_BAND1) | \ 582 MT_INT_RX(MT_RXQ_RRO_BAND2) | \ 583 MT_INT_RX(MT_RXQ_RRO_IND) | \ 584 MT_INT_RX(MT_RXQ_RRO_RXDMAD_C) | \ 585 MT_INT_RX(MT_RXQ_MSDU_PAGE_BAND0) | \ 586 MT_INT_RX(MT_RXQ_MSDU_PAGE_BAND1) | \ 587 MT_INT_RX(MT_RXQ_MSDU_PAGE_BAND2)) 588 589 #define MT_INT_RX_DONE_ALL (MT_INT_RX_DONE_MCU | \ 590 MT_INT_BAND0_RX_DONE | \ 591 MT_INT_BAND1_RX_DONE | \ 592 MT_INT_BAND2_RX_DONE | \ 593 MT_INT_RRO_RX_DONE) 594 595 #define MT_INT_TX_DONE_FWDL BIT(26) 596 #define MT_INT_TX_DONE_MCU_WM BIT(27) 597 #define MT_INT_TX_DONE_MCU_WA BIT(22) 598 #define MT_INT_TX_DONE_BAND0 BIT(30) 599 #define MT_INT_TX_DONE_BAND1 BIT(31) 600 #define MT_INT_TX_DONE_BAND2 BIT(15) 601 602 #define MT_INT_TX_RX_DONE_EXT (MT_INT_TX_DONE_BAND2 | \ 603 MT_INT_RX_DONE_BAND2_EXT | \ 604 MT_INT_RX_TXFREE_EXT) 605 606 #define MT_INT_TX_DONE_MCU (MT_INT_TX_MCU(MT_MCUQ_WA) | \ 607 MT_INT_TX_MCU(MT_MCUQ_WM) | \ 608 MT_INT_TX_MCU(MT_MCUQ_FWDL)) 609 610 #define MT_MCU_CMD MT_WFDMA0(0x1f0) 611 #define MT_MCU_CMD_STOP_DMA BIT(2) 612 #define MT_MCU_CMD_RESET_DONE BIT(3) 613 #define MT_MCU_CMD_RECOVERY_DONE BIT(4) 614 #define MT_MCU_CMD_NORMAL_STATE BIT(5) 615 #define MT_MCU_CMD_ERROR_MASK GENMASK(5, 1) 616 617 #define MT_MCU_CMD_WA_WDT BIT(31) 618 #define MT_MCU_CMD_WM_WDT BIT(30) 619 #define MT_MCU_CMD_WDT_MASK GENMASK(31, 30) 620 621 /* l1/l2 remap */ 622 #define CONN_BUS_CR_VON_BASE 0x155000 623 #define MT_HIF_REMAP_L1 (CONN_BUS_CR_VON_BASE + __OFFS(HIF_REMAP_L1)) 624 #define MT_HIF_REMAP_L1_MASK_7996 GENMASK(31, 16) 625 #define MT_HIF_REMAP_L1_MASK GENMASK(15, 0) 626 #define MT_HIF_REMAP_L1_OFFSET GENMASK(15, 0) 627 #define MT_HIF_REMAP_L1_BASE GENMASK(31, 16) 628 #define MT_HIF_REMAP_BASE_L1 __OFFS(HIF_REMAP_BASE_L1) 629 630 #define MT_HIF_REMAP_L2 __OFFS(HIF_REMAP_L2) 631 #define MT_HIF_REMAP_L2_MASK GENMASK(19, 0) 632 #define MT_HIF_REMAP_L2_OFFSET GENMASK(11, 0) 633 #define MT_HIF_REMAP_L2_BASE GENMASK(31, 12) 634 #define MT_HIF_REMAP_L2_MASK_7990 GENMASK(15, 0) 635 #define MT_HIF_REMAP_L2_OFFSET_7990 GENMASK(15, 0) 636 #define MT_HIF_REMAP_L2_BASE_7990 GENMASK(31, 16) 637 #define MT_HIF_REMAP_BASE_L2 __OFFS(HIF_REMAP_BASE_L2) 638 639 /* for mt7990 only */ 640 #define MT_HIF_REMAP_CBTOP 0x1f6554 641 #define MT_HIF_REMAP_CBTOP_MASK GENMASK(15, 0) 642 #define MT_HIF_REMAP_CBTOP_OFFSET GENMASK(15, 0) 643 #define MT_HIF_REMAP_CBTOP_BASE GENMASK(31, 16) 644 #define MT_HIF_REMAP_BASE_CBTOP 0x1c0000 645 646 #define MT_INFRA_BASE 0x18000000 647 #define MT_WFSYS0_PHY_START 0x18400000 648 #define MT_WFSYS1_PHY_START 0x18800000 649 #define MT_WFSYS1_PHY_END 0x18bfffff 650 #define MT_CBTOP1_PHY_START 0x70000000 651 #define MT_CBTOP1_PHY_END __OFFS(CBTOP1_PHY_END) 652 #define MT_CBTOP2_PHY_START 0xf0000000 653 #define MT_INFRA_MCU_START 0x7c000000 654 #define MT_INFRA_MCU_END __OFFS(INFRA_MCU_END) 655 656 /* FW MODE SYNC */ 657 #define MT_FW_ASSERT_CNT 0x02208274 658 #define MT_FW_DUMP_STATE 0x02209e90 659 660 #define MT_SWDEF_BASE 0x00401400 661 662 #define MT_SWDEF(ofs) (MT_SWDEF_BASE + (ofs)) 663 #define MT_SWDEF_MODE MT_SWDEF(0x3c) 664 #define MT_SWDEF_NORMAL_MODE 0 665 666 #define MT_SWDEF_SER_STATS MT_SWDEF(0x040) 667 #define MT_SWDEF_PLE_STATS MT_SWDEF(0x044) 668 #define MT_SWDEF_PLE1_STATS MT_SWDEF(0x048) 669 #define MT_SWDEF_PLE_AMSDU_STATS MT_SWDEF(0x04c) 670 #define MT_SWDEF_PSE_STATS MT_SWDEF(0x050) 671 #define MT_SWDEF_PSE1_STATS MT_SWDEF(0x054) 672 #define MT_SWDEF_LAMC_WISR6_BN0_STATS MT_SWDEF(0x058) 673 #define MT_SWDEF_LAMC_WISR6_BN1_STATS MT_SWDEF(0x05c) 674 #define MT_SWDEF_LAMC_WISR6_BN2_STATS MT_SWDEF(0x060) 675 #define MT_SWDEF_LAMC_WISR7_BN0_STATS MT_SWDEF(0x064) 676 #define MT_SWDEF_LAMC_WISR7_BN1_STATS MT_SWDEF(0x068) 677 #define MT_SWDEF_LAMC_WISR7_BN2_STATS MT_SWDEF(0x06c) 678 679 /* LED */ 680 #define MT_LED_TOP_BASE 0x18013000 681 #define MT_LED_PHYS(_n) (MT_LED_TOP_BASE + (_n)) 682 683 #define MT_LED_CTRL(_n) MT_LED_PHYS(0x00 + ((_n) * 4)) 684 #define MT_LED_CTRL_KICK BIT(7) 685 #define MT_LED_CTRL_BLINK_BAND_SEL BIT(4) 686 #define MT_LED_CTRL_BLINK_MODE BIT(2) 687 #define MT_LED_CTRL_POLARITY BIT(1) 688 689 #define MT_LED_TX_BLINK(_n) MT_LED_PHYS(0x10 + ((_n) * 4)) 690 #define MT_LED_TX_BLINK_ON_MASK GENMASK(7, 0) 691 #define MT_LED_TX_BLINK_OFF_MASK GENMASK(15, 8) 692 693 #define MT_LED_EN(_n) MT_LED_PHYS(0x40 + ((_n) * 4)) 694 695 /* CONN DBG */ 696 #define MT_CONN_DBG_CTL_BASE 0x18023000 697 #define MT_CONN_DBG_CTL(ofs) (MT_CONN_DBG_CTL_BASE + (ofs)) 698 #define MT_CONN_DBG_CTL_OUT_SEL MT_CONN_DBG_CTL(0x604) 699 #define MT_CONN_DBG_CTL_PC_LOG_SEL MT_CONN_DBG_CTL(0x60c) 700 #define MT_CONN_DBG_CTL_PC_LOG MT_CONN_DBG_CTL(0x610) 701 702 #define MT_LED_GPIO_MUX2 0x70005058 /* GPIO 18 */ 703 #define MT_LED_GPIO_MUX3 0x7000505C /* GPIO 26 */ 704 #define MT_LED_GPIO_SEL_MASK GENMASK(11, 8) 705 706 /* MT TOP */ 707 #define MT_TOP_BASE 0xe0000 708 #define MT_TOP(ofs) (MT_TOP_BASE + (ofs)) 709 710 #define MT_TOP_LPCR_HOST_BAND(_band) MT_TOP(0x10 + ((_band) * 0x10)) 711 #define MT_TOP_LPCR_HOST_FW_OWN BIT(0) 712 #define MT_TOP_LPCR_HOST_DRV_OWN BIT(1) 713 #define MT_TOP_LPCR_HOST_FW_OWN_STAT BIT(2) 714 715 #define MT_TOP_LPCR_HOST_BAND_IRQ_STAT(_band) MT_TOP(0x14 + ((_band) * 0x10)) 716 #define MT_TOP_LPCR_HOST_BAND_STAT BIT(0) 717 718 #define MT_TOP_MISC MT_TOP(0xf0) 719 #define MT_TOP_MISC_FW_STATE GENMASK(2, 0) 720 721 /* ADIE */ 722 #define MT_ADIE_CHIP_ID(_idx) (0x0f00002c + ((_idx) << 28)) 723 #define MT_ADIE_VERSION_MASK GENMASK(15, 0) 724 #define MT_ADIE_CHIP_ID_MASK GENMASK(31, 16) 725 726 #define MT_PAD_GPIO 0x700056f0 727 #define MT_PAD_GPIO_ADIE_COMB GENMASK(16, 15) 728 #define MT_PAD_GPIO_2ADIE_TBTC BIT(19) 729 /* for mt7992 */ 730 #define MT_PAD_GPIO_ADIE_COMB_7992 GENMASK(17, 16) 731 #define MT_PAD_GPIO_ADIE_SINGLE BIT(15) 732 733 #define MT_HW_REV 0x70010204 734 #define MT_HW_REV1 0x8a00 735 736 #define MT_WF_SUBSYS_RST 0x70028600 737 738 /* PCIE MAC */ 739 #define MT_PCIE_MAC_BASE 0x74030000 740 #define MT_PCIE_MAC(ofs) (MT_PCIE_MAC_BASE + (ofs)) 741 #define MT_PCIE_MAC_INT_ENABLE MT_PCIE_MAC(0x188) 742 743 #define MT_PCIE1_MAC_BASE 0x74090000 744 #define MT_PCIE1_MAC(ofs) (MT_PCIE1_MAC_BASE + (ofs)) 745 746 #define MT_PCIE1_MAC_INT_ENABLE MT_PCIE1_MAC(0x188) 747 748 /* PHYRX CSD */ 749 #define MT_WF_PHYRX_CSD_BASE 0x83000000 750 #define MT_WF_PHYRX_CSD(_band, _wf, ofs) (MT_WF_PHYRX_CSD_BASE + \ 751 ((_band) << 20) + \ 752 ((_wf) << 16) + (ofs)) 753 #define MT_WF_PHYRX_CSD_IRPI(_band, _wf) MT_WF_PHYRX_CSD(_band, _wf, 0x1000) 754 755 /* PHYRX CTRL */ 756 #define MT_WF_PHYRX_BAND_BASE 0x83080000 757 #define MT_WF_PHYRX_BAND(_band, ofs) (MT_WF_PHYRX_BAND_BASE + \ 758 ((_band) << 20) + (ofs)) 759 760 #define MT_WF_PHYRX_BAND_GID_TAB_VLD0(_band) MT_WF_PHYRX_BAND(_band, 0x1054) 761 #define MT_WF_PHYRX_BAND_GID_TAB_VLD1(_band) MT_WF_PHYRX_BAND(_band, 0x1058) 762 #define MT_WF_PHYRX_BAND_GID_TAB_POS0(_band) MT_WF_PHYRX_BAND(_band, 0x105c) 763 #define MT_WF_PHYRX_BAND_GID_TAB_POS1(_band) MT_WF_PHYRX_BAND(_band, 0x1060) 764 #define MT_WF_PHYRX_BAND_GID_TAB_POS2(_band) MT_WF_PHYRX_BAND(_band, 0x1064) 765 #define MT_WF_PHYRX_BAND_GID_TAB_POS3(_band) MT_WF_PHYRX_BAND(_band, 0x1068) 766 767 #define MT_WF_PHYRX_BAND_RX_CTRL1(_band) MT_WF_PHYRX_BAND(_band, 0x2004) 768 #define MT_WF_PHYRX_BAND_RX_CTRL1_IPI_EN GENMASK(2, 0) 769 #define MT_WF_PHYRX_BAND_RX_CTRL1_STSCNT_EN GENMASK(11, 9) 770 771 /* PHYRX CSD BAND */ 772 #define MT_WF_PHYRX_CSD_BAND_RXTD12(_band) MT_WF_PHYRX_BAND(_band, 0x8230) 773 #define MT_WF_PHYRX_CSD_BAND_RXTD12_IRPI_SW_CLR_ONLY BIT(18) 774 #define MT_WF_PHYRX_CSD_BAND_RXTD12_IRPI_SW_CLR BIT(29) 775 776 /* CONN MCU EXCP CON */ 777 #define MT_MCU_WM_EXCP_BASE 0x89050000 778 #define MT_MCU_WM_EXCP(ofs) (MT_MCU_WM_EXCP_BASE + (ofs)) 779 #define MT_MCU_WM_EXCP_PC_CTRL MT_MCU_WM_EXCP(0x100) 780 #define MT_MCU_WM_EXCP_PC_LOG MT_MCU_WM_EXCP(0x104) 781 #define MT_MCU_WM_EXCP_LR_CTRL MT_MCU_WM_EXCP(0x200) 782 #define MT_MCU_WM_EXCP_LR_LOG MT_MCU_WM_EXCP(0x204) 783 784 /* CONN AFE CTL CON */ 785 #define MT_AFE_CTL_BASE 0x18043000 786 #define MT_AFE_CTL_BAND(_band, ofs) (MT_AFE_CTL_BASE + \ 787 ((_band) * 0x1000) + (ofs)) 788 #define MT_AFE_CTL_BAND_PLL_03(_band) MT_AFE_CTL_BAND(_band, 0x2c) 789 #define MT_AFE_CTL_BAND_PLL_03_MSB_EN BIT(1) 790 791 #endif 792