1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #ifndef __MT7996_H 7 #define __MT7996_H 8 9 #include <linux/interrupt.h> 10 #include <linux/ktime.h> 11 #include "../mt76_connac.h" 12 #include "regs.h" 13 14 #define MT7996_MAX_RADIOS 3 15 #define MT7996_MAX_INTERFACES 19 /* per-band */ 16 #define MT7996_MAX_WMM_SETS 4 17 #define MT7996_WTBL_BMC_SIZE (is_mt7992(&dev->mt76) ? 32 : 64) 18 #define MT7996_WTBL_RESERVED (mt7996_wtbl_size(dev) - 1) 19 #define MT7996_WTBL_STA (MT7996_WTBL_RESERVED - \ 20 mt7996_max_interface_num(dev)) 21 22 #define MT7996_WATCHDOG_TIME (HZ / 10) 23 #define MT7996_RESET_TIMEOUT (30 * HZ) 24 25 #define MT7996_TX_RING_SIZE 2048 26 #define MT7996_TX_MCU_RING_SIZE 256 27 #define MT7996_TX_FWDL_RING_SIZE 128 28 29 #define MT7996_RX_RING_SIZE 1536 30 #define MT7996_RX_MCU_RING_SIZE 512 31 #define MT7996_RX_MCU_RING_SIZE_WA 1024 32 33 #define MT7996_FIRMWARE_WA "mediatek/mt7996/mt7996_wa.bin" 34 #define MT7996_FIRMWARE_WM "mediatek/mt7996/mt7996_wm.bin" 35 #define MT7996_FIRMWARE_DSP "mediatek/mt7996/mt7996_dsp.bin" 36 #define MT7996_ROM_PATCH "mediatek/mt7996/mt7996_rom_patch.bin" 37 38 #define MT7996_FIRMWARE_WA_233 "mediatek/mt7996/mt7996_wa_233.bin" 39 #define MT7996_FIRMWARE_WM_233 "mediatek/mt7996/mt7996_wm_233.bin" 40 #define MT7996_FIRMWARE_DSP_233 MT7996_FIRMWARE_DSP 41 #define MT7996_ROM_PATCH_233 "mediatek/mt7996/mt7996_rom_patch_233.bin" 42 43 #define MT7992_FIRMWARE_WA "mediatek/mt7996/mt7992_wa.bin" 44 #define MT7992_FIRMWARE_WM "mediatek/mt7996/mt7992_wm.bin" 45 #define MT7992_FIRMWARE_DSP "mediatek/mt7996/mt7992_dsp.bin" 46 #define MT7992_ROM_PATCH "mediatek/mt7996/mt7992_rom_patch.bin" 47 48 #define MT7992_FIRMWARE_WA_23 "mediatek/mt7996/mt7992_wa_23.bin" 49 #define MT7992_FIRMWARE_WM_23 "mediatek/mt7996/mt7992_wm_23.bin" 50 #define MT7992_FIRMWARE_DSP_23 "mediatek/mt7996/mt7992_dsp_23.bin" 51 #define MT7992_ROM_PATCH_23 "mediatek/mt7996/mt7992_rom_patch_23.bin" 52 53 #define MT7996_EEPROM_DEFAULT "mediatek/mt7996/mt7996_eeprom.bin" 54 #define MT7996_EEPROM_DEFAULT_INT "mediatek/mt7996/mt7996_eeprom_2i5i6i.bin" 55 #define MT7996_EEPROM_DEFAULT_233 "mediatek/mt7996/mt7996_eeprom_233.bin" 56 #define MT7996_EEPROM_DEFAULT_233_INT "mediatek/mt7996/mt7996_eeprom_233_2i5i6i.bin" 57 58 #define MT7992_EEPROM_DEFAULT "mediatek/mt7996/mt7992_eeprom.bin" 59 #define MT7992_EEPROM_DEFAULT_INT "mediatek/mt7996/mt7992_eeprom_2i5i.bin" 60 #define MT7992_EEPROM_DEFAULT_MIX "mediatek/mt7996/mt7992_eeprom_2i5e.bin" 61 #define MT7992_EEPROM_DEFAULT_23 "mediatek/mt7996/mt7992_eeprom_23.bin" 62 #define MT7992_EEPROM_DEFAULT_23_INT "mediatek/mt7996/mt7992_eeprom_23_2i5i.bin" 63 64 #define MT7996_EEPROM_SIZE 7680 65 #define MT7996_EEPROM_BLOCK_SIZE 16 66 #define MT7996_TOKEN_SIZE 16384 67 #define MT7996_HW_TOKEN_SIZE 8192 68 69 #define MT7996_CFEND_RATE_DEFAULT 0x49 /* OFDM 24M */ 70 #define MT7996_CFEND_RATE_11B 0x03 /* 11B LP, 11M */ 71 #define MT7996_IBF_MAX_NC 2 72 #define MT7996_IBF_TIMEOUT 0x18 73 #define MT7996_IBF_TIMEOUT_LEGACY 0x48 74 75 #define MT7992_CFEND_RATE_DEFAULT 0x4b /* OFDM 6M */ 76 #define MT7992_IBF_TIMEOUT 0xff 77 78 #define MT7996_SKU_RATE_NUM 417 79 #define MT7996_SKU_PATH_NUM 494 80 81 #define MT7996_MAX_TWT_AGRT 16 82 #define MT7996_MAX_STA_TWT_AGRT 8 83 #define MT7996_MIN_TWT_DUR 64 84 #define MT7996_MAX_QUEUE (__MT_RXQ_MAX + __MT_MCUQ_MAX + 3) 85 86 /* NOTE: used to map mt76_rates. idx may change if firmware expands table */ 87 #define MT7996_BASIC_RATES_TBL 31 88 #define MT7996_BEACON_RATES_TBL 25 89 90 #define MT7996_THERMAL_THROTTLE_MAX 100 91 #define MT7996_CDEV_THROTTLE_MAX 99 92 #define MT7996_CRIT_TEMP_IDX 0 93 #define MT7996_MAX_TEMP_IDX 1 94 #define MT7996_CRIT_TEMP 110 95 #define MT7996_MAX_TEMP 120 96 97 #define MT7996_RRO_MAX_SESSION 1024 98 #define MT7996_RRO_WINDOW_MAX_LEN 1024 99 #define MT7996_RRO_ADDR_ELEM_LEN 128 100 #define MT7996_RRO_BA_BITMAP_LEN 2 101 #define MT7996_RRO_BA_BITMAP_CR_SIZE ((MT7996_RRO_MAX_SESSION * 128) / \ 102 MT7996_RRO_BA_BITMAP_LEN) 103 #define MT7996_RRO_BA_BITMAP_SESSION_SIZE (MT7996_RRO_MAX_SESSION / \ 104 MT7996_RRO_ADDR_ELEM_LEN) 105 #define MT7996_RRO_WINDOW_MAX_SIZE (MT7996_RRO_WINDOW_MAX_LEN * \ 106 MT7996_RRO_BA_BITMAP_SESSION_SIZE) 107 108 #define MT7996_RX_BUF_SIZE (1800 + \ 109 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 110 #define MT7996_RX_MSDU_PAGE_SIZE (128 + \ 111 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 112 113 struct mt7996_vif; 114 struct mt7996_sta; 115 struct mt7996_dfs_pulse; 116 struct mt7996_dfs_pattern; 117 118 enum mt7996_ram_type { 119 MT7996_RAM_TYPE_WM, 120 MT7996_RAM_TYPE_WA, 121 MT7996_RAM_TYPE_DSP, 122 }; 123 124 enum mt7996_var_type { 125 MT7996_VAR_TYPE_444, 126 MT7996_VAR_TYPE_233, 127 }; 128 129 enum mt7992_var_type { 130 MT7992_VAR_TYPE_44, 131 MT7992_VAR_TYPE_23, 132 }; 133 134 enum mt7996_fem_type { 135 MT7996_FEM_EXT, 136 MT7996_FEM_INT, 137 MT7996_FEM_MIX, 138 }; 139 140 enum mt7996_txq_id { 141 MT7996_TXQ_FWDL = 16, 142 MT7996_TXQ_MCU_WM, 143 MT7996_TXQ_BAND0, 144 MT7996_TXQ_BAND1, 145 MT7996_TXQ_MCU_WA, 146 MT7996_TXQ_BAND2, 147 }; 148 149 enum mt7996_rxq_id { 150 MT7996_RXQ_MCU_WM = 0, 151 MT7996_RXQ_MCU_WA, 152 MT7996_RXQ_MCU_WA_MAIN = 2, 153 MT7996_RXQ_MCU_WA_EXT = 3, /* for mt7992 */ 154 MT7996_RXQ_MCU_WA_TRI = 3, 155 MT7996_RXQ_BAND0 = 4, 156 MT7996_RXQ_BAND1 = 5, /* for mt7992 */ 157 MT7996_RXQ_BAND2 = 5, 158 MT7996_RXQ_RRO_BAND0 = 8, 159 MT7996_RXQ_RRO_BAND1 = 8,/* unused */ 160 MT7996_RXQ_RRO_BAND2 = 6, 161 MT7996_RXQ_MSDU_PG_BAND0 = 10, 162 MT7996_RXQ_MSDU_PG_BAND1 = 11, 163 MT7996_RXQ_MSDU_PG_BAND2 = 12, 164 MT7996_RXQ_TXFREE0 = 9, 165 MT7996_RXQ_TXFREE1 = 9, 166 MT7996_RXQ_TXFREE2 = 7, 167 MT7996_RXQ_RRO_IND = 0, 168 }; 169 170 struct mt7996_twt_flow { 171 struct list_head list; 172 u64 start_tsf; 173 u64 tsf; 174 u32 duration; 175 u16 wcid; 176 __le16 mantissa; 177 u8 exp; 178 u8 table_id; 179 u8 id; 180 u8 protection:1; 181 u8 flowtype:1; 182 u8 trigger:1; 183 u8 sched:1; 184 }; 185 186 DECLARE_EWMA(avg_signal, 10, 8) 187 188 struct mt7996_sta { 189 struct mt76_wcid wcid; /* must be first */ 190 191 struct mt7996_vif *vif; 192 193 struct list_head rc_list; 194 u32 airtime_ac[8]; 195 196 int ack_signal; 197 struct ewma_avg_signal avg_ack_signal; 198 199 unsigned long changed; 200 201 struct mt76_connac_sta_key_conf bip; 202 203 struct { 204 u8 flowid_mask; 205 struct mt7996_twt_flow flow[MT7996_MAX_STA_TWT_AGRT]; 206 } twt; 207 }; 208 209 struct mt7996_vif_link { 210 struct mt76_vif_link mt76; /* must be first */ 211 212 struct mt7996_sta sta; 213 struct mt7996_phy *phy; 214 215 struct ieee80211_tx_queue_params queue_params[IEEE80211_NUM_ACS]; 216 struct cfg80211_bitrate_mask bitrate_mask; 217 }; 218 219 struct mt7996_vif { 220 struct mt7996_vif_link deflink; /* must be first */ 221 struct mt76_vif_data mt76; 222 }; 223 224 /* crash-dump */ 225 struct mt7996_crash_data { 226 guid_t guid; 227 struct timespec64 timestamp; 228 229 u8 *memdump_buf; 230 size_t memdump_buf_len; 231 }; 232 233 struct mt7996_hif { 234 struct list_head list; 235 236 struct device *dev; 237 void __iomem *regs; 238 int irq; 239 }; 240 241 struct mt7996_wed_rro_addr { 242 u32 head_low; 243 u32 head_high : 4; 244 u32 count: 11; 245 u32 oor: 1; 246 u32 rsv : 8; 247 u32 signature : 8; 248 }; 249 250 struct mt7996_wed_rro_session_id { 251 struct list_head list; 252 u16 id; 253 }; 254 255 struct mt7996_phy { 256 struct mt76_phy *mt76; 257 struct mt7996_dev *dev; 258 259 struct ieee80211_sband_iftype_data iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES]; 260 261 struct thermal_cooling_device *cdev; 262 u8 cdev_state; 263 u8 throttle_state; 264 u32 throttle_temp[2]; /* 0: critical high, 1: maximum */ 265 266 u32 rxfilter; 267 u64 omac_mask; 268 269 u16 noise; 270 271 s16 coverage_class; 272 u8 slottime; 273 274 u8 rdd_state; 275 276 u16 beacon_rate; 277 278 u32 rx_ampdu_ts; 279 u32 ampdu_ref; 280 int txpower; 281 282 struct mt76_mib_stats mib; 283 struct mt76_channel_state state_ts; 284 285 u16 orig_chainmask; 286 287 bool has_aux_rx; 288 bool counter_reset; 289 }; 290 291 struct mt7996_dev { 292 union { /* must be first */ 293 struct mt76_dev mt76; 294 struct mt76_phy mphy; 295 }; 296 297 struct mt7996_phy *radio_phy[MT7996_MAX_RADIOS]; 298 struct wiphy_radio radios[MT7996_MAX_RADIOS]; 299 struct wiphy_radio_freq_range radio_freqs[MT7996_MAX_RADIOS]; 300 301 struct mt7996_hif *hif2; 302 struct mt7996_reg_desc reg; 303 u8 q_id[MT7996_MAX_QUEUE]; 304 u32 q_int_mask[MT7996_MAX_QUEUE]; 305 u32 q_wfdma_mask; 306 307 const struct mt76_bus_ops *bus_ops; 308 struct mt7996_phy phy; 309 310 /* monitor rx chain configured channel */ 311 struct cfg80211_chan_def rdd2_chandef; 312 struct mt7996_phy *rdd2_phy; 313 314 u16 chainmask; 315 u8 chainshift[__MT_MAX_BAND]; 316 u32 hif_idx; 317 318 struct work_struct init_work; 319 struct work_struct rc_work; 320 struct work_struct dump_work; 321 struct work_struct reset_work; 322 wait_queue_head_t reset_wait; 323 struct { 324 u32 state; 325 u32 wa_reset_count; 326 u32 wm_reset_count; 327 bool hw_full_reset:1; 328 bool hw_init_done:1; 329 bool restart:1; 330 } recovery; 331 332 /* protects coredump data */ 333 struct mutex dump_mutex; 334 #ifdef CONFIG_DEV_COREDUMP 335 struct { 336 struct mt7996_crash_data *crash_data; 337 } coredump; 338 #endif 339 340 struct list_head sta_rc_list; 341 struct list_head twt_list; 342 343 u32 hw_pattern; 344 345 bool flash_mode:1; 346 bool has_eht:1; 347 bool has_rro:1; 348 349 struct { 350 struct { 351 void *ptr; 352 dma_addr_t phy_addr; 353 } ba_bitmap[MT7996_RRO_BA_BITMAP_LEN]; 354 struct { 355 void *ptr; 356 dma_addr_t phy_addr; 357 } addr_elem[MT7996_RRO_ADDR_ELEM_LEN]; 358 struct { 359 void *ptr; 360 dma_addr_t phy_addr; 361 } session; 362 363 struct work_struct work; 364 struct list_head poll_list; 365 spinlock_t lock; 366 } wed_rro; 367 368 bool ibf; 369 u8 fw_debug_wm; 370 u8 fw_debug_wa; 371 u8 fw_debug_bin; 372 u16 fw_debug_seq; 373 374 struct dentry *debugfs_dir; 375 struct rchan *relay_fwlog; 376 377 struct { 378 u16 table_mask; 379 u8 n_agrt; 380 } twt; 381 382 spinlock_t reg_lock; 383 384 u8 wtbl_size_group; 385 struct { 386 u8 type:4; 387 u8 fem:4; 388 } var; 389 }; 390 391 enum { 392 WFDMA0 = 0x0, 393 WFDMA1, 394 WFDMA_EXT, 395 __MT_WFDMA_MAX, 396 }; 397 398 enum { 399 MT_RX_SEL0, 400 MT_RX_SEL1, 401 MT_RX_SEL2, /* monitor chain */ 402 }; 403 404 enum mt7996_rdd_cmd { 405 RDD_STOP, 406 RDD_START, 407 RDD_DET_MODE, 408 RDD_RADAR_EMULATE, 409 RDD_START_TXQ = 20, 410 RDD_CAC_START = 50, 411 RDD_CAC_END, 412 RDD_NORMAL_START, 413 RDD_DISABLE_DFS_CAL, 414 RDD_PULSE_DBG, 415 RDD_READ_PULSE, 416 RDD_RESUME_BF, 417 RDD_IRQ_OFF, 418 }; 419 420 static inline struct mt7996_dev * 421 mt7996_hw_dev(struct ieee80211_hw *hw) 422 { 423 struct mt76_phy *phy = hw->priv; 424 425 return container_of(phy->dev, struct mt7996_dev, mt76); 426 } 427 428 static inline struct mt7996_phy * 429 __mt7996_phy(struct mt7996_dev *dev, enum mt76_band_id band) 430 { 431 struct mt76_phy *phy = dev->mt76.phys[band]; 432 433 if (!phy) 434 return NULL; 435 436 return phy->priv; 437 } 438 439 static inline struct mt7996_phy * 440 mt7996_phy2(struct mt7996_dev *dev) 441 { 442 return __mt7996_phy(dev, MT_BAND1); 443 } 444 445 static inline struct mt7996_phy * 446 mt7996_phy3(struct mt7996_dev *dev) 447 { 448 return __mt7996_phy(dev, MT_BAND2); 449 } 450 451 static inline bool 452 mt7996_band_valid(struct mt7996_dev *dev, u8 band) 453 { 454 if (is_mt7992(&dev->mt76)) 455 return band <= MT_BAND1; 456 457 return band <= MT_BAND2; 458 } 459 460 static inline bool 461 mt7996_has_background_radar(struct mt7996_dev *dev) 462 { 463 switch (mt76_chip(&dev->mt76)) { 464 case 0x7990: 465 if (dev->var.type == MT7996_VAR_TYPE_233) 466 return false; 467 break; 468 case 0x7992: 469 if (dev->var.type == MT7992_VAR_TYPE_23) 470 return false; 471 break; 472 default: 473 return false; 474 } 475 476 return true; 477 } 478 479 static inline struct mt7996_phy * 480 mt7996_band_phy(struct mt7996_dev *dev, enum nl80211_band band) 481 { 482 struct mt76_phy *mphy; 483 484 mphy = dev->mt76.band_phys[band]; 485 if (!mphy) 486 return NULL; 487 488 return mphy->priv; 489 } 490 491 static inline struct mt7996_vif_link * 492 mt7996_vif_link(struct mt7996_dev *dev, struct ieee80211_vif *vif, int link_id) 493 { 494 return (struct mt7996_vif_link *)mt76_vif_link(&dev->mt76, vif, link_id); 495 } 496 497 static inline struct mt7996_phy * 498 mt7996_vif_link_phy(struct mt7996_vif_link *link) 499 { 500 struct mt76_phy *mphy = mt76_vif_link_phy(&link->mt76); 501 502 if (!mphy) 503 return NULL; 504 505 return mphy->priv; 506 } 507 508 static inline struct mt7996_vif_link * 509 mt7996_vif_conf_link(struct mt7996_dev *dev, struct ieee80211_vif *vif, 510 struct ieee80211_bss_conf *link_conf) 511 { 512 return (struct mt7996_vif_link *)mt76_vif_conf_link(&dev->mt76, vif, 513 link_conf); 514 } 515 516 #define mt7996_for_each_phy(dev, phy) \ 517 for (int __i = 0; __i < ARRAY_SIZE((dev)->radio_phy); __i++) \ 518 if (((phy) = (dev)->radio_phy[__i]) != NULL) 519 520 extern const struct ieee80211_ops mt7996_ops; 521 extern struct pci_driver mt7996_pci_driver; 522 extern struct pci_driver mt7996_hif_driver; 523 524 struct mt7996_dev *mt7996_mmio_probe(struct device *pdev, 525 void __iomem *mem_base, u32 device_id); 526 void mt7996_wfsys_reset(struct mt7996_dev *dev); 527 irqreturn_t mt7996_irq_handler(int irq, void *dev_instance); 528 u64 __mt7996_get_tsf(struct ieee80211_hw *hw, struct mt7996_vif *mvif); 529 int mt7996_register_device(struct mt7996_dev *dev); 530 void mt7996_unregister_device(struct mt7996_dev *dev); 531 int mt7996_vif_link_add(struct mt76_phy *mphy, struct ieee80211_vif *vif, 532 struct ieee80211_bss_conf *link_conf, 533 struct mt76_vif_link *mlink); 534 void mt7996_vif_link_remove(struct mt76_phy *mphy, struct ieee80211_vif *vif, 535 struct ieee80211_bss_conf *link_conf, 536 struct mt76_vif_link *mlink); 537 int mt7996_eeprom_init(struct mt7996_dev *dev); 538 int mt7996_eeprom_parse_hw_cap(struct mt7996_dev *dev, struct mt7996_phy *phy); 539 int mt7996_eeprom_get_target_power(struct mt7996_dev *dev, 540 struct ieee80211_channel *chan); 541 s8 mt7996_eeprom_get_power_delta(struct mt7996_dev *dev, int band); 542 int mt7996_dma_init(struct mt7996_dev *dev); 543 void mt7996_dma_reset(struct mt7996_dev *dev, bool force); 544 void mt7996_dma_prefetch(struct mt7996_dev *dev); 545 void mt7996_dma_cleanup(struct mt7996_dev *dev); 546 void mt7996_dma_start(struct mt7996_dev *dev, bool reset, bool wed_reset); 547 int mt7996_init_tx_queues(struct mt7996_phy *phy, int idx, 548 int n_desc, int ring_base, struct mtk_wed_device *wed); 549 void mt7996_init_txpower(struct mt7996_phy *phy); 550 int mt7996_txbf_init(struct mt7996_dev *dev); 551 void mt7996_reset(struct mt7996_dev *dev); 552 int mt7996_run(struct mt7996_phy *phy); 553 int mt7996_mcu_init(struct mt7996_dev *dev); 554 int mt7996_mcu_init_firmware(struct mt7996_dev *dev); 555 int mt7996_mcu_twt_agrt_update(struct mt7996_dev *dev, 556 struct mt7996_vif *mvif, 557 struct mt7996_twt_flow *flow, 558 int cmd); 559 int mt7996_mcu_add_dev_info(struct mt7996_phy *phy, struct ieee80211_vif *vif, 560 struct ieee80211_bss_conf *link_conf, 561 struct mt76_vif_link *mlink, bool enable); 562 int mt7996_mcu_add_bss_info(struct mt7996_phy *phy, struct ieee80211_vif *vif, 563 struct ieee80211_bss_conf *link_conf, 564 struct mt76_vif_link *mlink, int enable); 565 int mt7996_mcu_add_sta(struct mt7996_dev *dev, struct ieee80211_vif *vif, 566 struct mt76_vif_link *mlink, 567 struct ieee80211_sta *sta, int conn_state, bool newly); 568 int mt7996_mcu_add_tx_ba(struct mt7996_dev *dev, 569 struct ieee80211_ampdu_params *params, 570 bool add); 571 int mt7996_mcu_add_rx_ba(struct mt7996_dev *dev, 572 struct ieee80211_ampdu_params *params, 573 bool add); 574 int mt7996_mcu_update_bss_color(struct mt7996_dev *dev, 575 struct mt76_vif_link *mlink, 576 struct cfg80211_he_bss_color *he_bss_color); 577 int mt7996_mcu_add_beacon(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 578 struct ieee80211_bss_conf *link_conf); 579 int mt7996_mcu_beacon_inband_discov(struct mt7996_dev *dev, 580 struct ieee80211_vif *vif, u32 changed); 581 int mt7996_mcu_add_obss_spr(struct mt7996_phy *phy, struct ieee80211_vif *vif, 582 struct ieee80211_he_obss_pd *he_obss_pd); 583 int mt7996_mcu_add_rate_ctrl(struct mt7996_dev *dev, struct ieee80211_vif *vif, 584 struct ieee80211_sta *sta, bool changed); 585 int mt7996_set_channel(struct mt76_phy *mphy); 586 int mt7996_mcu_set_chan_info(struct mt7996_phy *phy, u16 tag); 587 int mt7996_mcu_set_tx(struct mt7996_dev *dev, struct ieee80211_vif *vif, 588 struct ieee80211_bss_conf *link_conf); 589 int mt7996_mcu_set_fixed_rate_ctrl(struct mt7996_dev *dev, 590 void *data, u16 version); 591 int mt7996_mcu_set_fixed_field(struct mt7996_dev *dev, struct ieee80211_vif *vif, 592 struct ieee80211_sta *sta, void *data, u32 field); 593 int mt7996_mcu_set_eeprom(struct mt7996_dev *dev); 594 int mt7996_mcu_get_eeprom(struct mt7996_dev *dev, u32 offset, u8 *buf, u32 buf_len); 595 int mt7996_mcu_get_eeprom_free_block(struct mt7996_dev *dev, u8 *block_num); 596 int mt7996_mcu_get_chip_config(struct mt7996_dev *dev, u32 *cap); 597 int mt7996_mcu_set_ser(struct mt7996_dev *dev, u8 action, u8 set, u8 band); 598 int mt7996_mcu_set_txbf(struct mt7996_dev *dev, u8 action); 599 int mt7996_mcu_set_fcc5_lpn(struct mt7996_dev *dev, int val); 600 int mt7996_mcu_set_pulse_th(struct mt7996_dev *dev, 601 const struct mt7996_dfs_pulse *pulse); 602 int mt7996_mcu_set_radar_th(struct mt7996_dev *dev, int index, 603 const struct mt7996_dfs_pattern *pattern); 604 int mt7996_mcu_set_radio_en(struct mt7996_phy *phy, bool enable); 605 int mt7996_mcu_set_rts_thresh(struct mt7996_phy *phy, u32 val); 606 int mt7996_mcu_set_timing(struct mt7996_phy *phy, struct ieee80211_vif *vif, 607 struct ieee80211_bss_conf *link_conf); 608 int mt7996_mcu_get_chan_mib_info(struct mt7996_phy *phy, bool chan_switch); 609 int mt7996_mcu_get_temperature(struct mt7996_phy *phy); 610 int mt7996_mcu_set_thermal_throttling(struct mt7996_phy *phy, u8 state); 611 int mt7996_mcu_set_thermal_protect(struct mt7996_phy *phy, bool enable); 612 int mt7996_mcu_set_txpower_sku(struct mt7996_phy *phy); 613 int mt7996_mcu_rdd_cmd(struct mt7996_dev *dev, int cmd, u8 index, 614 u8 rx_sel, u8 val); 615 int mt7996_mcu_rdd_background_enable(struct mt7996_phy *phy, 616 struct cfg80211_chan_def *chandef); 617 int mt7996_mcu_set_fixed_rate_table(struct mt7996_phy *phy, u8 table_idx, 618 u16 rate_idx, bool beacon); 619 int mt7996_mcu_rf_regval(struct mt7996_dev *dev, u32 regidx, u32 *val, bool set); 620 int mt7996_mcu_set_hdr_trans(struct mt7996_dev *dev, bool hdr_trans); 621 int mt7996_mcu_set_rro(struct mt7996_dev *dev, u16 tag, u16 val); 622 int mt7996_mcu_wa_cmd(struct mt7996_dev *dev, int cmd, u32 a1, u32 a2, u32 a3); 623 int mt7996_mcu_fw_log_2_host(struct mt7996_dev *dev, u8 type, u8 ctrl); 624 int mt7996_mcu_fw_dbg_ctrl(struct mt7996_dev *dev, u32 module, u8 level); 625 int mt7996_mcu_trigger_assert(struct mt7996_dev *dev); 626 void mt7996_mcu_rx_event(struct mt7996_dev *dev, struct sk_buff *skb); 627 void mt7996_mcu_exit(struct mt7996_dev *dev); 628 int mt7996_mcu_get_all_sta_info(struct mt7996_phy *phy, u16 tag); 629 int mt7996_mcu_wed_rro_reset_sessions(struct mt7996_dev *dev, u16 id); 630 int mt7996_mcu_set_sniffer_mode(struct mt7996_phy *phy, bool enabled); 631 632 static inline u8 mt7996_max_interface_num(struct mt7996_dev *dev) 633 { 634 return min(MT7996_MAX_INTERFACES * (1 + mt7996_band_valid(dev, MT_BAND1) + 635 mt7996_band_valid(dev, MT_BAND2)), 636 MT7996_WTBL_BMC_SIZE); 637 } 638 639 static inline u16 mt7996_wtbl_size(struct mt7996_dev *dev) 640 { 641 return (dev->wtbl_size_group << 8) + MT7996_WTBL_BMC_SIZE; 642 } 643 644 void mt7996_dual_hif_set_irq_mask(struct mt7996_dev *dev, bool write_reg, 645 u32 clear, u32 set); 646 647 static inline void mt7996_irq_enable(struct mt7996_dev *dev, u32 mask) 648 { 649 if (dev->hif2) 650 mt7996_dual_hif_set_irq_mask(dev, false, 0, mask); 651 else 652 mt76_set_irq_mask(&dev->mt76, 0, 0, mask); 653 654 tasklet_schedule(&dev->mt76.irq_tasklet); 655 } 656 657 static inline void mt7996_irq_disable(struct mt7996_dev *dev, u32 mask) 658 { 659 if (dev->hif2) 660 mt7996_dual_hif_set_irq_mask(dev, true, mask, 0); 661 else 662 mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0); 663 } 664 665 void mt7996_memcpy_fromio(struct mt7996_dev *dev, void *buf, u32 offset, 666 size_t len); 667 668 static inline u16 mt7996_rx_chainmask(struct mt7996_phy *phy) 669 { 670 int max_nss = hweight8(phy->mt76->hw->wiphy->available_antennas_tx); 671 int cur_nss = hweight8(phy->mt76->antenna_mask); 672 u16 tx_chainmask = phy->mt76->chainmask; 673 674 if (cur_nss != max_nss) 675 return tx_chainmask; 676 677 return tx_chainmask | (BIT(fls(tx_chainmask)) * phy->has_aux_rx); 678 } 679 680 void mt7996_mac_init(struct mt7996_dev *dev); 681 u32 mt7996_mac_wtbl_lmac_addr(struct mt7996_dev *dev, u16 wcid, u8 dw); 682 bool mt7996_mac_wtbl_update(struct mt7996_dev *dev, int idx, u32 mask); 683 void mt7996_mac_reset_counters(struct mt7996_phy *phy); 684 void mt7996_mac_cca_stats_reset(struct mt7996_phy *phy); 685 void mt7996_mac_enable_nf(struct mt7996_dev *dev, u8 band); 686 void mt7996_mac_enable_rtscts(struct mt7996_dev *dev, 687 struct ieee80211_vif *vif, bool enable); 688 void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi, 689 struct sk_buff *skb, struct mt76_wcid *wcid, 690 struct ieee80211_key_conf *key, int pid, 691 enum mt76_txq_id qid, u32 changed); 692 void mt7996_mac_set_coverage_class(struct mt7996_phy *phy); 693 int mt7996_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif, 694 struct ieee80211_sta *sta); 695 int mt7996_mac_sta_event(struct mt76_dev *mdev, struct ieee80211_vif *vif, 696 struct ieee80211_sta *sta, enum mt76_sta_event ev); 697 void mt7996_mac_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif, 698 struct ieee80211_sta *sta); 699 void mt7996_mac_work(struct work_struct *work); 700 void mt7996_mac_reset_work(struct work_struct *work); 701 void mt7996_mac_dump_work(struct work_struct *work); 702 void mt7996_mac_sta_rc_work(struct work_struct *work); 703 void mt7996_mac_update_stats(struct mt7996_phy *phy); 704 void mt7996_mac_twt_teardown_flow(struct mt7996_dev *dev, 705 struct mt7996_sta *msta, 706 u8 flowid); 707 void mt7996_mac_add_twt_setup(struct ieee80211_hw *hw, 708 struct ieee80211_sta *sta, 709 struct ieee80211_twt_setup *twt); 710 int mt7996_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, 711 enum mt76_txq_id qid, struct mt76_wcid *wcid, 712 struct ieee80211_sta *sta, 713 struct mt76_tx_info *tx_info); 714 void mt7996_tx_token_put(struct mt7996_dev *dev); 715 void mt7996_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 716 struct sk_buff *skb, u32 *info); 717 bool mt7996_rx_check(struct mt76_dev *mdev, void *data, int len); 718 void mt7996_stats_work(struct work_struct *work); 719 int mt76_dfs_start_rdd(struct mt7996_dev *dev, bool force); 720 int mt7996_dfs_init_radar_detector(struct mt7996_phy *phy); 721 void mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy); 722 void mt7996_set_stream_vht_txbf_caps(struct mt7996_phy *phy); 723 void mt7996_update_channel(struct mt76_phy *mphy); 724 int mt7996_init_debugfs(struct mt7996_dev *dev); 725 void mt7996_debugfs_rx_fw_monitor(struct mt7996_dev *dev, const void *data, int len); 726 bool mt7996_debugfs_rx_log(struct mt7996_dev *dev, const void *data, int len); 727 int mt7996_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif, 728 struct ieee80211_key_conf *key, int mcu_cmd, 729 struct mt76_wcid *wcid, enum set_key_cmd cmd); 730 int mt7996_mcu_bcn_prot_enable(struct mt7996_dev *dev, struct ieee80211_vif *vif, 731 struct ieee80211_key_conf *key); 732 int mt7996_mcu_wtbl_update_hdr_trans(struct mt7996_dev *dev, 733 struct ieee80211_vif *vif, 734 struct ieee80211_sta *sta); 735 int mt7996_mcu_cp_support(struct mt7996_dev *dev, u8 mode); 736 #ifdef CONFIG_MAC80211_DEBUGFS 737 void mt7996_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 738 struct ieee80211_sta *sta, struct dentry *dir); 739 #endif 740 int mt7996_mmio_wed_init(struct mt7996_dev *dev, void *pdev_ptr, 741 bool hif2, int *irq); 742 u32 mt7996_wed_init_buf(void *ptr, dma_addr_t phys, int token_id); 743 744 #ifdef CONFIG_MTK_DEBUG 745 int mt7996_mtk_init_debugfs(struct mt7996_phy *phy, struct dentry *dir); 746 #endif 747 748 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 749 int mt7996_dma_rro_init(struct mt7996_dev *dev); 750 #endif /* CONFIG_NET_MEDIATEK_SOC_WED */ 751 752 #endif 753