1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/module.h> 8 #include <linux/pci.h> 9 #include <linux/rtnetlink.h> 10 11 #include "mt7996.h" 12 #include "mac.h" 13 #include "mcu.h" 14 #include "../trace.h" 15 #include "../dma.h" 16 17 static bool wed_enable; 18 module_param(wed_enable, bool, 0644); 19 20 static const struct __base mt7996_reg_base[] = { 21 [WF_AGG_BASE] = { { 0x820e2000, 0x820f2000, 0x830e2000 } }, 22 [WF_ARB_BASE] = { { 0x820e3000, 0x820f3000, 0x830e3000 } }, 23 [WF_TMAC_BASE] = { { 0x820e4000, 0x820f4000, 0x830e4000 } }, 24 [WF_RMAC_BASE] = { { 0x820e5000, 0x820f5000, 0x830e5000 } }, 25 [WF_DMA_BASE] = { { 0x820e7000, 0x820f7000, 0x830e7000 } }, 26 [WF_WTBLOFF_BASE] = { { 0x820e9000, 0x820f9000, 0x830e9000 } }, 27 [WF_ETBF_BASE] = { { 0x820ea000, 0x820fa000, 0x830ea000 } }, 28 [WF_LPON_BASE] = { { 0x820eb000, 0x820fb000, 0x830eb000 } }, 29 [WF_MIB_BASE] = { { 0x820ed000, 0x820fd000, 0x830ed000 } }, 30 [WF_RATE_BASE] = { { 0x820ee000, 0x820fe000, 0x830ee000 } }, 31 }; 32 33 static const u32 mt7996_offs[] = { 34 [MIB_RVSR0] = 0x720, 35 [MIB_RVSR1] = 0x724, 36 [MIB_BTSCR5] = 0x788, 37 [MIB_BTSCR6] = 0x798, 38 [MIB_RSCR1] = 0x7ac, 39 [MIB_RSCR27] = 0x954, 40 [MIB_RSCR28] = 0x958, 41 [MIB_RSCR29] = 0x95c, 42 [MIB_RSCR30] = 0x960, 43 [MIB_RSCR31] = 0x964, 44 [MIB_RSCR33] = 0x96c, 45 [MIB_RSCR35] = 0x974, 46 [MIB_RSCR36] = 0x978, 47 [MIB_BSCR0] = 0x9cc, 48 [MIB_BSCR1] = 0x9d0, 49 [MIB_BSCR2] = 0x9d4, 50 [MIB_BSCR3] = 0x9d8, 51 [MIB_BSCR4] = 0x9dc, 52 [MIB_BSCR5] = 0x9e0, 53 [MIB_BSCR6] = 0x9e4, 54 [MIB_BSCR7] = 0x9e8, 55 [MIB_BSCR17] = 0xa10, 56 [MIB_TRDR1] = 0xa28, 57 }; 58 59 static const u32 mt7992_offs[] = { 60 [MIB_RVSR0] = 0x760, 61 [MIB_RVSR1] = 0x764, 62 [MIB_BTSCR5] = 0x7c8, 63 [MIB_BTSCR6] = 0x7d8, 64 [MIB_RSCR1] = 0x7f0, 65 [MIB_RSCR27] = 0x998, 66 [MIB_RSCR28] = 0x99c, 67 [MIB_RSCR29] = 0x9a0, 68 [MIB_RSCR30] = 0x9a4, 69 [MIB_RSCR31] = 0x9a8, 70 [MIB_RSCR33] = 0x9b0, 71 [MIB_RSCR35] = 0x9b8, 72 [MIB_RSCR36] = 0x9bc, 73 [MIB_BSCR0] = 0xac8, 74 [MIB_BSCR1] = 0xacc, 75 [MIB_BSCR2] = 0xad0, 76 [MIB_BSCR3] = 0xad4, 77 [MIB_BSCR4] = 0xad8, 78 [MIB_BSCR5] = 0xadc, 79 [MIB_BSCR6] = 0xae0, 80 [MIB_BSCR7] = 0xae4, 81 [MIB_BSCR17] = 0xb0c, 82 [MIB_TRDR1] = 0xb24, 83 }; 84 85 static const struct __map mt7996_reg_map[] = { 86 { 0x54000000, 0x02000, 0x1000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */ 87 { 0x55000000, 0x03000, 0x1000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */ 88 { 0x56000000, 0x04000, 0x1000 }, /* WFDMA reserved */ 89 { 0x57000000, 0x05000, 0x1000 }, /* WFDMA MCU wrap CR */ 90 { 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */ 91 { 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */ 92 { 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */ 93 { 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */ 94 { 0x820cc000, 0x0e000, 0x1000 }, /* WF_UMAC_TOP (PP) */ 95 { 0x74030000, 0x10000, 0x1000 }, /* PCIe MAC */ 96 { 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */ 97 { 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */ 98 { 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ 99 { 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */ 100 { 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ 101 { 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */ 102 { 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */ 103 { 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ 104 { 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */ 105 { 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ 106 { 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */ 107 { 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ 108 { 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */ 109 { 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ 110 { 0x820ca000, 0x26000, 0x2000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */ 111 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ 112 { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */ 113 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */ 114 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure register) */ 115 { 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */ 116 { 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */ 117 { 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */ 118 { 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */ 119 { 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */ 120 { 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */ 121 { 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */ 122 { 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ 123 { 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */ 124 { 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */ 125 { 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */ 126 { 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */ 127 { 0x820cc000, 0xa5000, 0x2000 }, /* WF_LMAC_TOP BN1 (WF_MUCOP) */ 128 { 0x820c4000, 0xa8000, 0x4000 }, /* WF_LMAC_TOP BN1 (WF_MUCOP) */ 129 { 0x820b0000, 0xae000, 0x1000 }, /* [APB2] WFSYS_ON */ 130 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */ 131 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */ 132 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, wfdma */ 133 { 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */ 134 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */ 135 { 0x0, 0x0, 0x0 }, /* imply end of search */ 136 }; 137 138 static u32 mt7996_reg_map_l1(struct mt7996_dev *dev, u32 addr) 139 { 140 u32 offset = FIELD_GET(MT_HIF_REMAP_L1_OFFSET, addr); 141 u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, addr); 142 143 dev->reg_l1_backup = dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1); 144 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L1, 145 MT_HIF_REMAP_L1_MASK, 146 FIELD_PREP(MT_HIF_REMAP_L1_MASK, base)); 147 /* use read to push write */ 148 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1); 149 150 return MT_HIF_REMAP_BASE_L1 + offset; 151 } 152 153 static u32 mt7996_reg_map_l2(struct mt7996_dev *dev, u32 addr) 154 { 155 u32 offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET, addr); 156 u32 base = FIELD_GET(MT_HIF_REMAP_L2_BASE, addr); 157 158 dev->reg_l2_backup = dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2); 159 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2, 160 MT_HIF_REMAP_L2_MASK, 161 FIELD_PREP(MT_HIF_REMAP_L2_MASK, base)); 162 /* use read to push write */ 163 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2); 164 165 return MT_HIF_REMAP_BASE_L2 + offset; 166 } 167 168 static void mt7996_reg_remap_restore(struct mt7996_dev *dev) 169 { 170 /* remap to ori status */ 171 if (unlikely(dev->reg_l1_backup)) { 172 dev->bus_ops->wr(&dev->mt76, MT_HIF_REMAP_L1, dev->reg_l1_backup); 173 dev->reg_l1_backup = 0; 174 } 175 176 if (dev->reg_l2_backup) { 177 dev->bus_ops->wr(&dev->mt76, MT_HIF_REMAP_L2, dev->reg_l2_backup); 178 dev->reg_l2_backup = 0; 179 } 180 } 181 182 static u32 __mt7996_reg_addr(struct mt7996_dev *dev, u32 addr) 183 { 184 int i; 185 186 mt7996_reg_remap_restore(dev); 187 188 if (addr < 0x100000) 189 return addr; 190 191 for (i = 0; i < dev->reg.map_size; i++) { 192 u32 ofs; 193 194 if (addr < dev->reg.map[i].phys) 195 continue; 196 197 ofs = addr - dev->reg.map[i].phys; 198 if (ofs > dev->reg.map[i].size) 199 continue; 200 201 return dev->reg.map[i].mapped + ofs; 202 } 203 204 if ((addr >= MT_INFRA_BASE && addr < MT_WFSYS0_PHY_START) || 205 (addr >= MT_WFSYS0_PHY_START && addr < MT_WFSYS1_PHY_START) || 206 (addr >= MT_WFSYS1_PHY_START && addr <= MT_WFSYS1_PHY_END)) 207 return mt7996_reg_map_l1(dev, addr); 208 209 if (dev_is_pci(dev->mt76.dev) && 210 ((addr >= MT_CBTOP1_PHY_START && addr <= MT_CBTOP1_PHY_END) || 211 addr >= MT_CBTOP2_PHY_START)) 212 return mt7996_reg_map_l1(dev, addr); 213 214 /* CONN_INFRA: covert to phyiscal addr and use layer 1 remap */ 215 if (addr >= MT_INFRA_MCU_START && addr <= MT_INFRA_MCU_END) { 216 addr = addr - MT_INFRA_MCU_START + MT_INFRA_BASE; 217 return mt7996_reg_map_l1(dev, addr); 218 } 219 220 return mt7996_reg_map_l2(dev, addr); 221 } 222 223 void mt7996_memcpy_fromio(struct mt7996_dev *dev, void *buf, u32 offset, 224 size_t len) 225 { 226 u32 addr = __mt7996_reg_addr(dev, offset); 227 228 memcpy_fromio(buf, dev->mt76.mmio.regs + addr, len); 229 } 230 231 static u32 mt7996_rr(struct mt76_dev *mdev, u32 offset) 232 { 233 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 234 235 return dev->bus_ops->rr(mdev, __mt7996_reg_addr(dev, offset)); 236 } 237 238 static void mt7996_wr(struct mt76_dev *mdev, u32 offset, u32 val) 239 { 240 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 241 242 dev->bus_ops->wr(mdev, __mt7996_reg_addr(dev, offset), val); 243 } 244 245 static u32 mt7996_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val) 246 { 247 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 248 249 return dev->bus_ops->rmw(mdev, __mt7996_reg_addr(dev, offset), mask, val); 250 } 251 252 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 253 static int mt7996_mmio_wed_reset(struct mtk_wed_device *wed) 254 { 255 struct mt76_dev *mdev = container_of(wed, struct mt76_dev, mmio.wed); 256 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 257 struct mt76_phy *mphy = &dev->mphy; 258 int ret; 259 260 ASSERT_RTNL(); 261 262 if (test_and_set_bit(MT76_STATE_WED_RESET, &mphy->state)) 263 return -EBUSY; 264 265 ret = mt7996_mcu_set_ser(dev, UNI_CMD_SER_TRIGGER, UNI_CMD_SER_SET_RECOVER_L1, 266 mphy->band_idx); 267 if (ret) 268 goto out; 269 270 rtnl_unlock(); 271 if (!wait_for_completion_timeout(&mdev->mmio.wed_reset, 20 * HZ)) { 272 dev_err(mdev->dev, "wed reset timeout\n"); 273 ret = -ETIMEDOUT; 274 } 275 rtnl_lock(); 276 out: 277 clear_bit(MT76_STATE_WED_RESET, &mphy->state); 278 279 return ret; 280 } 281 #endif 282 283 int mt7996_mmio_wed_init(struct mt7996_dev *dev, void *pdev_ptr, 284 bool hif2, int *irq) 285 { 286 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 287 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 288 struct pci_dev *pci_dev = pdev_ptr; 289 u32 hif1_ofs = 0; 290 291 if (!wed_enable) 292 return 0; 293 294 dev->has_rro = true; 295 296 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); 297 298 if (hif2) 299 wed = &dev->mt76.mmio.wed_hif2; 300 301 wed->wlan.pci_dev = pci_dev; 302 wed->wlan.bus_type = MTK_WED_BUS_PCIE; 303 304 wed->wlan.base = devm_ioremap(dev->mt76.dev, 305 pci_resource_start(pci_dev, 0), 306 pci_resource_len(pci_dev, 0)); 307 wed->wlan.phy_base = pci_resource_start(pci_dev, 0); 308 309 if (hif2) { 310 wed->wlan.wpdma_int = wed->wlan.phy_base + 311 MT_INT_PCIE1_SOURCE_CSR_EXT; 312 wed->wlan.wpdma_mask = wed->wlan.phy_base + 313 MT_INT_PCIE1_MASK_CSR; 314 wed->wlan.wpdma_tx = wed->wlan.phy_base + hif1_ofs + 315 MT_TXQ_RING_BASE(0) + 316 MT7996_TXQ_BAND2 * MT_RING_SIZE; 317 if (dev->has_rro) { 318 wed->wlan.wpdma_txfree = wed->wlan.phy_base + hif1_ofs + 319 MT_RXQ_RING_BASE(0) + 320 MT7996_RXQ_TXFREE2 * MT_RING_SIZE; 321 wed->wlan.txfree_tbit = ffs(MT_INT_RX_TXFREE_EXT) - 1; 322 } else { 323 wed->wlan.wpdma_txfree = wed->wlan.phy_base + hif1_ofs + 324 MT_RXQ_RING_BASE(0) + 325 MT7996_RXQ_MCU_WA_TRI * MT_RING_SIZE; 326 wed->wlan.txfree_tbit = ffs(MT_INT_RX_DONE_WA_TRI) - 1; 327 } 328 329 wed->wlan.wpdma_rx_glo = wed->wlan.phy_base + hif1_ofs + MT_WFDMA0_GLO_CFG; 330 wed->wlan.wpdma_rx = wed->wlan.phy_base + hif1_ofs + 331 MT_RXQ_RING_BASE(MT7996_RXQ_BAND0) + 332 MT7996_RXQ_BAND0 * MT_RING_SIZE; 333 334 wed->wlan.id = 0x7991; 335 wed->wlan.tx_tbit[0] = ffs(MT_INT_TX_DONE_BAND2) - 1; 336 } else { 337 wed->wlan.hw_rro = dev->has_rro; /* default on */ 338 wed->wlan.wpdma_int = wed->wlan.phy_base + MT_INT_SOURCE_CSR; 339 wed->wlan.wpdma_mask = wed->wlan.phy_base + MT_INT_MASK_CSR; 340 wed->wlan.wpdma_tx = wed->wlan.phy_base + MT_TXQ_RING_BASE(0) + 341 MT7996_TXQ_BAND0 * MT_RING_SIZE; 342 343 wed->wlan.wpdma_rx_glo = wed->wlan.phy_base + MT_WFDMA0_GLO_CFG; 344 345 wed->wlan.wpdma_rx = wed->wlan.phy_base + 346 MT_RXQ_RING_BASE(MT7996_RXQ_BAND0) + 347 MT7996_RXQ_BAND0 * MT_RING_SIZE; 348 349 wed->wlan.wpdma_rx_rro[0] = wed->wlan.phy_base + 350 MT_RXQ_RING_BASE(MT7996_RXQ_RRO_BAND0) + 351 MT7996_RXQ_RRO_BAND0 * MT_RING_SIZE; 352 wed->wlan.wpdma_rx_rro[1] = wed->wlan.phy_base + hif1_ofs + 353 MT_RXQ_RING_BASE(MT7996_RXQ_RRO_BAND2) + 354 MT7996_RXQ_RRO_BAND2 * MT_RING_SIZE; 355 wed->wlan.wpdma_rx_pg = wed->wlan.phy_base + 356 MT_RXQ_RING_BASE(MT7996_RXQ_MSDU_PG_BAND0) + 357 MT7996_RXQ_MSDU_PG_BAND0 * MT_RING_SIZE; 358 359 wed->wlan.rx_nbuf = 65536; 360 wed->wlan.rx_npkt = dev->hif2 ? 32768 : 24576; 361 wed->wlan.rx_size = SKB_WITH_OVERHEAD(MT_RX_BUF_SIZE); 362 363 wed->wlan.rx_tbit[0] = ffs(MT_INT_RX_DONE_BAND0) - 1; 364 wed->wlan.rx_tbit[1] = ffs(MT_INT_RX_DONE_BAND2) - 1; 365 366 wed->wlan.rro_rx_tbit[0] = ffs(MT_INT_RX_DONE_RRO_BAND0) - 1; 367 wed->wlan.rro_rx_tbit[1] = ffs(MT_INT_RX_DONE_RRO_BAND2) - 1; 368 369 wed->wlan.rx_pg_tbit[0] = ffs(MT_INT_RX_DONE_MSDU_PG_BAND0) - 1; 370 wed->wlan.rx_pg_tbit[1] = ffs(MT_INT_RX_DONE_MSDU_PG_BAND1) - 1; 371 wed->wlan.rx_pg_tbit[2] = ffs(MT_INT_RX_DONE_MSDU_PG_BAND2) - 1; 372 373 wed->wlan.tx_tbit[0] = ffs(MT_INT_TX_DONE_BAND0) - 1; 374 wed->wlan.tx_tbit[1] = ffs(MT_INT_TX_DONE_BAND1) - 1; 375 if (dev->has_rro) { 376 wed->wlan.wpdma_txfree = wed->wlan.phy_base + MT_RXQ_RING_BASE(0) + 377 MT7996_RXQ_TXFREE0 * MT_RING_SIZE; 378 wed->wlan.txfree_tbit = ffs(MT_INT_RX_TXFREE_MAIN) - 1; 379 } else { 380 wed->wlan.txfree_tbit = ffs(MT_INT_RX_DONE_WA_MAIN) - 1; 381 wed->wlan.wpdma_txfree = wed->wlan.phy_base + MT_RXQ_RING_BASE(0) + 382 MT7996_RXQ_MCU_WA_MAIN * MT_RING_SIZE; 383 } 384 dev->mt76.rx_token_size = MT7996_TOKEN_SIZE + wed->wlan.rx_npkt; 385 } 386 387 wed->wlan.nbuf = MT7996_HW_TOKEN_SIZE; 388 wed->wlan.token_start = MT7996_TOKEN_SIZE - wed->wlan.nbuf; 389 390 wed->wlan.amsdu_max_subframes = 8; 391 wed->wlan.amsdu_max_len = 1536; 392 393 wed->wlan.init_buf = mt7996_wed_init_buf; 394 wed->wlan.init_rx_buf = mt76_mmio_wed_init_rx_buf; 395 wed->wlan.release_rx_buf = mt76_mmio_wed_release_rx_buf; 396 wed->wlan.offload_enable = mt76_mmio_wed_offload_enable; 397 wed->wlan.offload_disable = mt76_mmio_wed_offload_disable; 398 if (!hif2) { 399 wed->wlan.reset = mt7996_mmio_wed_reset; 400 wed->wlan.reset_complete = mt76_mmio_wed_reset_complete; 401 } 402 403 if (mtk_wed_device_attach(wed)) 404 return 0; 405 406 *irq = wed->irq; 407 dev->mt76.dma_dev = wed->dev; 408 409 return 1; 410 #else 411 return 0; 412 #endif 413 } 414 415 static int mt7996_mmio_init(struct mt76_dev *mdev, 416 void __iomem *mem_base, 417 u32 device_id) 418 { 419 struct mt76_bus_ops *bus_ops; 420 struct mt7996_dev *dev; 421 422 dev = container_of(mdev, struct mt7996_dev, mt76); 423 mt76_mmio_init(&dev->mt76, mem_base); 424 425 switch (device_id) { 426 case 0x7990: 427 dev->reg.base = mt7996_reg_base; 428 dev->reg.offs_rev = mt7996_offs; 429 dev->reg.map = mt7996_reg_map; 430 dev->reg.map_size = ARRAY_SIZE(mt7996_reg_map); 431 break; 432 case 0x7992: 433 dev->reg.base = mt7996_reg_base; 434 dev->reg.offs_rev = mt7992_offs; 435 dev->reg.map = mt7996_reg_map; 436 dev->reg.map_size = ARRAY_SIZE(mt7996_reg_map); 437 break; 438 default: 439 return -EINVAL; 440 } 441 442 dev->bus_ops = dev->mt76.bus; 443 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops), 444 GFP_KERNEL); 445 if (!bus_ops) 446 return -ENOMEM; 447 448 bus_ops->rr = mt7996_rr; 449 bus_ops->wr = mt7996_wr; 450 bus_ops->rmw = mt7996_rmw; 451 dev->mt76.bus = bus_ops; 452 453 mdev->rev = (device_id << 16) | (mt76_rr(dev, MT_HW_REV) & 0xff); 454 455 dev_dbg(mdev->dev, "ASIC revision: %04x\n", mdev->rev); 456 457 return 0; 458 } 459 460 void mt7996_dual_hif_set_irq_mask(struct mt7996_dev *dev, bool write_reg, 461 u32 clear, u32 set) 462 { 463 struct mt76_dev *mdev = &dev->mt76; 464 unsigned long flags; 465 466 spin_lock_irqsave(&mdev->mmio.irq_lock, flags); 467 468 mdev->mmio.irqmask &= ~clear; 469 mdev->mmio.irqmask |= set; 470 471 if (write_reg) { 472 if (mtk_wed_device_active(&mdev->mmio.wed)) { 473 mtk_wed_device_irq_set_mask(&mdev->mmio.wed, 474 mdev->mmio.irqmask); 475 if (mtk_wed_device_active(&mdev->mmio.wed_hif2)) { 476 mtk_wed_device_irq_set_mask(&mdev->mmio.wed_hif2, 477 mdev->mmio.irqmask); 478 } 479 } else { 480 mt76_wr(dev, MT_INT_MASK_CSR, mdev->mmio.irqmask); 481 mt76_wr(dev, MT_INT1_MASK_CSR, mdev->mmio.irqmask); 482 } 483 } 484 485 spin_unlock_irqrestore(&mdev->mmio.irq_lock, flags); 486 } 487 488 static void mt7996_rx_poll_complete(struct mt76_dev *mdev, 489 enum mt76_rxq_id q) 490 { 491 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 492 493 mt7996_irq_enable(dev, MT_INT_RX(q)); 494 } 495 496 /* TODO: support 2/4/6/8 MSI-X vectors */ 497 static void mt7996_irq_tasklet(struct tasklet_struct *t) 498 { 499 struct mt7996_dev *dev = from_tasklet(dev, t, mt76.irq_tasklet); 500 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 501 struct mtk_wed_device *wed_hif2 = &dev->mt76.mmio.wed_hif2; 502 u32 i, intr, mask, intr1; 503 504 if (dev->hif2 && mtk_wed_device_active(wed_hif2)) { 505 mtk_wed_device_irq_set_mask(wed_hif2, 0); 506 intr1 = mtk_wed_device_irq_get(wed_hif2, 507 dev->mt76.mmio.irqmask); 508 if (intr1 & MT_INT_RX_TXFREE_EXT) 509 napi_schedule(&dev->mt76.napi[MT_RXQ_TXFREE_BAND2]); 510 } 511 512 if (mtk_wed_device_active(wed)) { 513 mtk_wed_device_irq_set_mask(wed, 0); 514 intr = mtk_wed_device_irq_get(wed, dev->mt76.mmio.irqmask); 515 intr |= (intr1 & ~MT_INT_RX_TXFREE_EXT); 516 } else { 517 mt76_wr(dev, MT_INT_MASK_CSR, 0); 518 if (dev->hif2) 519 mt76_wr(dev, MT_INT1_MASK_CSR, 0); 520 521 intr = mt76_rr(dev, MT_INT_SOURCE_CSR); 522 intr &= dev->mt76.mmio.irqmask; 523 mt76_wr(dev, MT_INT_SOURCE_CSR, intr); 524 if (dev->hif2) { 525 intr1 = mt76_rr(dev, MT_INT1_SOURCE_CSR); 526 intr1 &= dev->mt76.mmio.irqmask; 527 mt76_wr(dev, MT_INT1_SOURCE_CSR, intr1); 528 intr |= intr1; 529 } 530 } 531 532 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); 533 534 mask = intr & MT_INT_RX_DONE_ALL; 535 if (intr & MT_INT_TX_DONE_MCU) 536 mask |= MT_INT_TX_DONE_MCU; 537 mt7996_irq_disable(dev, mask); 538 539 if (intr & MT_INT_TX_DONE_MCU) 540 napi_schedule(&dev->mt76.tx_napi); 541 542 for (i = 0; i < __MT_RXQ_MAX; i++) { 543 if ((intr & MT_INT_RX(i))) 544 napi_schedule(&dev->mt76.napi[i]); 545 } 546 547 if (intr & MT_INT_MCU_CMD) { 548 u32 val = mt76_rr(dev, MT_MCU_CMD); 549 550 mt76_wr(dev, MT_MCU_CMD, val); 551 if (val & (MT_MCU_CMD_ERROR_MASK | MT_MCU_CMD_WDT_MASK)) { 552 dev->recovery.state = val; 553 mt7996_reset(dev); 554 } 555 } 556 } 557 558 irqreturn_t mt7996_irq_handler(int irq, void *dev_instance) 559 { 560 struct mt7996_dev *dev = dev_instance; 561 562 if (mtk_wed_device_active(&dev->mt76.mmio.wed)) 563 mtk_wed_device_irq_set_mask(&dev->mt76.mmio.wed, 0); 564 else 565 mt76_wr(dev, MT_INT_MASK_CSR, 0); 566 567 if (dev->hif2) { 568 if (mtk_wed_device_active(&dev->mt76.mmio.wed_hif2)) 569 mtk_wed_device_irq_set_mask(&dev->mt76.mmio.wed_hif2, 0); 570 else 571 mt76_wr(dev, MT_INT1_MASK_CSR, 0); 572 } 573 574 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state)) 575 return IRQ_NONE; 576 577 tasklet_schedule(&dev->mt76.irq_tasklet); 578 579 return IRQ_HANDLED; 580 } 581 582 struct mt7996_dev *mt7996_mmio_probe(struct device *pdev, 583 void __iomem *mem_base, u32 device_id) 584 { 585 static const struct mt76_driver_ops drv_ops = { 586 /* txwi_size = txd size + txp size */ 587 .txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_fw_txp), 588 .drv_flags = MT_DRV_TXWI_NO_FREE | 589 MT_DRV_AMSDU_OFFLOAD | 590 MT_DRV_HW_MGMT_TXQ, 591 .survey_flags = SURVEY_INFO_TIME_TX | 592 SURVEY_INFO_TIME_RX | 593 SURVEY_INFO_TIME_BSS_RX, 594 .token_size = MT7996_TOKEN_SIZE, 595 .tx_prepare_skb = mt7996_tx_prepare_skb, 596 .tx_complete_skb = mt76_connac_tx_complete_skb, 597 .rx_skb = mt7996_queue_rx_skb, 598 .rx_check = mt7996_rx_check, 599 .rx_poll_complete = mt7996_rx_poll_complete, 600 .sta_add = mt7996_mac_sta_add, 601 .sta_remove = mt7996_mac_sta_remove, 602 .update_survey = mt7996_update_channel, 603 }; 604 struct mt7996_dev *dev; 605 struct mt76_dev *mdev; 606 int ret; 607 608 mdev = mt76_alloc_device(pdev, sizeof(*dev), &mt7996_ops, &drv_ops); 609 if (!mdev) 610 return ERR_PTR(-ENOMEM); 611 612 dev = container_of(mdev, struct mt7996_dev, mt76); 613 614 ret = mt7996_mmio_init(mdev, mem_base, device_id); 615 if (ret) 616 goto error; 617 618 tasklet_setup(&mdev->irq_tasklet, mt7996_irq_tasklet); 619 620 mt76_wr(dev, MT_INT_MASK_CSR, 0); 621 622 return dev; 623 624 error: 625 mt76_free_device(&dev->mt76); 626 627 return ERR_PTR(ret); 628 } 629 630 static int __init mt7996_init(void) 631 { 632 int ret; 633 634 ret = pci_register_driver(&mt7996_hif_driver); 635 if (ret) 636 return ret; 637 638 ret = pci_register_driver(&mt7996_pci_driver); 639 if (ret) 640 pci_unregister_driver(&mt7996_hif_driver); 641 642 return ret; 643 } 644 645 static void __exit mt7996_exit(void) 646 { 647 pci_unregister_driver(&mt7996_pci_driver); 648 pci_unregister_driver(&mt7996_hif_driver); 649 } 650 651 module_init(mt7996_init); 652 module_exit(mt7996_exit); 653 MODULE_LICENSE("Dual BSD/GPL"); 654