1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #include <linux/etherdevice.h> 7 #include <linux/timekeeping.h> 8 #include "coredump.h" 9 #include "mt7996.h" 10 #include "../dma.h" 11 #include "mac.h" 12 #include "mcu.h" 13 14 #define to_rssi(field, rcpi) ((FIELD_GET(field, rcpi) - 220) / 2) 15 16 static const struct mt7996_dfs_radar_spec etsi_radar_specs = { 17 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 18 .radar_pattern = { 19 [5] = { 1, 0, 6, 32, 28, 0, 990, 5010, 17, 1, 1 }, 20 [6] = { 1, 0, 9, 32, 28, 0, 615, 5010, 27, 1, 1 }, 21 [7] = { 1, 0, 15, 32, 28, 0, 240, 445, 27, 1, 1 }, 22 [8] = { 1, 0, 12, 32, 28, 0, 240, 510, 42, 1, 1 }, 23 [9] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 12, 32, 28, { }, 126 }, 24 [10] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 15, 32, 24, { }, 126 }, 25 [11] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 18, 32, 28, { }, 54 }, 26 [12] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 27, 32, 24, { }, 54 }, 27 }, 28 }; 29 30 static const struct mt7996_dfs_radar_spec fcc_radar_specs = { 31 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 32 .radar_pattern = { 33 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 }, 34 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 }, 35 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 }, 36 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 }, 37 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 }, 38 }, 39 }; 40 41 static const struct mt7996_dfs_radar_spec jp_radar_specs = { 42 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 43 .radar_pattern = { 44 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 }, 45 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 }, 46 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 }, 47 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 }, 48 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 }, 49 [13] = { 1, 0, 7, 32, 28, 0, 3836, 3856, 14, 1, 1 }, 50 [14] = { 1, 0, 6, 32, 28, 0, 615, 5010, 110, 1, 1 }, 51 [15] = { 1, 1, 0, 0, 0, 0, 15, 5010, 110, 0, 0, 12, 32, 28 }, 52 }, 53 }; 54 55 static struct mt76_wcid *mt7996_rx_get_wcid(struct mt7996_dev *dev, 56 u16 idx, bool unicast) 57 { 58 struct mt7996_sta *sta; 59 struct mt76_wcid *wcid; 60 61 if (idx >= ARRAY_SIZE(dev->mt76.wcid)) 62 return NULL; 63 64 wcid = rcu_dereference(dev->mt76.wcid[idx]); 65 if (unicast || !wcid) 66 return wcid; 67 68 if (!wcid->sta) 69 return NULL; 70 71 sta = container_of(wcid, struct mt7996_sta, wcid); 72 if (!sta->vif) 73 return NULL; 74 75 return &sta->vif->sta.wcid; 76 } 77 78 bool mt7996_mac_wtbl_update(struct mt7996_dev *dev, int idx, u32 mask) 79 { 80 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX, 81 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask); 82 83 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 84 0, 5000); 85 } 86 87 u32 mt7996_mac_wtbl_lmac_addr(struct mt7996_dev *dev, u16 wcid, u8 dw) 88 { 89 mt76_wr(dev, MT_WTBLON_TOP_WDUCR, 90 FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (wcid >> 7))); 91 92 return MT_WTBL_LMAC_OFFS(wcid, dw); 93 } 94 95 static void mt7996_mac_sta_poll(struct mt7996_dev *dev) 96 { 97 static const u8 ac_to_tid[] = { 98 [IEEE80211_AC_BE] = 0, 99 [IEEE80211_AC_BK] = 1, 100 [IEEE80211_AC_VI] = 4, 101 [IEEE80211_AC_VO] = 6 102 }; 103 struct ieee80211_sta *sta; 104 struct mt7996_sta *msta; 105 struct rate_info *rate; 106 u32 tx_time[IEEE80211_NUM_ACS], rx_time[IEEE80211_NUM_ACS]; 107 LIST_HEAD(sta_poll_list); 108 int i; 109 110 spin_lock_bh(&dev->mt76.sta_poll_lock); 111 list_splice_init(&dev->mt76.sta_poll_list, &sta_poll_list); 112 spin_unlock_bh(&dev->mt76.sta_poll_lock); 113 114 rcu_read_lock(); 115 116 while (true) { 117 bool clear = false; 118 u32 addr, val; 119 u16 idx; 120 s8 rssi[4]; 121 u8 bw; 122 123 spin_lock_bh(&dev->mt76.sta_poll_lock); 124 if (list_empty(&sta_poll_list)) { 125 spin_unlock_bh(&dev->mt76.sta_poll_lock); 126 break; 127 } 128 msta = list_first_entry(&sta_poll_list, 129 struct mt7996_sta, wcid.poll_list); 130 list_del_init(&msta->wcid.poll_list); 131 spin_unlock_bh(&dev->mt76.sta_poll_lock); 132 133 idx = msta->wcid.idx; 134 135 /* refresh peer's airtime reporting */ 136 addr = mt7996_mac_wtbl_lmac_addr(dev, idx, 20); 137 138 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 139 u32 tx_last = msta->airtime_ac[i]; 140 u32 rx_last = msta->airtime_ac[i + 4]; 141 142 msta->airtime_ac[i] = mt76_rr(dev, addr); 143 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4); 144 145 tx_time[i] = msta->airtime_ac[i] - tx_last; 146 rx_time[i] = msta->airtime_ac[i + 4] - rx_last; 147 148 if ((tx_last | rx_last) & BIT(30)) 149 clear = true; 150 151 addr += 8; 152 } 153 154 if (clear) { 155 mt7996_mac_wtbl_update(dev, idx, 156 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 157 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac)); 158 } 159 160 if (!msta->wcid.sta) 161 continue; 162 163 sta = container_of((void *)msta, struct ieee80211_sta, 164 drv_priv); 165 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 166 u8 q = mt76_connac_lmac_mapping(i); 167 u32 tx_cur = tx_time[q]; 168 u32 rx_cur = rx_time[q]; 169 u8 tid = ac_to_tid[i]; 170 171 if (!tx_cur && !rx_cur) 172 continue; 173 174 ieee80211_sta_register_airtime(sta, tid, tx_cur, rx_cur); 175 } 176 177 /* We don't support reading GI info from txs packets. 178 * For accurate tx status reporting and AQL improvement, 179 * we need to make sure that flags match so polling GI 180 * from per-sta counters directly. 181 */ 182 rate = &msta->wcid.rate; 183 184 switch (rate->bw) { 185 case RATE_INFO_BW_320: 186 bw = IEEE80211_STA_RX_BW_320; 187 break; 188 case RATE_INFO_BW_160: 189 bw = IEEE80211_STA_RX_BW_160; 190 break; 191 case RATE_INFO_BW_80: 192 bw = IEEE80211_STA_RX_BW_80; 193 break; 194 case RATE_INFO_BW_40: 195 bw = IEEE80211_STA_RX_BW_40; 196 break; 197 default: 198 bw = IEEE80211_STA_RX_BW_20; 199 break; 200 } 201 202 addr = mt7996_mac_wtbl_lmac_addr(dev, idx, 6); 203 val = mt76_rr(dev, addr); 204 if (rate->flags & RATE_INFO_FLAGS_EHT_MCS) { 205 addr = mt7996_mac_wtbl_lmac_addr(dev, idx, 5); 206 val = mt76_rr(dev, addr); 207 rate->eht_gi = FIELD_GET(GENMASK(25, 24), val); 208 } else if (rate->flags & RATE_INFO_FLAGS_HE_MCS) { 209 u8 offs = 24 + 2 * bw; 210 211 rate->he_gi = (val & (0x3 << offs)) >> offs; 212 } else if (rate->flags & 213 (RATE_INFO_FLAGS_VHT_MCS | RATE_INFO_FLAGS_MCS)) { 214 if (val & BIT(12 + bw)) 215 rate->flags |= RATE_INFO_FLAGS_SHORT_GI; 216 else 217 rate->flags &= ~RATE_INFO_FLAGS_SHORT_GI; 218 } 219 220 /* get signal strength of resp frames (CTS/BA/ACK) */ 221 addr = mt7996_mac_wtbl_lmac_addr(dev, idx, 34); 222 val = mt76_rr(dev, addr); 223 224 rssi[0] = to_rssi(GENMASK(7, 0), val); 225 rssi[1] = to_rssi(GENMASK(15, 8), val); 226 rssi[2] = to_rssi(GENMASK(23, 16), val); 227 rssi[3] = to_rssi(GENMASK(31, 14), val); 228 229 msta->ack_signal = 230 mt76_rx_signal(msta->vif->phy->mt76->antenna_mask, rssi); 231 232 ewma_avg_signal_add(&msta->avg_ack_signal, -msta->ack_signal); 233 } 234 235 rcu_read_unlock(); 236 } 237 238 void mt7996_mac_enable_rtscts(struct mt7996_dev *dev, 239 struct ieee80211_vif *vif, bool enable) 240 { 241 struct mt7996_vif *mvif = (struct mt7996_vif *)vif->drv_priv; 242 u32 addr; 243 244 addr = mt7996_mac_wtbl_lmac_addr(dev, mvif->sta.wcid.idx, 5); 245 if (enable) 246 mt76_set(dev, addr, BIT(5)); 247 else 248 mt76_clear(dev, addr, BIT(5)); 249 } 250 251 void mt7996_mac_set_fixed_rate_table(struct mt7996_dev *dev, 252 u8 tbl_idx, u16 rate_idx) 253 { 254 u32 ctrl = MT_WTBL_ITCR_WR | MT_WTBL_ITCR_EXEC | tbl_idx; 255 256 mt76_wr(dev, MT_WTBL_ITDR0, rate_idx); 257 /* use wtbl spe idx */ 258 mt76_wr(dev, MT_WTBL_ITDR1, MT_WTBL_SPE_IDX_SEL); 259 mt76_wr(dev, MT_WTBL_ITCR, ctrl); 260 } 261 262 /* The HW does not translate the mac header to 802.3 for mesh point */ 263 static int mt7996_reverse_frag0_hdr_trans(struct sk_buff *skb, u16 hdr_gap) 264 { 265 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 266 struct ethhdr *eth_hdr = (struct ethhdr *)(skb->data + hdr_gap); 267 struct mt7996_sta *msta = (struct mt7996_sta *)status->wcid; 268 __le32 *rxd = (__le32 *)skb->data; 269 struct ieee80211_sta *sta; 270 struct ieee80211_vif *vif; 271 struct ieee80211_hdr hdr; 272 u16 frame_control; 273 274 if (le32_get_bits(rxd[3], MT_RXD3_NORMAL_ADDR_TYPE) != 275 MT_RXD3_NORMAL_U2M) 276 return -EINVAL; 277 278 if (!(le32_to_cpu(rxd[1]) & MT_RXD1_NORMAL_GROUP_4)) 279 return -EINVAL; 280 281 if (!msta || !msta->vif) 282 return -EINVAL; 283 284 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv); 285 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); 286 287 /* store the info from RXD and ethhdr to avoid being overridden */ 288 frame_control = le32_get_bits(rxd[8], MT_RXD8_FRAME_CONTROL); 289 hdr.frame_control = cpu_to_le16(frame_control); 290 hdr.seq_ctrl = cpu_to_le16(le32_get_bits(rxd[10], MT_RXD10_SEQ_CTRL)); 291 hdr.duration_id = 0; 292 293 ether_addr_copy(hdr.addr1, vif->addr); 294 ether_addr_copy(hdr.addr2, sta->addr); 295 switch (frame_control & (IEEE80211_FCTL_TODS | 296 IEEE80211_FCTL_FROMDS)) { 297 case 0: 298 ether_addr_copy(hdr.addr3, vif->bss_conf.bssid); 299 break; 300 case IEEE80211_FCTL_FROMDS: 301 ether_addr_copy(hdr.addr3, eth_hdr->h_source); 302 break; 303 case IEEE80211_FCTL_TODS: 304 ether_addr_copy(hdr.addr3, eth_hdr->h_dest); 305 break; 306 case IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS: 307 ether_addr_copy(hdr.addr3, eth_hdr->h_dest); 308 ether_addr_copy(hdr.addr4, eth_hdr->h_source); 309 break; 310 default: 311 return -EINVAL; 312 } 313 314 skb_pull(skb, hdr_gap + sizeof(struct ethhdr) - 2); 315 if (eth_hdr->h_proto == cpu_to_be16(ETH_P_AARP) || 316 eth_hdr->h_proto == cpu_to_be16(ETH_P_IPX)) 317 ether_addr_copy(skb_push(skb, ETH_ALEN), bridge_tunnel_header); 318 else if (be16_to_cpu(eth_hdr->h_proto) >= ETH_P_802_3_MIN) 319 ether_addr_copy(skb_push(skb, ETH_ALEN), rfc1042_header); 320 else 321 skb_pull(skb, 2); 322 323 if (ieee80211_has_order(hdr.frame_control)) 324 memcpy(skb_push(skb, IEEE80211_HT_CTL_LEN), &rxd[11], 325 IEEE80211_HT_CTL_LEN); 326 if (ieee80211_is_data_qos(hdr.frame_control)) { 327 __le16 qos_ctrl; 328 329 qos_ctrl = cpu_to_le16(le32_get_bits(rxd[10], MT_RXD10_QOS_CTL)); 330 memcpy(skb_push(skb, IEEE80211_QOS_CTL_LEN), &qos_ctrl, 331 IEEE80211_QOS_CTL_LEN); 332 } 333 334 if (ieee80211_has_a4(hdr.frame_control)) 335 memcpy(skb_push(skb, sizeof(hdr)), &hdr, sizeof(hdr)); 336 else 337 memcpy(skb_push(skb, sizeof(hdr) - 6), &hdr, sizeof(hdr) - 6); 338 339 return 0; 340 } 341 342 static int 343 mt7996_mac_fill_rx_rate(struct mt7996_dev *dev, 344 struct mt76_rx_status *status, 345 struct ieee80211_supported_band *sband, 346 __le32 *rxv, u8 *mode) 347 { 348 u32 v0, v2; 349 u8 stbc, gi, bw, dcm, nss; 350 int i, idx; 351 bool cck = false; 352 353 v0 = le32_to_cpu(rxv[0]); 354 v2 = le32_to_cpu(rxv[2]); 355 356 idx = FIELD_GET(MT_PRXV_TX_RATE, v0); 357 i = idx; 358 nss = FIELD_GET(MT_PRXV_NSTS, v0) + 1; 359 360 stbc = FIELD_GET(MT_PRXV_HT_STBC, v2); 361 gi = FIELD_GET(MT_PRXV_HT_SHORT_GI, v2); 362 *mode = FIELD_GET(MT_PRXV_TX_MODE, v2); 363 dcm = FIELD_GET(MT_PRXV_DCM, v2); 364 bw = FIELD_GET(MT_PRXV_FRAME_MODE, v2); 365 366 switch (*mode) { 367 case MT_PHY_TYPE_CCK: 368 cck = true; 369 fallthrough; 370 case MT_PHY_TYPE_OFDM: 371 i = mt76_get_rate(&dev->mt76, sband, i, cck); 372 break; 373 case MT_PHY_TYPE_HT_GF: 374 case MT_PHY_TYPE_HT: 375 status->encoding = RX_ENC_HT; 376 if (gi) 377 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 378 if (i > 31) 379 return -EINVAL; 380 break; 381 case MT_PHY_TYPE_VHT: 382 status->nss = nss; 383 status->encoding = RX_ENC_VHT; 384 if (gi) 385 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 386 if (i > 11) 387 return -EINVAL; 388 break; 389 case MT_PHY_TYPE_HE_MU: 390 case MT_PHY_TYPE_HE_SU: 391 case MT_PHY_TYPE_HE_EXT_SU: 392 case MT_PHY_TYPE_HE_TB: 393 status->nss = nss; 394 status->encoding = RX_ENC_HE; 395 i &= GENMASK(3, 0); 396 397 if (gi <= NL80211_RATE_INFO_HE_GI_3_2) 398 status->he_gi = gi; 399 400 status->he_dcm = dcm; 401 break; 402 case MT_PHY_TYPE_EHT_SU: 403 case MT_PHY_TYPE_EHT_TRIG: 404 case MT_PHY_TYPE_EHT_MU: 405 status->nss = nss; 406 status->encoding = RX_ENC_EHT; 407 i &= GENMASK(3, 0); 408 409 if (gi <= NL80211_RATE_INFO_EHT_GI_3_2) 410 status->eht.gi = gi; 411 break; 412 default: 413 return -EINVAL; 414 } 415 status->rate_idx = i; 416 417 switch (bw) { 418 case IEEE80211_STA_RX_BW_20: 419 break; 420 case IEEE80211_STA_RX_BW_40: 421 if (*mode & MT_PHY_TYPE_HE_EXT_SU && 422 (idx & MT_PRXV_TX_ER_SU_106T)) { 423 status->bw = RATE_INFO_BW_HE_RU; 424 status->he_ru = 425 NL80211_RATE_INFO_HE_RU_ALLOC_106; 426 } else { 427 status->bw = RATE_INFO_BW_40; 428 } 429 break; 430 case IEEE80211_STA_RX_BW_80: 431 status->bw = RATE_INFO_BW_80; 432 break; 433 case IEEE80211_STA_RX_BW_160: 434 status->bw = RATE_INFO_BW_160; 435 break; 436 /* rxv reports bw 320-1 and 320-2 separately */ 437 case IEEE80211_STA_RX_BW_320: 438 case IEEE80211_STA_RX_BW_320 + 1: 439 status->bw = RATE_INFO_BW_320; 440 break; 441 default: 442 return -EINVAL; 443 } 444 445 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc; 446 if (*mode < MT_PHY_TYPE_HE_SU && gi) 447 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 448 449 return 0; 450 } 451 452 static int 453 mt7996_mac_fill_rx(struct mt7996_dev *dev, struct sk_buff *skb) 454 { 455 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 456 struct mt76_phy *mphy = &dev->mt76.phy; 457 struct mt7996_phy *phy = &dev->phy; 458 struct ieee80211_supported_band *sband; 459 __le32 *rxd = (__le32 *)skb->data; 460 __le32 *rxv = NULL; 461 u32 rxd0 = le32_to_cpu(rxd[0]); 462 u32 rxd1 = le32_to_cpu(rxd[1]); 463 u32 rxd2 = le32_to_cpu(rxd[2]); 464 u32 rxd3 = le32_to_cpu(rxd[3]); 465 u32 rxd4 = le32_to_cpu(rxd[4]); 466 u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM; 467 u32 csum_status = *(u32 *)skb->cb; 468 u32 mesh_mask = MT_RXD0_MESH | MT_RXD0_MHCP; 469 bool is_mesh = (rxd0 & mesh_mask) == mesh_mask; 470 bool unicast, insert_ccmp_hdr = false; 471 u8 remove_pad, amsdu_info, band_idx; 472 u8 mode = 0, qos_ctl = 0; 473 bool hdr_trans; 474 u16 hdr_gap; 475 u16 seq_ctrl = 0; 476 __le16 fc = 0; 477 int idx; 478 479 memset(status, 0, sizeof(*status)); 480 481 band_idx = FIELD_GET(MT_RXD1_NORMAL_BAND_IDX, rxd1); 482 mphy = dev->mt76.phys[band_idx]; 483 phy = mphy->priv; 484 status->phy_idx = mphy->band_idx; 485 486 if (!test_bit(MT76_STATE_RUNNING, &mphy->state)) 487 return -EINVAL; 488 489 if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR) 490 return -EINVAL; 491 492 hdr_trans = rxd2 & MT_RXD2_NORMAL_HDR_TRANS; 493 if (hdr_trans && (rxd1 & MT_RXD1_NORMAL_CM)) 494 return -EINVAL; 495 496 /* ICV error or CCMP/BIP/WPI MIC error */ 497 if (rxd1 & MT_RXD1_NORMAL_ICV_ERR) 498 status->flag |= RX_FLAG_ONLY_MONITOR; 499 500 unicast = FIELD_GET(MT_RXD3_NORMAL_ADDR_TYPE, rxd3) == MT_RXD3_NORMAL_U2M; 501 idx = FIELD_GET(MT_RXD1_NORMAL_WLAN_IDX, rxd1); 502 status->wcid = mt7996_rx_get_wcid(dev, idx, unicast); 503 504 if (status->wcid) { 505 struct mt7996_sta *msta; 506 507 msta = container_of(status->wcid, struct mt7996_sta, wcid); 508 spin_lock_bh(&dev->mt76.sta_poll_lock); 509 if (list_empty(&msta->wcid.poll_list)) 510 list_add_tail(&msta->wcid.poll_list, 511 &dev->mt76.sta_poll_list); 512 spin_unlock_bh(&dev->mt76.sta_poll_lock); 513 } 514 515 status->freq = mphy->chandef.chan->center_freq; 516 status->band = mphy->chandef.chan->band; 517 if (status->band == NL80211_BAND_5GHZ) 518 sband = &mphy->sband_5g.sband; 519 else if (status->band == NL80211_BAND_6GHZ) 520 sband = &mphy->sband_6g.sband; 521 else 522 sband = &mphy->sband_2g.sband; 523 524 if (!sband->channels) 525 return -EINVAL; 526 527 if ((rxd0 & csum_mask) == csum_mask && 528 !(csum_status & (BIT(0) | BIT(2) | BIT(3)))) 529 skb->ip_summed = CHECKSUM_UNNECESSARY; 530 531 if (rxd1 & MT_RXD3_NORMAL_FCS_ERR) 532 status->flag |= RX_FLAG_FAILED_FCS_CRC; 533 534 if (rxd1 & MT_RXD1_NORMAL_TKIP_MIC_ERR) 535 status->flag |= RX_FLAG_MMIC_ERROR; 536 537 if (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2) != 0 && 538 !(rxd1 & (MT_RXD1_NORMAL_CLM | MT_RXD1_NORMAL_CM))) { 539 status->flag |= RX_FLAG_DECRYPTED; 540 status->flag |= RX_FLAG_IV_STRIPPED; 541 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED; 542 } 543 544 remove_pad = FIELD_GET(MT_RXD2_NORMAL_HDR_OFFSET, rxd2); 545 546 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR) 547 return -EINVAL; 548 549 rxd += 8; 550 if (rxd1 & MT_RXD1_NORMAL_GROUP_4) { 551 u32 v0 = le32_to_cpu(rxd[0]); 552 u32 v2 = le32_to_cpu(rxd[2]); 553 554 fc = cpu_to_le16(FIELD_GET(MT_RXD8_FRAME_CONTROL, v0)); 555 qos_ctl = FIELD_GET(MT_RXD10_QOS_CTL, v2); 556 seq_ctrl = FIELD_GET(MT_RXD10_SEQ_CTRL, v2); 557 558 rxd += 4; 559 if ((u8 *)rxd - skb->data >= skb->len) 560 return -EINVAL; 561 } 562 563 if (rxd1 & MT_RXD1_NORMAL_GROUP_1) { 564 u8 *data = (u8 *)rxd; 565 566 if (status->flag & RX_FLAG_DECRYPTED) { 567 switch (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2)) { 568 case MT_CIPHER_AES_CCMP: 569 case MT_CIPHER_CCMP_CCX: 570 case MT_CIPHER_CCMP_256: 571 insert_ccmp_hdr = 572 FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2); 573 fallthrough; 574 case MT_CIPHER_TKIP: 575 case MT_CIPHER_TKIP_NO_MIC: 576 case MT_CIPHER_GCMP: 577 case MT_CIPHER_GCMP_256: 578 status->iv[0] = data[5]; 579 status->iv[1] = data[4]; 580 status->iv[2] = data[3]; 581 status->iv[3] = data[2]; 582 status->iv[4] = data[1]; 583 status->iv[5] = data[0]; 584 break; 585 default: 586 break; 587 } 588 } 589 rxd += 4; 590 if ((u8 *)rxd - skb->data >= skb->len) 591 return -EINVAL; 592 } 593 594 if (rxd1 & MT_RXD1_NORMAL_GROUP_2) { 595 status->timestamp = le32_to_cpu(rxd[0]); 596 status->flag |= RX_FLAG_MACTIME_START; 597 598 if (!(rxd2 & MT_RXD2_NORMAL_NON_AMPDU)) { 599 status->flag |= RX_FLAG_AMPDU_DETAILS; 600 601 /* all subframes of an A-MPDU have the same timestamp */ 602 if (phy->rx_ampdu_ts != status->timestamp) { 603 if (!++phy->ampdu_ref) 604 phy->ampdu_ref++; 605 } 606 phy->rx_ampdu_ts = status->timestamp; 607 608 status->ampdu_ref = phy->ampdu_ref; 609 } 610 611 rxd += 4; 612 if ((u8 *)rxd - skb->data >= skb->len) 613 return -EINVAL; 614 } 615 616 /* RXD Group 3 - P-RXV */ 617 if (rxd1 & MT_RXD1_NORMAL_GROUP_3) { 618 u32 v3; 619 int ret; 620 621 rxv = rxd; 622 rxd += 4; 623 if ((u8 *)rxd - skb->data >= skb->len) 624 return -EINVAL; 625 626 v3 = le32_to_cpu(rxv[3]); 627 628 status->chains = mphy->antenna_mask; 629 status->chain_signal[0] = to_rssi(MT_PRXV_RCPI0, v3); 630 status->chain_signal[1] = to_rssi(MT_PRXV_RCPI1, v3); 631 status->chain_signal[2] = to_rssi(MT_PRXV_RCPI2, v3); 632 status->chain_signal[3] = to_rssi(MT_PRXV_RCPI3, v3); 633 634 /* RXD Group 5 - C-RXV */ 635 if (rxd1 & MT_RXD1_NORMAL_GROUP_5) { 636 rxd += 24; 637 if ((u8 *)rxd - skb->data >= skb->len) 638 return -EINVAL; 639 } 640 641 ret = mt7996_mac_fill_rx_rate(dev, status, sband, rxv, &mode); 642 if (ret < 0) 643 return ret; 644 } 645 646 amsdu_info = FIELD_GET(MT_RXD4_NORMAL_PAYLOAD_FORMAT, rxd4); 647 status->amsdu = !!amsdu_info; 648 if (status->amsdu) { 649 status->first_amsdu = amsdu_info == MT_RXD4_FIRST_AMSDU_FRAME; 650 status->last_amsdu = amsdu_info == MT_RXD4_LAST_AMSDU_FRAME; 651 } 652 653 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad; 654 if (hdr_trans && ieee80211_has_morefrags(fc)) { 655 if (mt7996_reverse_frag0_hdr_trans(skb, hdr_gap)) 656 return -EINVAL; 657 hdr_trans = false; 658 } else { 659 int pad_start = 0; 660 661 skb_pull(skb, hdr_gap); 662 if (!hdr_trans && status->amsdu && !(ieee80211_has_a4(fc) && is_mesh)) { 663 pad_start = ieee80211_get_hdrlen_from_skb(skb); 664 } else if (hdr_trans && (rxd2 & MT_RXD2_NORMAL_HDR_TRANS_ERROR)) { 665 /* When header translation failure is indicated, 666 * the hardware will insert an extra 2-byte field 667 * containing the data length after the protocol 668 * type field. This happens either when the LLC-SNAP 669 * pattern did not match, or if a VLAN header was 670 * detected. 671 */ 672 pad_start = 12; 673 if (get_unaligned_be16(skb->data + pad_start) == ETH_P_8021Q) 674 pad_start += 4; 675 else 676 pad_start = 0; 677 } 678 679 if (pad_start) { 680 memmove(skb->data + 2, skb->data, pad_start); 681 skb_pull(skb, 2); 682 } 683 } 684 685 if (!hdr_trans) { 686 struct ieee80211_hdr *hdr; 687 688 if (insert_ccmp_hdr) { 689 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1); 690 691 mt76_insert_ccmp_hdr(skb, key_id); 692 } 693 694 hdr = mt76_skb_get_hdr(skb); 695 fc = hdr->frame_control; 696 if (ieee80211_is_data_qos(fc)) { 697 u8 *qos = ieee80211_get_qos_ctl(hdr); 698 699 seq_ctrl = le16_to_cpu(hdr->seq_ctrl); 700 qos_ctl = *qos; 701 702 /* Mesh DA/SA/Length will be stripped after hardware 703 * de-amsdu, so here needs to clear amsdu present bit 704 * to mark it as a normal mesh frame. 705 */ 706 if (ieee80211_has_a4(fc) && is_mesh && status->amsdu) 707 *qos &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT; 708 } 709 } else { 710 status->flag |= RX_FLAG_8023; 711 } 712 713 if (rxv && mode >= MT_PHY_TYPE_HE_SU && !(status->flag & RX_FLAG_8023)) 714 mt76_connac3_mac_decode_he_radiotap(skb, rxv, mode); 715 716 if (!status->wcid || !ieee80211_is_data_qos(fc)) 717 return 0; 718 719 status->aggr = unicast && 720 !ieee80211_is_qos_nullfunc(fc); 721 status->qos_ctl = qos_ctl; 722 status->seqno = IEEE80211_SEQ_TO_SN(seq_ctrl); 723 724 return 0; 725 } 726 727 static void 728 mt7996_mac_write_txwi_8023(struct mt7996_dev *dev, __le32 *txwi, 729 struct sk_buff *skb, struct mt76_wcid *wcid) 730 { 731 u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 732 u8 fc_type, fc_stype; 733 u16 ethertype; 734 bool wmm = false; 735 u32 val; 736 737 if (wcid->sta) { 738 struct ieee80211_sta *sta; 739 740 sta = container_of((void *)wcid, struct ieee80211_sta, drv_priv); 741 wmm = sta->wme; 742 } 743 744 val = FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_3) | 745 FIELD_PREP(MT_TXD1_TID, tid); 746 747 ethertype = get_unaligned_be16(&skb->data[12]); 748 if (ethertype >= ETH_P_802_3_MIN) 749 val |= MT_TXD1_ETH_802_3; 750 751 txwi[1] |= cpu_to_le32(val); 752 753 fc_type = IEEE80211_FTYPE_DATA >> 2; 754 fc_stype = wmm ? IEEE80211_STYPE_QOS_DATA >> 4 : 0; 755 756 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) | 757 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype); 758 759 txwi[2] |= cpu_to_le32(val); 760 } 761 762 static void 763 mt7996_mac_write_txwi_80211(struct mt7996_dev *dev, __le32 *txwi, 764 struct sk_buff *skb, struct ieee80211_key_conf *key) 765 { 766 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 767 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 768 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 769 bool multicast = is_multicast_ether_addr(hdr->addr1); 770 u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 771 __le16 fc = hdr->frame_control; 772 u8 fc_type, fc_stype; 773 u32 val; 774 775 if (ieee80211_is_action(fc) && 776 mgmt->u.action.category == WLAN_CATEGORY_BACK && 777 mgmt->u.action.u.addba_req.action_code == WLAN_ACTION_ADDBA_REQ) 778 tid = MT_TX_ADDBA; 779 else if (ieee80211_is_mgmt(hdr->frame_control)) 780 tid = MT_TX_NORMAL; 781 782 val = FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) | 783 FIELD_PREP(MT_TXD1_HDR_INFO, 784 ieee80211_get_hdrlen_from_skb(skb) / 2) | 785 FIELD_PREP(MT_TXD1_TID, tid); 786 787 if (!ieee80211_is_data(fc) || multicast || 788 info->flags & IEEE80211_TX_CTL_USE_MINRATE) 789 val |= MT_TXD1_FIXED_RATE; 790 791 if (key && multicast && ieee80211_is_robust_mgmt_frame(skb) && 792 key->cipher == WLAN_CIPHER_SUITE_AES_CMAC) { 793 val |= MT_TXD1_BIP; 794 txwi[3] &= ~cpu_to_le32(MT_TXD3_PROTECT_FRAME); 795 } 796 797 txwi[1] |= cpu_to_le32(val); 798 799 fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2; 800 fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4; 801 802 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) | 803 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype); 804 805 txwi[2] |= cpu_to_le32(val); 806 807 txwi[3] |= cpu_to_le32(FIELD_PREP(MT_TXD3_BCM, multicast)); 808 if (ieee80211_is_beacon(fc)) { 809 txwi[3] &= ~cpu_to_le32(MT_TXD3_SW_POWER_MGMT); 810 txwi[3] |= cpu_to_le32(MT_TXD3_REM_TX_COUNT); 811 } 812 813 if (info->flags & IEEE80211_TX_CTL_INJECTED) { 814 u16 seqno = le16_to_cpu(hdr->seq_ctrl); 815 816 if (ieee80211_is_back_req(hdr->frame_control)) { 817 struct ieee80211_bar *bar; 818 819 bar = (struct ieee80211_bar *)skb->data; 820 seqno = le16_to_cpu(bar->start_seq_num); 821 } 822 823 val = MT_TXD3_SN_VALID | 824 FIELD_PREP(MT_TXD3_SEQ, IEEE80211_SEQ_TO_SN(seqno)); 825 txwi[3] |= cpu_to_le32(val); 826 txwi[3] &= ~cpu_to_le32(MT_TXD3_HW_AMSDU); 827 } 828 } 829 830 void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi, 831 struct sk_buff *skb, struct mt76_wcid *wcid, 832 struct ieee80211_key_conf *key, int pid, 833 enum mt76_txq_id qid, u32 changed) 834 { 835 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 836 struct ieee80211_vif *vif = info->control.vif; 837 u8 band_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2; 838 u8 p_fmt, q_idx, omac_idx = 0, wmm_idx = 0; 839 bool is_8023 = info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP; 840 struct mt76_vif *mvif; 841 u16 tx_count = 15; 842 u32 val; 843 bool beacon = !!(changed & (BSS_CHANGED_BEACON | 844 BSS_CHANGED_BEACON_ENABLED)); 845 bool inband_disc = !!(changed & (BSS_CHANGED_UNSOL_BCAST_PROBE_RESP | 846 BSS_CHANGED_FILS_DISCOVERY)); 847 848 mvif = vif ? (struct mt76_vif *)vif->drv_priv : NULL; 849 if (mvif) { 850 omac_idx = mvif->omac_idx; 851 wmm_idx = mvif->wmm_idx; 852 band_idx = mvif->band_idx; 853 } 854 855 if (inband_disc) { 856 p_fmt = MT_TX_TYPE_FW; 857 q_idx = MT_LMAC_ALTX0; 858 } else if (beacon) { 859 p_fmt = MT_TX_TYPE_FW; 860 q_idx = MT_LMAC_BCN0; 861 } else if (qid >= MT_TXQ_PSD) { 862 p_fmt = MT_TX_TYPE_CT; 863 q_idx = MT_LMAC_ALTX0; 864 } else { 865 p_fmt = MT_TX_TYPE_CT; 866 q_idx = wmm_idx * MT7996_MAX_WMM_SETS + 867 mt76_connac_lmac_mapping(skb_get_queue_mapping(skb)); 868 } 869 870 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) | 871 FIELD_PREP(MT_TXD0_PKT_FMT, p_fmt) | 872 FIELD_PREP(MT_TXD0_Q_IDX, q_idx); 873 txwi[0] = cpu_to_le32(val); 874 875 val = FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) | 876 FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx); 877 878 if (band_idx) 879 val |= FIELD_PREP(MT_TXD1_TGID, band_idx); 880 881 txwi[1] = cpu_to_le32(val); 882 txwi[2] = 0; 883 884 val = MT_TXD3_SW_POWER_MGMT | 885 FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count); 886 if (key) 887 val |= MT_TXD3_PROTECT_FRAME; 888 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 889 val |= MT_TXD3_NO_ACK; 890 if (wcid->amsdu) 891 val |= MT_TXD3_HW_AMSDU; 892 893 txwi[3] = cpu_to_le32(val); 894 txwi[4] = 0; 895 896 val = FIELD_PREP(MT_TXD5_PID, pid); 897 if (pid >= MT_PACKET_ID_FIRST) 898 val |= MT_TXD5_TX_STATUS_HOST; 899 txwi[5] = cpu_to_le32(val); 900 901 val = MT_TXD6_DIS_MAT | MT_TXD6_DAS | 902 FIELD_PREP(MT_TXD6_MSDU_CNT, 1); 903 txwi[6] = cpu_to_le32(val); 904 txwi[7] = 0; 905 906 if (is_8023) 907 mt7996_mac_write_txwi_8023(dev, txwi, skb, wcid); 908 else 909 mt7996_mac_write_txwi_80211(dev, txwi, skb, key); 910 911 if (txwi[1] & cpu_to_le32(MT_TXD1_FIXED_RATE)) { 912 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 913 bool mcast = ieee80211_is_data(hdr->frame_control) && 914 is_multicast_ether_addr(hdr->addr1); 915 u8 idx = MT7996_BASIC_RATES_TBL; 916 917 if (mvif) { 918 if (mcast && mvif->mcast_rates_idx) 919 idx = mvif->mcast_rates_idx; 920 else if (beacon && mvif->beacon_rates_idx) 921 idx = mvif->beacon_rates_idx; 922 else 923 idx = mvif->basic_rates_idx; 924 } 925 926 txwi[6] |= cpu_to_le32(FIELD_PREP(MT_TXD6_TX_RATE, idx)); 927 txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE); 928 } 929 } 930 931 int mt7996_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, 932 enum mt76_txq_id qid, struct mt76_wcid *wcid, 933 struct ieee80211_sta *sta, 934 struct mt76_tx_info *tx_info) 935 { 936 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_info->skb->data; 937 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 938 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb); 939 struct ieee80211_key_conf *key = info->control.hw_key; 940 struct ieee80211_vif *vif = info->control.vif; 941 struct mt76_connac_txp_common *txp; 942 struct mt76_txwi_cache *t; 943 int id, i, pid, nbuf = tx_info->nbuf - 1; 944 bool is_8023 = info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP; 945 u8 *txwi = (u8 *)txwi_ptr; 946 947 if (unlikely(tx_info->skb->len <= ETH_HLEN)) 948 return -EINVAL; 949 950 if (!wcid) 951 wcid = &dev->mt76.global_wcid; 952 953 t = (struct mt76_txwi_cache *)(txwi + mdev->drv->txwi_size); 954 t->skb = tx_info->skb; 955 956 id = mt76_token_consume(mdev, &t); 957 if (id < 0) 958 return id; 959 960 pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb); 961 mt7996_mac_write_txwi(dev, txwi_ptr, tx_info->skb, wcid, key, 962 pid, qid, 0); 963 964 txp = (struct mt76_connac_txp_common *)(txwi + MT_TXD_SIZE); 965 for (i = 0; i < nbuf; i++) { 966 txp->fw.buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr); 967 txp->fw.len[i] = cpu_to_le16(tx_info->buf[i + 1].len); 968 } 969 txp->fw.nbuf = nbuf; 970 971 txp->fw.flags = 972 cpu_to_le16(MT_CT_INFO_FROM_HOST | MT_CT_INFO_APPLY_TXD); 973 974 if (!key) 975 txp->fw.flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME); 976 977 if (!is_8023 && ieee80211_is_mgmt(hdr->frame_control)) 978 txp->fw.flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME); 979 980 if (vif) { 981 struct mt7996_vif *mvif = (struct mt7996_vif *)vif->drv_priv; 982 983 txp->fw.bss_idx = mvif->mt76.idx; 984 } 985 986 txp->fw.token = cpu_to_le16(id); 987 txp->fw.rept_wds_wcid = cpu_to_le16(sta ? wcid->idx : 0xfff); 988 989 tx_info->skb = NULL; 990 991 /* pass partial skb header to fw */ 992 tx_info->buf[1].len = MT_CT_PARSE_LEN; 993 tx_info->buf[1].skip_unmap = true; 994 tx_info->nbuf = MT_CT_DMA_BUF_NUM; 995 996 return 0; 997 } 998 999 static void 1000 mt7996_tx_check_aggr(struct ieee80211_sta *sta, struct sk_buff *skb) 1001 { 1002 struct mt7996_sta *msta; 1003 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1004 bool is_8023 = info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP; 1005 u16 fc, tid; 1006 1007 if (!sta || !(sta->deflink.ht_cap.ht_supported || sta->deflink.he_cap.has_he)) 1008 return; 1009 1010 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 1011 if (tid >= 6) /* skip VO queue */ 1012 return; 1013 1014 if (is_8023) { 1015 fc = IEEE80211_FTYPE_DATA | 1016 (sta->wme ? IEEE80211_STYPE_QOS_DATA : IEEE80211_STYPE_DATA); 1017 } else { 1018 /* No need to get precise TID for Action/Management Frame, 1019 * since it will not meet the following Frame Control 1020 * condition anyway. 1021 */ 1022 1023 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1024 1025 fc = le16_to_cpu(hdr->frame_control) & 1026 (IEEE80211_FCTL_FTYPE | IEEE80211_FCTL_STYPE); 1027 } 1028 1029 if (unlikely(fc != (IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_DATA))) 1030 return; 1031 1032 msta = (struct mt7996_sta *)sta->drv_priv; 1033 if (!test_and_set_bit(tid, &msta->wcid.ampdu_state)) 1034 ieee80211_start_tx_ba_session(sta, tid, 0); 1035 } 1036 1037 static void 1038 mt7996_txwi_free(struct mt7996_dev *dev, struct mt76_txwi_cache *t, 1039 struct ieee80211_sta *sta, struct list_head *free_list) 1040 { 1041 struct mt76_dev *mdev = &dev->mt76; 1042 struct mt76_wcid *wcid; 1043 __le32 *txwi; 1044 u16 wcid_idx; 1045 1046 mt76_connac_txp_skb_unmap(mdev, t); 1047 if (!t->skb) 1048 goto out; 1049 1050 txwi = (__le32 *)mt76_get_txwi_ptr(mdev, t); 1051 if (sta) { 1052 wcid = (struct mt76_wcid *)sta->drv_priv; 1053 wcid_idx = wcid->idx; 1054 1055 if (likely(t->skb->protocol != cpu_to_be16(ETH_P_PAE))) 1056 mt7996_tx_check_aggr(sta, t->skb); 1057 } else { 1058 wcid_idx = le32_get_bits(txwi[9], MT_TXD9_WLAN_IDX); 1059 } 1060 1061 __mt76_tx_complete_skb(mdev, wcid_idx, t->skb, free_list); 1062 1063 out: 1064 t->skb = NULL; 1065 mt76_put_txwi(mdev, t); 1066 } 1067 1068 static void 1069 mt7996_mac_tx_free(struct mt7996_dev *dev, void *data, int len) 1070 { 1071 __le32 *tx_free = (__le32 *)data, *cur_info; 1072 struct mt76_dev *mdev = &dev->mt76; 1073 struct mt76_phy *phy2 = mdev->phys[MT_BAND1]; 1074 struct mt76_phy *phy3 = mdev->phys[MT_BAND2]; 1075 struct mt76_txwi_cache *txwi; 1076 struct ieee80211_sta *sta = NULL; 1077 struct mt76_wcid *wcid; 1078 LIST_HEAD(free_list); 1079 struct sk_buff *skb, *tmp; 1080 void *end = data + len; 1081 bool wake = false; 1082 u16 total, count = 0; 1083 1084 /* clean DMA queues and unmap buffers first */ 1085 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false); 1086 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false); 1087 if (phy2) { 1088 mt76_queue_tx_cleanup(dev, phy2->q_tx[MT_TXQ_PSD], false); 1089 mt76_queue_tx_cleanup(dev, phy2->q_tx[MT_TXQ_BE], false); 1090 } 1091 if (phy3) { 1092 mt76_queue_tx_cleanup(dev, phy3->q_tx[MT_TXQ_PSD], false); 1093 mt76_queue_tx_cleanup(dev, phy3->q_tx[MT_TXQ_BE], false); 1094 } 1095 1096 if (WARN_ON_ONCE(le32_get_bits(tx_free[1], MT_TXFREE1_VER) < 5)) 1097 return; 1098 1099 total = le32_get_bits(tx_free[0], MT_TXFREE0_MSDU_CNT); 1100 for (cur_info = &tx_free[2]; count < total; cur_info++) { 1101 u32 msdu, info; 1102 u8 i; 1103 1104 if (WARN_ON_ONCE((void *)cur_info >= end)) 1105 return; 1106 /* 1'b1: new wcid pair. 1107 * 1'b0: msdu_id with the same 'wcid pair' as above. 1108 */ 1109 info = le32_to_cpu(*cur_info); 1110 if (info & MT_TXFREE_INFO_PAIR) { 1111 struct mt7996_sta *msta; 1112 u16 idx; 1113 1114 idx = FIELD_GET(MT_TXFREE_INFO_WLAN_ID, info); 1115 wcid = rcu_dereference(dev->mt76.wcid[idx]); 1116 sta = wcid_to_sta(wcid); 1117 if (!sta) 1118 continue; 1119 1120 msta = container_of(wcid, struct mt7996_sta, wcid); 1121 spin_lock_bh(&mdev->sta_poll_lock); 1122 if (list_empty(&msta->wcid.poll_list)) 1123 list_add_tail(&msta->wcid.poll_list, 1124 &mdev->sta_poll_list); 1125 spin_unlock_bh(&mdev->sta_poll_lock); 1126 continue; 1127 } else if (info & MT_TXFREE_INFO_HEADER) { 1128 u32 tx_retries = 0, tx_failed = 0; 1129 1130 if (!wcid) 1131 continue; 1132 1133 tx_retries = 1134 FIELD_GET(MT_TXFREE_INFO_COUNT, info) - 1; 1135 tx_failed = tx_retries + 1136 !!FIELD_GET(MT_TXFREE_INFO_STAT, info); 1137 1138 wcid->stats.tx_retries += tx_retries; 1139 wcid->stats.tx_failed += tx_failed; 1140 continue; 1141 } 1142 1143 for (i = 0; i < 2; i++) { 1144 msdu = (info >> (15 * i)) & MT_TXFREE_INFO_MSDU_ID; 1145 if (msdu == MT_TXFREE_INFO_MSDU_ID) 1146 continue; 1147 1148 count++; 1149 txwi = mt76_token_release(mdev, msdu, &wake); 1150 if (!txwi) 1151 continue; 1152 1153 mt7996_txwi_free(dev, txwi, sta, &free_list); 1154 } 1155 } 1156 1157 mt7996_mac_sta_poll(dev); 1158 1159 if (wake) 1160 mt76_set_tx_blocked(&dev->mt76, false); 1161 1162 mt76_worker_schedule(&dev->mt76.tx_worker); 1163 1164 list_for_each_entry_safe(skb, tmp, &free_list, list) { 1165 skb_list_del_init(skb); 1166 napi_consume_skb(skb, 1); 1167 } 1168 } 1169 1170 static bool 1171 mt7996_mac_add_txs_skb(struct mt7996_dev *dev, struct mt76_wcid *wcid, 1172 int pid, __le32 *txs_data) 1173 { 1174 struct mt76_sta_stats *stats = &wcid->stats; 1175 struct ieee80211_supported_band *sband; 1176 struct mt76_dev *mdev = &dev->mt76; 1177 struct mt76_phy *mphy; 1178 struct ieee80211_tx_info *info; 1179 struct sk_buff_head list; 1180 struct rate_info rate = {}; 1181 struct sk_buff *skb; 1182 bool cck = false; 1183 u32 txrate, txs, mode, stbc; 1184 1185 txs = le32_to_cpu(txs_data[0]); 1186 1187 mt76_tx_status_lock(mdev, &list); 1188 skb = mt76_tx_status_skb_get(mdev, wcid, pid, &list); 1189 1190 if (skb) { 1191 info = IEEE80211_SKB_CB(skb); 1192 if (!(txs & MT_TXS0_ACK_ERROR_MASK)) 1193 info->flags |= IEEE80211_TX_STAT_ACK; 1194 1195 info->status.ampdu_len = 1; 1196 info->status.ampdu_ack_len = 1197 !!(info->flags & IEEE80211_TX_STAT_ACK); 1198 1199 info->status.rates[0].idx = -1; 1200 } 1201 1202 if (mtk_wed_device_active(&dev->mt76.mmio.wed) && wcid->sta) { 1203 struct ieee80211_sta *sta; 1204 u8 tid; 1205 1206 sta = container_of((void *)wcid, struct ieee80211_sta, drv_priv); 1207 tid = FIELD_GET(MT_TXS0_TID, txs); 1208 ieee80211_refresh_tx_agg_session_timer(sta, tid); 1209 } 1210 1211 txrate = FIELD_GET(MT_TXS0_TX_RATE, txs); 1212 1213 rate.mcs = FIELD_GET(MT_TX_RATE_IDX, txrate); 1214 rate.nss = FIELD_GET(MT_TX_RATE_NSS, txrate) + 1; 1215 stbc = le32_get_bits(txs_data[3], MT_TXS3_RATE_STBC); 1216 1217 if (stbc && rate.nss > 1) 1218 rate.nss >>= 1; 1219 1220 if (rate.nss - 1 < ARRAY_SIZE(stats->tx_nss)) 1221 stats->tx_nss[rate.nss - 1]++; 1222 if (rate.mcs < ARRAY_SIZE(stats->tx_mcs)) 1223 stats->tx_mcs[rate.mcs]++; 1224 1225 mode = FIELD_GET(MT_TX_RATE_MODE, txrate); 1226 switch (mode) { 1227 case MT_PHY_TYPE_CCK: 1228 cck = true; 1229 fallthrough; 1230 case MT_PHY_TYPE_OFDM: 1231 mphy = mt76_dev_phy(mdev, wcid->phy_idx); 1232 1233 if (mphy->chandef.chan->band == NL80211_BAND_5GHZ) 1234 sband = &mphy->sband_5g.sband; 1235 else if (mphy->chandef.chan->band == NL80211_BAND_6GHZ) 1236 sband = &mphy->sband_6g.sband; 1237 else 1238 sband = &mphy->sband_2g.sband; 1239 1240 rate.mcs = mt76_get_rate(mphy->dev, sband, rate.mcs, cck); 1241 rate.legacy = sband->bitrates[rate.mcs].bitrate; 1242 break; 1243 case MT_PHY_TYPE_HT: 1244 case MT_PHY_TYPE_HT_GF: 1245 if (rate.mcs > 31) 1246 goto out; 1247 1248 rate.flags = RATE_INFO_FLAGS_MCS; 1249 if (wcid->rate.flags & RATE_INFO_FLAGS_SHORT_GI) 1250 rate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1251 break; 1252 case MT_PHY_TYPE_VHT: 1253 if (rate.mcs > 9) 1254 goto out; 1255 1256 rate.flags = RATE_INFO_FLAGS_VHT_MCS; 1257 break; 1258 case MT_PHY_TYPE_HE_SU: 1259 case MT_PHY_TYPE_HE_EXT_SU: 1260 case MT_PHY_TYPE_HE_TB: 1261 case MT_PHY_TYPE_HE_MU: 1262 if (rate.mcs > 11) 1263 goto out; 1264 1265 rate.he_gi = wcid->rate.he_gi; 1266 rate.he_dcm = FIELD_GET(MT_TX_RATE_DCM, txrate); 1267 rate.flags = RATE_INFO_FLAGS_HE_MCS; 1268 break; 1269 case MT_PHY_TYPE_EHT_SU: 1270 case MT_PHY_TYPE_EHT_TRIG: 1271 case MT_PHY_TYPE_EHT_MU: 1272 if (rate.mcs > 13) 1273 goto out; 1274 1275 rate.eht_gi = wcid->rate.eht_gi; 1276 rate.flags = RATE_INFO_FLAGS_EHT_MCS; 1277 break; 1278 default: 1279 goto out; 1280 } 1281 1282 stats->tx_mode[mode]++; 1283 1284 switch (FIELD_GET(MT_TXS0_BW, txs)) { 1285 case IEEE80211_STA_RX_BW_320: 1286 rate.bw = RATE_INFO_BW_320; 1287 stats->tx_bw[4]++; 1288 break; 1289 case IEEE80211_STA_RX_BW_160: 1290 rate.bw = RATE_INFO_BW_160; 1291 stats->tx_bw[3]++; 1292 break; 1293 case IEEE80211_STA_RX_BW_80: 1294 rate.bw = RATE_INFO_BW_80; 1295 stats->tx_bw[2]++; 1296 break; 1297 case IEEE80211_STA_RX_BW_40: 1298 rate.bw = RATE_INFO_BW_40; 1299 stats->tx_bw[1]++; 1300 break; 1301 default: 1302 rate.bw = RATE_INFO_BW_20; 1303 stats->tx_bw[0]++; 1304 break; 1305 } 1306 wcid->rate = rate; 1307 1308 out: 1309 if (skb) 1310 mt76_tx_status_skb_done(mdev, skb, &list); 1311 mt76_tx_status_unlock(mdev, &list); 1312 1313 return !!skb; 1314 } 1315 1316 static void mt7996_mac_add_txs(struct mt7996_dev *dev, void *data) 1317 { 1318 struct mt7996_sta *msta = NULL; 1319 struct mt76_wcid *wcid; 1320 __le32 *txs_data = data; 1321 u16 wcidx; 1322 u8 pid; 1323 1324 wcidx = le32_get_bits(txs_data[2], MT_TXS2_WCID); 1325 pid = le32_get_bits(txs_data[3], MT_TXS3_PID); 1326 1327 if (pid < MT_PACKET_ID_NO_SKB) 1328 return; 1329 1330 if (wcidx >= mt7996_wtbl_size(dev)) 1331 return; 1332 1333 rcu_read_lock(); 1334 1335 wcid = rcu_dereference(dev->mt76.wcid[wcidx]); 1336 if (!wcid) 1337 goto out; 1338 1339 msta = container_of(wcid, struct mt7996_sta, wcid); 1340 1341 mt7996_mac_add_txs_skb(dev, wcid, pid, txs_data); 1342 1343 if (!wcid->sta) 1344 goto out; 1345 1346 spin_lock_bh(&dev->mt76.sta_poll_lock); 1347 if (list_empty(&msta->wcid.poll_list)) 1348 list_add_tail(&msta->wcid.poll_list, &dev->mt76.sta_poll_list); 1349 spin_unlock_bh(&dev->mt76.sta_poll_lock); 1350 1351 out: 1352 rcu_read_unlock(); 1353 } 1354 1355 bool mt7996_rx_check(struct mt76_dev *mdev, void *data, int len) 1356 { 1357 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 1358 __le32 *rxd = (__le32 *)data; 1359 __le32 *end = (__le32 *)&rxd[len / 4]; 1360 enum rx_pkt_type type; 1361 1362 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); 1363 if (type != PKT_TYPE_NORMAL) { 1364 u32 sw_type = le32_get_bits(rxd[0], MT_RXD0_SW_PKT_TYPE_MASK); 1365 1366 if (unlikely((sw_type & MT_RXD0_SW_PKT_TYPE_MAP) == 1367 MT_RXD0_SW_PKT_TYPE_FRAME)) 1368 return true; 1369 } 1370 1371 switch (type) { 1372 case PKT_TYPE_TXRX_NOTIFY: 1373 mt7996_mac_tx_free(dev, data, len); 1374 return false; 1375 case PKT_TYPE_TXS: 1376 for (rxd += 4; rxd + 8 <= end; rxd += 8) 1377 mt7996_mac_add_txs(dev, rxd); 1378 return false; 1379 case PKT_TYPE_RX_FW_MONITOR: 1380 mt7996_debugfs_rx_fw_monitor(dev, data, len); 1381 return false; 1382 default: 1383 return true; 1384 } 1385 } 1386 1387 void mt7996_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 1388 struct sk_buff *skb, u32 *info) 1389 { 1390 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 1391 __le32 *rxd = (__le32 *)skb->data; 1392 __le32 *end = (__le32 *)&skb->data[skb->len]; 1393 enum rx_pkt_type type; 1394 1395 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); 1396 if (type != PKT_TYPE_NORMAL) { 1397 u32 sw_type = le32_get_bits(rxd[0], MT_RXD0_SW_PKT_TYPE_MASK); 1398 1399 if (unlikely((sw_type & MT_RXD0_SW_PKT_TYPE_MAP) == 1400 MT_RXD0_SW_PKT_TYPE_FRAME)) 1401 type = PKT_TYPE_NORMAL; 1402 } 1403 1404 switch (type) { 1405 case PKT_TYPE_TXRX_NOTIFY: 1406 mt7996_mac_tx_free(dev, skb->data, skb->len); 1407 napi_consume_skb(skb, 1); 1408 break; 1409 case PKT_TYPE_RX_EVENT: 1410 mt7996_mcu_rx_event(dev, skb); 1411 break; 1412 case PKT_TYPE_TXS: 1413 for (rxd += 4; rxd + 8 <= end; rxd += 8) 1414 mt7996_mac_add_txs(dev, rxd); 1415 dev_kfree_skb(skb); 1416 break; 1417 case PKT_TYPE_RX_FW_MONITOR: 1418 mt7996_debugfs_rx_fw_monitor(dev, skb->data, skb->len); 1419 dev_kfree_skb(skb); 1420 break; 1421 case PKT_TYPE_NORMAL: 1422 if (!mt7996_mac_fill_rx(dev, skb)) { 1423 mt76_rx(&dev->mt76, q, skb); 1424 return; 1425 } 1426 fallthrough; 1427 default: 1428 dev_kfree_skb(skb); 1429 break; 1430 } 1431 } 1432 1433 void mt7996_mac_cca_stats_reset(struct mt7996_phy *phy) 1434 { 1435 struct mt7996_dev *dev = phy->dev; 1436 u32 reg = MT_WF_PHYRX_BAND_RX_CTRL1(phy->mt76->band_idx); 1437 1438 mt76_clear(dev, reg, MT_WF_PHYRX_BAND_RX_CTRL1_STSCNT_EN); 1439 mt76_set(dev, reg, BIT(11) | BIT(9)); 1440 } 1441 1442 void mt7996_mac_reset_counters(struct mt7996_phy *phy) 1443 { 1444 struct mt7996_dev *dev = phy->dev; 1445 u8 band_idx = phy->mt76->band_idx; 1446 int i; 1447 1448 for (i = 0; i < 16; i++) 1449 mt76_rr(dev, MT_TX_AGG_CNT(band_idx, i)); 1450 1451 phy->mt76->survey_time = ktime_get_boottime(); 1452 1453 memset(phy->mt76->aggr_stats, 0, sizeof(phy->mt76->aggr_stats)); 1454 1455 /* reset airtime counters */ 1456 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(band_idx), 1457 MT_WF_RMAC_MIB_RXTIME_CLR); 1458 1459 mt7996_mcu_get_chan_mib_info(phy, true); 1460 } 1461 1462 void mt7996_mac_set_coverage_class(struct mt7996_phy *phy) 1463 { 1464 s16 coverage_class = phy->coverage_class; 1465 struct mt7996_dev *dev = phy->dev; 1466 struct mt7996_phy *phy2 = mt7996_phy2(dev); 1467 struct mt7996_phy *phy3 = mt7996_phy3(dev); 1468 u32 reg_offset; 1469 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | 1470 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); 1471 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | 1472 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28); 1473 u8 band_idx = phy->mt76->band_idx; 1474 int offset; 1475 1476 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state)) 1477 return; 1478 1479 if (phy2) 1480 coverage_class = max_t(s16, dev->phy.coverage_class, 1481 phy2->coverage_class); 1482 1483 if (phy3) 1484 coverage_class = max_t(s16, coverage_class, 1485 phy3->coverage_class); 1486 1487 offset = 3 * coverage_class; 1488 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | 1489 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); 1490 1491 mt76_wr(dev, MT_TMAC_CDTR(band_idx), cck + reg_offset); 1492 mt76_wr(dev, MT_TMAC_ODTR(band_idx), ofdm + reg_offset); 1493 } 1494 1495 void mt7996_mac_enable_nf(struct mt7996_dev *dev, u8 band) 1496 { 1497 mt76_set(dev, MT_WF_PHYRX_CSD_BAND_RXTD12(band), 1498 MT_WF_PHYRX_CSD_BAND_RXTD12_IRPI_SW_CLR_ONLY | 1499 MT_WF_PHYRX_CSD_BAND_RXTD12_IRPI_SW_CLR); 1500 1501 mt76_set(dev, MT_WF_PHYRX_BAND_RX_CTRL1(band), 1502 FIELD_PREP(MT_WF_PHYRX_BAND_RX_CTRL1_IPI_EN, 0x5)); 1503 } 1504 1505 static u8 1506 mt7996_phy_get_nf(struct mt7996_phy *phy, u8 band_idx) 1507 { 1508 static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 }; 1509 struct mt7996_dev *dev = phy->dev; 1510 u32 val, sum = 0, n = 0; 1511 int ant, i; 1512 1513 for (ant = 0; ant < hweight8(phy->mt76->antenna_mask); ant++) { 1514 u32 reg = MT_WF_PHYRX_CSD_IRPI(band_idx, ant); 1515 1516 for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) { 1517 val = mt76_rr(dev, reg); 1518 sum += val * nf_power[i]; 1519 n += val; 1520 } 1521 } 1522 1523 return n ? sum / n : 0; 1524 } 1525 1526 void mt7996_update_channel(struct mt76_phy *mphy) 1527 { 1528 struct mt7996_phy *phy = (struct mt7996_phy *)mphy->priv; 1529 struct mt76_channel_state *state = mphy->chan_state; 1530 int nf; 1531 1532 mt7996_mcu_get_chan_mib_info(phy, false); 1533 1534 nf = mt7996_phy_get_nf(phy, mphy->band_idx); 1535 if (!phy->noise) 1536 phy->noise = nf << 4; 1537 else if (nf) 1538 phy->noise += nf - (phy->noise >> 4); 1539 1540 state->noise = -(phy->noise >> 4); 1541 } 1542 1543 static bool 1544 mt7996_wait_reset_state(struct mt7996_dev *dev, u32 state) 1545 { 1546 bool ret; 1547 1548 ret = wait_event_timeout(dev->reset_wait, 1549 (READ_ONCE(dev->recovery.state) & state), 1550 MT7996_RESET_TIMEOUT); 1551 1552 WARN(!ret, "Timeout waiting for MCU reset state %x\n", state); 1553 return ret; 1554 } 1555 1556 static void 1557 mt7996_update_vif_beacon(void *priv, u8 *mac, struct ieee80211_vif *vif) 1558 { 1559 struct ieee80211_hw *hw = priv; 1560 1561 switch (vif->type) { 1562 case NL80211_IFTYPE_MESH_POINT: 1563 case NL80211_IFTYPE_ADHOC: 1564 case NL80211_IFTYPE_AP: 1565 mt7996_mcu_add_beacon(hw, vif, vif->bss_conf.enable_beacon); 1566 break; 1567 default: 1568 break; 1569 } 1570 } 1571 1572 static void 1573 mt7996_update_beacons(struct mt7996_dev *dev) 1574 { 1575 struct mt76_phy *phy2, *phy3; 1576 1577 ieee80211_iterate_active_interfaces(dev->mt76.hw, 1578 IEEE80211_IFACE_ITER_RESUME_ALL, 1579 mt7996_update_vif_beacon, dev->mt76.hw); 1580 1581 phy2 = dev->mt76.phys[MT_BAND1]; 1582 if (!phy2) 1583 return; 1584 1585 ieee80211_iterate_active_interfaces(phy2->hw, 1586 IEEE80211_IFACE_ITER_RESUME_ALL, 1587 mt7996_update_vif_beacon, phy2->hw); 1588 1589 phy3 = dev->mt76.phys[MT_BAND2]; 1590 if (!phy3) 1591 return; 1592 1593 ieee80211_iterate_active_interfaces(phy3->hw, 1594 IEEE80211_IFACE_ITER_RESUME_ALL, 1595 mt7996_update_vif_beacon, phy3->hw); 1596 } 1597 1598 void mt7996_tx_token_put(struct mt7996_dev *dev) 1599 { 1600 struct mt76_txwi_cache *txwi; 1601 int id; 1602 1603 spin_lock_bh(&dev->mt76.token_lock); 1604 idr_for_each_entry(&dev->mt76.token, txwi, id) { 1605 mt7996_txwi_free(dev, txwi, NULL, NULL); 1606 dev->mt76.token_count--; 1607 } 1608 spin_unlock_bh(&dev->mt76.token_lock); 1609 idr_destroy(&dev->mt76.token); 1610 } 1611 1612 static int 1613 mt7996_mac_restart(struct mt7996_dev *dev) 1614 { 1615 struct mt7996_phy *phy2, *phy3; 1616 struct mt76_dev *mdev = &dev->mt76; 1617 int i, ret; 1618 1619 phy2 = mt7996_phy2(dev); 1620 phy3 = mt7996_phy3(dev); 1621 1622 if (dev->hif2) { 1623 mt76_wr(dev, MT_INT1_MASK_CSR, 0x0); 1624 mt76_wr(dev, MT_INT1_SOURCE_CSR, ~0); 1625 } 1626 1627 if (dev_is_pci(mdev->dev)) { 1628 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0); 1629 if (dev->hif2) 1630 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE, 0x0); 1631 } 1632 1633 set_bit(MT76_RESET, &dev->mphy.state); 1634 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1635 wake_up(&dev->mt76.mcu.wait); 1636 if (phy2) { 1637 set_bit(MT76_RESET, &phy2->mt76->state); 1638 set_bit(MT76_MCU_RESET, &phy2->mt76->state); 1639 } 1640 if (phy3) { 1641 set_bit(MT76_RESET, &phy3->mt76->state); 1642 set_bit(MT76_MCU_RESET, &phy3->mt76->state); 1643 } 1644 1645 /* lock/unlock all queues to ensure that no tx is pending */ 1646 mt76_txq_schedule_all(&dev->mphy); 1647 if (phy2) 1648 mt76_txq_schedule_all(phy2->mt76); 1649 if (phy3) 1650 mt76_txq_schedule_all(phy3->mt76); 1651 1652 /* disable all tx/rx napi */ 1653 mt76_worker_disable(&dev->mt76.tx_worker); 1654 mt76_for_each_q_rx(mdev, i) { 1655 if (mdev->q_rx[i].ndesc) 1656 napi_disable(&dev->mt76.napi[i]); 1657 } 1658 napi_disable(&dev->mt76.tx_napi); 1659 1660 /* token reinit */ 1661 mt7996_tx_token_put(dev); 1662 idr_init(&dev->mt76.token); 1663 1664 mt7996_dma_reset(dev, true); 1665 1666 local_bh_disable(); 1667 mt76_for_each_q_rx(mdev, i) { 1668 if (mdev->q_rx[i].ndesc) { 1669 napi_enable(&dev->mt76.napi[i]); 1670 napi_schedule(&dev->mt76.napi[i]); 1671 } 1672 } 1673 local_bh_enable(); 1674 clear_bit(MT76_MCU_RESET, &dev->mphy.state); 1675 clear_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state); 1676 1677 mt76_wr(dev, MT_INT_MASK_CSR, dev->mt76.mmio.irqmask); 1678 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 1679 if (dev->hif2) { 1680 mt76_wr(dev, MT_INT1_MASK_CSR, dev->mt76.mmio.irqmask); 1681 mt76_wr(dev, MT_INT1_SOURCE_CSR, ~0); 1682 } 1683 if (dev_is_pci(mdev->dev)) { 1684 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff); 1685 if (dev->hif2) 1686 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE, 0xff); 1687 } 1688 1689 /* load firmware */ 1690 ret = mt7996_mcu_init_firmware(dev); 1691 if (ret) 1692 goto out; 1693 1694 /* set the necessary init items */ 1695 ret = mt7996_mcu_set_eeprom(dev); 1696 if (ret) 1697 goto out; 1698 1699 mt7996_mac_init(dev); 1700 mt7996_init_txpower(dev, &dev->mphy.sband_2g.sband); 1701 mt7996_init_txpower(dev, &dev->mphy.sband_5g.sband); 1702 mt7996_init_txpower(dev, &dev->mphy.sband_6g.sband); 1703 ret = mt7996_txbf_init(dev); 1704 1705 if (test_bit(MT76_STATE_RUNNING, &dev->mphy.state)) { 1706 ret = mt7996_run(dev->mphy.hw); 1707 if (ret) 1708 goto out; 1709 } 1710 1711 if (phy2 && test_bit(MT76_STATE_RUNNING, &phy2->mt76->state)) { 1712 ret = mt7996_run(phy2->mt76->hw); 1713 if (ret) 1714 goto out; 1715 } 1716 1717 if (phy3 && test_bit(MT76_STATE_RUNNING, &phy3->mt76->state)) { 1718 ret = mt7996_run(phy3->mt76->hw); 1719 if (ret) 1720 goto out; 1721 } 1722 1723 out: 1724 /* reset done */ 1725 clear_bit(MT76_RESET, &dev->mphy.state); 1726 if (phy2) 1727 clear_bit(MT76_RESET, &phy2->mt76->state); 1728 if (phy3) 1729 clear_bit(MT76_RESET, &phy3->mt76->state); 1730 1731 local_bh_disable(); 1732 napi_enable(&dev->mt76.tx_napi); 1733 napi_schedule(&dev->mt76.tx_napi); 1734 local_bh_enable(); 1735 1736 mt76_worker_enable(&dev->mt76.tx_worker); 1737 return ret; 1738 } 1739 1740 static void 1741 mt7996_mac_full_reset(struct mt7996_dev *dev) 1742 { 1743 struct mt7996_phy *phy2, *phy3; 1744 int i; 1745 1746 phy2 = mt7996_phy2(dev); 1747 phy3 = mt7996_phy3(dev); 1748 dev->recovery.hw_full_reset = true; 1749 1750 wake_up(&dev->mt76.mcu.wait); 1751 ieee80211_stop_queues(mt76_hw(dev)); 1752 if (phy2) 1753 ieee80211_stop_queues(phy2->mt76->hw); 1754 if (phy3) 1755 ieee80211_stop_queues(phy3->mt76->hw); 1756 1757 cancel_delayed_work_sync(&dev->mphy.mac_work); 1758 if (phy2) 1759 cancel_delayed_work_sync(&phy2->mt76->mac_work); 1760 if (phy3) 1761 cancel_delayed_work_sync(&phy3->mt76->mac_work); 1762 1763 mutex_lock(&dev->mt76.mutex); 1764 for (i = 0; i < 10; i++) { 1765 if (!mt7996_mac_restart(dev)) 1766 break; 1767 } 1768 mutex_unlock(&dev->mt76.mutex); 1769 1770 if (i == 10) 1771 dev_err(dev->mt76.dev, "chip full reset failed\n"); 1772 1773 ieee80211_restart_hw(mt76_hw(dev)); 1774 if (phy2) 1775 ieee80211_restart_hw(phy2->mt76->hw); 1776 if (phy3) 1777 ieee80211_restart_hw(phy3->mt76->hw); 1778 1779 ieee80211_wake_queues(mt76_hw(dev)); 1780 if (phy2) 1781 ieee80211_wake_queues(phy2->mt76->hw); 1782 if (phy3) 1783 ieee80211_wake_queues(phy3->mt76->hw); 1784 1785 dev->recovery.hw_full_reset = false; 1786 ieee80211_queue_delayed_work(mt76_hw(dev), 1787 &dev->mphy.mac_work, 1788 MT7996_WATCHDOG_TIME); 1789 if (phy2) 1790 ieee80211_queue_delayed_work(phy2->mt76->hw, 1791 &phy2->mt76->mac_work, 1792 MT7996_WATCHDOG_TIME); 1793 if (phy3) 1794 ieee80211_queue_delayed_work(phy3->mt76->hw, 1795 &phy3->mt76->mac_work, 1796 MT7996_WATCHDOG_TIME); 1797 } 1798 1799 void mt7996_mac_reset_work(struct work_struct *work) 1800 { 1801 struct mt7996_phy *phy2, *phy3; 1802 struct mt7996_dev *dev; 1803 int i; 1804 1805 dev = container_of(work, struct mt7996_dev, reset_work); 1806 phy2 = mt7996_phy2(dev); 1807 phy3 = mt7996_phy3(dev); 1808 1809 /* chip full reset */ 1810 if (dev->recovery.restart) { 1811 /* disable WA/WM WDT */ 1812 mt76_clear(dev, MT_WFDMA0_MCU_HOST_INT_ENA, 1813 MT_MCU_CMD_WDT_MASK); 1814 1815 if (READ_ONCE(dev->recovery.state) & MT_MCU_CMD_WA_WDT) 1816 dev->recovery.wa_reset_count++; 1817 else 1818 dev->recovery.wm_reset_count++; 1819 1820 mt7996_mac_full_reset(dev); 1821 1822 /* enable mcu irq */ 1823 mt7996_irq_enable(dev, MT_INT_MCU_CMD); 1824 mt7996_irq_disable(dev, 0); 1825 1826 /* enable WA/WM WDT */ 1827 mt76_set(dev, MT_WFDMA0_MCU_HOST_INT_ENA, MT_MCU_CMD_WDT_MASK); 1828 1829 dev->recovery.state = MT_MCU_CMD_NORMAL_STATE; 1830 dev->recovery.restart = false; 1831 return; 1832 } 1833 1834 if (!(READ_ONCE(dev->recovery.state) & MT_MCU_CMD_STOP_DMA)) 1835 return; 1836 1837 dev_info(dev->mt76.dev,"\n%s L1 SER recovery start.", 1838 wiphy_name(dev->mt76.hw->wiphy)); 1839 ieee80211_stop_queues(mt76_hw(dev)); 1840 if (phy2) 1841 ieee80211_stop_queues(phy2->mt76->hw); 1842 if (phy3) 1843 ieee80211_stop_queues(phy3->mt76->hw); 1844 1845 set_bit(MT76_RESET, &dev->mphy.state); 1846 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1847 wake_up(&dev->mt76.mcu.wait); 1848 cancel_delayed_work_sync(&dev->mphy.mac_work); 1849 if (phy2) { 1850 set_bit(MT76_RESET, &phy2->mt76->state); 1851 cancel_delayed_work_sync(&phy2->mt76->mac_work); 1852 } 1853 if (phy3) { 1854 set_bit(MT76_RESET, &phy3->mt76->state); 1855 cancel_delayed_work_sync(&phy3->mt76->mac_work); 1856 } 1857 mt76_worker_disable(&dev->mt76.tx_worker); 1858 mt76_for_each_q_rx(&dev->mt76, i) 1859 napi_disable(&dev->mt76.napi[i]); 1860 napi_disable(&dev->mt76.tx_napi); 1861 1862 mutex_lock(&dev->mt76.mutex); 1863 1864 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_STOPPED); 1865 1866 if (mt7996_wait_reset_state(dev, MT_MCU_CMD_RESET_DONE)) { 1867 mt7996_dma_reset(dev, false); 1868 1869 mt7996_tx_token_put(dev); 1870 idr_init(&dev->mt76.token); 1871 1872 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_INIT); 1873 mt7996_wait_reset_state(dev, MT_MCU_CMD_RECOVERY_DONE); 1874 } 1875 1876 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_RESET_DONE); 1877 mt7996_wait_reset_state(dev, MT_MCU_CMD_NORMAL_STATE); 1878 1879 /* enable DMA Tx/Tx and interrupt */ 1880 mt7996_dma_start(dev, false); 1881 1882 clear_bit(MT76_MCU_RESET, &dev->mphy.state); 1883 clear_bit(MT76_RESET, &dev->mphy.state); 1884 if (phy2) 1885 clear_bit(MT76_RESET, &phy2->mt76->state); 1886 if (phy3) 1887 clear_bit(MT76_RESET, &phy3->mt76->state); 1888 1889 local_bh_disable(); 1890 mt76_for_each_q_rx(&dev->mt76, i) { 1891 napi_enable(&dev->mt76.napi[i]); 1892 napi_schedule(&dev->mt76.napi[i]); 1893 } 1894 local_bh_enable(); 1895 1896 tasklet_schedule(&dev->mt76.irq_tasklet); 1897 1898 mt76_worker_enable(&dev->mt76.tx_worker); 1899 1900 local_bh_disable(); 1901 napi_enable(&dev->mt76.tx_napi); 1902 napi_schedule(&dev->mt76.tx_napi); 1903 local_bh_enable(); 1904 1905 ieee80211_wake_queues(mt76_hw(dev)); 1906 if (phy2) 1907 ieee80211_wake_queues(phy2->mt76->hw); 1908 if (phy3) 1909 ieee80211_wake_queues(phy3->mt76->hw); 1910 1911 mutex_unlock(&dev->mt76.mutex); 1912 1913 mt7996_update_beacons(dev); 1914 1915 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work, 1916 MT7996_WATCHDOG_TIME); 1917 if (phy2) 1918 ieee80211_queue_delayed_work(phy2->mt76->hw, 1919 &phy2->mt76->mac_work, 1920 MT7996_WATCHDOG_TIME); 1921 if (phy3) 1922 ieee80211_queue_delayed_work(phy3->mt76->hw, 1923 &phy3->mt76->mac_work, 1924 MT7996_WATCHDOG_TIME); 1925 dev_info(dev->mt76.dev,"\n%s L1 SER recovery completed.", 1926 wiphy_name(dev->mt76.hw->wiphy)); 1927 } 1928 1929 /* firmware coredump */ 1930 void mt7996_mac_dump_work(struct work_struct *work) 1931 { 1932 const struct mt7996_mem_region *mem_region; 1933 struct mt7996_crash_data *crash_data; 1934 struct mt7996_dev *dev; 1935 struct mt7996_mem_hdr *hdr; 1936 size_t buf_len; 1937 int i; 1938 u32 num; 1939 u8 *buf; 1940 1941 dev = container_of(work, struct mt7996_dev, dump_work); 1942 1943 mutex_lock(&dev->dump_mutex); 1944 1945 crash_data = mt7996_coredump_new(dev); 1946 if (!crash_data) { 1947 mutex_unlock(&dev->dump_mutex); 1948 goto skip_coredump; 1949 } 1950 1951 mem_region = mt7996_coredump_get_mem_layout(dev, &num); 1952 if (!mem_region || !crash_data->memdump_buf_len) { 1953 mutex_unlock(&dev->dump_mutex); 1954 goto skip_memdump; 1955 } 1956 1957 buf = crash_data->memdump_buf; 1958 buf_len = crash_data->memdump_buf_len; 1959 1960 /* dumping memory content... */ 1961 memset(buf, 0, buf_len); 1962 for (i = 0; i < num; i++) { 1963 if (mem_region->len > buf_len) { 1964 dev_warn(dev->mt76.dev, "%s len %zu is too large\n", 1965 mem_region->name, mem_region->len); 1966 break; 1967 } 1968 1969 /* reserve space for the header */ 1970 hdr = (void *)buf; 1971 buf += sizeof(*hdr); 1972 buf_len -= sizeof(*hdr); 1973 1974 mt7996_memcpy_fromio(dev, buf, mem_region->start, 1975 mem_region->len); 1976 1977 hdr->start = mem_region->start; 1978 hdr->len = mem_region->len; 1979 1980 if (!mem_region->len) 1981 /* note: the header remains, just with zero length */ 1982 break; 1983 1984 buf += mem_region->len; 1985 buf_len -= mem_region->len; 1986 1987 mem_region++; 1988 } 1989 1990 mutex_unlock(&dev->dump_mutex); 1991 1992 skip_memdump: 1993 mt7996_coredump_submit(dev); 1994 skip_coredump: 1995 queue_work(dev->mt76.wq, &dev->reset_work); 1996 } 1997 1998 void mt7996_reset(struct mt7996_dev *dev) 1999 { 2000 if (!dev->recovery.hw_init_done) 2001 return; 2002 2003 if (dev->recovery.hw_full_reset) 2004 return; 2005 2006 /* wm/wa exception: do full recovery */ 2007 if (READ_ONCE(dev->recovery.state) & MT_MCU_CMD_WDT_MASK) { 2008 dev->recovery.restart = true; 2009 dev_info(dev->mt76.dev, 2010 "%s indicated firmware crash, attempting recovery\n", 2011 wiphy_name(dev->mt76.hw->wiphy)); 2012 2013 mt7996_irq_disable(dev, MT_INT_MCU_CMD); 2014 queue_work(dev->mt76.wq, &dev->dump_work); 2015 return; 2016 } 2017 2018 queue_work(dev->mt76.wq, &dev->reset_work); 2019 wake_up(&dev->reset_wait); 2020 } 2021 2022 void mt7996_mac_update_stats(struct mt7996_phy *phy) 2023 { 2024 struct mt76_mib_stats *mib = &phy->mib; 2025 struct mt7996_dev *dev = phy->dev; 2026 u8 band_idx = phy->mt76->band_idx; 2027 u32 cnt; 2028 int i; 2029 2030 cnt = mt76_rr(dev, MT_MIB_RSCR1(band_idx)); 2031 mib->fcs_err_cnt += cnt; 2032 2033 cnt = mt76_rr(dev, MT_MIB_RSCR33(band_idx)); 2034 mib->rx_fifo_full_cnt += cnt; 2035 2036 cnt = mt76_rr(dev, MT_MIB_RSCR31(band_idx)); 2037 mib->rx_mpdu_cnt += cnt; 2038 2039 cnt = mt76_rr(dev, MT_MIB_SDR6(band_idx)); 2040 mib->channel_idle_cnt += FIELD_GET(MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK, cnt); 2041 2042 cnt = mt76_rr(dev, MT_MIB_RVSR0(band_idx)); 2043 mib->rx_vector_mismatch_cnt += cnt; 2044 2045 cnt = mt76_rr(dev, MT_MIB_RSCR35(band_idx)); 2046 mib->rx_delimiter_fail_cnt += cnt; 2047 2048 cnt = mt76_rr(dev, MT_MIB_RSCR36(band_idx)); 2049 mib->rx_len_mismatch_cnt += cnt; 2050 2051 cnt = mt76_rr(dev, MT_MIB_TSCR0(band_idx)); 2052 mib->tx_ampdu_cnt += cnt; 2053 2054 cnt = mt76_rr(dev, MT_MIB_TSCR2(band_idx)); 2055 mib->tx_stop_q_empty_cnt += cnt; 2056 2057 cnt = mt76_rr(dev, MT_MIB_TSCR3(band_idx)); 2058 mib->tx_mpdu_attempts_cnt += cnt; 2059 2060 cnt = mt76_rr(dev, MT_MIB_TSCR4(band_idx)); 2061 mib->tx_mpdu_success_cnt += cnt; 2062 2063 cnt = mt76_rr(dev, MT_MIB_RSCR27(band_idx)); 2064 mib->rx_ampdu_cnt += cnt; 2065 2066 cnt = mt76_rr(dev, MT_MIB_RSCR28(band_idx)); 2067 mib->rx_ampdu_bytes_cnt += cnt; 2068 2069 cnt = mt76_rr(dev, MT_MIB_RSCR29(band_idx)); 2070 mib->rx_ampdu_valid_subframe_cnt += cnt; 2071 2072 cnt = mt76_rr(dev, MT_MIB_RSCR30(band_idx)); 2073 mib->rx_ampdu_valid_subframe_bytes_cnt += cnt; 2074 2075 cnt = mt76_rr(dev, MT_MIB_SDR27(band_idx)); 2076 mib->tx_rwp_fail_cnt += FIELD_GET(MT_MIB_SDR27_TX_RWP_FAIL_CNT, cnt); 2077 2078 cnt = mt76_rr(dev, MT_MIB_SDR28(band_idx)); 2079 mib->tx_rwp_need_cnt += FIELD_GET(MT_MIB_SDR28_TX_RWP_NEED_CNT, cnt); 2080 2081 cnt = mt76_rr(dev, MT_UMIB_RPDCR(band_idx)); 2082 mib->rx_pfdrop_cnt += cnt; 2083 2084 cnt = mt76_rr(dev, MT_MIB_RVSR1(band_idx)); 2085 mib->rx_vec_queue_overflow_drop_cnt += cnt; 2086 2087 cnt = mt76_rr(dev, MT_MIB_TSCR1(band_idx)); 2088 mib->rx_ba_cnt += cnt; 2089 2090 cnt = mt76_rr(dev, MT_MIB_BSCR0(band_idx)); 2091 mib->tx_bf_ebf_ppdu_cnt += cnt; 2092 2093 cnt = mt76_rr(dev, MT_MIB_BSCR1(band_idx)); 2094 mib->tx_bf_ibf_ppdu_cnt += cnt; 2095 2096 cnt = mt76_rr(dev, MT_MIB_BSCR2(band_idx)); 2097 mib->tx_mu_bf_cnt += cnt; 2098 2099 cnt = mt76_rr(dev, MT_MIB_TSCR5(band_idx)); 2100 mib->tx_mu_mpdu_cnt += cnt; 2101 2102 cnt = mt76_rr(dev, MT_MIB_TSCR6(band_idx)); 2103 mib->tx_mu_acked_mpdu_cnt += cnt; 2104 2105 cnt = mt76_rr(dev, MT_MIB_TSCR7(band_idx)); 2106 mib->tx_su_acked_mpdu_cnt += cnt; 2107 2108 cnt = mt76_rr(dev, MT_MIB_BSCR3(band_idx)); 2109 mib->tx_bf_rx_fb_ht_cnt += cnt; 2110 mib->tx_bf_rx_fb_all_cnt += cnt; 2111 2112 cnt = mt76_rr(dev, MT_MIB_BSCR4(band_idx)); 2113 mib->tx_bf_rx_fb_vht_cnt += cnt; 2114 mib->tx_bf_rx_fb_all_cnt += cnt; 2115 2116 cnt = mt76_rr(dev, MT_MIB_BSCR5(band_idx)); 2117 mib->tx_bf_rx_fb_he_cnt += cnt; 2118 mib->tx_bf_rx_fb_all_cnt += cnt; 2119 2120 cnt = mt76_rr(dev, MT_MIB_BSCR6(band_idx)); 2121 mib->tx_bf_rx_fb_eht_cnt += cnt; 2122 mib->tx_bf_rx_fb_all_cnt += cnt; 2123 2124 cnt = mt76_rr(dev, MT_ETBF_RX_FB_CONT(band_idx)); 2125 mib->tx_bf_rx_fb_bw = FIELD_GET(MT_ETBF_RX_FB_BW, cnt); 2126 mib->tx_bf_rx_fb_nc_cnt += FIELD_GET(MT_ETBF_RX_FB_NC, cnt); 2127 mib->tx_bf_rx_fb_nr_cnt += FIELD_GET(MT_ETBF_RX_FB_NR, cnt); 2128 2129 cnt = mt76_rr(dev, MT_MIB_BSCR7(band_idx)); 2130 mib->tx_bf_fb_trig_cnt += cnt; 2131 2132 cnt = mt76_rr(dev, MT_MIB_BSCR17(band_idx)); 2133 mib->tx_bf_fb_cpl_cnt += cnt; 2134 2135 for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) { 2136 cnt = mt76_rr(dev, MT_PLE_AMSDU_PACK_MSDU_CNT(i)); 2137 mib->tx_amsdu[i] += cnt; 2138 mib->tx_amsdu_cnt += cnt; 2139 } 2140 2141 /* rts count */ 2142 cnt = mt76_rr(dev, MT_MIB_BTSCR5(band_idx)); 2143 mib->rts_cnt += cnt; 2144 2145 /* rts retry count */ 2146 cnt = mt76_rr(dev, MT_MIB_BTSCR6(band_idx)); 2147 mib->rts_retries_cnt += cnt; 2148 2149 /* ba miss count */ 2150 cnt = mt76_rr(dev, MT_MIB_BTSCR0(band_idx)); 2151 mib->ba_miss_cnt += cnt; 2152 2153 /* ack fail count */ 2154 cnt = mt76_rr(dev, MT_MIB_BFTFCR(band_idx)); 2155 mib->ack_fail_cnt += cnt; 2156 2157 for (i = 0; i < 16; i++) { 2158 cnt = mt76_rr(dev, MT_TX_AGG_CNT(band_idx, i)); 2159 phy->mt76->aggr_stats[i] += cnt; 2160 } 2161 } 2162 2163 void mt7996_mac_sta_rc_work(struct work_struct *work) 2164 { 2165 struct mt7996_dev *dev = container_of(work, struct mt7996_dev, rc_work); 2166 struct ieee80211_sta *sta; 2167 struct ieee80211_vif *vif; 2168 struct mt7996_sta *msta; 2169 u32 changed; 2170 LIST_HEAD(list); 2171 2172 spin_lock_bh(&dev->mt76.sta_poll_lock); 2173 list_splice_init(&dev->sta_rc_list, &list); 2174 2175 while (!list_empty(&list)) { 2176 msta = list_first_entry(&list, struct mt7996_sta, rc_list); 2177 list_del_init(&msta->rc_list); 2178 changed = msta->changed; 2179 msta->changed = 0; 2180 spin_unlock_bh(&dev->mt76.sta_poll_lock); 2181 2182 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv); 2183 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); 2184 2185 if (changed & (IEEE80211_RC_SUPP_RATES_CHANGED | 2186 IEEE80211_RC_NSS_CHANGED | 2187 IEEE80211_RC_BW_CHANGED)) 2188 mt7996_mcu_add_rate_ctrl(dev, vif, sta, true); 2189 2190 /* TODO: smps change */ 2191 2192 spin_lock_bh(&dev->mt76.sta_poll_lock); 2193 } 2194 2195 spin_unlock_bh(&dev->mt76.sta_poll_lock); 2196 } 2197 2198 void mt7996_mac_work(struct work_struct *work) 2199 { 2200 struct mt7996_phy *phy; 2201 struct mt76_phy *mphy; 2202 2203 mphy = (struct mt76_phy *)container_of(work, struct mt76_phy, 2204 mac_work.work); 2205 phy = mphy->priv; 2206 2207 mutex_lock(&mphy->dev->mutex); 2208 2209 mt76_update_survey(mphy); 2210 if (++mphy->mac_work_count == 5) { 2211 mphy->mac_work_count = 0; 2212 2213 mt7996_mac_update_stats(phy); 2214 2215 if (mtk_wed_device_active(&phy->dev->mt76.mmio.wed)) { 2216 mt7996_mcu_get_all_sta_info(phy, UNI_ALL_STA_TXRX_ADM_STAT); 2217 mt7996_mcu_get_all_sta_info(phy, UNI_ALL_STA_TXRX_MSDU_COUNT); 2218 } 2219 } 2220 2221 mutex_unlock(&mphy->dev->mutex); 2222 2223 mt76_tx_status_check(mphy->dev, false); 2224 2225 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, 2226 MT7996_WATCHDOG_TIME); 2227 } 2228 2229 static void mt7996_dfs_stop_radar_detector(struct mt7996_phy *phy) 2230 { 2231 struct mt7996_dev *dev = phy->dev; 2232 2233 if (phy->rdd_state & BIT(0)) 2234 mt7996_mcu_rdd_cmd(dev, RDD_STOP, 0, 2235 MT_RX_SEL0, 0); 2236 if (phy->rdd_state & BIT(1)) 2237 mt7996_mcu_rdd_cmd(dev, RDD_STOP, 1, 2238 MT_RX_SEL0, 0); 2239 } 2240 2241 static int mt7996_dfs_start_rdd(struct mt7996_dev *dev, int chain) 2242 { 2243 int err, region; 2244 2245 switch (dev->mt76.region) { 2246 case NL80211_DFS_ETSI: 2247 region = 0; 2248 break; 2249 case NL80211_DFS_JP: 2250 region = 2; 2251 break; 2252 case NL80211_DFS_FCC: 2253 default: 2254 region = 1; 2255 break; 2256 } 2257 2258 err = mt7996_mcu_rdd_cmd(dev, RDD_START, chain, 2259 MT_RX_SEL0, region); 2260 if (err < 0) 2261 return err; 2262 2263 return mt7996_mcu_rdd_cmd(dev, RDD_DET_MODE, chain, 2264 MT_RX_SEL0, 1); 2265 } 2266 2267 static int mt7996_dfs_start_radar_detector(struct mt7996_phy *phy) 2268 { 2269 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 2270 struct mt7996_dev *dev = phy->dev; 2271 u8 band_idx = phy->mt76->band_idx; 2272 int err; 2273 2274 /* start CAC */ 2275 err = mt7996_mcu_rdd_cmd(dev, RDD_CAC_START, band_idx, 2276 MT_RX_SEL0, 0); 2277 if (err < 0) 2278 return err; 2279 2280 err = mt7996_dfs_start_rdd(dev, band_idx); 2281 if (err < 0) 2282 return err; 2283 2284 phy->rdd_state |= BIT(band_idx); 2285 2286 if (chandef->width == NL80211_CHAN_WIDTH_160 || 2287 chandef->width == NL80211_CHAN_WIDTH_80P80) { 2288 err = mt7996_dfs_start_rdd(dev, 1); 2289 if (err < 0) 2290 return err; 2291 2292 phy->rdd_state |= BIT(1); 2293 } 2294 2295 return 0; 2296 } 2297 2298 static int 2299 mt7996_dfs_init_radar_specs(struct mt7996_phy *phy) 2300 { 2301 const struct mt7996_dfs_radar_spec *radar_specs; 2302 struct mt7996_dev *dev = phy->dev; 2303 int err, i; 2304 2305 switch (dev->mt76.region) { 2306 case NL80211_DFS_FCC: 2307 radar_specs = &fcc_radar_specs; 2308 err = mt7996_mcu_set_fcc5_lpn(dev, 8); 2309 if (err < 0) 2310 return err; 2311 break; 2312 case NL80211_DFS_ETSI: 2313 radar_specs = &etsi_radar_specs; 2314 break; 2315 case NL80211_DFS_JP: 2316 radar_specs = &jp_radar_specs; 2317 break; 2318 default: 2319 return -EINVAL; 2320 } 2321 2322 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) { 2323 err = mt7996_mcu_set_radar_th(dev, i, 2324 &radar_specs->radar_pattern[i]); 2325 if (err < 0) 2326 return err; 2327 } 2328 2329 return mt7996_mcu_set_pulse_th(dev, &radar_specs->pulse_th); 2330 } 2331 2332 int mt7996_dfs_init_radar_detector(struct mt7996_phy *phy) 2333 { 2334 struct mt7996_dev *dev = phy->dev; 2335 enum mt76_dfs_state dfs_state, prev_state; 2336 int err; 2337 2338 prev_state = phy->mt76->dfs_state; 2339 dfs_state = mt76_phy_dfs_state(phy->mt76); 2340 2341 if (prev_state == dfs_state) 2342 return 0; 2343 2344 if (prev_state == MT_DFS_STATE_UNKNOWN) 2345 mt7996_dfs_stop_radar_detector(phy); 2346 2347 if (dfs_state == MT_DFS_STATE_DISABLED) 2348 goto stop; 2349 2350 if (prev_state <= MT_DFS_STATE_DISABLED) { 2351 err = mt7996_dfs_init_radar_specs(phy); 2352 if (err < 0) 2353 return err; 2354 2355 err = mt7996_dfs_start_radar_detector(phy); 2356 if (err < 0) 2357 return err; 2358 2359 phy->mt76->dfs_state = MT_DFS_STATE_CAC; 2360 } 2361 2362 if (dfs_state == MT_DFS_STATE_CAC) 2363 return 0; 2364 2365 err = mt7996_mcu_rdd_cmd(dev, RDD_CAC_END, 2366 phy->mt76->band_idx, MT_RX_SEL0, 0); 2367 if (err < 0) { 2368 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN; 2369 return err; 2370 } 2371 2372 phy->mt76->dfs_state = MT_DFS_STATE_ACTIVE; 2373 return 0; 2374 2375 stop: 2376 err = mt7996_mcu_rdd_cmd(dev, RDD_NORMAL_START, 2377 phy->mt76->band_idx, MT_RX_SEL0, 0); 2378 if (err < 0) 2379 return err; 2380 2381 mt7996_dfs_stop_radar_detector(phy); 2382 phy->mt76->dfs_state = MT_DFS_STATE_DISABLED; 2383 2384 return 0; 2385 } 2386 2387 static int 2388 mt7996_mac_twt_duration_align(int duration) 2389 { 2390 return duration << 8; 2391 } 2392 2393 static u64 2394 mt7996_mac_twt_sched_list_add(struct mt7996_dev *dev, 2395 struct mt7996_twt_flow *flow) 2396 { 2397 struct mt7996_twt_flow *iter, *iter_next; 2398 u32 duration = flow->duration << 8; 2399 u64 start_tsf; 2400 2401 iter = list_first_entry_or_null(&dev->twt_list, 2402 struct mt7996_twt_flow, list); 2403 if (!iter || !iter->sched || iter->start_tsf > duration) { 2404 /* add flow as first entry in the list */ 2405 list_add(&flow->list, &dev->twt_list); 2406 return 0; 2407 } 2408 2409 list_for_each_entry_safe(iter, iter_next, &dev->twt_list, list) { 2410 start_tsf = iter->start_tsf + 2411 mt7996_mac_twt_duration_align(iter->duration); 2412 if (list_is_last(&iter->list, &dev->twt_list)) 2413 break; 2414 2415 if (!iter_next->sched || 2416 iter_next->start_tsf > start_tsf + duration) { 2417 list_add(&flow->list, &iter->list); 2418 goto out; 2419 } 2420 } 2421 2422 /* add flow as last entry in the list */ 2423 list_add_tail(&flow->list, &dev->twt_list); 2424 out: 2425 return start_tsf; 2426 } 2427 2428 static int mt7996_mac_check_twt_req(struct ieee80211_twt_setup *twt) 2429 { 2430 struct ieee80211_twt_params *twt_agrt; 2431 u64 interval, duration; 2432 u16 mantissa; 2433 u8 exp; 2434 2435 /* only individual agreement supported */ 2436 if (twt->control & IEEE80211_TWT_CONTROL_NEG_TYPE_BROADCAST) 2437 return -EOPNOTSUPP; 2438 2439 /* only 256us unit supported */ 2440 if (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT) 2441 return -EOPNOTSUPP; 2442 2443 twt_agrt = (struct ieee80211_twt_params *)twt->params; 2444 2445 /* explicit agreement not supported */ 2446 if (!(twt_agrt->req_type & cpu_to_le16(IEEE80211_TWT_REQTYPE_IMPLICIT))) 2447 return -EOPNOTSUPP; 2448 2449 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, 2450 le16_to_cpu(twt_agrt->req_type)); 2451 mantissa = le16_to_cpu(twt_agrt->mantissa); 2452 duration = twt_agrt->min_twt_dur << 8; 2453 2454 interval = (u64)mantissa << exp; 2455 if (interval < duration) 2456 return -EOPNOTSUPP; 2457 2458 return 0; 2459 } 2460 2461 void mt7996_mac_add_twt_setup(struct ieee80211_hw *hw, 2462 struct ieee80211_sta *sta, 2463 struct ieee80211_twt_setup *twt) 2464 { 2465 enum ieee80211_twt_setup_cmd setup_cmd = TWT_SETUP_CMD_REJECT; 2466 struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv; 2467 struct ieee80211_twt_params *twt_agrt = (void *)twt->params; 2468 u16 req_type = le16_to_cpu(twt_agrt->req_type); 2469 enum ieee80211_twt_setup_cmd sta_setup_cmd; 2470 struct mt7996_dev *dev = mt7996_hw_dev(hw); 2471 struct mt7996_twt_flow *flow; 2472 int flowid, table_id; 2473 u8 exp; 2474 2475 if (mt7996_mac_check_twt_req(twt)) 2476 goto out; 2477 2478 mutex_lock(&dev->mt76.mutex); 2479 2480 if (dev->twt.n_agrt == MT7996_MAX_TWT_AGRT) 2481 goto unlock; 2482 2483 if (hweight8(msta->twt.flowid_mask) == ARRAY_SIZE(msta->twt.flow)) 2484 goto unlock; 2485 2486 flowid = ffs(~msta->twt.flowid_mask) - 1; 2487 le16p_replace_bits(&twt_agrt->req_type, flowid, 2488 IEEE80211_TWT_REQTYPE_FLOWID); 2489 2490 table_id = ffs(~dev->twt.table_mask) - 1; 2491 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, req_type); 2492 sta_setup_cmd = FIELD_GET(IEEE80211_TWT_REQTYPE_SETUP_CMD, req_type); 2493 2494 flow = &msta->twt.flow[flowid]; 2495 memset(flow, 0, sizeof(*flow)); 2496 INIT_LIST_HEAD(&flow->list); 2497 flow->wcid = msta->wcid.idx; 2498 flow->table_id = table_id; 2499 flow->id = flowid; 2500 flow->duration = twt_agrt->min_twt_dur; 2501 flow->mantissa = twt_agrt->mantissa; 2502 flow->exp = exp; 2503 flow->protection = !!(req_type & IEEE80211_TWT_REQTYPE_PROTECTION); 2504 flow->flowtype = !!(req_type & IEEE80211_TWT_REQTYPE_FLOWTYPE); 2505 flow->trigger = !!(req_type & IEEE80211_TWT_REQTYPE_TRIGGER); 2506 2507 if (sta_setup_cmd == TWT_SETUP_CMD_REQUEST || 2508 sta_setup_cmd == TWT_SETUP_CMD_SUGGEST) { 2509 u64 interval = (u64)le16_to_cpu(twt_agrt->mantissa) << exp; 2510 u64 flow_tsf, curr_tsf; 2511 u32 rem; 2512 2513 flow->sched = true; 2514 flow->start_tsf = mt7996_mac_twt_sched_list_add(dev, flow); 2515 curr_tsf = __mt7996_get_tsf(hw, msta->vif); 2516 div_u64_rem(curr_tsf - flow->start_tsf, interval, &rem); 2517 flow_tsf = curr_tsf + interval - rem; 2518 twt_agrt->twt = cpu_to_le64(flow_tsf); 2519 } else { 2520 list_add_tail(&flow->list, &dev->twt_list); 2521 } 2522 flow->tsf = le64_to_cpu(twt_agrt->twt); 2523 2524 if (mt7996_mcu_twt_agrt_update(dev, msta->vif, flow, MCU_TWT_AGRT_ADD)) 2525 goto unlock; 2526 2527 setup_cmd = TWT_SETUP_CMD_ACCEPT; 2528 dev->twt.table_mask |= BIT(table_id); 2529 msta->twt.flowid_mask |= BIT(flowid); 2530 dev->twt.n_agrt++; 2531 2532 unlock: 2533 mutex_unlock(&dev->mt76.mutex); 2534 out: 2535 le16p_replace_bits(&twt_agrt->req_type, setup_cmd, 2536 IEEE80211_TWT_REQTYPE_SETUP_CMD); 2537 twt->control = (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT) | 2538 (twt->control & IEEE80211_TWT_CONTROL_RX_DISABLED); 2539 } 2540 2541 void mt7996_mac_twt_teardown_flow(struct mt7996_dev *dev, 2542 struct mt7996_sta *msta, 2543 u8 flowid) 2544 { 2545 struct mt7996_twt_flow *flow; 2546 2547 lockdep_assert_held(&dev->mt76.mutex); 2548 2549 if (flowid >= ARRAY_SIZE(msta->twt.flow)) 2550 return; 2551 2552 if (!(msta->twt.flowid_mask & BIT(flowid))) 2553 return; 2554 2555 flow = &msta->twt.flow[flowid]; 2556 if (mt7996_mcu_twt_agrt_update(dev, msta->vif, flow, 2557 MCU_TWT_AGRT_DELETE)) 2558 return; 2559 2560 list_del_init(&flow->list); 2561 msta->twt.flowid_mask &= ~BIT(flowid); 2562 dev->twt.table_mask &= ~BIT(flow->table_id); 2563 dev->twt.n_agrt--; 2564 } 2565