1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #include <linux/etherdevice.h> 7 #include <linux/timekeeping.h> 8 #include "coredump.h" 9 #include "mt7996.h" 10 #include "../dma.h" 11 #include "mac.h" 12 #include "mcu.h" 13 14 #define to_rssi(field, rcpi) ((FIELD_GET(field, rcpi) - 220) / 2) 15 16 static const struct mt7996_dfs_radar_spec etsi_radar_specs = { 17 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 18 .radar_pattern = { 19 [5] = { 1, 0, 6, 32, 28, 0, 990, 5010, 17, 1, 1 }, 20 [6] = { 1, 0, 9, 32, 28, 0, 615, 5010, 27, 1, 1 }, 21 [7] = { 1, 0, 15, 32, 28, 0, 240, 445, 27, 1, 1 }, 22 [8] = { 1, 0, 12, 32, 28, 0, 240, 510, 42, 1, 1 }, 23 [9] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 12, 32, 28, { }, 126 }, 24 [10] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 15, 32, 24, { }, 126 }, 25 [11] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 18, 32, 28, { }, 54 }, 26 [12] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 27, 32, 24, { }, 54 }, 27 }, 28 }; 29 30 static const struct mt7996_dfs_radar_spec fcc_radar_specs = { 31 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 32 .radar_pattern = { 33 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 }, 34 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 }, 35 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 }, 36 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 }, 37 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 }, 38 }, 39 }; 40 41 static const struct mt7996_dfs_radar_spec jp_radar_specs = { 42 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 43 .radar_pattern = { 44 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 }, 45 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 }, 46 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 }, 47 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 }, 48 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 }, 49 [13] = { 1, 0, 7, 32, 28, 0, 3836, 3856, 14, 1, 1 }, 50 [14] = { 1, 0, 6, 32, 28, 0, 615, 5010, 110, 1, 1 }, 51 [15] = { 1, 1, 0, 0, 0, 0, 15, 5010, 110, 0, 0, 12, 32, 28 }, 52 }, 53 }; 54 55 static struct mt76_wcid *mt7996_rx_get_wcid(struct mt7996_dev *dev, 56 u16 idx, u8 band_idx) 57 { 58 struct mt7996_sta_link *msta_link; 59 struct mt7996_sta *msta; 60 struct mt7996_vif *mvif; 61 struct mt76_wcid *wcid; 62 int i; 63 64 if (idx >= ARRAY_SIZE(dev->mt76.wcid)) 65 return NULL; 66 67 wcid = rcu_dereference(dev->mt76.wcid[idx]); 68 if (!wcid) 69 return NULL; 70 71 if (!mt7996_band_valid(dev, band_idx)) 72 return NULL; 73 74 if (wcid->phy_idx == band_idx) 75 return wcid; 76 77 msta_link = container_of(wcid, struct mt7996_sta_link, wcid); 78 msta = msta_link->sta; 79 if (!msta || !msta->vif) 80 return NULL; 81 82 mvif = msta->vif; 83 for (i = 0; i < ARRAY_SIZE(mvif->mt76.link); i++) { 84 struct mt76_vif_link *mlink; 85 86 mlink = rcu_dereference(mvif->mt76.link[i]); 87 if (!mlink) 88 continue; 89 90 if (mlink->band_idx != band_idx) 91 continue; 92 93 msta_link = rcu_dereference(msta->link[i]); 94 break; 95 } 96 97 return &msta_link->wcid; 98 } 99 100 bool mt7996_mac_wtbl_update(struct mt7996_dev *dev, int idx, u32 mask) 101 { 102 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX, 103 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask); 104 105 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 106 0, 5000); 107 } 108 109 u32 mt7996_mac_wtbl_lmac_addr(struct mt7996_dev *dev, u16 wcid, u8 dw) 110 { 111 mt76_wr(dev, MT_WTBLON_TOP_WDUCR, 112 FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (wcid >> 7))); 113 114 return MT_WTBL_LMAC_OFFS(wcid, dw); 115 } 116 117 static void mt7996_mac_sta_poll(struct mt7996_dev *dev) 118 { 119 static const u8 ac_to_tid[] = { 120 [IEEE80211_AC_BE] = 0, 121 [IEEE80211_AC_BK] = 1, 122 [IEEE80211_AC_VI] = 4, 123 [IEEE80211_AC_VO] = 6 124 }; 125 struct mt7996_sta_link *msta_link; 126 struct mt76_vif_link *mlink; 127 struct ieee80211_sta *sta; 128 struct mt7996_sta *msta; 129 u32 tx_time[IEEE80211_NUM_ACS], rx_time[IEEE80211_NUM_ACS]; 130 LIST_HEAD(sta_poll_list); 131 struct mt76_wcid *wcid; 132 int i; 133 134 spin_lock_bh(&dev->mt76.sta_poll_lock); 135 list_splice_init(&dev->mt76.sta_poll_list, &sta_poll_list); 136 spin_unlock_bh(&dev->mt76.sta_poll_lock); 137 138 rcu_read_lock(); 139 140 while (true) { 141 bool clear = false; 142 u32 addr, val; 143 u16 idx; 144 s8 rssi[4]; 145 146 spin_lock_bh(&dev->mt76.sta_poll_lock); 147 if (list_empty(&sta_poll_list)) { 148 spin_unlock_bh(&dev->mt76.sta_poll_lock); 149 break; 150 } 151 msta_link = list_first_entry(&sta_poll_list, 152 struct mt7996_sta_link, 153 wcid.poll_list); 154 msta = msta_link->sta; 155 wcid = &msta_link->wcid; 156 list_del_init(&wcid->poll_list); 157 spin_unlock_bh(&dev->mt76.sta_poll_lock); 158 159 idx = wcid->idx; 160 161 /* refresh peer's airtime reporting */ 162 addr = mt7996_mac_wtbl_lmac_addr(dev, idx, 20); 163 164 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 165 u32 tx_last = msta_link->airtime_ac[i]; 166 u32 rx_last = msta_link->airtime_ac[i + 4]; 167 168 msta_link->airtime_ac[i] = mt76_rr(dev, addr); 169 msta_link->airtime_ac[i + 4] = mt76_rr(dev, addr + 4); 170 171 tx_time[i] = msta_link->airtime_ac[i] - tx_last; 172 rx_time[i] = msta_link->airtime_ac[i + 4] - rx_last; 173 174 if ((tx_last | rx_last) & BIT(30)) 175 clear = true; 176 177 addr += 8; 178 } 179 180 if (clear) { 181 mt7996_mac_wtbl_update(dev, idx, 182 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 183 memset(msta_link->airtime_ac, 0, 184 sizeof(msta_link->airtime_ac)); 185 } 186 187 if (!wcid->sta) 188 continue; 189 190 sta = container_of((void *)msta, struct ieee80211_sta, 191 drv_priv); 192 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 193 u8 q = mt76_connac_lmac_mapping(i); 194 u32 tx_cur = tx_time[q]; 195 u32 rx_cur = rx_time[q]; 196 u8 tid = ac_to_tid[i]; 197 198 if (!tx_cur && !rx_cur) 199 continue; 200 201 ieee80211_sta_register_airtime(sta, tid, tx_cur, rx_cur); 202 } 203 204 /* get signal strength of resp frames (CTS/BA/ACK) */ 205 addr = mt7996_mac_wtbl_lmac_addr(dev, idx, 34); 206 val = mt76_rr(dev, addr); 207 208 rssi[0] = to_rssi(GENMASK(7, 0), val); 209 rssi[1] = to_rssi(GENMASK(15, 8), val); 210 rssi[2] = to_rssi(GENMASK(23, 16), val); 211 rssi[3] = to_rssi(GENMASK(31, 14), val); 212 213 mlink = rcu_dereference(msta->vif->mt76.link[wcid->link_id]); 214 if (mlink) { 215 struct mt76_phy *mphy = mt76_vif_link_phy(mlink); 216 217 if (mphy) 218 msta_link->ack_signal = 219 mt76_rx_signal(mphy->antenna_mask, 220 rssi); 221 } 222 223 ewma_avg_signal_add(&msta_link->avg_ack_signal, 224 -msta_link->ack_signal); 225 } 226 227 rcu_read_unlock(); 228 } 229 230 /* The HW does not translate the mac header to 802.3 for mesh point */ 231 static int mt7996_reverse_frag0_hdr_trans(struct sk_buff *skb, u16 hdr_gap) 232 { 233 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 234 struct ethhdr *eth_hdr = (struct ethhdr *)(skb->data + hdr_gap); 235 struct mt7996_sta *msta = (struct mt7996_sta *)status->wcid; 236 __le32 *rxd = (__le32 *)skb->data; 237 struct ieee80211_sta *sta; 238 struct ieee80211_vif *vif; 239 struct ieee80211_hdr hdr; 240 u16 frame_control; 241 242 if (le32_get_bits(rxd[3], MT_RXD3_NORMAL_ADDR_TYPE) != 243 MT_RXD3_NORMAL_U2M) 244 return -EINVAL; 245 246 if (!(le32_to_cpu(rxd[1]) & MT_RXD1_NORMAL_GROUP_4)) 247 return -EINVAL; 248 249 if (!msta || !msta->vif) 250 return -EINVAL; 251 252 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv); 253 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); 254 255 /* store the info from RXD and ethhdr to avoid being overridden */ 256 frame_control = le32_get_bits(rxd[8], MT_RXD8_FRAME_CONTROL); 257 hdr.frame_control = cpu_to_le16(frame_control); 258 hdr.seq_ctrl = cpu_to_le16(le32_get_bits(rxd[10], MT_RXD10_SEQ_CTRL)); 259 hdr.duration_id = 0; 260 261 ether_addr_copy(hdr.addr1, vif->addr); 262 ether_addr_copy(hdr.addr2, sta->addr); 263 switch (frame_control & (IEEE80211_FCTL_TODS | 264 IEEE80211_FCTL_FROMDS)) { 265 case 0: 266 ether_addr_copy(hdr.addr3, vif->bss_conf.bssid); 267 break; 268 case IEEE80211_FCTL_FROMDS: 269 ether_addr_copy(hdr.addr3, eth_hdr->h_source); 270 break; 271 case IEEE80211_FCTL_TODS: 272 ether_addr_copy(hdr.addr3, eth_hdr->h_dest); 273 break; 274 case IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS: 275 ether_addr_copy(hdr.addr3, eth_hdr->h_dest); 276 ether_addr_copy(hdr.addr4, eth_hdr->h_source); 277 break; 278 default: 279 return -EINVAL; 280 } 281 282 skb_pull(skb, hdr_gap + sizeof(struct ethhdr) - 2); 283 if (eth_hdr->h_proto == cpu_to_be16(ETH_P_AARP) || 284 eth_hdr->h_proto == cpu_to_be16(ETH_P_IPX)) 285 ether_addr_copy(skb_push(skb, ETH_ALEN), bridge_tunnel_header); 286 else if (be16_to_cpu(eth_hdr->h_proto) >= ETH_P_802_3_MIN) 287 ether_addr_copy(skb_push(skb, ETH_ALEN), rfc1042_header); 288 else 289 skb_pull(skb, 2); 290 291 if (ieee80211_has_order(hdr.frame_control)) 292 memcpy(skb_push(skb, IEEE80211_HT_CTL_LEN), &rxd[11], 293 IEEE80211_HT_CTL_LEN); 294 if (ieee80211_is_data_qos(hdr.frame_control)) { 295 __le16 qos_ctrl; 296 297 qos_ctrl = cpu_to_le16(le32_get_bits(rxd[10], MT_RXD10_QOS_CTL)); 298 memcpy(skb_push(skb, IEEE80211_QOS_CTL_LEN), &qos_ctrl, 299 IEEE80211_QOS_CTL_LEN); 300 } 301 302 if (ieee80211_has_a4(hdr.frame_control)) 303 memcpy(skb_push(skb, sizeof(hdr)), &hdr, sizeof(hdr)); 304 else 305 memcpy(skb_push(skb, sizeof(hdr) - 6), &hdr, sizeof(hdr) - 6); 306 307 return 0; 308 } 309 310 static int 311 mt7996_mac_fill_rx_rate(struct mt7996_dev *dev, 312 struct mt76_rx_status *status, 313 struct ieee80211_supported_band *sband, 314 __le32 *rxv, u8 *mode) 315 { 316 u32 v0, v2; 317 u8 stbc, gi, bw, dcm, nss; 318 int i, idx; 319 bool cck = false; 320 321 v0 = le32_to_cpu(rxv[0]); 322 v2 = le32_to_cpu(rxv[2]); 323 324 idx = FIELD_GET(MT_PRXV_TX_RATE, v0); 325 i = idx; 326 nss = FIELD_GET(MT_PRXV_NSTS, v0) + 1; 327 328 stbc = FIELD_GET(MT_PRXV_HT_STBC, v2); 329 gi = FIELD_GET(MT_PRXV_HT_SHORT_GI, v2); 330 *mode = FIELD_GET(MT_PRXV_TX_MODE, v2); 331 dcm = FIELD_GET(MT_PRXV_DCM, v2); 332 bw = FIELD_GET(MT_PRXV_FRAME_MODE, v2); 333 334 switch (*mode) { 335 case MT_PHY_TYPE_CCK: 336 cck = true; 337 fallthrough; 338 case MT_PHY_TYPE_OFDM: 339 i = mt76_get_rate(&dev->mt76, sband, i, cck); 340 break; 341 case MT_PHY_TYPE_HT_GF: 342 case MT_PHY_TYPE_HT: 343 status->encoding = RX_ENC_HT; 344 if (gi) 345 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 346 if (i > 31) 347 return -EINVAL; 348 break; 349 case MT_PHY_TYPE_VHT: 350 status->nss = nss; 351 status->encoding = RX_ENC_VHT; 352 if (gi) 353 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 354 if (i > 11) 355 return -EINVAL; 356 break; 357 case MT_PHY_TYPE_HE_MU: 358 case MT_PHY_TYPE_HE_SU: 359 case MT_PHY_TYPE_HE_EXT_SU: 360 case MT_PHY_TYPE_HE_TB: 361 status->nss = nss; 362 status->encoding = RX_ENC_HE; 363 i &= GENMASK(3, 0); 364 365 if (gi <= NL80211_RATE_INFO_HE_GI_3_2) 366 status->he_gi = gi; 367 368 status->he_dcm = dcm; 369 break; 370 case MT_PHY_TYPE_EHT_SU: 371 case MT_PHY_TYPE_EHT_TRIG: 372 case MT_PHY_TYPE_EHT_MU: 373 status->nss = nss; 374 status->encoding = RX_ENC_EHT; 375 i &= GENMASK(3, 0); 376 377 if (gi <= NL80211_RATE_INFO_EHT_GI_3_2) 378 status->eht.gi = gi; 379 break; 380 default: 381 return -EINVAL; 382 } 383 status->rate_idx = i; 384 385 switch (bw) { 386 case IEEE80211_STA_RX_BW_20: 387 break; 388 case IEEE80211_STA_RX_BW_40: 389 if (*mode & MT_PHY_TYPE_HE_EXT_SU && 390 (idx & MT_PRXV_TX_ER_SU_106T)) { 391 status->bw = RATE_INFO_BW_HE_RU; 392 status->he_ru = 393 NL80211_RATE_INFO_HE_RU_ALLOC_106; 394 } else { 395 status->bw = RATE_INFO_BW_40; 396 } 397 break; 398 case IEEE80211_STA_RX_BW_80: 399 status->bw = RATE_INFO_BW_80; 400 break; 401 case IEEE80211_STA_RX_BW_160: 402 status->bw = RATE_INFO_BW_160; 403 break; 404 /* rxv reports bw 320-1 and 320-2 separately */ 405 case IEEE80211_STA_RX_BW_320: 406 case IEEE80211_STA_RX_BW_320 + 1: 407 status->bw = RATE_INFO_BW_320; 408 break; 409 default: 410 return -EINVAL; 411 } 412 413 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc; 414 if (*mode < MT_PHY_TYPE_HE_SU && gi) 415 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 416 417 return 0; 418 } 419 420 static void 421 mt7996_wed_check_ppe(struct mt7996_dev *dev, struct mt76_queue *q, 422 struct mt7996_sta *msta, struct sk_buff *skb, 423 u32 info) 424 { 425 struct ieee80211_vif *vif; 426 struct wireless_dev *wdev; 427 428 if (!msta || !msta->vif) 429 return; 430 431 if (!mt76_queue_is_wed_rx(q)) 432 return; 433 434 if (!(info & MT_DMA_INFO_PPE_VLD)) 435 return; 436 437 vif = container_of((void *)msta->vif, struct ieee80211_vif, 438 drv_priv); 439 wdev = ieee80211_vif_to_wdev(vif); 440 skb->dev = wdev->netdev; 441 442 mtk_wed_device_ppe_check(&dev->mt76.mmio.wed, skb, 443 FIELD_GET(MT_DMA_PPE_CPU_REASON, info), 444 FIELD_GET(MT_DMA_PPE_ENTRY, info)); 445 } 446 447 static int 448 mt7996_mac_fill_rx(struct mt7996_dev *dev, enum mt76_rxq_id q, 449 struct sk_buff *skb, u32 *info) 450 { 451 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 452 struct mt76_phy *mphy = &dev->mt76.phy; 453 struct mt7996_phy *phy = &dev->phy; 454 struct ieee80211_supported_band *sband; 455 __le32 *rxd = (__le32 *)skb->data; 456 __le32 *rxv = NULL; 457 u32 rxd0 = le32_to_cpu(rxd[0]); 458 u32 rxd1 = le32_to_cpu(rxd[1]); 459 u32 rxd2 = le32_to_cpu(rxd[2]); 460 u32 rxd3 = le32_to_cpu(rxd[3]); 461 u32 rxd4 = le32_to_cpu(rxd[4]); 462 u32 csum_mask = MT_RXD3_NORMAL_IP_SUM | MT_RXD3_NORMAL_UDP_TCP_SUM; 463 u32 csum_status = *(u32 *)skb->cb; 464 u32 mesh_mask = MT_RXD0_MESH | MT_RXD0_MHCP; 465 bool is_mesh = (rxd0 & mesh_mask) == mesh_mask; 466 bool unicast, insert_ccmp_hdr = false; 467 u8 remove_pad, amsdu_info, band_idx; 468 u8 mode = 0, qos_ctl = 0; 469 bool hdr_trans; 470 u16 hdr_gap; 471 u16 seq_ctrl = 0; 472 __le16 fc = 0; 473 int idx; 474 u8 hw_aggr = false; 475 struct mt7996_sta *msta = NULL; 476 477 hw_aggr = status->aggr; 478 memset(status, 0, sizeof(*status)); 479 480 band_idx = FIELD_GET(MT_RXD1_NORMAL_BAND_IDX, rxd1); 481 mphy = dev->mt76.phys[band_idx]; 482 phy = mphy->priv; 483 status->phy_idx = mphy->band_idx; 484 485 if (!test_bit(MT76_STATE_RUNNING, &mphy->state)) 486 return -EINVAL; 487 488 if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR) 489 return -EINVAL; 490 491 hdr_trans = rxd2 & MT_RXD2_NORMAL_HDR_TRANS; 492 if (hdr_trans && (rxd1 & MT_RXD1_NORMAL_CM)) 493 return -EINVAL; 494 495 /* ICV error or CCMP/BIP/WPI MIC error */ 496 if (rxd1 & MT_RXD1_NORMAL_ICV_ERR) 497 status->flag |= RX_FLAG_ONLY_MONITOR; 498 499 unicast = FIELD_GET(MT_RXD3_NORMAL_ADDR_TYPE, rxd3) == MT_RXD3_NORMAL_U2M; 500 idx = FIELD_GET(MT_RXD1_NORMAL_WLAN_IDX, rxd1); 501 status->wcid = mt7996_rx_get_wcid(dev, idx, band_idx); 502 503 if (status->wcid) { 504 struct mt7996_sta_link *msta_link; 505 506 msta_link = container_of(status->wcid, struct mt7996_sta_link, 507 wcid); 508 msta = msta_link->sta; 509 mt76_wcid_add_poll(&dev->mt76, &msta_link->wcid); 510 } 511 512 status->freq = mphy->chandef.chan->center_freq; 513 status->band = mphy->chandef.chan->band; 514 if (status->band == NL80211_BAND_5GHZ) 515 sband = &mphy->sband_5g.sband; 516 else if (status->band == NL80211_BAND_6GHZ) 517 sband = &mphy->sband_6g.sband; 518 else 519 sband = &mphy->sband_2g.sband; 520 521 if (!sband->channels) 522 return -EINVAL; 523 524 if ((rxd3 & csum_mask) == csum_mask && 525 !(csum_status & (BIT(0) | BIT(2) | BIT(3)))) 526 skb->ip_summed = CHECKSUM_UNNECESSARY; 527 528 if (rxd1 & MT_RXD3_NORMAL_FCS_ERR) 529 status->flag |= RX_FLAG_FAILED_FCS_CRC; 530 531 if (rxd1 & MT_RXD1_NORMAL_TKIP_MIC_ERR) 532 status->flag |= RX_FLAG_MMIC_ERROR; 533 534 if (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2) != 0 && 535 !(rxd1 & (MT_RXD1_NORMAL_CLM | MT_RXD1_NORMAL_CM))) { 536 status->flag |= RX_FLAG_DECRYPTED; 537 status->flag |= RX_FLAG_IV_STRIPPED; 538 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED; 539 } 540 541 remove_pad = FIELD_GET(MT_RXD2_NORMAL_HDR_OFFSET, rxd2); 542 543 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR) 544 return -EINVAL; 545 546 rxd += 8; 547 if (rxd1 & MT_RXD1_NORMAL_GROUP_4) { 548 u32 v0 = le32_to_cpu(rxd[0]); 549 u32 v2 = le32_to_cpu(rxd[2]); 550 551 fc = cpu_to_le16(FIELD_GET(MT_RXD8_FRAME_CONTROL, v0)); 552 qos_ctl = FIELD_GET(MT_RXD10_QOS_CTL, v2); 553 seq_ctrl = FIELD_GET(MT_RXD10_SEQ_CTRL, v2); 554 555 rxd += 4; 556 if ((u8 *)rxd - skb->data >= skb->len) 557 return -EINVAL; 558 } 559 560 if (rxd1 & MT_RXD1_NORMAL_GROUP_1) { 561 u8 *data = (u8 *)rxd; 562 563 if (status->flag & RX_FLAG_DECRYPTED) { 564 switch (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2)) { 565 case MT_CIPHER_AES_CCMP: 566 case MT_CIPHER_CCMP_CCX: 567 case MT_CIPHER_CCMP_256: 568 insert_ccmp_hdr = 569 FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2); 570 fallthrough; 571 case MT_CIPHER_TKIP: 572 case MT_CIPHER_TKIP_NO_MIC: 573 case MT_CIPHER_GCMP: 574 case MT_CIPHER_GCMP_256: 575 status->iv[0] = data[5]; 576 status->iv[1] = data[4]; 577 status->iv[2] = data[3]; 578 status->iv[3] = data[2]; 579 status->iv[4] = data[1]; 580 status->iv[5] = data[0]; 581 break; 582 default: 583 break; 584 } 585 } 586 rxd += 4; 587 if ((u8 *)rxd - skb->data >= skb->len) 588 return -EINVAL; 589 } 590 591 if (rxd1 & MT_RXD1_NORMAL_GROUP_2) { 592 status->timestamp = le32_to_cpu(rxd[0]); 593 status->flag |= RX_FLAG_MACTIME_START; 594 595 if (!(rxd2 & MT_RXD2_NORMAL_NON_AMPDU)) { 596 status->flag |= RX_FLAG_AMPDU_DETAILS; 597 598 /* all subframes of an A-MPDU have the same timestamp */ 599 if (phy->rx_ampdu_ts != status->timestamp) { 600 if (!++phy->ampdu_ref) 601 phy->ampdu_ref++; 602 } 603 phy->rx_ampdu_ts = status->timestamp; 604 605 status->ampdu_ref = phy->ampdu_ref; 606 } 607 608 rxd += 4; 609 if ((u8 *)rxd - skb->data >= skb->len) 610 return -EINVAL; 611 } 612 613 /* RXD Group 3 - P-RXV */ 614 if (rxd1 & MT_RXD1_NORMAL_GROUP_3) { 615 u32 v3; 616 int ret; 617 618 rxv = rxd; 619 rxd += 4; 620 if ((u8 *)rxd - skb->data >= skb->len) 621 return -EINVAL; 622 623 v3 = le32_to_cpu(rxv[3]); 624 625 status->chains = mphy->antenna_mask; 626 status->chain_signal[0] = to_rssi(MT_PRXV_RCPI0, v3); 627 status->chain_signal[1] = to_rssi(MT_PRXV_RCPI1, v3); 628 status->chain_signal[2] = to_rssi(MT_PRXV_RCPI2, v3); 629 status->chain_signal[3] = to_rssi(MT_PRXV_RCPI3, v3); 630 631 /* RXD Group 5 - C-RXV */ 632 if (rxd1 & MT_RXD1_NORMAL_GROUP_5) { 633 rxd += 24; 634 if ((u8 *)rxd - skb->data >= skb->len) 635 return -EINVAL; 636 } 637 638 ret = mt7996_mac_fill_rx_rate(dev, status, sband, rxv, &mode); 639 if (ret < 0) 640 return ret; 641 } 642 643 amsdu_info = FIELD_GET(MT_RXD4_NORMAL_PAYLOAD_FORMAT, rxd4); 644 status->amsdu = !!amsdu_info; 645 if (status->amsdu) { 646 status->first_amsdu = amsdu_info == MT_RXD4_FIRST_AMSDU_FRAME; 647 status->last_amsdu = amsdu_info == MT_RXD4_LAST_AMSDU_FRAME; 648 } 649 650 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad; 651 if (hdr_trans && ieee80211_has_morefrags(fc)) { 652 if (mt7996_reverse_frag0_hdr_trans(skb, hdr_gap)) 653 return -EINVAL; 654 hdr_trans = false; 655 } else { 656 int pad_start = 0; 657 658 skb_pull(skb, hdr_gap); 659 if (!hdr_trans && status->amsdu && !(ieee80211_has_a4(fc) && is_mesh)) { 660 pad_start = ieee80211_get_hdrlen_from_skb(skb); 661 } else if (hdr_trans && (rxd2 & MT_RXD2_NORMAL_HDR_TRANS_ERROR)) { 662 /* When header translation failure is indicated, 663 * the hardware will insert an extra 2-byte field 664 * containing the data length after the protocol 665 * type field. This happens either when the LLC-SNAP 666 * pattern did not match, or if a VLAN header was 667 * detected. 668 */ 669 pad_start = 12; 670 if (get_unaligned_be16(skb->data + pad_start) == ETH_P_8021Q) 671 pad_start += 4; 672 else 673 pad_start = 0; 674 } 675 676 if (pad_start) { 677 memmove(skb->data + 2, skb->data, pad_start); 678 skb_pull(skb, 2); 679 } 680 } 681 682 if (!hdr_trans) { 683 struct ieee80211_hdr *hdr; 684 685 if (insert_ccmp_hdr) { 686 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1); 687 688 mt76_insert_ccmp_hdr(skb, key_id); 689 } 690 691 hdr = mt76_skb_get_hdr(skb); 692 fc = hdr->frame_control; 693 if (ieee80211_is_data_qos(fc)) { 694 u8 *qos = ieee80211_get_qos_ctl(hdr); 695 696 seq_ctrl = le16_to_cpu(hdr->seq_ctrl); 697 qos_ctl = *qos; 698 699 /* Mesh DA/SA/Length will be stripped after hardware 700 * de-amsdu, so here needs to clear amsdu present bit 701 * to mark it as a normal mesh frame. 702 */ 703 if (ieee80211_has_a4(fc) && is_mesh && status->amsdu) 704 *qos &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT; 705 } 706 skb_set_mac_header(skb, (unsigned char *)hdr - skb->data); 707 } else { 708 status->flag |= RX_FLAG_8023; 709 mt7996_wed_check_ppe(dev, &dev->mt76.q_rx[q], msta, skb, 710 *info); 711 } 712 713 if (rxv && !(status->flag & RX_FLAG_8023)) { 714 switch (status->encoding) { 715 case RX_ENC_EHT: 716 mt76_connac3_mac_decode_eht_radiotap(skb, rxv, mode); 717 break; 718 case RX_ENC_HE: 719 mt76_connac3_mac_decode_he_radiotap(skb, rxv, mode); 720 break; 721 default: 722 break; 723 } 724 } 725 726 if (!status->wcid || !ieee80211_is_data_qos(fc) || hw_aggr) 727 return 0; 728 729 status->aggr = unicast && 730 !ieee80211_is_qos_nullfunc(fc); 731 status->qos_ctl = qos_ctl; 732 status->seqno = IEEE80211_SEQ_TO_SN(seq_ctrl); 733 734 return 0; 735 } 736 737 static void 738 mt7996_mac_write_txwi_8023(struct mt7996_dev *dev, __le32 *txwi, 739 struct sk_buff *skb, struct mt76_wcid *wcid) 740 { 741 u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 742 u8 fc_type, fc_stype; 743 u16 ethertype; 744 bool wmm = false; 745 u32 val; 746 747 if (wcid->sta) { 748 struct ieee80211_sta *sta = wcid_to_sta(wcid); 749 750 wmm = sta->wme; 751 } 752 753 val = FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_3) | 754 FIELD_PREP(MT_TXD1_TID, tid); 755 756 ethertype = get_unaligned_be16(&skb->data[12]); 757 if (ethertype >= ETH_P_802_3_MIN) 758 val |= MT_TXD1_ETH_802_3; 759 760 txwi[1] |= cpu_to_le32(val); 761 762 fc_type = IEEE80211_FTYPE_DATA >> 2; 763 fc_stype = wmm ? IEEE80211_STYPE_QOS_DATA >> 4 : 0; 764 765 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) | 766 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype); 767 768 txwi[2] |= cpu_to_le32(val); 769 770 if (wcid->amsdu) 771 txwi[3] |= cpu_to_le32(MT_TXD3_HW_AMSDU); 772 } 773 774 static void 775 mt7996_mac_write_txwi_80211(struct mt7996_dev *dev, __le32 *txwi, 776 struct sk_buff *skb, 777 struct ieee80211_key_conf *key, 778 struct mt76_wcid *wcid) 779 { 780 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 781 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 782 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 783 bool multicast = is_multicast_ether_addr(hdr->addr1); 784 u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 785 __le16 fc = hdr->frame_control, sc = hdr->seq_ctrl; 786 u16 seqno = le16_to_cpu(sc); 787 u8 fc_type, fc_stype; 788 u32 val; 789 790 if (ieee80211_is_action(fc) && 791 mgmt->u.action.category == WLAN_CATEGORY_BACK && 792 mgmt->u.action.u.addba_req.action_code == WLAN_ACTION_ADDBA_REQ) 793 tid = MT_TX_ADDBA; 794 else if (ieee80211_is_mgmt(hdr->frame_control)) 795 tid = MT_TX_NORMAL; 796 797 val = FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) | 798 FIELD_PREP(MT_TXD1_HDR_INFO, 799 ieee80211_get_hdrlen_from_skb(skb) / 2) | 800 FIELD_PREP(MT_TXD1_TID, tid); 801 802 if (!ieee80211_is_data(fc) || multicast || 803 info->flags & IEEE80211_TX_CTL_USE_MINRATE) 804 val |= MT_TXD1_FIXED_RATE; 805 806 if (key && multicast && ieee80211_is_robust_mgmt_frame(skb)) { 807 val |= MT_TXD1_BIP; 808 txwi[3] &= ~cpu_to_le32(MT_TXD3_PROTECT_FRAME); 809 } 810 811 txwi[1] |= cpu_to_le32(val); 812 813 fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2; 814 fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4; 815 816 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) | 817 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype); 818 819 if (ieee80211_has_morefrags(fc) && ieee80211_is_first_frag(sc)) 820 val |= FIELD_PREP(MT_TXD2_FRAG, MT_TX_FRAG_FIRST); 821 else if (ieee80211_has_morefrags(fc) && !ieee80211_is_first_frag(sc)) 822 val |= FIELD_PREP(MT_TXD2_FRAG, MT_TX_FRAG_MID); 823 else if (!ieee80211_has_morefrags(fc) && !ieee80211_is_first_frag(sc)) 824 val |= FIELD_PREP(MT_TXD2_FRAG, MT_TX_FRAG_LAST); 825 else 826 val |= FIELD_PREP(MT_TXD2_FRAG, MT_TX_FRAG_NONE); 827 828 txwi[2] |= cpu_to_le32(val); 829 830 txwi[3] |= cpu_to_le32(FIELD_PREP(MT_TXD3_BCM, multicast)); 831 if (ieee80211_is_beacon(fc)) { 832 txwi[3] &= ~cpu_to_le32(MT_TXD3_SW_POWER_MGMT); 833 txwi[3] |= cpu_to_le32(MT_TXD3_REM_TX_COUNT); 834 } 835 836 if (multicast && ieee80211_vif_is_mld(info->control.vif)) { 837 val = MT_TXD3_SN_VALID | 838 FIELD_PREP(MT_TXD3_SEQ, IEEE80211_SEQ_TO_SN(seqno)); 839 txwi[3] |= cpu_to_le32(val); 840 } 841 842 if (info->flags & IEEE80211_TX_CTL_INJECTED) { 843 if (ieee80211_is_back_req(hdr->frame_control)) { 844 struct ieee80211_bar *bar; 845 846 bar = (struct ieee80211_bar *)skb->data; 847 seqno = le16_to_cpu(bar->start_seq_num); 848 } 849 850 val = MT_TXD3_SN_VALID | 851 FIELD_PREP(MT_TXD3_SEQ, IEEE80211_SEQ_TO_SN(seqno)); 852 txwi[3] |= cpu_to_le32(val); 853 txwi[3] &= ~cpu_to_le32(MT_TXD3_HW_AMSDU); 854 } 855 856 if (ieee80211_vif_is_mld(info->control.vif) && 857 (multicast || unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE)))) 858 txwi[5] |= cpu_to_le32(MT_TXD5_FL); 859 860 if (ieee80211_is_nullfunc(fc) && ieee80211_has_a4(fc) && 861 ieee80211_vif_is_mld(info->control.vif)) { 862 txwi[5] |= cpu_to_le32(MT_TXD5_FL); 863 txwi[6] |= cpu_to_le32(MT_TXD6_DIS_MAT); 864 } 865 866 if (!wcid->sta && ieee80211_is_mgmt(fc)) 867 txwi[6] |= cpu_to_le32(MT_TXD6_DIS_MAT); 868 } 869 870 void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi, 871 struct sk_buff *skb, struct mt76_wcid *wcid, 872 struct ieee80211_key_conf *key, int pid, 873 enum mt76_txq_id qid, u32 changed) 874 { 875 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 876 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 877 struct ieee80211_vif *vif = info->control.vif; 878 u8 band_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2; 879 u8 p_fmt, q_idx, omac_idx = 0, wmm_idx = 0; 880 bool is_8023 = info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP; 881 struct mt76_vif_link *mlink = NULL; 882 struct mt7996_vif *mvif; 883 unsigned int link_id; 884 u16 tx_count = 15; 885 u32 val; 886 bool inband_disc = !!(changed & (BSS_CHANGED_UNSOL_BCAST_PROBE_RESP | 887 BSS_CHANGED_FILS_DISCOVERY)); 888 bool beacon = !!(changed & (BSS_CHANGED_BEACON | 889 BSS_CHANGED_BEACON_ENABLED)) && (!inband_disc); 890 891 if (wcid != &dev->mt76.global_wcid) 892 link_id = wcid->link_id; 893 else 894 link_id = u32_get_bits(info->control.flags, 895 IEEE80211_TX_CTRL_MLO_LINK); 896 897 mvif = vif ? (struct mt7996_vif *)vif->drv_priv : NULL; 898 if (mvif) 899 mlink = rcu_dereference(mvif->mt76.link[link_id]); 900 901 if (mlink) { 902 omac_idx = mlink->omac_idx; 903 wmm_idx = mlink->wmm_idx; 904 band_idx = mlink->band_idx; 905 } 906 907 if (inband_disc) { 908 p_fmt = MT_TX_TYPE_FW; 909 q_idx = MT_LMAC_ALTX0; 910 } else if (beacon) { 911 p_fmt = MT_TX_TYPE_FW; 912 q_idx = MT_LMAC_BCN0; 913 } else if (qid >= MT_TXQ_PSD) { 914 p_fmt = MT_TX_TYPE_CT; 915 q_idx = MT_LMAC_ALTX0; 916 } else { 917 p_fmt = MT_TX_TYPE_CT; 918 q_idx = wmm_idx * MT7996_MAX_WMM_SETS + 919 mt76_connac_lmac_mapping(skb_get_queue_mapping(skb)); 920 } 921 922 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) | 923 FIELD_PREP(MT_TXD0_PKT_FMT, p_fmt) | 924 FIELD_PREP(MT_TXD0_Q_IDX, q_idx); 925 txwi[0] = cpu_to_le32(val); 926 927 val = FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) | 928 FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx); 929 930 if (band_idx) 931 val |= FIELD_PREP(MT_TXD1_TGID, band_idx); 932 933 txwi[1] = cpu_to_le32(val); 934 txwi[2] = 0; 935 936 val = MT_TXD3_SW_POWER_MGMT | 937 FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count); 938 if (key) 939 val |= MT_TXD3_PROTECT_FRAME; 940 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 941 val |= MT_TXD3_NO_ACK; 942 943 txwi[3] = cpu_to_le32(val); 944 txwi[4] = 0; 945 946 val = FIELD_PREP(MT_TXD5_PID, pid); 947 if (pid >= MT_PACKET_ID_FIRST) 948 val |= MT_TXD5_TX_STATUS_HOST; 949 txwi[5] = cpu_to_le32(val); 950 951 val = MT_TXD6_DAS; 952 if (q_idx >= MT_LMAC_ALTX0 && q_idx <= MT_LMAC_BCN0) 953 val |= MT_TXD6_DIS_MAT; 954 955 if (is_mt7996(&dev->mt76)) 956 val |= FIELD_PREP(MT_TXD6_MSDU_CNT, 1); 957 else if (is_8023 || !ieee80211_is_mgmt(hdr->frame_control)) 958 val |= FIELD_PREP(MT_TXD6_MSDU_CNT_V2, 1); 959 960 txwi[6] = cpu_to_le32(val); 961 txwi[7] = 0; 962 963 if (is_8023) 964 mt7996_mac_write_txwi_8023(dev, txwi, skb, wcid); 965 else 966 mt7996_mac_write_txwi_80211(dev, txwi, skb, key, wcid); 967 968 if (txwi[1] & cpu_to_le32(MT_TXD1_FIXED_RATE)) { 969 bool mcast = ieee80211_is_data(hdr->frame_control) && 970 is_multicast_ether_addr(hdr->addr1); 971 u8 idx = MT7996_BASIC_RATES_TBL; 972 973 if (mlink) { 974 if (mcast && mlink->mcast_rates_idx) 975 idx = mlink->mcast_rates_idx; 976 else if (beacon && mlink->beacon_rates_idx) 977 idx = mlink->beacon_rates_idx; 978 else 979 idx = mlink->basic_rates_idx; 980 } 981 982 val = FIELD_PREP(MT_TXD6_TX_RATE, idx) | MT_TXD6_FIXED_BW; 983 if (mcast) 984 val |= MT_TXD6_DIS_MAT; 985 txwi[6] |= cpu_to_le32(val); 986 txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE); 987 } 988 } 989 990 int mt7996_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, 991 enum mt76_txq_id qid, struct mt76_wcid *wcid, 992 struct ieee80211_sta *sta, 993 struct mt76_tx_info *tx_info) 994 { 995 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_info->skb->data; 996 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 997 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb); 998 struct ieee80211_key_conf *key = info->control.hw_key; 999 struct ieee80211_vif *vif = info->control.vif; 1000 struct mt76_connac_txp_common *txp; 1001 struct mt76_txwi_cache *t; 1002 int id, i, pid, nbuf = tx_info->nbuf - 1; 1003 bool is_8023 = info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP; 1004 u8 *txwi = (u8 *)txwi_ptr; 1005 1006 if (unlikely(tx_info->skb->len <= ETH_HLEN)) 1007 return -EINVAL; 1008 1009 if (!wcid) 1010 wcid = &dev->mt76.global_wcid; 1011 1012 t = (struct mt76_txwi_cache *)(txwi + mdev->drv->txwi_size); 1013 t->skb = tx_info->skb; 1014 1015 id = mt76_token_consume(mdev, &t); 1016 if (id < 0) 1017 return id; 1018 1019 pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb); 1020 mt7996_mac_write_txwi(dev, txwi_ptr, tx_info->skb, wcid, key, 1021 pid, qid, 0); 1022 1023 txp = (struct mt76_connac_txp_common *)(txwi + MT_TXD_SIZE); 1024 for (i = 0; i < nbuf; i++) { 1025 u16 len; 1026 1027 len = FIELD_PREP(MT_TXP_BUF_LEN, tx_info->buf[i + 1].len); 1028 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 1029 len |= FIELD_PREP(MT_TXP_DMA_ADDR_H, 1030 tx_info->buf[i + 1].addr >> 32); 1031 #endif 1032 1033 txp->fw.buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr); 1034 txp->fw.len[i] = cpu_to_le16(len); 1035 } 1036 txp->fw.nbuf = nbuf; 1037 1038 txp->fw.flags = 1039 cpu_to_le16(MT_CT_INFO_FROM_HOST | MT_CT_INFO_APPLY_TXD); 1040 1041 if (!key) 1042 txp->fw.flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME); 1043 1044 if (!is_8023 && ieee80211_is_mgmt(hdr->frame_control)) 1045 txp->fw.flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME); 1046 1047 if (vif) { 1048 struct mt7996_vif *mvif = (struct mt7996_vif *)vif->drv_priv; 1049 struct mt76_vif_link *mlink = NULL; 1050 1051 if (wcid->offchannel) 1052 mlink = rcu_dereference(mvif->mt76.offchannel_link); 1053 if (!mlink) 1054 mlink = &mvif->deflink.mt76; 1055 1056 txp->fw.bss_idx = mlink->idx; 1057 } 1058 1059 txp->fw.token = cpu_to_le16(id); 1060 txp->fw.rept_wds_wcid = cpu_to_le16(sta ? wcid->idx : 0xfff); 1061 1062 tx_info->skb = NULL; 1063 1064 /* pass partial skb header to fw */ 1065 tx_info->buf[1].len = MT_CT_PARSE_LEN; 1066 tx_info->buf[1].skip_unmap = true; 1067 tx_info->nbuf = MT_CT_DMA_BUF_NUM; 1068 1069 return 0; 1070 } 1071 1072 u32 mt7996_wed_init_buf(void *ptr, dma_addr_t phys, int token_id) 1073 { 1074 struct mt76_connac_fw_txp *txp = ptr + MT_TXD_SIZE; 1075 __le32 *txwi = ptr; 1076 u32 val; 1077 1078 memset(ptr, 0, MT_TXD_SIZE + sizeof(*txp)); 1079 1080 val = FIELD_PREP(MT_TXD0_TX_BYTES, MT_TXD_SIZE) | 1081 FIELD_PREP(MT_TXD0_PKT_FMT, MT_TX_TYPE_CT); 1082 txwi[0] = cpu_to_le32(val); 1083 1084 val = BIT(31) | 1085 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_3); 1086 txwi[1] = cpu_to_le32(val); 1087 1088 txp->token = cpu_to_le16(token_id); 1089 txp->nbuf = 1; 1090 txp->buf[0] = cpu_to_le32(phys + MT_TXD_SIZE + sizeof(*txp)); 1091 1092 return MT_TXD_SIZE + sizeof(*txp); 1093 } 1094 1095 static void 1096 mt7996_tx_check_aggr(struct ieee80211_sta *sta, struct sk_buff *skb) 1097 { 1098 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1099 bool is_8023 = info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP; 1100 struct mt7996_sta_link *msta_link; 1101 struct mt7996_sta *msta; 1102 u16 fc, tid; 1103 1104 if (!sta || !(sta->deflink.ht_cap.ht_supported || sta->deflink.he_cap.has_he)) 1105 return; 1106 1107 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 1108 if (tid >= 6) /* skip VO queue */ 1109 return; 1110 1111 if (is_8023) { 1112 fc = IEEE80211_FTYPE_DATA | 1113 (sta->wme ? IEEE80211_STYPE_QOS_DATA : IEEE80211_STYPE_DATA); 1114 } else { 1115 /* No need to get precise TID for Action/Management Frame, 1116 * since it will not meet the following Frame Control 1117 * condition anyway. 1118 */ 1119 1120 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1121 1122 fc = le16_to_cpu(hdr->frame_control) & 1123 (IEEE80211_FCTL_FTYPE | IEEE80211_FCTL_STYPE); 1124 } 1125 1126 if (unlikely(fc != (IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_DATA))) 1127 return; 1128 1129 msta = (struct mt7996_sta *)sta->drv_priv; 1130 msta_link = &msta->deflink; 1131 1132 if (!test_and_set_bit(tid, &msta_link->wcid.ampdu_state)) 1133 ieee80211_start_tx_ba_session(sta, tid, 0); 1134 } 1135 1136 static void 1137 mt7996_txwi_free(struct mt7996_dev *dev, struct mt76_txwi_cache *t, 1138 struct ieee80211_sta *sta, struct list_head *free_list) 1139 { 1140 struct mt76_dev *mdev = &dev->mt76; 1141 struct mt76_wcid *wcid; 1142 __le32 *txwi; 1143 u16 wcid_idx; 1144 1145 mt76_connac_txp_skb_unmap(mdev, t); 1146 if (!t->skb) 1147 goto out; 1148 1149 txwi = (__le32 *)mt76_get_txwi_ptr(mdev, t); 1150 if (sta) { 1151 wcid = (struct mt76_wcid *)sta->drv_priv; 1152 wcid_idx = wcid->idx; 1153 1154 if (likely(t->skb->protocol != cpu_to_be16(ETH_P_PAE))) 1155 mt7996_tx_check_aggr(sta, t->skb); 1156 } else { 1157 wcid_idx = le32_get_bits(txwi[9], MT_TXD9_WLAN_IDX); 1158 } 1159 1160 __mt76_tx_complete_skb(mdev, wcid_idx, t->skb, free_list); 1161 1162 out: 1163 t->skb = NULL; 1164 mt76_put_txwi(mdev, t); 1165 } 1166 1167 static void 1168 mt7996_mac_tx_free(struct mt7996_dev *dev, void *data, int len) 1169 { 1170 __le32 *tx_free = (__le32 *)data, *cur_info; 1171 struct mt76_dev *mdev = &dev->mt76; 1172 struct mt76_phy *phy2 = mdev->phys[MT_BAND1]; 1173 struct mt76_phy *phy3 = mdev->phys[MT_BAND2]; 1174 struct mt76_txwi_cache *txwi; 1175 struct ieee80211_sta *sta = NULL; 1176 struct mt76_wcid *wcid = NULL; 1177 LIST_HEAD(free_list); 1178 struct sk_buff *skb, *tmp; 1179 void *end = data + len; 1180 bool wake = false; 1181 u16 total, count = 0; 1182 1183 /* clean DMA queues and unmap buffers first */ 1184 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false); 1185 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false); 1186 if (phy2) { 1187 mt76_queue_tx_cleanup(dev, phy2->q_tx[MT_TXQ_PSD], false); 1188 mt76_queue_tx_cleanup(dev, phy2->q_tx[MT_TXQ_BE], false); 1189 } 1190 if (phy3) { 1191 mt76_queue_tx_cleanup(dev, phy3->q_tx[MT_TXQ_PSD], false); 1192 mt76_queue_tx_cleanup(dev, phy3->q_tx[MT_TXQ_BE], false); 1193 } 1194 1195 if (WARN_ON_ONCE(le32_get_bits(tx_free[1], MT_TXFREE1_VER) < 5)) 1196 return; 1197 1198 total = le32_get_bits(tx_free[0], MT_TXFREE0_MSDU_CNT); 1199 for (cur_info = &tx_free[2]; count < total; cur_info++) { 1200 u32 msdu, info; 1201 u8 i; 1202 1203 if (WARN_ON_ONCE((void *)cur_info >= end)) 1204 return; 1205 /* 1'b1: new wcid pair. 1206 * 1'b0: msdu_id with the same 'wcid pair' as above. 1207 */ 1208 info = le32_to_cpu(*cur_info); 1209 if (info & MT_TXFREE_INFO_PAIR) { 1210 struct mt7996_sta_link *msta_link; 1211 u16 idx; 1212 1213 idx = FIELD_GET(MT_TXFREE_INFO_WLAN_ID, info); 1214 wcid = rcu_dereference(dev->mt76.wcid[idx]); 1215 sta = wcid_to_sta(wcid); 1216 if (!sta) 1217 continue; 1218 1219 msta_link = container_of(wcid, struct mt7996_sta_link, 1220 wcid); 1221 mt76_wcid_add_poll(&dev->mt76, &msta_link->wcid); 1222 continue; 1223 } else if (info & MT_TXFREE_INFO_HEADER) { 1224 u32 tx_retries = 0, tx_failed = 0; 1225 1226 if (!wcid) 1227 continue; 1228 1229 tx_retries = 1230 FIELD_GET(MT_TXFREE_INFO_COUNT, info) - 1; 1231 tx_failed = tx_retries + 1232 !!FIELD_GET(MT_TXFREE_INFO_STAT, info); 1233 1234 wcid->stats.tx_retries += tx_retries; 1235 wcid->stats.tx_failed += tx_failed; 1236 continue; 1237 } 1238 1239 for (i = 0; i < 2; i++) { 1240 msdu = (info >> (15 * i)) & MT_TXFREE_INFO_MSDU_ID; 1241 if (msdu == MT_TXFREE_INFO_MSDU_ID) 1242 continue; 1243 1244 count++; 1245 txwi = mt76_token_release(mdev, msdu, &wake); 1246 if (!txwi) 1247 continue; 1248 1249 mt7996_txwi_free(dev, txwi, sta, &free_list); 1250 } 1251 } 1252 1253 mt7996_mac_sta_poll(dev); 1254 1255 if (wake) 1256 mt76_set_tx_blocked(&dev->mt76, false); 1257 1258 mt76_worker_schedule(&dev->mt76.tx_worker); 1259 1260 list_for_each_entry_safe(skb, tmp, &free_list, list) { 1261 skb_list_del_init(skb); 1262 napi_consume_skb(skb, 1); 1263 } 1264 } 1265 1266 static bool 1267 mt7996_mac_add_txs_skb(struct mt7996_dev *dev, struct mt76_wcid *wcid, 1268 int pid, __le32 *txs_data) 1269 { 1270 struct mt76_sta_stats *stats = &wcid->stats; 1271 struct ieee80211_supported_band *sband; 1272 struct mt76_dev *mdev = &dev->mt76; 1273 struct mt76_phy *mphy; 1274 struct ieee80211_tx_info *info; 1275 struct sk_buff_head list; 1276 struct rate_info rate = {}; 1277 struct sk_buff *skb = NULL; 1278 bool cck = false; 1279 u32 txrate, txs, mode, stbc; 1280 1281 txs = le32_to_cpu(txs_data[0]); 1282 1283 mt76_tx_status_lock(mdev, &list); 1284 1285 /* only report MPDU TXS */ 1286 if (le32_get_bits(txs_data[0], MT_TXS0_TXS_FORMAT) == 0) { 1287 skb = mt76_tx_status_skb_get(mdev, wcid, pid, &list); 1288 if (skb) { 1289 info = IEEE80211_SKB_CB(skb); 1290 if (!(txs & MT_TXS0_ACK_ERROR_MASK)) 1291 info->flags |= IEEE80211_TX_STAT_ACK; 1292 1293 info->status.ampdu_len = 1; 1294 info->status.ampdu_ack_len = 1295 !!(info->flags & IEEE80211_TX_STAT_ACK); 1296 1297 info->status.rates[0].idx = -1; 1298 } 1299 } 1300 1301 if (mtk_wed_device_active(&dev->mt76.mmio.wed) && wcid->sta) { 1302 struct ieee80211_sta *sta; 1303 u8 tid; 1304 1305 sta = wcid_to_sta(wcid); 1306 tid = FIELD_GET(MT_TXS0_TID, txs); 1307 ieee80211_refresh_tx_agg_session_timer(sta, tid); 1308 } 1309 1310 txrate = FIELD_GET(MT_TXS0_TX_RATE, txs); 1311 1312 rate.mcs = FIELD_GET(MT_TX_RATE_IDX, txrate); 1313 rate.nss = FIELD_GET(MT_TX_RATE_NSS, txrate) + 1; 1314 stbc = le32_get_bits(txs_data[3], MT_TXS3_RATE_STBC); 1315 1316 if (stbc && rate.nss > 1) 1317 rate.nss >>= 1; 1318 1319 if (rate.nss - 1 < ARRAY_SIZE(stats->tx_nss)) 1320 stats->tx_nss[rate.nss - 1]++; 1321 if (rate.mcs < ARRAY_SIZE(stats->tx_mcs)) 1322 stats->tx_mcs[rate.mcs]++; 1323 1324 mode = FIELD_GET(MT_TX_RATE_MODE, txrate); 1325 switch (mode) { 1326 case MT_PHY_TYPE_CCK: 1327 cck = true; 1328 fallthrough; 1329 case MT_PHY_TYPE_OFDM: 1330 mphy = mt76_dev_phy(mdev, wcid->phy_idx); 1331 1332 if (mphy->chandef.chan->band == NL80211_BAND_5GHZ) 1333 sband = &mphy->sband_5g.sband; 1334 else if (mphy->chandef.chan->band == NL80211_BAND_6GHZ) 1335 sband = &mphy->sband_6g.sband; 1336 else 1337 sband = &mphy->sband_2g.sband; 1338 1339 rate.mcs = mt76_get_rate(mphy->dev, sband, rate.mcs, cck); 1340 rate.legacy = sband->bitrates[rate.mcs].bitrate; 1341 break; 1342 case MT_PHY_TYPE_HT: 1343 case MT_PHY_TYPE_HT_GF: 1344 if (rate.mcs > 31) 1345 goto out; 1346 1347 rate.flags = RATE_INFO_FLAGS_MCS; 1348 if (wcid->rate.flags & RATE_INFO_FLAGS_SHORT_GI) 1349 rate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1350 break; 1351 case MT_PHY_TYPE_VHT: 1352 if (rate.mcs > 9) 1353 goto out; 1354 1355 rate.flags = RATE_INFO_FLAGS_VHT_MCS; 1356 if (wcid->rate.flags & RATE_INFO_FLAGS_SHORT_GI) 1357 rate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1358 break; 1359 case MT_PHY_TYPE_HE_SU: 1360 case MT_PHY_TYPE_HE_EXT_SU: 1361 case MT_PHY_TYPE_HE_TB: 1362 case MT_PHY_TYPE_HE_MU: 1363 if (rate.mcs > 11) 1364 goto out; 1365 1366 rate.he_gi = wcid->rate.he_gi; 1367 rate.he_dcm = FIELD_GET(MT_TX_RATE_DCM, txrate); 1368 rate.flags = RATE_INFO_FLAGS_HE_MCS; 1369 break; 1370 case MT_PHY_TYPE_EHT_SU: 1371 case MT_PHY_TYPE_EHT_TRIG: 1372 case MT_PHY_TYPE_EHT_MU: 1373 if (rate.mcs > 13) 1374 goto out; 1375 1376 rate.eht_gi = wcid->rate.eht_gi; 1377 rate.flags = RATE_INFO_FLAGS_EHT_MCS; 1378 break; 1379 default: 1380 goto out; 1381 } 1382 1383 stats->tx_mode[mode]++; 1384 1385 switch (FIELD_GET(MT_TXS0_BW, txs)) { 1386 case IEEE80211_STA_RX_BW_320: 1387 rate.bw = RATE_INFO_BW_320; 1388 stats->tx_bw[4]++; 1389 break; 1390 case IEEE80211_STA_RX_BW_160: 1391 rate.bw = RATE_INFO_BW_160; 1392 stats->tx_bw[3]++; 1393 break; 1394 case IEEE80211_STA_RX_BW_80: 1395 rate.bw = RATE_INFO_BW_80; 1396 stats->tx_bw[2]++; 1397 break; 1398 case IEEE80211_STA_RX_BW_40: 1399 rate.bw = RATE_INFO_BW_40; 1400 stats->tx_bw[1]++; 1401 break; 1402 default: 1403 rate.bw = RATE_INFO_BW_20; 1404 stats->tx_bw[0]++; 1405 break; 1406 } 1407 wcid->rate = rate; 1408 1409 out: 1410 if (skb) 1411 mt76_tx_status_skb_done(mdev, skb, &list); 1412 mt76_tx_status_unlock(mdev, &list); 1413 1414 return !!skb; 1415 } 1416 1417 static void mt7996_mac_add_txs(struct mt7996_dev *dev, void *data) 1418 { 1419 struct mt7996_sta_link *msta_link; 1420 struct mt76_wcid *wcid; 1421 __le32 *txs_data = data; 1422 u16 wcidx; 1423 u8 pid; 1424 1425 wcidx = le32_get_bits(txs_data[2], MT_TXS2_WCID); 1426 pid = le32_get_bits(txs_data[3], MT_TXS3_PID); 1427 1428 if (pid < MT_PACKET_ID_NO_SKB) 1429 return; 1430 1431 if (wcidx >= mt7996_wtbl_size(dev)) 1432 return; 1433 1434 rcu_read_lock(); 1435 1436 wcid = rcu_dereference(dev->mt76.wcid[wcidx]); 1437 if (!wcid) 1438 goto out; 1439 1440 mt7996_mac_add_txs_skb(dev, wcid, pid, txs_data); 1441 1442 if (!wcid->sta) 1443 goto out; 1444 1445 msta_link = container_of(wcid, struct mt7996_sta_link, wcid); 1446 mt76_wcid_add_poll(&dev->mt76, &msta_link->wcid); 1447 1448 out: 1449 rcu_read_unlock(); 1450 } 1451 1452 bool mt7996_rx_check(struct mt76_dev *mdev, void *data, int len) 1453 { 1454 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 1455 __le32 *rxd = (__le32 *)data; 1456 __le32 *end = (__le32 *)&rxd[len / 4]; 1457 enum rx_pkt_type type; 1458 1459 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); 1460 if (type != PKT_TYPE_NORMAL) { 1461 u32 sw_type = le32_get_bits(rxd[0], MT_RXD0_SW_PKT_TYPE_MASK); 1462 1463 if (unlikely((sw_type & MT_RXD0_SW_PKT_TYPE_MAP) == 1464 MT_RXD0_SW_PKT_TYPE_FRAME)) 1465 return true; 1466 } 1467 1468 switch (type) { 1469 case PKT_TYPE_TXRX_NOTIFY: 1470 mt7996_mac_tx_free(dev, data, len); 1471 return false; 1472 case PKT_TYPE_TXS: 1473 for (rxd += MT_TXS_HDR_SIZE; rxd + MT_TXS_SIZE <= end; rxd += MT_TXS_SIZE) 1474 mt7996_mac_add_txs(dev, rxd); 1475 return false; 1476 case PKT_TYPE_RX_FW_MONITOR: 1477 mt7996_debugfs_rx_fw_monitor(dev, data, len); 1478 return false; 1479 default: 1480 return true; 1481 } 1482 } 1483 1484 void mt7996_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 1485 struct sk_buff *skb, u32 *info) 1486 { 1487 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 1488 __le32 *rxd = (__le32 *)skb->data; 1489 __le32 *end = (__le32 *)&skb->data[skb->len]; 1490 enum rx_pkt_type type; 1491 1492 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); 1493 if (type != PKT_TYPE_NORMAL) { 1494 u32 sw_type = le32_get_bits(rxd[0], MT_RXD0_SW_PKT_TYPE_MASK); 1495 1496 if (unlikely((sw_type & MT_RXD0_SW_PKT_TYPE_MAP) == 1497 MT_RXD0_SW_PKT_TYPE_FRAME)) 1498 type = PKT_TYPE_NORMAL; 1499 } 1500 1501 switch (type) { 1502 case PKT_TYPE_TXRX_NOTIFY: 1503 if (mtk_wed_device_active(&dev->mt76.mmio.wed_hif2) && 1504 q == MT_RXQ_TXFREE_BAND2) { 1505 dev_kfree_skb(skb); 1506 break; 1507 } 1508 1509 mt7996_mac_tx_free(dev, skb->data, skb->len); 1510 napi_consume_skb(skb, 1); 1511 break; 1512 case PKT_TYPE_RX_EVENT: 1513 mt7996_mcu_rx_event(dev, skb); 1514 break; 1515 case PKT_TYPE_TXS: 1516 for (rxd += MT_TXS_HDR_SIZE; rxd + MT_TXS_SIZE <= end; rxd += MT_TXS_SIZE) 1517 mt7996_mac_add_txs(dev, rxd); 1518 dev_kfree_skb(skb); 1519 break; 1520 case PKT_TYPE_RX_FW_MONITOR: 1521 mt7996_debugfs_rx_fw_monitor(dev, skb->data, skb->len); 1522 dev_kfree_skb(skb); 1523 break; 1524 case PKT_TYPE_NORMAL: 1525 if (!mt7996_mac_fill_rx(dev, q, skb, info)) { 1526 mt76_rx(&dev->mt76, q, skb); 1527 return; 1528 } 1529 fallthrough; 1530 default: 1531 dev_kfree_skb(skb); 1532 break; 1533 } 1534 } 1535 1536 void mt7996_mac_cca_stats_reset(struct mt7996_phy *phy) 1537 { 1538 struct mt7996_dev *dev = phy->dev; 1539 u32 reg = MT_WF_PHYRX_BAND_RX_CTRL1(phy->mt76->band_idx); 1540 1541 mt76_clear(dev, reg, MT_WF_PHYRX_BAND_RX_CTRL1_STSCNT_EN); 1542 mt76_set(dev, reg, BIT(11) | BIT(9)); 1543 } 1544 1545 void mt7996_mac_reset_counters(struct mt7996_phy *phy) 1546 { 1547 struct mt7996_dev *dev = phy->dev; 1548 u8 band_idx = phy->mt76->band_idx; 1549 int i; 1550 1551 for (i = 0; i < 16; i++) 1552 mt76_rr(dev, MT_TX_AGG_CNT(band_idx, i)); 1553 1554 phy->mt76->survey_time = ktime_get_boottime(); 1555 1556 memset(phy->mt76->aggr_stats, 0, sizeof(phy->mt76->aggr_stats)); 1557 1558 /* reset airtime counters */ 1559 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(band_idx), 1560 MT_WF_RMAC_MIB_RXTIME_CLR); 1561 1562 mt7996_mcu_get_chan_mib_info(phy, true); 1563 } 1564 1565 void mt7996_mac_set_coverage_class(struct mt7996_phy *phy) 1566 { 1567 s16 coverage_class = phy->coverage_class; 1568 struct mt7996_dev *dev = phy->dev; 1569 struct mt7996_phy *phy2 = mt7996_phy2(dev); 1570 struct mt7996_phy *phy3 = mt7996_phy3(dev); 1571 u32 reg_offset; 1572 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | 1573 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); 1574 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | 1575 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28); 1576 u8 band_idx = phy->mt76->band_idx; 1577 int offset; 1578 1579 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state)) 1580 return; 1581 1582 if (phy2) 1583 coverage_class = max_t(s16, dev->phy.coverage_class, 1584 phy2->coverage_class); 1585 1586 if (phy3) 1587 coverage_class = max_t(s16, coverage_class, 1588 phy3->coverage_class); 1589 1590 offset = 3 * coverage_class; 1591 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | 1592 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); 1593 1594 mt76_wr(dev, MT_TMAC_CDTR(band_idx), cck + reg_offset); 1595 mt76_wr(dev, MT_TMAC_ODTR(band_idx), ofdm + reg_offset); 1596 } 1597 1598 void mt7996_mac_enable_nf(struct mt7996_dev *dev, u8 band) 1599 { 1600 mt76_set(dev, MT_WF_PHYRX_CSD_BAND_RXTD12(band), 1601 MT_WF_PHYRX_CSD_BAND_RXTD12_IRPI_SW_CLR_ONLY | 1602 MT_WF_PHYRX_CSD_BAND_RXTD12_IRPI_SW_CLR); 1603 1604 mt76_set(dev, MT_WF_PHYRX_BAND_RX_CTRL1(band), 1605 FIELD_PREP(MT_WF_PHYRX_BAND_RX_CTRL1_IPI_EN, 0x5)); 1606 } 1607 1608 static u8 1609 mt7996_phy_get_nf(struct mt7996_phy *phy, u8 band_idx) 1610 { 1611 static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 }; 1612 struct mt7996_dev *dev = phy->dev; 1613 u32 val, sum = 0, n = 0; 1614 int ant, i; 1615 1616 for (ant = 0; ant < hweight8(phy->mt76->antenna_mask); ant++) { 1617 u32 reg = MT_WF_PHYRX_CSD_IRPI(band_idx, ant); 1618 1619 for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) { 1620 val = mt76_rr(dev, reg); 1621 sum += val * nf_power[i]; 1622 n += val; 1623 } 1624 } 1625 1626 return n ? sum / n : 0; 1627 } 1628 1629 void mt7996_update_channel(struct mt76_phy *mphy) 1630 { 1631 struct mt7996_phy *phy = mphy->priv; 1632 struct mt76_channel_state *state = mphy->chan_state; 1633 int nf; 1634 1635 mt7996_mcu_get_chan_mib_info(phy, false); 1636 1637 nf = mt7996_phy_get_nf(phy, mphy->band_idx); 1638 if (!phy->noise) 1639 phy->noise = nf << 4; 1640 else if (nf) 1641 phy->noise += nf - (phy->noise >> 4); 1642 1643 state->noise = -(phy->noise >> 4); 1644 } 1645 1646 static bool 1647 mt7996_wait_reset_state(struct mt7996_dev *dev, u32 state) 1648 { 1649 bool ret; 1650 1651 ret = wait_event_timeout(dev->reset_wait, 1652 (READ_ONCE(dev->recovery.state) & state), 1653 MT7996_RESET_TIMEOUT); 1654 1655 WARN(!ret, "Timeout waiting for MCU reset state %x\n", state); 1656 return ret; 1657 } 1658 1659 static void 1660 mt7996_update_vif_beacon(void *priv, u8 *mac, struct ieee80211_vif *vif) 1661 { 1662 struct ieee80211_hw *hw = priv; 1663 1664 switch (vif->type) { 1665 case NL80211_IFTYPE_MESH_POINT: 1666 case NL80211_IFTYPE_ADHOC: 1667 case NL80211_IFTYPE_AP: 1668 mt7996_mcu_add_beacon(hw, vif, &vif->bss_conf); 1669 break; 1670 default: 1671 break; 1672 } 1673 } 1674 1675 static void 1676 mt7996_update_beacons(struct mt7996_dev *dev) 1677 { 1678 struct mt76_phy *phy2, *phy3; 1679 1680 ieee80211_iterate_active_interfaces(dev->mt76.hw, 1681 IEEE80211_IFACE_ITER_RESUME_ALL, 1682 mt7996_update_vif_beacon, dev->mt76.hw); 1683 1684 phy2 = dev->mt76.phys[MT_BAND1]; 1685 if (!phy2) 1686 return; 1687 1688 ieee80211_iterate_active_interfaces(phy2->hw, 1689 IEEE80211_IFACE_ITER_RESUME_ALL, 1690 mt7996_update_vif_beacon, phy2->hw); 1691 1692 phy3 = dev->mt76.phys[MT_BAND2]; 1693 if (!phy3) 1694 return; 1695 1696 ieee80211_iterate_active_interfaces(phy3->hw, 1697 IEEE80211_IFACE_ITER_RESUME_ALL, 1698 mt7996_update_vif_beacon, phy3->hw); 1699 } 1700 1701 void mt7996_tx_token_put(struct mt7996_dev *dev) 1702 { 1703 struct mt76_txwi_cache *txwi; 1704 int id; 1705 1706 spin_lock_bh(&dev->mt76.token_lock); 1707 idr_for_each_entry(&dev->mt76.token, txwi, id) { 1708 mt7996_txwi_free(dev, txwi, NULL, NULL); 1709 dev->mt76.token_count--; 1710 } 1711 spin_unlock_bh(&dev->mt76.token_lock); 1712 idr_destroy(&dev->mt76.token); 1713 } 1714 1715 static int 1716 mt7996_mac_restart(struct mt7996_dev *dev) 1717 { 1718 struct mt7996_phy *phy2, *phy3; 1719 struct mt76_dev *mdev = &dev->mt76; 1720 int i, ret; 1721 1722 phy2 = mt7996_phy2(dev); 1723 phy3 = mt7996_phy3(dev); 1724 1725 if (dev->hif2) { 1726 mt76_wr(dev, MT_INT1_MASK_CSR, 0x0); 1727 mt76_wr(dev, MT_INT1_SOURCE_CSR, ~0); 1728 } 1729 1730 if (dev_is_pci(mdev->dev)) { 1731 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0); 1732 if (dev->hif2) 1733 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE, 0x0); 1734 } 1735 1736 set_bit(MT76_RESET, &dev->mphy.state); 1737 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1738 wake_up(&dev->mt76.mcu.wait); 1739 if (phy2) 1740 set_bit(MT76_RESET, &phy2->mt76->state); 1741 if (phy3) 1742 set_bit(MT76_RESET, &phy3->mt76->state); 1743 1744 /* lock/unlock all queues to ensure that no tx is pending */ 1745 mt76_txq_schedule_all(&dev->mphy); 1746 if (phy2) 1747 mt76_txq_schedule_all(phy2->mt76); 1748 if (phy3) 1749 mt76_txq_schedule_all(phy3->mt76); 1750 1751 /* disable all tx/rx napi */ 1752 mt76_worker_disable(&dev->mt76.tx_worker); 1753 mt76_for_each_q_rx(mdev, i) { 1754 if (mtk_wed_device_active(&dev->mt76.mmio.wed) && 1755 mt76_queue_is_wed_rro(&mdev->q_rx[i])) 1756 continue; 1757 1758 if (mdev->q_rx[i].ndesc) 1759 napi_disable(&dev->mt76.napi[i]); 1760 } 1761 napi_disable(&dev->mt76.tx_napi); 1762 1763 /* token reinit */ 1764 mt7996_tx_token_put(dev); 1765 idr_init(&dev->mt76.token); 1766 1767 mt7996_dma_reset(dev, true); 1768 1769 mt76_for_each_q_rx(mdev, i) { 1770 if (mtk_wed_device_active(&dev->mt76.mmio.wed) && 1771 mt76_queue_is_wed_rro(&mdev->q_rx[i])) 1772 continue; 1773 1774 if (mdev->q_rx[i].ndesc) { 1775 napi_enable(&dev->mt76.napi[i]); 1776 local_bh_disable(); 1777 napi_schedule(&dev->mt76.napi[i]); 1778 local_bh_enable(); 1779 } 1780 } 1781 clear_bit(MT76_MCU_RESET, &dev->mphy.state); 1782 clear_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state); 1783 1784 mt76_wr(dev, MT_INT_MASK_CSR, dev->mt76.mmio.irqmask); 1785 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 1786 if (dev->hif2) { 1787 mt76_wr(dev, MT_INT1_MASK_CSR, dev->mt76.mmio.irqmask); 1788 mt76_wr(dev, MT_INT1_SOURCE_CSR, ~0); 1789 } 1790 if (dev_is_pci(mdev->dev)) { 1791 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff); 1792 if (dev->hif2) 1793 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE, 0xff); 1794 } 1795 1796 /* load firmware */ 1797 ret = mt7996_mcu_init_firmware(dev); 1798 if (ret) 1799 goto out; 1800 1801 /* set the necessary init items */ 1802 ret = mt7996_mcu_set_eeprom(dev); 1803 if (ret) 1804 goto out; 1805 1806 mt7996_mac_init(dev); 1807 mt7996_init_txpower(&dev->phy); 1808 mt7996_init_txpower(phy2); 1809 mt7996_init_txpower(phy3); 1810 ret = mt7996_txbf_init(dev); 1811 1812 if (test_bit(MT76_STATE_RUNNING, &dev->mphy.state)) { 1813 ret = mt7996_run(&dev->phy); 1814 if (ret) 1815 goto out; 1816 } 1817 1818 if (phy2 && test_bit(MT76_STATE_RUNNING, &phy2->mt76->state)) { 1819 ret = mt7996_run(phy2); 1820 if (ret) 1821 goto out; 1822 } 1823 1824 if (phy3 && test_bit(MT76_STATE_RUNNING, &phy3->mt76->state)) { 1825 ret = mt7996_run(phy3); 1826 if (ret) 1827 goto out; 1828 } 1829 1830 out: 1831 /* reset done */ 1832 clear_bit(MT76_RESET, &dev->mphy.state); 1833 if (phy2) 1834 clear_bit(MT76_RESET, &phy2->mt76->state); 1835 if (phy3) 1836 clear_bit(MT76_RESET, &phy3->mt76->state); 1837 1838 napi_enable(&dev->mt76.tx_napi); 1839 local_bh_disable(); 1840 napi_schedule(&dev->mt76.tx_napi); 1841 local_bh_enable(); 1842 1843 mt76_worker_enable(&dev->mt76.tx_worker); 1844 return ret; 1845 } 1846 1847 static void 1848 mt7996_mac_full_reset(struct mt7996_dev *dev) 1849 { 1850 struct mt7996_phy *phy2, *phy3; 1851 int i; 1852 1853 phy2 = mt7996_phy2(dev); 1854 phy3 = mt7996_phy3(dev); 1855 dev->recovery.hw_full_reset = true; 1856 1857 wake_up(&dev->mt76.mcu.wait); 1858 ieee80211_stop_queues(mt76_hw(dev)); 1859 if (phy2) 1860 ieee80211_stop_queues(phy2->mt76->hw); 1861 if (phy3) 1862 ieee80211_stop_queues(phy3->mt76->hw); 1863 1864 cancel_work_sync(&dev->wed_rro.work); 1865 cancel_delayed_work_sync(&dev->mphy.mac_work); 1866 if (phy2) 1867 cancel_delayed_work_sync(&phy2->mt76->mac_work); 1868 if (phy3) 1869 cancel_delayed_work_sync(&phy3->mt76->mac_work); 1870 1871 mutex_lock(&dev->mt76.mutex); 1872 for (i = 0; i < 10; i++) { 1873 if (!mt7996_mac_restart(dev)) 1874 break; 1875 } 1876 mutex_unlock(&dev->mt76.mutex); 1877 1878 if (i == 10) 1879 dev_err(dev->mt76.dev, "chip full reset failed\n"); 1880 1881 ieee80211_restart_hw(mt76_hw(dev)); 1882 if (phy2) 1883 ieee80211_restart_hw(phy2->mt76->hw); 1884 if (phy3) 1885 ieee80211_restart_hw(phy3->mt76->hw); 1886 1887 ieee80211_wake_queues(mt76_hw(dev)); 1888 if (phy2) 1889 ieee80211_wake_queues(phy2->mt76->hw); 1890 if (phy3) 1891 ieee80211_wake_queues(phy3->mt76->hw); 1892 1893 dev->recovery.hw_full_reset = false; 1894 ieee80211_queue_delayed_work(mt76_hw(dev), 1895 &dev->mphy.mac_work, 1896 MT7996_WATCHDOG_TIME); 1897 if (phy2) 1898 ieee80211_queue_delayed_work(phy2->mt76->hw, 1899 &phy2->mt76->mac_work, 1900 MT7996_WATCHDOG_TIME); 1901 if (phy3) 1902 ieee80211_queue_delayed_work(phy3->mt76->hw, 1903 &phy3->mt76->mac_work, 1904 MT7996_WATCHDOG_TIME); 1905 } 1906 1907 void mt7996_mac_reset_work(struct work_struct *work) 1908 { 1909 struct mt7996_phy *phy2, *phy3; 1910 struct mt7996_dev *dev; 1911 int i; 1912 1913 dev = container_of(work, struct mt7996_dev, reset_work); 1914 phy2 = mt7996_phy2(dev); 1915 phy3 = mt7996_phy3(dev); 1916 1917 /* chip full reset */ 1918 if (dev->recovery.restart) { 1919 /* disable WA/WM WDT */ 1920 mt76_clear(dev, MT_WFDMA0_MCU_HOST_INT_ENA, 1921 MT_MCU_CMD_WDT_MASK); 1922 1923 if (READ_ONCE(dev->recovery.state) & MT_MCU_CMD_WA_WDT) 1924 dev->recovery.wa_reset_count++; 1925 else 1926 dev->recovery.wm_reset_count++; 1927 1928 mt7996_mac_full_reset(dev); 1929 1930 /* enable mcu irq */ 1931 mt7996_irq_enable(dev, MT_INT_MCU_CMD); 1932 mt7996_irq_disable(dev, 0); 1933 1934 /* enable WA/WM WDT */ 1935 mt76_set(dev, MT_WFDMA0_MCU_HOST_INT_ENA, MT_MCU_CMD_WDT_MASK); 1936 1937 dev->recovery.state = MT_MCU_CMD_NORMAL_STATE; 1938 dev->recovery.restart = false; 1939 return; 1940 } 1941 1942 if (!(READ_ONCE(dev->recovery.state) & MT_MCU_CMD_STOP_DMA)) 1943 return; 1944 1945 dev_info(dev->mt76.dev,"\n%s L1 SER recovery start.", 1946 wiphy_name(dev->mt76.hw->wiphy)); 1947 1948 if (mtk_wed_device_active(&dev->mt76.mmio.wed_hif2)) 1949 mtk_wed_device_stop(&dev->mt76.mmio.wed_hif2); 1950 1951 if (mtk_wed_device_active(&dev->mt76.mmio.wed)) 1952 mtk_wed_device_stop(&dev->mt76.mmio.wed); 1953 1954 ieee80211_stop_queues(mt76_hw(dev)); 1955 if (phy2) 1956 ieee80211_stop_queues(phy2->mt76->hw); 1957 if (phy3) 1958 ieee80211_stop_queues(phy3->mt76->hw); 1959 1960 set_bit(MT76_RESET, &dev->mphy.state); 1961 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1962 wake_up(&dev->mt76.mcu.wait); 1963 1964 cancel_work_sync(&dev->wed_rro.work); 1965 cancel_delayed_work_sync(&dev->mphy.mac_work); 1966 if (phy2) { 1967 set_bit(MT76_RESET, &phy2->mt76->state); 1968 cancel_delayed_work_sync(&phy2->mt76->mac_work); 1969 } 1970 if (phy3) { 1971 set_bit(MT76_RESET, &phy3->mt76->state); 1972 cancel_delayed_work_sync(&phy3->mt76->mac_work); 1973 } 1974 mt76_worker_disable(&dev->mt76.tx_worker); 1975 mt76_for_each_q_rx(&dev->mt76, i) { 1976 if (mtk_wed_device_active(&dev->mt76.mmio.wed) && 1977 mt76_queue_is_wed_rro(&dev->mt76.q_rx[i])) 1978 continue; 1979 1980 napi_disable(&dev->mt76.napi[i]); 1981 } 1982 napi_disable(&dev->mt76.tx_napi); 1983 1984 mutex_lock(&dev->mt76.mutex); 1985 1986 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_STOPPED); 1987 1988 if (mt7996_wait_reset_state(dev, MT_MCU_CMD_RESET_DONE)) { 1989 mt7996_dma_reset(dev, false); 1990 1991 mt7996_tx_token_put(dev); 1992 idr_init(&dev->mt76.token); 1993 1994 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_INIT); 1995 mt7996_wait_reset_state(dev, MT_MCU_CMD_RECOVERY_DONE); 1996 } 1997 1998 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_RESET_DONE); 1999 mt7996_wait_reset_state(dev, MT_MCU_CMD_NORMAL_STATE); 2000 2001 /* enable DMA Tx/Tx and interrupt */ 2002 mt7996_dma_start(dev, false, false); 2003 2004 if (mtk_wed_device_active(&dev->mt76.mmio.wed)) { 2005 u32 wed_irq_mask = MT_INT_RRO_RX_DONE | MT_INT_TX_DONE_BAND2 | 2006 dev->mt76.mmio.irqmask; 2007 2008 if (mtk_wed_get_rx_capa(&dev->mt76.mmio.wed)) 2009 wed_irq_mask &= ~MT_INT_RX_DONE_RRO_IND; 2010 2011 mt76_wr(dev, MT_INT_MASK_CSR, wed_irq_mask); 2012 2013 mtk_wed_device_start_hw_rro(&dev->mt76.mmio.wed, wed_irq_mask, 2014 true); 2015 mt7996_irq_enable(dev, wed_irq_mask); 2016 mt7996_irq_disable(dev, 0); 2017 } 2018 2019 if (mtk_wed_device_active(&dev->mt76.mmio.wed_hif2)) { 2020 mt76_wr(dev, MT_INT_PCIE1_MASK_CSR, MT_INT_TX_RX_DONE_EXT); 2021 mtk_wed_device_start(&dev->mt76.mmio.wed_hif2, 2022 MT_INT_TX_RX_DONE_EXT); 2023 } 2024 2025 clear_bit(MT76_MCU_RESET, &dev->mphy.state); 2026 clear_bit(MT76_RESET, &dev->mphy.state); 2027 if (phy2) 2028 clear_bit(MT76_RESET, &phy2->mt76->state); 2029 if (phy3) 2030 clear_bit(MT76_RESET, &phy3->mt76->state); 2031 2032 mt76_for_each_q_rx(&dev->mt76, i) { 2033 if (mtk_wed_device_active(&dev->mt76.mmio.wed) && 2034 mt76_queue_is_wed_rro(&dev->mt76.q_rx[i])) 2035 continue; 2036 2037 napi_enable(&dev->mt76.napi[i]); 2038 local_bh_disable(); 2039 napi_schedule(&dev->mt76.napi[i]); 2040 local_bh_enable(); 2041 } 2042 2043 tasklet_schedule(&dev->mt76.irq_tasklet); 2044 2045 mt76_worker_enable(&dev->mt76.tx_worker); 2046 2047 napi_enable(&dev->mt76.tx_napi); 2048 local_bh_disable(); 2049 napi_schedule(&dev->mt76.tx_napi); 2050 local_bh_enable(); 2051 2052 ieee80211_wake_queues(mt76_hw(dev)); 2053 if (phy2) 2054 ieee80211_wake_queues(phy2->mt76->hw); 2055 if (phy3) 2056 ieee80211_wake_queues(phy3->mt76->hw); 2057 2058 mutex_unlock(&dev->mt76.mutex); 2059 2060 mt7996_update_beacons(dev); 2061 2062 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work, 2063 MT7996_WATCHDOG_TIME); 2064 if (phy2) 2065 ieee80211_queue_delayed_work(phy2->mt76->hw, 2066 &phy2->mt76->mac_work, 2067 MT7996_WATCHDOG_TIME); 2068 if (phy3) 2069 ieee80211_queue_delayed_work(phy3->mt76->hw, 2070 &phy3->mt76->mac_work, 2071 MT7996_WATCHDOG_TIME); 2072 dev_info(dev->mt76.dev,"\n%s L1 SER recovery completed.", 2073 wiphy_name(dev->mt76.hw->wiphy)); 2074 } 2075 2076 /* firmware coredump */ 2077 void mt7996_mac_dump_work(struct work_struct *work) 2078 { 2079 const struct mt7996_mem_region *mem_region; 2080 struct mt7996_crash_data *crash_data; 2081 struct mt7996_dev *dev; 2082 struct mt7996_mem_hdr *hdr; 2083 size_t buf_len; 2084 int i; 2085 u32 num; 2086 u8 *buf; 2087 2088 dev = container_of(work, struct mt7996_dev, dump_work); 2089 2090 mutex_lock(&dev->dump_mutex); 2091 2092 crash_data = mt7996_coredump_new(dev); 2093 if (!crash_data) { 2094 mutex_unlock(&dev->dump_mutex); 2095 goto skip_coredump; 2096 } 2097 2098 mem_region = mt7996_coredump_get_mem_layout(dev, &num); 2099 if (!mem_region || !crash_data->memdump_buf_len) { 2100 mutex_unlock(&dev->dump_mutex); 2101 goto skip_memdump; 2102 } 2103 2104 buf = crash_data->memdump_buf; 2105 buf_len = crash_data->memdump_buf_len; 2106 2107 /* dumping memory content... */ 2108 memset(buf, 0, buf_len); 2109 for (i = 0; i < num; i++) { 2110 if (mem_region->len > buf_len) { 2111 dev_warn(dev->mt76.dev, "%s len %zu is too large\n", 2112 mem_region->name, mem_region->len); 2113 break; 2114 } 2115 2116 /* reserve space for the header */ 2117 hdr = (void *)buf; 2118 buf += sizeof(*hdr); 2119 buf_len -= sizeof(*hdr); 2120 2121 mt7996_memcpy_fromio(dev, buf, mem_region->start, 2122 mem_region->len); 2123 2124 hdr->start = mem_region->start; 2125 hdr->len = mem_region->len; 2126 2127 if (!mem_region->len) 2128 /* note: the header remains, just with zero length */ 2129 break; 2130 2131 buf += mem_region->len; 2132 buf_len -= mem_region->len; 2133 2134 mem_region++; 2135 } 2136 2137 mutex_unlock(&dev->dump_mutex); 2138 2139 skip_memdump: 2140 mt7996_coredump_submit(dev); 2141 skip_coredump: 2142 queue_work(dev->mt76.wq, &dev->reset_work); 2143 } 2144 2145 void mt7996_reset(struct mt7996_dev *dev) 2146 { 2147 if (!dev->recovery.hw_init_done) 2148 return; 2149 2150 if (dev->recovery.hw_full_reset) 2151 return; 2152 2153 /* wm/wa exception: do full recovery */ 2154 if (READ_ONCE(dev->recovery.state) & MT_MCU_CMD_WDT_MASK) { 2155 dev->recovery.restart = true; 2156 dev_info(dev->mt76.dev, 2157 "%s indicated firmware crash, attempting recovery\n", 2158 wiphy_name(dev->mt76.hw->wiphy)); 2159 2160 mt7996_irq_disable(dev, MT_INT_MCU_CMD); 2161 queue_work(dev->mt76.wq, &dev->dump_work); 2162 return; 2163 } 2164 2165 queue_work(dev->mt76.wq, &dev->reset_work); 2166 wake_up(&dev->reset_wait); 2167 } 2168 2169 void mt7996_mac_update_stats(struct mt7996_phy *phy) 2170 { 2171 struct mt76_mib_stats *mib = &phy->mib; 2172 struct mt7996_dev *dev = phy->dev; 2173 u8 band_idx = phy->mt76->band_idx; 2174 u32 cnt; 2175 int i; 2176 2177 cnt = mt76_rr(dev, MT_MIB_RSCR1(band_idx)); 2178 mib->fcs_err_cnt += cnt; 2179 2180 cnt = mt76_rr(dev, MT_MIB_RSCR33(band_idx)); 2181 mib->rx_fifo_full_cnt += cnt; 2182 2183 cnt = mt76_rr(dev, MT_MIB_RSCR31(band_idx)); 2184 mib->rx_mpdu_cnt += cnt; 2185 2186 cnt = mt76_rr(dev, MT_MIB_SDR6(band_idx)); 2187 mib->channel_idle_cnt += FIELD_GET(MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK, cnt); 2188 2189 cnt = mt76_rr(dev, MT_MIB_RVSR0(band_idx)); 2190 mib->rx_vector_mismatch_cnt += cnt; 2191 2192 cnt = mt76_rr(dev, MT_MIB_RSCR35(band_idx)); 2193 mib->rx_delimiter_fail_cnt += cnt; 2194 2195 cnt = mt76_rr(dev, MT_MIB_RSCR36(band_idx)); 2196 mib->rx_len_mismatch_cnt += cnt; 2197 2198 cnt = mt76_rr(dev, MT_MIB_TSCR0(band_idx)); 2199 mib->tx_ampdu_cnt += cnt; 2200 2201 cnt = mt76_rr(dev, MT_MIB_TSCR2(band_idx)); 2202 mib->tx_stop_q_empty_cnt += cnt; 2203 2204 cnt = mt76_rr(dev, MT_MIB_TSCR3(band_idx)); 2205 mib->tx_mpdu_attempts_cnt += cnt; 2206 2207 cnt = mt76_rr(dev, MT_MIB_TSCR4(band_idx)); 2208 mib->tx_mpdu_success_cnt += cnt; 2209 2210 cnt = mt76_rr(dev, MT_MIB_RSCR27(band_idx)); 2211 mib->rx_ampdu_cnt += cnt; 2212 2213 cnt = mt76_rr(dev, MT_MIB_RSCR28(band_idx)); 2214 mib->rx_ampdu_bytes_cnt += cnt; 2215 2216 cnt = mt76_rr(dev, MT_MIB_RSCR29(band_idx)); 2217 mib->rx_ampdu_valid_subframe_cnt += cnt; 2218 2219 cnt = mt76_rr(dev, MT_MIB_RSCR30(band_idx)); 2220 mib->rx_ampdu_valid_subframe_bytes_cnt += cnt; 2221 2222 cnt = mt76_rr(dev, MT_MIB_SDR27(band_idx)); 2223 mib->tx_rwp_fail_cnt += FIELD_GET(MT_MIB_SDR27_TX_RWP_FAIL_CNT, cnt); 2224 2225 cnt = mt76_rr(dev, MT_MIB_SDR28(band_idx)); 2226 mib->tx_rwp_need_cnt += FIELD_GET(MT_MIB_SDR28_TX_RWP_NEED_CNT, cnt); 2227 2228 cnt = mt76_rr(dev, MT_UMIB_RPDCR(band_idx)); 2229 mib->rx_pfdrop_cnt += cnt; 2230 2231 cnt = mt76_rr(dev, MT_MIB_RVSR1(band_idx)); 2232 mib->rx_vec_queue_overflow_drop_cnt += cnt; 2233 2234 cnt = mt76_rr(dev, MT_MIB_TSCR1(band_idx)); 2235 mib->rx_ba_cnt += cnt; 2236 2237 cnt = mt76_rr(dev, MT_MIB_BSCR0(band_idx)); 2238 mib->tx_bf_ebf_ppdu_cnt += cnt; 2239 2240 cnt = mt76_rr(dev, MT_MIB_BSCR1(band_idx)); 2241 mib->tx_bf_ibf_ppdu_cnt += cnt; 2242 2243 cnt = mt76_rr(dev, MT_MIB_BSCR2(band_idx)); 2244 mib->tx_mu_bf_cnt += cnt; 2245 2246 cnt = mt76_rr(dev, MT_MIB_TSCR5(band_idx)); 2247 mib->tx_mu_mpdu_cnt += cnt; 2248 2249 cnt = mt76_rr(dev, MT_MIB_TSCR6(band_idx)); 2250 mib->tx_mu_acked_mpdu_cnt += cnt; 2251 2252 cnt = mt76_rr(dev, MT_MIB_TSCR7(band_idx)); 2253 mib->tx_su_acked_mpdu_cnt += cnt; 2254 2255 cnt = mt76_rr(dev, MT_MIB_BSCR3(band_idx)); 2256 mib->tx_bf_rx_fb_ht_cnt += cnt; 2257 mib->tx_bf_rx_fb_all_cnt += cnt; 2258 2259 cnt = mt76_rr(dev, MT_MIB_BSCR4(band_idx)); 2260 mib->tx_bf_rx_fb_vht_cnt += cnt; 2261 mib->tx_bf_rx_fb_all_cnt += cnt; 2262 2263 cnt = mt76_rr(dev, MT_MIB_BSCR5(band_idx)); 2264 mib->tx_bf_rx_fb_he_cnt += cnt; 2265 mib->tx_bf_rx_fb_all_cnt += cnt; 2266 2267 cnt = mt76_rr(dev, MT_MIB_BSCR6(band_idx)); 2268 mib->tx_bf_rx_fb_eht_cnt += cnt; 2269 mib->tx_bf_rx_fb_all_cnt += cnt; 2270 2271 cnt = mt76_rr(dev, MT_ETBF_RX_FB_CONT(band_idx)); 2272 mib->tx_bf_rx_fb_bw = FIELD_GET(MT_ETBF_RX_FB_BW, cnt); 2273 mib->tx_bf_rx_fb_nc_cnt += FIELD_GET(MT_ETBF_RX_FB_NC, cnt); 2274 mib->tx_bf_rx_fb_nr_cnt += FIELD_GET(MT_ETBF_RX_FB_NR, cnt); 2275 2276 cnt = mt76_rr(dev, MT_MIB_BSCR7(band_idx)); 2277 mib->tx_bf_fb_trig_cnt += cnt; 2278 2279 cnt = mt76_rr(dev, MT_MIB_BSCR17(band_idx)); 2280 mib->tx_bf_fb_cpl_cnt += cnt; 2281 2282 for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) { 2283 cnt = mt76_rr(dev, MT_PLE_AMSDU_PACK_MSDU_CNT(i)); 2284 mib->tx_amsdu[i] += cnt; 2285 mib->tx_amsdu_cnt += cnt; 2286 } 2287 2288 /* rts count */ 2289 cnt = mt76_rr(dev, MT_MIB_BTSCR5(band_idx)); 2290 mib->rts_cnt += cnt; 2291 2292 /* rts retry count */ 2293 cnt = mt76_rr(dev, MT_MIB_BTSCR6(band_idx)); 2294 mib->rts_retries_cnt += cnt; 2295 2296 /* ba miss count */ 2297 cnt = mt76_rr(dev, MT_MIB_BTSCR0(band_idx)); 2298 mib->ba_miss_cnt += cnt; 2299 2300 /* ack fail count */ 2301 cnt = mt76_rr(dev, MT_MIB_BFTFCR(band_idx)); 2302 mib->ack_fail_cnt += cnt; 2303 2304 for (i = 0; i < 16; i++) { 2305 cnt = mt76_rr(dev, MT_TX_AGG_CNT(band_idx, i)); 2306 phy->mt76->aggr_stats[i] += cnt; 2307 } 2308 } 2309 2310 void mt7996_mac_sta_rc_work(struct work_struct *work) 2311 { 2312 struct mt7996_dev *dev = container_of(work, struct mt7996_dev, rc_work); 2313 struct ieee80211_bss_conf *link_conf; 2314 struct ieee80211_link_sta *link_sta; 2315 struct mt7996_sta_link *msta_link; 2316 struct mt7996_vif_link *link; 2317 struct mt76_vif_link *mlink; 2318 struct ieee80211_sta *sta; 2319 struct ieee80211_vif *vif; 2320 struct mt7996_sta *msta; 2321 struct mt7996_vif *mvif; 2322 LIST_HEAD(list); 2323 u32 changed; 2324 u8 link_id; 2325 2326 rcu_read_lock(); 2327 spin_lock_bh(&dev->mt76.sta_poll_lock); 2328 list_splice_init(&dev->sta_rc_list, &list); 2329 2330 while (!list_empty(&list)) { 2331 msta_link = list_first_entry(&list, struct mt7996_sta_link, 2332 rc_list); 2333 list_del_init(&msta_link->rc_list); 2334 2335 changed = msta_link->changed; 2336 msta_link->changed = 0; 2337 2338 sta = wcid_to_sta(&msta_link->wcid); 2339 link_id = msta_link->wcid.link_id; 2340 msta = msta_link->sta; 2341 mvif = msta->vif; 2342 vif = container_of((void *)mvif, struct ieee80211_vif, drv_priv); 2343 2344 mlink = rcu_dereference(mvif->mt76.link[link_id]); 2345 if (!mlink) 2346 continue; 2347 2348 link_sta = rcu_dereference(sta->link[link_id]); 2349 if (!link_sta) 2350 continue; 2351 2352 link_conf = rcu_dereference(vif->link_conf[link_id]); 2353 if (!link_conf) 2354 continue; 2355 2356 spin_unlock_bh(&dev->mt76.sta_poll_lock); 2357 2358 link = (struct mt7996_vif_link *)mlink; 2359 2360 if (changed & (IEEE80211_RC_SUPP_RATES_CHANGED | 2361 IEEE80211_RC_NSS_CHANGED | 2362 IEEE80211_RC_BW_CHANGED)) 2363 mt7996_mcu_add_rate_ctrl(dev, vif, link_conf, 2364 link_sta, link, msta_link, 2365 true); 2366 2367 if (changed & IEEE80211_RC_SMPS_CHANGED) 2368 mt7996_mcu_set_fixed_field(dev, link_sta, link, 2369 msta_link, NULL, 2370 RATE_PARAM_MMPS_UPDATE); 2371 2372 spin_lock_bh(&dev->mt76.sta_poll_lock); 2373 } 2374 2375 spin_unlock_bh(&dev->mt76.sta_poll_lock); 2376 rcu_read_unlock(); 2377 } 2378 2379 void mt7996_mac_work(struct work_struct *work) 2380 { 2381 struct mt7996_phy *phy; 2382 struct mt76_phy *mphy; 2383 2384 mphy = (struct mt76_phy *)container_of(work, struct mt76_phy, 2385 mac_work.work); 2386 phy = mphy->priv; 2387 2388 mutex_lock(&mphy->dev->mutex); 2389 2390 mt76_update_survey(mphy); 2391 if (++mphy->mac_work_count == 5) { 2392 mphy->mac_work_count = 0; 2393 2394 mt7996_mac_update_stats(phy); 2395 2396 mt7996_mcu_get_all_sta_info(phy, UNI_ALL_STA_TXRX_RATE); 2397 if (mtk_wed_device_active(&phy->dev->mt76.mmio.wed)) { 2398 mt7996_mcu_get_all_sta_info(phy, UNI_ALL_STA_TXRX_ADM_STAT); 2399 mt7996_mcu_get_all_sta_info(phy, UNI_ALL_STA_TXRX_MSDU_COUNT); 2400 } 2401 } 2402 2403 mutex_unlock(&mphy->dev->mutex); 2404 2405 mt76_tx_status_check(mphy->dev, false); 2406 2407 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, 2408 MT7996_WATCHDOG_TIME); 2409 } 2410 2411 static void mt7996_dfs_stop_radar_detector(struct mt7996_phy *phy) 2412 { 2413 struct mt7996_dev *dev = phy->dev; 2414 2415 if (phy->rdd_state & BIT(0)) 2416 mt7996_mcu_rdd_cmd(dev, RDD_STOP, 0, 2417 MT_RX_SEL0, 0); 2418 if (phy->rdd_state & BIT(1)) 2419 mt7996_mcu_rdd_cmd(dev, RDD_STOP, 1, 2420 MT_RX_SEL0, 0); 2421 } 2422 2423 static int mt7996_dfs_start_rdd(struct mt7996_dev *dev, int chain) 2424 { 2425 int err, region; 2426 2427 switch (dev->mt76.region) { 2428 case NL80211_DFS_ETSI: 2429 region = 0; 2430 break; 2431 case NL80211_DFS_JP: 2432 region = 2; 2433 break; 2434 case NL80211_DFS_FCC: 2435 default: 2436 region = 1; 2437 break; 2438 } 2439 2440 err = mt7996_mcu_rdd_cmd(dev, RDD_START, chain, 2441 MT_RX_SEL0, region); 2442 if (err < 0) 2443 return err; 2444 2445 return mt7996_mcu_rdd_cmd(dev, RDD_DET_MODE, chain, 2446 MT_RX_SEL0, 1); 2447 } 2448 2449 static int mt7996_dfs_start_radar_detector(struct mt7996_phy *phy) 2450 { 2451 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 2452 struct mt7996_dev *dev = phy->dev; 2453 u8 band_idx = phy->mt76->band_idx; 2454 int err; 2455 2456 /* start CAC */ 2457 err = mt7996_mcu_rdd_cmd(dev, RDD_CAC_START, band_idx, 2458 MT_RX_SEL0, 0); 2459 if (err < 0) 2460 return err; 2461 2462 err = mt7996_dfs_start_rdd(dev, band_idx); 2463 if (err < 0) 2464 return err; 2465 2466 phy->rdd_state |= BIT(band_idx); 2467 2468 if (chandef->width == NL80211_CHAN_WIDTH_160 || 2469 chandef->width == NL80211_CHAN_WIDTH_80P80) { 2470 err = mt7996_dfs_start_rdd(dev, 1); 2471 if (err < 0) 2472 return err; 2473 2474 phy->rdd_state |= BIT(1); 2475 } 2476 2477 return 0; 2478 } 2479 2480 static int 2481 mt7996_dfs_init_radar_specs(struct mt7996_phy *phy) 2482 { 2483 const struct mt7996_dfs_radar_spec *radar_specs; 2484 struct mt7996_dev *dev = phy->dev; 2485 int err, i; 2486 2487 switch (dev->mt76.region) { 2488 case NL80211_DFS_FCC: 2489 radar_specs = &fcc_radar_specs; 2490 err = mt7996_mcu_set_fcc5_lpn(dev, 8); 2491 if (err < 0) 2492 return err; 2493 break; 2494 case NL80211_DFS_ETSI: 2495 radar_specs = &etsi_radar_specs; 2496 break; 2497 case NL80211_DFS_JP: 2498 radar_specs = &jp_radar_specs; 2499 break; 2500 default: 2501 return -EINVAL; 2502 } 2503 2504 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) { 2505 err = mt7996_mcu_set_radar_th(dev, i, 2506 &radar_specs->radar_pattern[i]); 2507 if (err < 0) 2508 return err; 2509 } 2510 2511 return mt7996_mcu_set_pulse_th(dev, &radar_specs->pulse_th); 2512 } 2513 2514 int mt7996_dfs_init_radar_detector(struct mt7996_phy *phy) 2515 { 2516 struct mt7996_dev *dev = phy->dev; 2517 enum mt76_dfs_state dfs_state, prev_state; 2518 int err; 2519 2520 prev_state = phy->mt76->dfs_state; 2521 dfs_state = mt76_phy_dfs_state(phy->mt76); 2522 2523 if (prev_state == dfs_state) 2524 return 0; 2525 2526 if (prev_state == MT_DFS_STATE_UNKNOWN) 2527 mt7996_dfs_stop_radar_detector(phy); 2528 2529 if (dfs_state == MT_DFS_STATE_DISABLED) 2530 goto stop; 2531 2532 if (prev_state <= MT_DFS_STATE_DISABLED) { 2533 err = mt7996_dfs_init_radar_specs(phy); 2534 if (err < 0) 2535 return err; 2536 2537 err = mt7996_dfs_start_radar_detector(phy); 2538 if (err < 0) 2539 return err; 2540 2541 phy->mt76->dfs_state = MT_DFS_STATE_CAC; 2542 } 2543 2544 if (dfs_state == MT_DFS_STATE_CAC) 2545 return 0; 2546 2547 err = mt7996_mcu_rdd_cmd(dev, RDD_CAC_END, 2548 phy->mt76->band_idx, MT_RX_SEL0, 0); 2549 if (err < 0) { 2550 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN; 2551 return err; 2552 } 2553 2554 phy->mt76->dfs_state = MT_DFS_STATE_ACTIVE; 2555 return 0; 2556 2557 stop: 2558 err = mt7996_mcu_rdd_cmd(dev, RDD_NORMAL_START, 2559 phy->mt76->band_idx, MT_RX_SEL0, 0); 2560 if (err < 0) 2561 return err; 2562 2563 mt7996_dfs_stop_radar_detector(phy); 2564 phy->mt76->dfs_state = MT_DFS_STATE_DISABLED; 2565 2566 return 0; 2567 } 2568 2569 static int 2570 mt7996_mac_twt_duration_align(int duration) 2571 { 2572 return duration << 8; 2573 } 2574 2575 static u64 2576 mt7996_mac_twt_sched_list_add(struct mt7996_dev *dev, 2577 struct mt7996_twt_flow *flow) 2578 { 2579 struct mt7996_twt_flow *iter, *iter_next; 2580 u32 duration = flow->duration << 8; 2581 u64 start_tsf; 2582 2583 iter = list_first_entry_or_null(&dev->twt_list, 2584 struct mt7996_twt_flow, list); 2585 if (!iter || !iter->sched || iter->start_tsf > duration) { 2586 /* add flow as first entry in the list */ 2587 list_add(&flow->list, &dev->twt_list); 2588 return 0; 2589 } 2590 2591 list_for_each_entry_safe(iter, iter_next, &dev->twt_list, list) { 2592 start_tsf = iter->start_tsf + 2593 mt7996_mac_twt_duration_align(iter->duration); 2594 if (list_is_last(&iter->list, &dev->twt_list)) 2595 break; 2596 2597 if (!iter_next->sched || 2598 iter_next->start_tsf > start_tsf + duration) { 2599 list_add(&flow->list, &iter->list); 2600 goto out; 2601 } 2602 } 2603 2604 /* add flow as last entry in the list */ 2605 list_add_tail(&flow->list, &dev->twt_list); 2606 out: 2607 return start_tsf; 2608 } 2609 2610 static int mt7996_mac_check_twt_req(struct ieee80211_twt_setup *twt) 2611 { 2612 struct ieee80211_twt_params *twt_agrt; 2613 u64 interval, duration; 2614 u16 mantissa; 2615 u8 exp; 2616 2617 /* only individual agreement supported */ 2618 if (twt->control & IEEE80211_TWT_CONTROL_NEG_TYPE_BROADCAST) 2619 return -EOPNOTSUPP; 2620 2621 /* only 256us unit supported */ 2622 if (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT) 2623 return -EOPNOTSUPP; 2624 2625 twt_agrt = (struct ieee80211_twt_params *)twt->params; 2626 2627 /* explicit agreement not supported */ 2628 if (!(twt_agrt->req_type & cpu_to_le16(IEEE80211_TWT_REQTYPE_IMPLICIT))) 2629 return -EOPNOTSUPP; 2630 2631 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, 2632 le16_to_cpu(twt_agrt->req_type)); 2633 mantissa = le16_to_cpu(twt_agrt->mantissa); 2634 duration = twt_agrt->min_twt_dur << 8; 2635 2636 interval = (u64)mantissa << exp; 2637 if (interval < duration) 2638 return -EOPNOTSUPP; 2639 2640 return 0; 2641 } 2642 2643 static bool 2644 mt7996_mac_twt_param_equal(struct mt7996_sta_link *msta_link, 2645 struct ieee80211_twt_params *twt_agrt) 2646 { 2647 u16 type = le16_to_cpu(twt_agrt->req_type); 2648 u8 exp; 2649 int i; 2650 2651 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, type); 2652 for (i = 0; i < MT7996_MAX_STA_TWT_AGRT; i++) { 2653 struct mt7996_twt_flow *f; 2654 2655 if (!(msta_link->twt.flowid_mask & BIT(i))) 2656 continue; 2657 2658 f = &msta_link->twt.flow[i]; 2659 if (f->duration == twt_agrt->min_twt_dur && 2660 f->mantissa == twt_agrt->mantissa && 2661 f->exp == exp && 2662 f->protection == !!(type & IEEE80211_TWT_REQTYPE_PROTECTION) && 2663 f->flowtype == !!(type & IEEE80211_TWT_REQTYPE_FLOWTYPE) && 2664 f->trigger == !!(type & IEEE80211_TWT_REQTYPE_TRIGGER)) 2665 return true; 2666 } 2667 2668 return false; 2669 } 2670 2671 void mt7996_mac_add_twt_setup(struct ieee80211_hw *hw, 2672 struct ieee80211_sta *sta, 2673 struct ieee80211_twt_setup *twt) 2674 { 2675 enum ieee80211_twt_setup_cmd setup_cmd = TWT_SETUP_CMD_REJECT; 2676 struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv; 2677 struct ieee80211_twt_params *twt_agrt = (void *)twt->params; 2678 struct mt7996_sta_link *msta_link = &msta->deflink; 2679 u16 req_type = le16_to_cpu(twt_agrt->req_type); 2680 enum ieee80211_twt_setup_cmd sta_setup_cmd; 2681 struct mt7996_dev *dev = mt7996_hw_dev(hw); 2682 struct mt7996_twt_flow *flow; 2683 u8 flowid, table_id, exp; 2684 2685 if (mt7996_mac_check_twt_req(twt)) 2686 goto out; 2687 2688 mutex_lock(&dev->mt76.mutex); 2689 2690 if (dev->twt.n_agrt == MT7996_MAX_TWT_AGRT) 2691 goto unlock; 2692 2693 if (hweight8(msta_link->twt.flowid_mask) == 2694 ARRAY_SIZE(msta_link->twt.flow)) 2695 goto unlock; 2696 2697 if (twt_agrt->min_twt_dur < MT7996_MIN_TWT_DUR) { 2698 setup_cmd = TWT_SETUP_CMD_DICTATE; 2699 twt_agrt->min_twt_dur = MT7996_MIN_TWT_DUR; 2700 goto unlock; 2701 } 2702 2703 if (mt7996_mac_twt_param_equal(msta_link, twt_agrt)) 2704 goto unlock; 2705 2706 flowid = ffs(~msta_link->twt.flowid_mask) - 1; 2707 twt_agrt->req_type &= ~cpu_to_le16(IEEE80211_TWT_REQTYPE_FLOWID); 2708 twt_agrt->req_type |= le16_encode_bits(flowid, 2709 IEEE80211_TWT_REQTYPE_FLOWID); 2710 2711 table_id = ffs(~dev->twt.table_mask) - 1; 2712 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, req_type); 2713 sta_setup_cmd = FIELD_GET(IEEE80211_TWT_REQTYPE_SETUP_CMD, req_type); 2714 2715 flow = &msta_link->twt.flow[flowid]; 2716 memset(flow, 0, sizeof(*flow)); 2717 INIT_LIST_HEAD(&flow->list); 2718 flow->wcid = msta_link->wcid.idx; 2719 flow->table_id = table_id; 2720 flow->id = flowid; 2721 flow->duration = twt_agrt->min_twt_dur; 2722 flow->mantissa = twt_agrt->mantissa; 2723 flow->exp = exp; 2724 flow->protection = !!(req_type & IEEE80211_TWT_REQTYPE_PROTECTION); 2725 flow->flowtype = !!(req_type & IEEE80211_TWT_REQTYPE_FLOWTYPE); 2726 flow->trigger = !!(req_type & IEEE80211_TWT_REQTYPE_TRIGGER); 2727 2728 if (sta_setup_cmd == TWT_SETUP_CMD_REQUEST || 2729 sta_setup_cmd == TWT_SETUP_CMD_SUGGEST) { 2730 u64 interval = (u64)le16_to_cpu(twt_agrt->mantissa) << exp; 2731 u64 flow_tsf, curr_tsf; 2732 u32 rem; 2733 2734 flow->sched = true; 2735 flow->start_tsf = mt7996_mac_twt_sched_list_add(dev, flow); 2736 curr_tsf = __mt7996_get_tsf(hw, &msta->vif->deflink); 2737 div_u64_rem(curr_tsf - flow->start_tsf, interval, &rem); 2738 flow_tsf = curr_tsf + interval - rem; 2739 twt_agrt->twt = cpu_to_le64(flow_tsf); 2740 } else { 2741 list_add_tail(&flow->list, &dev->twt_list); 2742 } 2743 flow->tsf = le64_to_cpu(twt_agrt->twt); 2744 2745 if (mt7996_mcu_twt_agrt_update(dev, &msta->vif->deflink, flow, 2746 MCU_TWT_AGRT_ADD)) 2747 goto unlock; 2748 2749 setup_cmd = TWT_SETUP_CMD_ACCEPT; 2750 dev->twt.table_mask |= BIT(table_id); 2751 msta_link->twt.flowid_mask |= BIT(flowid); 2752 dev->twt.n_agrt++; 2753 2754 unlock: 2755 mutex_unlock(&dev->mt76.mutex); 2756 out: 2757 twt_agrt->req_type &= ~cpu_to_le16(IEEE80211_TWT_REQTYPE_SETUP_CMD); 2758 twt_agrt->req_type |= 2759 le16_encode_bits(setup_cmd, IEEE80211_TWT_REQTYPE_SETUP_CMD); 2760 twt->control = twt->control & IEEE80211_TWT_CONTROL_RX_DISABLED; 2761 } 2762 2763 void mt7996_mac_twt_teardown_flow(struct mt7996_dev *dev, 2764 struct mt7996_vif_link *link, 2765 struct mt7996_sta_link *msta_link, 2766 u8 flowid) 2767 { 2768 struct mt7996_twt_flow *flow; 2769 2770 lockdep_assert_held(&dev->mt76.mutex); 2771 2772 if (flowid >= ARRAY_SIZE(msta_link->twt.flow)) 2773 return; 2774 2775 if (!(msta_link->twt.flowid_mask & BIT(flowid))) 2776 return; 2777 2778 flow = &msta_link->twt.flow[flowid]; 2779 if (mt7996_mcu_twt_agrt_update(dev, link, flow, MCU_TWT_AGRT_DELETE)) 2780 return; 2781 2782 list_del_init(&flow->list); 2783 msta_link->twt.flowid_mask &= ~BIT(flowid); 2784 dev->twt.table_mask &= ~BIT(flow->table_id); 2785 dev->twt.n_agrt--; 2786 } 2787