1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #include <linux/etherdevice.h> 7 #include <linux/timekeeping.h> 8 #include "coredump.h" 9 #include "mt7996.h" 10 #include "../dma.h" 11 #include "mac.h" 12 #include "mcu.h" 13 14 #define to_rssi(field, rcpi) ((FIELD_GET(field, rcpi) - 220) / 2) 15 16 static const struct mt7996_dfs_radar_spec etsi_radar_specs = { 17 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 18 .radar_pattern = { 19 [5] = { 1, 0, 6, 32, 28, 0, 990, 5010, 17, 1, 1 }, 20 [6] = { 1, 0, 9, 32, 28, 0, 615, 5010, 27, 1, 1 }, 21 [7] = { 1, 0, 15, 32, 28, 0, 240, 445, 27, 1, 1 }, 22 [8] = { 1, 0, 12, 32, 28, 0, 240, 510, 42, 1, 1 }, 23 [9] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 12, 32, 28, { }, 126 }, 24 [10] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 15, 32, 24, { }, 126 }, 25 [11] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 18, 32, 28, { }, 54 }, 26 [12] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 27, 32, 24, { }, 54 }, 27 }, 28 }; 29 30 static const struct mt7996_dfs_radar_spec fcc_radar_specs = { 31 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 32 .radar_pattern = { 33 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 }, 34 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 }, 35 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 }, 36 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 }, 37 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 }, 38 }, 39 }; 40 41 static const struct mt7996_dfs_radar_spec jp_radar_specs = { 42 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 43 .radar_pattern = { 44 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 }, 45 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 }, 46 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 }, 47 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 }, 48 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 }, 49 [13] = { 1, 0, 7, 32, 28, 0, 3836, 3856, 14, 1, 1 }, 50 [14] = { 1, 0, 6, 32, 28, 0, 615, 5010, 110, 1, 1 }, 51 [15] = { 1, 1, 0, 0, 0, 0, 15, 5010, 110, 0, 0, 12, 32, 28 }, 52 }, 53 }; 54 55 static struct mt76_wcid *mt7996_rx_get_wcid(struct mt7996_dev *dev, 56 u16 idx, u8 band_idx) 57 { 58 struct mt7996_sta_link *msta_link; 59 struct mt7996_sta *msta; 60 struct mt7996_vif *mvif; 61 struct mt76_wcid *wcid; 62 int i; 63 64 if (idx >= ARRAY_SIZE(dev->mt76.wcid)) 65 return NULL; 66 67 wcid = rcu_dereference(dev->mt76.wcid[idx]); 68 if (!wcid) 69 return NULL; 70 71 if (!mt7996_band_valid(dev, band_idx)) 72 return NULL; 73 74 if (wcid->phy_idx == band_idx) 75 return wcid; 76 77 msta_link = container_of(wcid, struct mt7996_sta_link, wcid); 78 msta = msta_link->sta; 79 if (!msta || !msta->vif) 80 return NULL; 81 82 mvif = msta->vif; 83 for (i = 0; i < ARRAY_SIZE(mvif->mt76.link); i++) { 84 struct mt76_vif_link *mlink; 85 86 mlink = rcu_dereference(mvif->mt76.link[i]); 87 if (!mlink) 88 continue; 89 90 if (mlink->band_idx != band_idx) 91 continue; 92 93 msta_link = rcu_dereference(msta->link[i]); 94 break; 95 } 96 97 return &msta_link->wcid; 98 } 99 100 bool mt7996_mac_wtbl_update(struct mt7996_dev *dev, int idx, u32 mask) 101 { 102 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX, 103 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask); 104 105 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 106 0, 5000); 107 } 108 109 u32 mt7996_mac_wtbl_lmac_addr(struct mt7996_dev *dev, u16 wcid, u8 dw) 110 { 111 mt76_wr(dev, MT_WTBLON_TOP_WDUCR, 112 FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (wcid >> 7))); 113 114 return MT_WTBL_LMAC_OFFS(wcid, dw); 115 } 116 117 static void mt7996_mac_sta_poll(struct mt7996_dev *dev) 118 { 119 static const u8 ac_to_tid[] = { 120 [IEEE80211_AC_BE] = 0, 121 [IEEE80211_AC_BK] = 1, 122 [IEEE80211_AC_VI] = 4, 123 [IEEE80211_AC_VO] = 6 124 }; 125 struct mt7996_sta_link *msta_link; 126 struct mt76_vif_link *mlink; 127 struct ieee80211_sta *sta; 128 struct mt7996_sta *msta; 129 u32 tx_time[IEEE80211_NUM_ACS], rx_time[IEEE80211_NUM_ACS]; 130 LIST_HEAD(sta_poll_list); 131 struct mt76_wcid *wcid; 132 int i; 133 134 spin_lock_bh(&dev->mt76.sta_poll_lock); 135 list_splice_init(&dev->mt76.sta_poll_list, &sta_poll_list); 136 spin_unlock_bh(&dev->mt76.sta_poll_lock); 137 138 rcu_read_lock(); 139 140 while (true) { 141 bool clear = false; 142 u32 addr, val; 143 u16 idx; 144 s8 rssi[4]; 145 146 spin_lock_bh(&dev->mt76.sta_poll_lock); 147 if (list_empty(&sta_poll_list)) { 148 spin_unlock_bh(&dev->mt76.sta_poll_lock); 149 break; 150 } 151 msta_link = list_first_entry(&sta_poll_list, 152 struct mt7996_sta_link, 153 wcid.poll_list); 154 msta = msta_link->sta; 155 wcid = &msta_link->wcid; 156 list_del_init(&wcid->poll_list); 157 spin_unlock_bh(&dev->mt76.sta_poll_lock); 158 159 idx = wcid->idx; 160 161 /* refresh peer's airtime reporting */ 162 addr = mt7996_mac_wtbl_lmac_addr(dev, idx, 20); 163 164 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 165 u32 tx_last = msta_link->airtime_ac[i]; 166 u32 rx_last = msta_link->airtime_ac[i + 4]; 167 168 msta_link->airtime_ac[i] = mt76_rr(dev, addr); 169 msta_link->airtime_ac[i + 4] = mt76_rr(dev, addr + 4); 170 171 tx_time[i] = msta_link->airtime_ac[i] - tx_last; 172 rx_time[i] = msta_link->airtime_ac[i + 4] - rx_last; 173 174 if ((tx_last | rx_last) & BIT(30)) 175 clear = true; 176 177 addr += 8; 178 } 179 180 if (clear) { 181 mt7996_mac_wtbl_update(dev, idx, 182 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 183 memset(msta_link->airtime_ac, 0, 184 sizeof(msta_link->airtime_ac)); 185 } 186 187 if (!wcid->sta) 188 continue; 189 190 sta = container_of((void *)msta, struct ieee80211_sta, 191 drv_priv); 192 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 193 u8 q = mt76_connac_lmac_mapping(i); 194 u32 tx_cur = tx_time[q]; 195 u32 rx_cur = rx_time[q]; 196 u8 tid = ac_to_tid[i]; 197 198 if (!tx_cur && !rx_cur) 199 continue; 200 201 ieee80211_sta_register_airtime(sta, tid, tx_cur, rx_cur); 202 } 203 204 /* get signal strength of resp frames (CTS/BA/ACK) */ 205 addr = mt7996_mac_wtbl_lmac_addr(dev, idx, 34); 206 val = mt76_rr(dev, addr); 207 208 rssi[0] = to_rssi(GENMASK(7, 0), val); 209 rssi[1] = to_rssi(GENMASK(15, 8), val); 210 rssi[2] = to_rssi(GENMASK(23, 16), val); 211 rssi[3] = to_rssi(GENMASK(31, 14), val); 212 213 mlink = rcu_dereference(msta->vif->mt76.link[wcid->link_id]); 214 if (mlink) { 215 struct mt76_phy *mphy = mt76_vif_link_phy(mlink); 216 217 if (mphy) 218 msta_link->ack_signal = 219 mt76_rx_signal(mphy->antenna_mask, 220 rssi); 221 } 222 223 ewma_avg_signal_add(&msta_link->avg_ack_signal, 224 -msta_link->ack_signal); 225 } 226 227 rcu_read_unlock(); 228 } 229 230 /* The HW does not translate the mac header to 802.3 for mesh point */ 231 static int mt7996_reverse_frag0_hdr_trans(struct sk_buff *skb, u16 hdr_gap) 232 { 233 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 234 struct ethhdr *eth_hdr = (struct ethhdr *)(skb->data + hdr_gap); 235 struct mt7996_sta *msta = (struct mt7996_sta *)status->wcid; 236 __le32 *rxd = (__le32 *)skb->data; 237 struct ieee80211_sta *sta; 238 struct ieee80211_vif *vif; 239 struct ieee80211_hdr hdr; 240 u16 frame_control; 241 242 if (le32_get_bits(rxd[3], MT_RXD3_NORMAL_ADDR_TYPE) != 243 MT_RXD3_NORMAL_U2M) 244 return -EINVAL; 245 246 if (!(le32_to_cpu(rxd[1]) & MT_RXD1_NORMAL_GROUP_4)) 247 return -EINVAL; 248 249 if (!msta || !msta->vif) 250 return -EINVAL; 251 252 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv); 253 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); 254 255 /* store the info from RXD and ethhdr to avoid being overridden */ 256 frame_control = le32_get_bits(rxd[8], MT_RXD8_FRAME_CONTROL); 257 hdr.frame_control = cpu_to_le16(frame_control); 258 hdr.seq_ctrl = cpu_to_le16(le32_get_bits(rxd[10], MT_RXD10_SEQ_CTRL)); 259 hdr.duration_id = 0; 260 261 ether_addr_copy(hdr.addr1, vif->addr); 262 ether_addr_copy(hdr.addr2, sta->addr); 263 switch (frame_control & (IEEE80211_FCTL_TODS | 264 IEEE80211_FCTL_FROMDS)) { 265 case 0: 266 ether_addr_copy(hdr.addr3, vif->bss_conf.bssid); 267 break; 268 case IEEE80211_FCTL_FROMDS: 269 ether_addr_copy(hdr.addr3, eth_hdr->h_source); 270 break; 271 case IEEE80211_FCTL_TODS: 272 ether_addr_copy(hdr.addr3, eth_hdr->h_dest); 273 break; 274 case IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS: 275 ether_addr_copy(hdr.addr3, eth_hdr->h_dest); 276 ether_addr_copy(hdr.addr4, eth_hdr->h_source); 277 break; 278 default: 279 return -EINVAL; 280 } 281 282 skb_pull(skb, hdr_gap + sizeof(struct ethhdr) - 2); 283 if (eth_hdr->h_proto == cpu_to_be16(ETH_P_AARP) || 284 eth_hdr->h_proto == cpu_to_be16(ETH_P_IPX)) 285 ether_addr_copy(skb_push(skb, ETH_ALEN), bridge_tunnel_header); 286 else if (be16_to_cpu(eth_hdr->h_proto) >= ETH_P_802_3_MIN) 287 ether_addr_copy(skb_push(skb, ETH_ALEN), rfc1042_header); 288 else 289 skb_pull(skb, 2); 290 291 if (ieee80211_has_order(hdr.frame_control)) 292 memcpy(skb_push(skb, IEEE80211_HT_CTL_LEN), &rxd[11], 293 IEEE80211_HT_CTL_LEN); 294 if (ieee80211_is_data_qos(hdr.frame_control)) { 295 __le16 qos_ctrl; 296 297 qos_ctrl = cpu_to_le16(le32_get_bits(rxd[10], MT_RXD10_QOS_CTL)); 298 memcpy(skb_push(skb, IEEE80211_QOS_CTL_LEN), &qos_ctrl, 299 IEEE80211_QOS_CTL_LEN); 300 } 301 302 if (ieee80211_has_a4(hdr.frame_control)) 303 memcpy(skb_push(skb, sizeof(hdr)), &hdr, sizeof(hdr)); 304 else 305 memcpy(skb_push(skb, sizeof(hdr) - 6), &hdr, sizeof(hdr) - 6); 306 307 return 0; 308 } 309 310 static int 311 mt7996_mac_fill_rx_rate(struct mt7996_dev *dev, 312 struct mt76_rx_status *status, 313 struct ieee80211_supported_band *sband, 314 __le32 *rxv, u8 *mode) 315 { 316 u32 v0, v2; 317 u8 stbc, gi, bw, dcm, nss; 318 int i, idx; 319 bool cck = false; 320 321 v0 = le32_to_cpu(rxv[0]); 322 v2 = le32_to_cpu(rxv[2]); 323 324 idx = FIELD_GET(MT_PRXV_TX_RATE, v0); 325 i = idx; 326 nss = FIELD_GET(MT_PRXV_NSTS, v0) + 1; 327 328 stbc = FIELD_GET(MT_PRXV_HT_STBC, v2); 329 gi = FIELD_GET(MT_PRXV_HT_SHORT_GI, v2); 330 *mode = FIELD_GET(MT_PRXV_TX_MODE, v2); 331 dcm = FIELD_GET(MT_PRXV_DCM, v2); 332 bw = FIELD_GET(MT_PRXV_FRAME_MODE, v2); 333 334 switch (*mode) { 335 case MT_PHY_TYPE_CCK: 336 cck = true; 337 fallthrough; 338 case MT_PHY_TYPE_OFDM: 339 i = mt76_get_rate(&dev->mt76, sband, i, cck); 340 break; 341 case MT_PHY_TYPE_HT_GF: 342 case MT_PHY_TYPE_HT: 343 status->encoding = RX_ENC_HT; 344 if (gi) 345 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 346 if (i > 31) 347 return -EINVAL; 348 break; 349 case MT_PHY_TYPE_VHT: 350 status->nss = nss; 351 status->encoding = RX_ENC_VHT; 352 if (gi) 353 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 354 if (i > 11) 355 return -EINVAL; 356 break; 357 case MT_PHY_TYPE_HE_MU: 358 case MT_PHY_TYPE_HE_SU: 359 case MT_PHY_TYPE_HE_EXT_SU: 360 case MT_PHY_TYPE_HE_TB: 361 status->nss = nss; 362 status->encoding = RX_ENC_HE; 363 i &= GENMASK(3, 0); 364 365 if (gi <= NL80211_RATE_INFO_HE_GI_3_2) 366 status->he_gi = gi; 367 368 status->he_dcm = dcm; 369 break; 370 case MT_PHY_TYPE_EHT_SU: 371 case MT_PHY_TYPE_EHT_TRIG: 372 case MT_PHY_TYPE_EHT_MU: 373 status->nss = nss; 374 status->encoding = RX_ENC_EHT; 375 i &= GENMASK(3, 0); 376 377 if (gi <= NL80211_RATE_INFO_EHT_GI_3_2) 378 status->eht.gi = gi; 379 break; 380 default: 381 return -EINVAL; 382 } 383 status->rate_idx = i; 384 385 switch (bw) { 386 case IEEE80211_STA_RX_BW_20: 387 break; 388 case IEEE80211_STA_RX_BW_40: 389 if (*mode & MT_PHY_TYPE_HE_EXT_SU && 390 (idx & MT_PRXV_TX_ER_SU_106T)) { 391 status->bw = RATE_INFO_BW_HE_RU; 392 status->he_ru = 393 NL80211_RATE_INFO_HE_RU_ALLOC_106; 394 } else { 395 status->bw = RATE_INFO_BW_40; 396 } 397 break; 398 case IEEE80211_STA_RX_BW_80: 399 status->bw = RATE_INFO_BW_80; 400 break; 401 case IEEE80211_STA_RX_BW_160: 402 status->bw = RATE_INFO_BW_160; 403 break; 404 /* rxv reports bw 320-1 and 320-2 separately */ 405 case IEEE80211_STA_RX_BW_320: 406 case IEEE80211_STA_RX_BW_320 + 1: 407 status->bw = RATE_INFO_BW_320; 408 break; 409 default: 410 return -EINVAL; 411 } 412 413 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc; 414 if (*mode < MT_PHY_TYPE_HE_SU && gi) 415 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 416 417 return 0; 418 } 419 420 static void 421 mt7996_wed_check_ppe(struct mt7996_dev *dev, struct mt76_queue *q, 422 struct mt7996_sta *msta, struct sk_buff *skb, 423 u32 info) 424 { 425 struct ieee80211_vif *vif; 426 struct wireless_dev *wdev; 427 428 if (!msta || !msta->vif) 429 return; 430 431 if (!mt76_queue_is_wed_rx(q)) 432 return; 433 434 if (!(info & MT_DMA_INFO_PPE_VLD)) 435 return; 436 437 vif = container_of((void *)msta->vif, struct ieee80211_vif, 438 drv_priv); 439 wdev = ieee80211_vif_to_wdev(vif); 440 skb->dev = wdev->netdev; 441 442 mtk_wed_device_ppe_check(&dev->mt76.mmio.wed, skb, 443 FIELD_GET(MT_DMA_PPE_CPU_REASON, info), 444 FIELD_GET(MT_DMA_PPE_ENTRY, info)); 445 } 446 447 static int 448 mt7996_mac_fill_rx(struct mt7996_dev *dev, enum mt76_rxq_id q, 449 struct sk_buff *skb, u32 *info) 450 { 451 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 452 struct mt76_phy *mphy = &dev->mt76.phy; 453 struct mt7996_phy *phy = &dev->phy; 454 struct ieee80211_supported_band *sband; 455 __le32 *rxd = (__le32 *)skb->data; 456 __le32 *rxv = NULL; 457 u32 rxd0 = le32_to_cpu(rxd[0]); 458 u32 rxd1 = le32_to_cpu(rxd[1]); 459 u32 rxd2 = le32_to_cpu(rxd[2]); 460 u32 rxd3 = le32_to_cpu(rxd[3]); 461 u32 rxd4 = le32_to_cpu(rxd[4]); 462 u32 csum_mask = MT_RXD3_NORMAL_IP_SUM | MT_RXD3_NORMAL_UDP_TCP_SUM; 463 u32 csum_status = *(u32 *)skb->cb; 464 u32 mesh_mask = MT_RXD0_MESH | MT_RXD0_MHCP; 465 bool is_mesh = (rxd0 & mesh_mask) == mesh_mask; 466 bool unicast, insert_ccmp_hdr = false; 467 u8 remove_pad, amsdu_info, band_idx; 468 u8 mode = 0, qos_ctl = 0; 469 bool hdr_trans; 470 u16 hdr_gap; 471 u16 seq_ctrl = 0; 472 __le16 fc = 0; 473 int idx; 474 u8 hw_aggr = false; 475 struct mt7996_sta *msta = NULL; 476 477 hw_aggr = status->aggr; 478 memset(status, 0, sizeof(*status)); 479 480 band_idx = FIELD_GET(MT_RXD1_NORMAL_BAND_IDX, rxd1); 481 mphy = dev->mt76.phys[band_idx]; 482 phy = mphy->priv; 483 status->phy_idx = mphy->band_idx; 484 485 if (!test_bit(MT76_STATE_RUNNING, &mphy->state)) 486 return -EINVAL; 487 488 if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR) 489 return -EINVAL; 490 491 hdr_trans = rxd2 & MT_RXD2_NORMAL_HDR_TRANS; 492 if (hdr_trans && (rxd1 & MT_RXD1_NORMAL_CM)) 493 return -EINVAL; 494 495 /* ICV error or CCMP/BIP/WPI MIC error */ 496 if (rxd1 & MT_RXD1_NORMAL_ICV_ERR) 497 status->flag |= RX_FLAG_ONLY_MONITOR; 498 499 unicast = FIELD_GET(MT_RXD3_NORMAL_ADDR_TYPE, rxd3) == MT_RXD3_NORMAL_U2M; 500 idx = FIELD_GET(MT_RXD1_NORMAL_WLAN_IDX, rxd1); 501 status->wcid = mt7996_rx_get_wcid(dev, idx, band_idx); 502 503 if (status->wcid) { 504 struct mt7996_sta_link *msta_link; 505 506 msta_link = container_of(status->wcid, struct mt7996_sta_link, 507 wcid); 508 msta = msta_link->sta; 509 mt76_wcid_add_poll(&dev->mt76, &msta_link->wcid); 510 } 511 512 status->freq = mphy->chandef.chan->center_freq; 513 status->band = mphy->chandef.chan->band; 514 if (status->band == NL80211_BAND_5GHZ) 515 sband = &mphy->sband_5g.sband; 516 else if (status->band == NL80211_BAND_6GHZ) 517 sband = &mphy->sband_6g.sband; 518 else 519 sband = &mphy->sband_2g.sband; 520 521 if (!sband->channels) 522 return -EINVAL; 523 524 if ((rxd3 & csum_mask) == csum_mask && 525 !(csum_status & (BIT(0) | BIT(2) | BIT(3)))) 526 skb->ip_summed = CHECKSUM_UNNECESSARY; 527 528 if (rxd1 & MT_RXD3_NORMAL_FCS_ERR) 529 status->flag |= RX_FLAG_FAILED_FCS_CRC; 530 531 if (rxd1 & MT_RXD1_NORMAL_TKIP_MIC_ERR) 532 status->flag |= RX_FLAG_MMIC_ERROR; 533 534 if (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2) != 0 && 535 !(rxd1 & (MT_RXD1_NORMAL_CLM | MT_RXD1_NORMAL_CM))) { 536 status->flag |= RX_FLAG_DECRYPTED; 537 status->flag |= RX_FLAG_IV_STRIPPED; 538 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED; 539 } 540 541 remove_pad = FIELD_GET(MT_RXD2_NORMAL_HDR_OFFSET, rxd2); 542 543 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR) 544 return -EINVAL; 545 546 rxd += 8; 547 if (rxd1 & MT_RXD1_NORMAL_GROUP_4) { 548 u32 v0 = le32_to_cpu(rxd[0]); 549 u32 v2 = le32_to_cpu(rxd[2]); 550 551 fc = cpu_to_le16(FIELD_GET(MT_RXD8_FRAME_CONTROL, v0)); 552 qos_ctl = FIELD_GET(MT_RXD10_QOS_CTL, v2); 553 seq_ctrl = FIELD_GET(MT_RXD10_SEQ_CTRL, v2); 554 555 rxd += 4; 556 if ((u8 *)rxd - skb->data >= skb->len) 557 return -EINVAL; 558 } 559 560 if (rxd1 & MT_RXD1_NORMAL_GROUP_1) { 561 u8 *data = (u8 *)rxd; 562 563 if (status->flag & RX_FLAG_DECRYPTED) { 564 switch (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2)) { 565 case MT_CIPHER_AES_CCMP: 566 case MT_CIPHER_CCMP_CCX: 567 case MT_CIPHER_CCMP_256: 568 insert_ccmp_hdr = 569 FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2); 570 fallthrough; 571 case MT_CIPHER_TKIP: 572 case MT_CIPHER_TKIP_NO_MIC: 573 case MT_CIPHER_GCMP: 574 case MT_CIPHER_GCMP_256: 575 status->iv[0] = data[5]; 576 status->iv[1] = data[4]; 577 status->iv[2] = data[3]; 578 status->iv[3] = data[2]; 579 status->iv[4] = data[1]; 580 status->iv[5] = data[0]; 581 break; 582 default: 583 break; 584 } 585 } 586 rxd += 4; 587 if ((u8 *)rxd - skb->data >= skb->len) 588 return -EINVAL; 589 } 590 591 if (rxd1 & MT_RXD1_NORMAL_GROUP_2) { 592 status->timestamp = le32_to_cpu(rxd[0]); 593 status->flag |= RX_FLAG_MACTIME_START; 594 595 if (!(rxd2 & MT_RXD2_NORMAL_NON_AMPDU)) { 596 status->flag |= RX_FLAG_AMPDU_DETAILS; 597 598 /* all subframes of an A-MPDU have the same timestamp */ 599 if (phy->rx_ampdu_ts != status->timestamp) { 600 if (!++phy->ampdu_ref) 601 phy->ampdu_ref++; 602 } 603 phy->rx_ampdu_ts = status->timestamp; 604 605 status->ampdu_ref = phy->ampdu_ref; 606 } 607 608 rxd += 4; 609 if ((u8 *)rxd - skb->data >= skb->len) 610 return -EINVAL; 611 } 612 613 /* RXD Group 3 - P-RXV */ 614 if (rxd1 & MT_RXD1_NORMAL_GROUP_3) { 615 u32 v3; 616 int ret; 617 618 rxv = rxd; 619 rxd += 4; 620 if ((u8 *)rxd - skb->data >= skb->len) 621 return -EINVAL; 622 623 v3 = le32_to_cpu(rxv[3]); 624 625 status->chains = mphy->antenna_mask; 626 status->chain_signal[0] = to_rssi(MT_PRXV_RCPI0, v3); 627 status->chain_signal[1] = to_rssi(MT_PRXV_RCPI1, v3); 628 status->chain_signal[2] = to_rssi(MT_PRXV_RCPI2, v3); 629 status->chain_signal[3] = to_rssi(MT_PRXV_RCPI3, v3); 630 631 /* RXD Group 5 - C-RXV */ 632 if (rxd1 & MT_RXD1_NORMAL_GROUP_5) { 633 rxd += 24; 634 if ((u8 *)rxd - skb->data >= skb->len) 635 return -EINVAL; 636 } 637 638 ret = mt7996_mac_fill_rx_rate(dev, status, sband, rxv, &mode); 639 if (ret < 0) 640 return ret; 641 } 642 643 amsdu_info = FIELD_GET(MT_RXD4_NORMAL_PAYLOAD_FORMAT, rxd4); 644 status->amsdu = !!amsdu_info; 645 if (status->amsdu) { 646 status->first_amsdu = amsdu_info == MT_RXD4_FIRST_AMSDU_FRAME; 647 status->last_amsdu = amsdu_info == MT_RXD4_LAST_AMSDU_FRAME; 648 } 649 650 /* IEEE 802.11 fragmentation can only be applied to unicast frames. 651 * Hence, drop fragments with multicast/broadcast RA. 652 * This check fixes vulnerabilities, like CVE-2020-26145. 653 */ 654 if ((ieee80211_has_morefrags(fc) || seq_ctrl & IEEE80211_SCTL_FRAG) && 655 FIELD_GET(MT_RXD3_NORMAL_ADDR_TYPE, rxd3) != MT_RXD3_NORMAL_U2M) 656 return -EINVAL; 657 658 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad; 659 if (hdr_trans && ieee80211_has_morefrags(fc)) { 660 if (mt7996_reverse_frag0_hdr_trans(skb, hdr_gap)) 661 return -EINVAL; 662 hdr_trans = false; 663 } else { 664 int pad_start = 0; 665 666 skb_pull(skb, hdr_gap); 667 if (!hdr_trans && status->amsdu && !(ieee80211_has_a4(fc) && is_mesh)) { 668 pad_start = ieee80211_get_hdrlen_from_skb(skb); 669 } else if (hdr_trans && (rxd2 & MT_RXD2_NORMAL_HDR_TRANS_ERROR)) { 670 /* When header translation failure is indicated, 671 * the hardware will insert an extra 2-byte field 672 * containing the data length after the protocol 673 * type field. This happens either when the LLC-SNAP 674 * pattern did not match, or if a VLAN header was 675 * detected. 676 */ 677 pad_start = 12; 678 if (get_unaligned_be16(skb->data + pad_start) == ETH_P_8021Q) 679 pad_start += 4; 680 else 681 pad_start = 0; 682 } 683 684 if (pad_start) { 685 memmove(skb->data + 2, skb->data, pad_start); 686 skb_pull(skb, 2); 687 } 688 } 689 690 if (!hdr_trans) { 691 struct ieee80211_hdr *hdr; 692 693 if (insert_ccmp_hdr) { 694 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1); 695 696 mt76_insert_ccmp_hdr(skb, key_id); 697 } 698 699 hdr = mt76_skb_get_hdr(skb); 700 fc = hdr->frame_control; 701 if (ieee80211_is_data_qos(fc)) { 702 u8 *qos = ieee80211_get_qos_ctl(hdr); 703 704 seq_ctrl = le16_to_cpu(hdr->seq_ctrl); 705 qos_ctl = *qos; 706 707 /* Mesh DA/SA/Length will be stripped after hardware 708 * de-amsdu, so here needs to clear amsdu present bit 709 * to mark it as a normal mesh frame. 710 */ 711 if (ieee80211_has_a4(fc) && is_mesh && status->amsdu) 712 *qos &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT; 713 } 714 skb_set_mac_header(skb, (unsigned char *)hdr - skb->data); 715 } else { 716 status->flag |= RX_FLAG_8023; 717 mt7996_wed_check_ppe(dev, &dev->mt76.q_rx[q], msta, skb, 718 *info); 719 } 720 721 if (rxv && !(status->flag & RX_FLAG_8023)) { 722 switch (status->encoding) { 723 case RX_ENC_EHT: 724 mt76_connac3_mac_decode_eht_radiotap(skb, rxv, mode); 725 break; 726 case RX_ENC_HE: 727 mt76_connac3_mac_decode_he_radiotap(skb, rxv, mode); 728 break; 729 default: 730 break; 731 } 732 } 733 734 if (!status->wcid || !ieee80211_is_data_qos(fc) || hw_aggr) 735 return 0; 736 737 status->aggr = unicast && 738 !ieee80211_is_qos_nullfunc(fc); 739 status->qos_ctl = qos_ctl; 740 status->seqno = IEEE80211_SEQ_TO_SN(seq_ctrl); 741 742 return 0; 743 } 744 745 static void 746 mt7996_mac_write_txwi_8023(struct mt7996_dev *dev, __le32 *txwi, 747 struct sk_buff *skb, struct mt76_wcid *wcid) 748 { 749 u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 750 u8 fc_type, fc_stype; 751 u16 ethertype; 752 bool wmm = false; 753 u32 val; 754 755 if (wcid->sta) { 756 struct ieee80211_sta *sta = wcid_to_sta(wcid); 757 758 wmm = sta->wme; 759 } 760 761 val = FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_3) | 762 FIELD_PREP(MT_TXD1_TID, tid); 763 764 ethertype = get_unaligned_be16(&skb->data[12]); 765 if (ethertype >= ETH_P_802_3_MIN) 766 val |= MT_TXD1_ETH_802_3; 767 768 txwi[1] |= cpu_to_le32(val); 769 770 fc_type = IEEE80211_FTYPE_DATA >> 2; 771 fc_stype = wmm ? IEEE80211_STYPE_QOS_DATA >> 4 : 0; 772 773 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) | 774 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype); 775 776 txwi[2] |= cpu_to_le32(val); 777 778 if (wcid->amsdu) 779 txwi[3] |= cpu_to_le32(MT_TXD3_HW_AMSDU); 780 } 781 782 static void 783 mt7996_mac_write_txwi_80211(struct mt7996_dev *dev, __le32 *txwi, 784 struct sk_buff *skb, 785 struct ieee80211_key_conf *key, 786 struct mt76_wcid *wcid) 787 { 788 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 789 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 790 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 791 bool multicast = is_multicast_ether_addr(hdr->addr1); 792 u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 793 __le16 fc = hdr->frame_control, sc = hdr->seq_ctrl; 794 u16 seqno = le16_to_cpu(sc); 795 u8 fc_type, fc_stype; 796 u32 val; 797 798 if (ieee80211_is_action(fc) && 799 mgmt->u.action.category == WLAN_CATEGORY_BACK && 800 mgmt->u.action.u.addba_req.action_code == WLAN_ACTION_ADDBA_REQ) { 801 if (is_mt7990(&dev->mt76)) 802 txwi[6] |= cpu_to_le32(FIELD_PREP(MT_TXD6_TID_ADDBA, tid)); 803 tid = MT_TX_ADDBA; 804 } else if (ieee80211_is_mgmt(hdr->frame_control)) { 805 tid = MT_TX_NORMAL; 806 } 807 808 val = FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) | 809 FIELD_PREP(MT_TXD1_HDR_INFO, 810 ieee80211_get_hdrlen_from_skb(skb) / 2) | 811 FIELD_PREP(MT_TXD1_TID, tid); 812 813 if (!ieee80211_is_data(fc) || multicast || 814 info->flags & IEEE80211_TX_CTL_USE_MINRATE) 815 val |= MT_TXD1_FIXED_RATE; 816 817 if (key && multicast && ieee80211_is_robust_mgmt_frame(skb)) { 818 val |= MT_TXD1_BIP; 819 txwi[3] &= ~cpu_to_le32(MT_TXD3_PROTECT_FRAME); 820 } 821 822 txwi[1] |= cpu_to_le32(val); 823 824 fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2; 825 fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4; 826 827 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) | 828 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype); 829 830 if (ieee80211_has_morefrags(fc) && ieee80211_is_first_frag(sc)) 831 val |= FIELD_PREP(MT_TXD2_FRAG, MT_TX_FRAG_FIRST); 832 else if (ieee80211_has_morefrags(fc) && !ieee80211_is_first_frag(sc)) 833 val |= FIELD_PREP(MT_TXD2_FRAG, MT_TX_FRAG_MID); 834 else if (!ieee80211_has_morefrags(fc) && !ieee80211_is_first_frag(sc)) 835 val |= FIELD_PREP(MT_TXD2_FRAG, MT_TX_FRAG_LAST); 836 else 837 val |= FIELD_PREP(MT_TXD2_FRAG, MT_TX_FRAG_NONE); 838 839 txwi[2] |= cpu_to_le32(val); 840 841 txwi[3] |= cpu_to_le32(FIELD_PREP(MT_TXD3_BCM, multicast)); 842 if (ieee80211_is_beacon(fc)) { 843 txwi[3] &= ~cpu_to_le32(MT_TXD3_SW_POWER_MGMT); 844 txwi[3] |= cpu_to_le32(MT_TXD3_REM_TX_COUNT); 845 } 846 847 if (multicast && ieee80211_vif_is_mld(info->control.vif)) { 848 val = MT_TXD3_SN_VALID | 849 FIELD_PREP(MT_TXD3_SEQ, IEEE80211_SEQ_TO_SN(seqno)); 850 txwi[3] |= cpu_to_le32(val); 851 } 852 853 if (info->flags & IEEE80211_TX_CTL_INJECTED) { 854 if (ieee80211_is_back_req(hdr->frame_control)) { 855 struct ieee80211_bar *bar; 856 857 bar = (struct ieee80211_bar *)skb->data; 858 seqno = le16_to_cpu(bar->start_seq_num); 859 } 860 861 val = MT_TXD3_SN_VALID | 862 FIELD_PREP(MT_TXD3_SEQ, IEEE80211_SEQ_TO_SN(seqno)); 863 txwi[3] |= cpu_to_le32(val); 864 txwi[3] &= ~cpu_to_le32(MT_TXD3_HW_AMSDU); 865 } 866 867 if (ieee80211_vif_is_mld(info->control.vif) && 868 (multicast || unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE)))) 869 txwi[5] |= cpu_to_le32(MT_TXD5_FL); 870 871 if (ieee80211_is_nullfunc(fc) && ieee80211_has_a4(fc) && 872 ieee80211_vif_is_mld(info->control.vif)) { 873 txwi[5] |= cpu_to_le32(MT_TXD5_FL); 874 txwi[6] |= cpu_to_le32(MT_TXD6_DIS_MAT); 875 } 876 877 if (!wcid->sta && ieee80211_is_mgmt(fc)) 878 txwi[6] |= cpu_to_le32(MT_TXD6_DIS_MAT); 879 } 880 881 void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi, 882 struct sk_buff *skb, struct mt76_wcid *wcid, 883 struct ieee80211_key_conf *key, int pid, 884 enum mt76_txq_id qid, u32 changed) 885 { 886 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 887 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 888 struct ieee80211_vif *vif = info->control.vif; 889 u8 band_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2; 890 u8 p_fmt, q_idx, omac_idx = 0, wmm_idx = 0; 891 bool is_8023 = info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP; 892 struct mt76_vif_link *mlink = NULL; 893 struct mt7996_vif *mvif; 894 unsigned int link_id; 895 u16 tx_count = 15; 896 u32 val; 897 bool inband_disc = !!(changed & (BSS_CHANGED_UNSOL_BCAST_PROBE_RESP | 898 BSS_CHANGED_FILS_DISCOVERY)); 899 bool beacon = !!(changed & (BSS_CHANGED_BEACON | 900 BSS_CHANGED_BEACON_ENABLED)) && (!inband_disc); 901 902 if (wcid != &dev->mt76.global_wcid) 903 link_id = wcid->link_id; 904 else 905 link_id = u32_get_bits(info->control.flags, 906 IEEE80211_TX_CTRL_MLO_LINK); 907 908 mvif = vif ? (struct mt7996_vif *)vif->drv_priv : NULL; 909 if (mvif) 910 mlink = rcu_dereference(mvif->mt76.link[link_id]); 911 912 if (mlink) { 913 omac_idx = mlink->omac_idx; 914 wmm_idx = mlink->wmm_idx; 915 band_idx = mlink->band_idx; 916 } 917 918 if (inband_disc) { 919 p_fmt = MT_TX_TYPE_FW; 920 q_idx = MT_LMAC_ALTX0; 921 } else if (beacon) { 922 p_fmt = MT_TX_TYPE_FW; 923 q_idx = MT_LMAC_BCN0; 924 } else if (qid >= MT_TXQ_PSD) { 925 p_fmt = MT_TX_TYPE_CT; 926 q_idx = MT_LMAC_ALTX0; 927 } else { 928 p_fmt = MT_TX_TYPE_CT; 929 q_idx = wmm_idx * MT7996_MAX_WMM_SETS + 930 mt76_connac_lmac_mapping(skb_get_queue_mapping(skb)); 931 } 932 933 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) | 934 FIELD_PREP(MT_TXD0_PKT_FMT, p_fmt) | 935 FIELD_PREP(MT_TXD0_Q_IDX, q_idx); 936 txwi[0] = cpu_to_le32(val); 937 938 val = FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) | 939 FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx); 940 941 if (band_idx) 942 val |= FIELD_PREP(MT_TXD1_TGID, band_idx); 943 944 txwi[1] = cpu_to_le32(val); 945 txwi[2] = 0; 946 947 val = MT_TXD3_SW_POWER_MGMT | 948 FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count); 949 if (key) 950 val |= MT_TXD3_PROTECT_FRAME; 951 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 952 val |= MT_TXD3_NO_ACK; 953 954 txwi[3] = cpu_to_le32(val); 955 txwi[4] = 0; 956 957 val = FIELD_PREP(MT_TXD5_PID, pid); 958 if (pid >= MT_PACKET_ID_FIRST) 959 val |= MT_TXD5_TX_STATUS_HOST; 960 txwi[5] = cpu_to_le32(val); 961 962 val = MT_TXD6_DAS; 963 if (q_idx >= MT_LMAC_ALTX0 && q_idx <= MT_LMAC_BCN0) 964 val |= MT_TXD6_DIS_MAT; 965 966 if (is_mt7996(&dev->mt76)) 967 val |= FIELD_PREP(MT_TXD6_MSDU_CNT, 1); 968 else if (is_8023 || !ieee80211_is_mgmt(hdr->frame_control)) 969 val |= FIELD_PREP(MT_TXD6_MSDU_CNT_V2, 1); 970 971 txwi[6] = cpu_to_le32(val); 972 txwi[7] = 0; 973 974 if (is_8023) 975 mt7996_mac_write_txwi_8023(dev, txwi, skb, wcid); 976 else 977 mt7996_mac_write_txwi_80211(dev, txwi, skb, key, wcid); 978 979 if (txwi[1] & cpu_to_le32(MT_TXD1_FIXED_RATE)) { 980 bool mcast = ieee80211_is_data(hdr->frame_control) && 981 is_multicast_ether_addr(hdr->addr1); 982 u8 idx = MT7996_BASIC_RATES_TBL; 983 984 if (mlink) { 985 if (mcast && mlink->mcast_rates_idx) 986 idx = mlink->mcast_rates_idx; 987 else if (beacon && mlink->beacon_rates_idx) 988 idx = mlink->beacon_rates_idx; 989 else 990 idx = mlink->basic_rates_idx; 991 } 992 993 val = FIELD_PREP(MT_TXD6_TX_RATE, idx) | MT_TXD6_FIXED_BW; 994 if (mcast) 995 val |= MT_TXD6_DIS_MAT; 996 txwi[6] |= cpu_to_le32(val); 997 txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE); 998 } 999 } 1000 1001 static bool 1002 mt7996_tx_use_mgmt(struct mt7996_dev *dev, struct sk_buff *skb) 1003 { 1004 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1005 1006 if (ieee80211_is_mgmt(hdr->frame_control)) 1007 return true; 1008 1009 /* for SDO to bypass specific data frame */ 1010 if (!mt7996_has_wa(dev)) { 1011 if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) 1012 return true; 1013 1014 if (ieee80211_has_a4(hdr->frame_control) && 1015 !ieee80211_is_data_present(hdr->frame_control)) 1016 return true; 1017 } 1018 1019 return false; 1020 } 1021 1022 int mt7996_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, 1023 enum mt76_txq_id qid, struct mt76_wcid *wcid, 1024 struct ieee80211_sta *sta, 1025 struct mt76_tx_info *tx_info) 1026 { 1027 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 1028 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb); 1029 struct ieee80211_key_conf *key = info->control.hw_key; 1030 struct ieee80211_vif *vif = info->control.vif; 1031 struct mt76_connac_txp_common *txp; 1032 struct mt76_txwi_cache *t; 1033 int id, i, pid, nbuf = tx_info->nbuf - 1; 1034 bool is_8023 = info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP; 1035 u8 *txwi = (u8 *)txwi_ptr; 1036 1037 if (unlikely(tx_info->skb->len <= ETH_HLEN)) 1038 return -EINVAL; 1039 1040 if (!wcid) 1041 wcid = &dev->mt76.global_wcid; 1042 1043 t = (struct mt76_txwi_cache *)(txwi + mdev->drv->txwi_size); 1044 t->skb = tx_info->skb; 1045 1046 id = mt76_token_consume(mdev, &t); 1047 if (id < 0) 1048 return id; 1049 1050 pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb); 1051 memset(txwi_ptr, 0, MT_TXD_SIZE); 1052 /* Transmit non qos data by 802.11 header and need to fill txd by host*/ 1053 if (!is_8023 || pid >= MT_PACKET_ID_FIRST) 1054 mt7996_mac_write_txwi(dev, txwi_ptr, tx_info->skb, wcid, key, 1055 pid, qid, 0); 1056 1057 txp = (struct mt76_connac_txp_common *)(txwi + MT_TXD_SIZE); 1058 for (i = 0; i < nbuf; i++) { 1059 u16 len; 1060 1061 len = FIELD_PREP(MT_TXP_BUF_LEN, tx_info->buf[i + 1].len); 1062 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 1063 len |= FIELD_PREP(MT_TXP_DMA_ADDR_H, 1064 tx_info->buf[i + 1].addr >> 32); 1065 #endif 1066 1067 txp->fw.buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr); 1068 txp->fw.len[i] = cpu_to_le16(len); 1069 } 1070 txp->fw.nbuf = nbuf; 1071 1072 txp->fw.flags = cpu_to_le16(MT_CT_INFO_FROM_HOST); 1073 1074 if (!is_8023 || pid >= MT_PACKET_ID_FIRST) 1075 txp->fw.flags |= cpu_to_le16(MT_CT_INFO_APPLY_TXD); 1076 1077 if (!key) 1078 txp->fw.flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME); 1079 1080 if (!is_8023 && mt7996_tx_use_mgmt(dev, tx_info->skb)) 1081 txp->fw.flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME); 1082 1083 if (vif) { 1084 struct mt7996_vif *mvif = (struct mt7996_vif *)vif->drv_priv; 1085 struct mt76_vif_link *mlink = NULL; 1086 1087 if (wcid->offchannel) 1088 mlink = rcu_dereference(mvif->mt76.offchannel_link); 1089 if (!mlink) 1090 mlink = rcu_dereference(mvif->mt76.link[wcid->link_id]); 1091 1092 txp->fw.bss_idx = mlink ? mlink->idx : mvif->deflink.mt76.idx; 1093 } 1094 1095 txp->fw.token = cpu_to_le16(id); 1096 txp->fw.rept_wds_wcid = cpu_to_le16(sta ? wcid->idx : 0xfff); 1097 1098 tx_info->skb = NULL; 1099 1100 /* pass partial skb header to fw */ 1101 tx_info->buf[1].len = MT_CT_PARSE_LEN; 1102 tx_info->buf[1].skip_unmap = true; 1103 tx_info->nbuf = MT_CT_DMA_BUF_NUM; 1104 1105 return 0; 1106 } 1107 1108 u32 mt7996_wed_init_buf(void *ptr, dma_addr_t phys, int token_id) 1109 { 1110 struct mt76_connac_fw_txp *txp = ptr + MT_TXD_SIZE; 1111 __le32 *txwi = ptr; 1112 u32 val; 1113 1114 memset(ptr, 0, MT_TXD_SIZE + sizeof(*txp)); 1115 1116 val = FIELD_PREP(MT_TXD0_TX_BYTES, MT_TXD_SIZE) | 1117 FIELD_PREP(MT_TXD0_PKT_FMT, MT_TX_TYPE_CT); 1118 txwi[0] = cpu_to_le32(val); 1119 1120 val = BIT(31) | 1121 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_3); 1122 txwi[1] = cpu_to_le32(val); 1123 1124 txp->token = cpu_to_le16(token_id); 1125 txp->nbuf = 1; 1126 txp->buf[0] = cpu_to_le32(phys + MT_TXD_SIZE + sizeof(*txp)); 1127 1128 return MT_TXD_SIZE + sizeof(*txp); 1129 } 1130 1131 static void 1132 mt7996_tx_check_aggr(struct ieee80211_link_sta *link_sta, 1133 struct mt76_wcid *wcid, struct sk_buff *skb) 1134 { 1135 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1136 bool is_8023 = info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP; 1137 u16 fc, tid; 1138 1139 if (!(link_sta->ht_cap.ht_supported || link_sta->he_cap.has_he)) 1140 return; 1141 1142 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 1143 if (tid >= 6) /* skip VO queue */ 1144 return; 1145 1146 if (is_8023) { 1147 fc = IEEE80211_FTYPE_DATA | 1148 (link_sta->sta->wme ? IEEE80211_STYPE_QOS_DATA 1149 : IEEE80211_STYPE_DATA); 1150 } else { 1151 /* No need to get precise TID for Action/Management Frame, 1152 * since it will not meet the following Frame Control 1153 * condition anyway. 1154 */ 1155 1156 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1157 1158 fc = le16_to_cpu(hdr->frame_control) & 1159 (IEEE80211_FCTL_FTYPE | IEEE80211_FCTL_STYPE); 1160 } 1161 1162 if (unlikely(fc != (IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_DATA))) 1163 return; 1164 1165 if (!test_and_set_bit(tid, &wcid->ampdu_state)) 1166 ieee80211_start_tx_ba_session(link_sta->sta, tid, 0); 1167 } 1168 1169 static void 1170 mt7996_txwi_free(struct mt7996_dev *dev, struct mt76_txwi_cache *t, 1171 struct ieee80211_link_sta *link_sta, 1172 struct mt76_wcid *wcid, struct list_head *free_list) 1173 { 1174 struct mt76_dev *mdev = &dev->mt76; 1175 __le32 *txwi; 1176 u16 wcid_idx; 1177 1178 mt76_connac_txp_skb_unmap(mdev, t); 1179 if (!t->skb) 1180 goto out; 1181 1182 txwi = (__le32 *)mt76_get_txwi_ptr(mdev, t); 1183 if (link_sta) { 1184 wcid_idx = wcid->idx; 1185 if (likely(t->skb->protocol != cpu_to_be16(ETH_P_PAE))) 1186 mt7996_tx_check_aggr(link_sta, wcid, t->skb); 1187 } else { 1188 wcid_idx = le32_get_bits(txwi[9], MT_TXD9_WLAN_IDX); 1189 } 1190 1191 __mt76_tx_complete_skb(mdev, wcid_idx, t->skb, free_list); 1192 1193 out: 1194 t->skb = NULL; 1195 mt76_put_txwi(mdev, t); 1196 } 1197 1198 static void 1199 mt7996_mac_tx_free(struct mt7996_dev *dev, void *data, int len) 1200 { 1201 __le32 *tx_free = (__le32 *)data, *cur_info; 1202 struct mt76_dev *mdev = &dev->mt76; 1203 struct mt76_phy *phy2 = mdev->phys[MT_BAND1]; 1204 struct mt76_phy *phy3 = mdev->phys[MT_BAND2]; 1205 struct ieee80211_link_sta *link_sta = NULL; 1206 struct mt76_txwi_cache *txwi; 1207 struct mt76_wcid *wcid = NULL; 1208 LIST_HEAD(free_list); 1209 struct sk_buff *skb, *tmp; 1210 void *end = data + len; 1211 bool wake = false; 1212 u16 total, count = 0; 1213 u8 ver; 1214 1215 /* clean DMA queues and unmap buffers first */ 1216 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false); 1217 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false); 1218 if (phy2) { 1219 mt76_queue_tx_cleanup(dev, phy2->q_tx[MT_TXQ_PSD], false); 1220 mt76_queue_tx_cleanup(dev, phy2->q_tx[MT_TXQ_BE], false); 1221 } 1222 if (phy3) { 1223 mt76_queue_tx_cleanup(dev, phy3->q_tx[MT_TXQ_PSD], false); 1224 mt76_queue_tx_cleanup(dev, phy3->q_tx[MT_TXQ_BE], false); 1225 } 1226 1227 ver = le32_get_bits(tx_free[1], MT_TXFREE1_VER); 1228 if (WARN_ON_ONCE(ver < 5)) 1229 return; 1230 1231 total = le32_get_bits(tx_free[0], MT_TXFREE0_MSDU_CNT); 1232 for (cur_info = &tx_free[2]; count < total; cur_info++) { 1233 u32 msdu, info; 1234 u8 i; 1235 1236 if (WARN_ON_ONCE((void *)cur_info >= end)) 1237 return; 1238 /* 1'b1: new wcid pair. 1239 * 1'b0: msdu_id with the same 'wcid pair' as above. 1240 */ 1241 info = le32_to_cpu(*cur_info); 1242 if (info & MT_TXFREE_INFO_PAIR) { 1243 struct ieee80211_sta *sta; 1244 u16 idx; 1245 1246 idx = FIELD_GET(MT_TXFREE_INFO_WLAN_ID, info); 1247 wcid = rcu_dereference(dev->mt76.wcid[idx]); 1248 sta = wcid_to_sta(wcid); 1249 if (!sta) 1250 goto next; 1251 1252 link_sta = rcu_dereference(sta->link[wcid->link_id]); 1253 if (!link_sta) 1254 goto next; 1255 1256 mt76_wcid_add_poll(&dev->mt76, wcid); 1257 next: 1258 /* ver 7 has a new DW with pair = 1, skip it */ 1259 if (ver == 7 && ((void *)(cur_info + 1) < end) && 1260 (le32_to_cpu(*(cur_info + 1)) & MT_TXFREE_INFO_PAIR)) 1261 cur_info++; 1262 continue; 1263 } else if (info & MT_TXFREE_INFO_HEADER) { 1264 u32 tx_retries = 0, tx_failed = 0; 1265 1266 if (!wcid) 1267 continue; 1268 1269 tx_retries = 1270 FIELD_GET(MT_TXFREE_INFO_COUNT, info) - 1; 1271 tx_failed = tx_retries + 1272 !!FIELD_GET(MT_TXFREE_INFO_STAT, info); 1273 1274 wcid->stats.tx_retries += tx_retries; 1275 wcid->stats.tx_failed += tx_failed; 1276 continue; 1277 } 1278 1279 for (i = 0; i < 2; i++) { 1280 msdu = (info >> (15 * i)) & MT_TXFREE_INFO_MSDU_ID; 1281 if (msdu == MT_TXFREE_INFO_MSDU_ID) 1282 continue; 1283 1284 count++; 1285 txwi = mt76_token_release(mdev, msdu, &wake); 1286 if (!txwi) 1287 continue; 1288 1289 mt7996_txwi_free(dev, txwi, link_sta, wcid, 1290 &free_list); 1291 } 1292 } 1293 1294 mt7996_mac_sta_poll(dev); 1295 1296 if (wake) 1297 mt76_set_tx_blocked(&dev->mt76, false); 1298 1299 mt76_worker_schedule(&dev->mt76.tx_worker); 1300 1301 list_for_each_entry_safe(skb, tmp, &free_list, list) { 1302 skb_list_del_init(skb); 1303 napi_consume_skb(skb, 1); 1304 } 1305 } 1306 1307 static bool 1308 mt7996_mac_add_txs_skb(struct mt7996_dev *dev, struct mt76_wcid *wcid, 1309 int pid, __le32 *txs_data) 1310 { 1311 struct mt76_sta_stats *stats = &wcid->stats; 1312 struct ieee80211_supported_band *sband; 1313 struct mt76_dev *mdev = &dev->mt76; 1314 struct mt76_phy *mphy; 1315 struct ieee80211_tx_info *info; 1316 struct sk_buff_head list; 1317 struct rate_info rate = {}; 1318 struct sk_buff *skb = NULL; 1319 bool cck = false; 1320 u32 txrate, txs, mode, stbc; 1321 1322 txs = le32_to_cpu(txs_data[0]); 1323 1324 mt76_tx_status_lock(mdev, &list); 1325 1326 /* only report MPDU TXS */ 1327 if (le32_get_bits(txs_data[0], MT_TXS0_TXS_FORMAT) == 0) { 1328 skb = mt76_tx_status_skb_get(mdev, wcid, pid, &list); 1329 if (skb) { 1330 info = IEEE80211_SKB_CB(skb); 1331 if (!(txs & MT_TXS0_ACK_ERROR_MASK)) 1332 info->flags |= IEEE80211_TX_STAT_ACK; 1333 1334 info->status.ampdu_len = 1; 1335 info->status.ampdu_ack_len = 1336 !!(info->flags & IEEE80211_TX_STAT_ACK); 1337 1338 info->status.rates[0].idx = -1; 1339 } 1340 } 1341 1342 if (mtk_wed_device_active(&dev->mt76.mmio.wed) && wcid->sta) { 1343 struct ieee80211_sta *sta; 1344 u8 tid; 1345 1346 sta = wcid_to_sta(wcid); 1347 tid = FIELD_GET(MT_TXS0_TID, txs); 1348 ieee80211_refresh_tx_agg_session_timer(sta, tid); 1349 } 1350 1351 txrate = FIELD_GET(MT_TXS0_TX_RATE, txs); 1352 1353 rate.mcs = FIELD_GET(MT_TX_RATE_IDX, txrate); 1354 rate.nss = FIELD_GET(MT_TX_RATE_NSS, txrate) + 1; 1355 stbc = le32_get_bits(txs_data[3], MT_TXS3_RATE_STBC); 1356 1357 if (stbc && rate.nss > 1) 1358 rate.nss >>= 1; 1359 1360 if (rate.nss - 1 < ARRAY_SIZE(stats->tx_nss)) 1361 stats->tx_nss[rate.nss - 1]++; 1362 if (rate.mcs < ARRAY_SIZE(stats->tx_mcs)) 1363 stats->tx_mcs[rate.mcs]++; 1364 1365 mode = FIELD_GET(MT_TX_RATE_MODE, txrate); 1366 switch (mode) { 1367 case MT_PHY_TYPE_CCK: 1368 cck = true; 1369 fallthrough; 1370 case MT_PHY_TYPE_OFDM: 1371 mphy = mt76_dev_phy(mdev, wcid->phy_idx); 1372 1373 if (mphy->chandef.chan->band == NL80211_BAND_5GHZ) 1374 sband = &mphy->sband_5g.sband; 1375 else if (mphy->chandef.chan->band == NL80211_BAND_6GHZ) 1376 sband = &mphy->sband_6g.sband; 1377 else 1378 sband = &mphy->sband_2g.sband; 1379 1380 rate.mcs = mt76_get_rate(mphy->dev, sband, rate.mcs, cck); 1381 rate.legacy = sband->bitrates[rate.mcs].bitrate; 1382 break; 1383 case MT_PHY_TYPE_HT: 1384 case MT_PHY_TYPE_HT_GF: 1385 if (rate.mcs > 31) 1386 goto out; 1387 1388 rate.flags = RATE_INFO_FLAGS_MCS; 1389 if (wcid->rate.flags & RATE_INFO_FLAGS_SHORT_GI) 1390 rate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1391 break; 1392 case MT_PHY_TYPE_VHT: 1393 if (rate.mcs > 9) 1394 goto out; 1395 1396 rate.flags = RATE_INFO_FLAGS_VHT_MCS; 1397 if (wcid->rate.flags & RATE_INFO_FLAGS_SHORT_GI) 1398 rate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1399 break; 1400 case MT_PHY_TYPE_HE_SU: 1401 case MT_PHY_TYPE_HE_EXT_SU: 1402 case MT_PHY_TYPE_HE_TB: 1403 case MT_PHY_TYPE_HE_MU: 1404 if (rate.mcs > 11) 1405 goto out; 1406 1407 rate.he_gi = wcid->rate.he_gi; 1408 rate.he_dcm = FIELD_GET(MT_TX_RATE_DCM, txrate); 1409 rate.flags = RATE_INFO_FLAGS_HE_MCS; 1410 break; 1411 case MT_PHY_TYPE_EHT_SU: 1412 case MT_PHY_TYPE_EHT_TRIG: 1413 case MT_PHY_TYPE_EHT_MU: 1414 if (rate.mcs > 13) 1415 goto out; 1416 1417 rate.eht_gi = wcid->rate.eht_gi; 1418 rate.flags = RATE_INFO_FLAGS_EHT_MCS; 1419 break; 1420 default: 1421 goto out; 1422 } 1423 1424 stats->tx_mode[mode]++; 1425 1426 switch (FIELD_GET(MT_TXS0_BW, txs)) { 1427 case IEEE80211_STA_RX_BW_320: 1428 rate.bw = RATE_INFO_BW_320; 1429 stats->tx_bw[4]++; 1430 break; 1431 case IEEE80211_STA_RX_BW_160: 1432 rate.bw = RATE_INFO_BW_160; 1433 stats->tx_bw[3]++; 1434 break; 1435 case IEEE80211_STA_RX_BW_80: 1436 rate.bw = RATE_INFO_BW_80; 1437 stats->tx_bw[2]++; 1438 break; 1439 case IEEE80211_STA_RX_BW_40: 1440 rate.bw = RATE_INFO_BW_40; 1441 stats->tx_bw[1]++; 1442 break; 1443 default: 1444 rate.bw = RATE_INFO_BW_20; 1445 stats->tx_bw[0]++; 1446 break; 1447 } 1448 wcid->rate = rate; 1449 1450 out: 1451 if (skb) 1452 mt76_tx_status_skb_done(mdev, skb, &list); 1453 mt76_tx_status_unlock(mdev, &list); 1454 1455 return !!skb; 1456 } 1457 1458 static void mt7996_mac_add_txs(struct mt7996_dev *dev, void *data) 1459 { 1460 struct mt7996_sta_link *msta_link; 1461 struct mt76_wcid *wcid; 1462 __le32 *txs_data = data; 1463 u16 wcidx; 1464 u8 pid; 1465 1466 wcidx = le32_get_bits(txs_data[2], MT_TXS2_WCID); 1467 pid = le32_get_bits(txs_data[3], MT_TXS3_PID); 1468 1469 if (pid < MT_PACKET_ID_NO_SKB) 1470 return; 1471 1472 if (wcidx >= mt7996_wtbl_size(dev)) 1473 return; 1474 1475 rcu_read_lock(); 1476 1477 wcid = rcu_dereference(dev->mt76.wcid[wcidx]); 1478 if (!wcid) 1479 goto out; 1480 1481 mt7996_mac_add_txs_skb(dev, wcid, pid, txs_data); 1482 1483 if (!wcid->sta) 1484 goto out; 1485 1486 msta_link = container_of(wcid, struct mt7996_sta_link, wcid); 1487 mt76_wcid_add_poll(&dev->mt76, &msta_link->wcid); 1488 1489 out: 1490 rcu_read_unlock(); 1491 } 1492 1493 bool mt7996_rx_check(struct mt76_dev *mdev, void *data, int len) 1494 { 1495 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 1496 __le32 *rxd = (__le32 *)data; 1497 __le32 *end = (__le32 *)&rxd[len / 4]; 1498 enum rx_pkt_type type; 1499 1500 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); 1501 if (type != PKT_TYPE_NORMAL) { 1502 u32 sw_type = le32_get_bits(rxd[0], MT_RXD0_SW_PKT_TYPE_MASK); 1503 1504 if (unlikely((sw_type & MT_RXD0_SW_PKT_TYPE_MAP) == 1505 MT_RXD0_SW_PKT_TYPE_FRAME)) 1506 return true; 1507 } 1508 1509 switch (type) { 1510 case PKT_TYPE_TXRX_NOTIFY: 1511 mt7996_mac_tx_free(dev, data, len); 1512 return false; 1513 case PKT_TYPE_TXS: 1514 for (rxd += MT_TXS_HDR_SIZE; rxd + MT_TXS_SIZE <= end; rxd += MT_TXS_SIZE) 1515 mt7996_mac_add_txs(dev, rxd); 1516 return false; 1517 case PKT_TYPE_RX_FW_MONITOR: 1518 mt7996_debugfs_rx_fw_monitor(dev, data, len); 1519 return false; 1520 default: 1521 return true; 1522 } 1523 } 1524 1525 void mt7996_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 1526 struct sk_buff *skb, u32 *info) 1527 { 1528 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 1529 __le32 *rxd = (__le32 *)skb->data; 1530 __le32 *end = (__le32 *)&skb->data[skb->len]; 1531 enum rx_pkt_type type; 1532 1533 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); 1534 if (type != PKT_TYPE_NORMAL) { 1535 u32 sw_type = le32_get_bits(rxd[0], MT_RXD0_SW_PKT_TYPE_MASK); 1536 1537 if (unlikely((sw_type & MT_RXD0_SW_PKT_TYPE_MAP) == 1538 MT_RXD0_SW_PKT_TYPE_FRAME)) 1539 type = PKT_TYPE_NORMAL; 1540 } 1541 1542 switch (type) { 1543 case PKT_TYPE_TXRX_NOTIFY: 1544 if (mtk_wed_device_active(&dev->mt76.mmio.wed_hif2) && 1545 q == MT_RXQ_TXFREE_BAND2) { 1546 dev_kfree_skb(skb); 1547 break; 1548 } 1549 1550 mt7996_mac_tx_free(dev, skb->data, skb->len); 1551 napi_consume_skb(skb, 1); 1552 break; 1553 case PKT_TYPE_RX_EVENT: 1554 mt7996_mcu_rx_event(dev, skb); 1555 break; 1556 case PKT_TYPE_TXS: 1557 for (rxd += MT_TXS_HDR_SIZE; rxd + MT_TXS_SIZE <= end; rxd += MT_TXS_SIZE) 1558 mt7996_mac_add_txs(dev, rxd); 1559 dev_kfree_skb(skb); 1560 break; 1561 case PKT_TYPE_RX_FW_MONITOR: 1562 mt7996_debugfs_rx_fw_monitor(dev, skb->data, skb->len); 1563 dev_kfree_skb(skb); 1564 break; 1565 case PKT_TYPE_NORMAL: 1566 if (!mt7996_mac_fill_rx(dev, q, skb, info)) { 1567 mt76_rx(&dev->mt76, q, skb); 1568 return; 1569 } 1570 fallthrough; 1571 default: 1572 dev_kfree_skb(skb); 1573 break; 1574 } 1575 } 1576 1577 void mt7996_mac_cca_stats_reset(struct mt7996_phy *phy) 1578 { 1579 struct mt7996_dev *dev = phy->dev; 1580 u32 reg = MT_WF_PHYRX_BAND_RX_CTRL1(phy->mt76->band_idx); 1581 1582 mt76_clear(dev, reg, MT_WF_PHYRX_BAND_RX_CTRL1_STSCNT_EN); 1583 mt76_set(dev, reg, BIT(11) | BIT(9)); 1584 } 1585 1586 void mt7996_mac_reset_counters(struct mt7996_phy *phy) 1587 { 1588 struct mt7996_dev *dev = phy->dev; 1589 u8 band_idx = phy->mt76->band_idx; 1590 int i; 1591 1592 for (i = 0; i < 16; i++) 1593 mt76_rr(dev, MT_TX_AGG_CNT(band_idx, i)); 1594 1595 phy->mt76->survey_time = ktime_get_boottime(); 1596 1597 memset(phy->mt76->aggr_stats, 0, sizeof(phy->mt76->aggr_stats)); 1598 1599 /* reset airtime counters */ 1600 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(band_idx), 1601 MT_WF_RMAC_MIB_RXTIME_CLR); 1602 1603 mt7996_mcu_get_chan_mib_info(phy, true); 1604 } 1605 1606 void mt7996_mac_set_coverage_class(struct mt7996_phy *phy) 1607 { 1608 s16 coverage_class = phy->coverage_class; 1609 struct mt7996_dev *dev = phy->dev; 1610 struct mt7996_phy *phy2 = mt7996_phy2(dev); 1611 struct mt7996_phy *phy3 = mt7996_phy3(dev); 1612 u32 reg_offset; 1613 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | 1614 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); 1615 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | 1616 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28); 1617 u8 band_idx = phy->mt76->band_idx; 1618 int offset; 1619 1620 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state)) 1621 return; 1622 1623 if (phy2) 1624 coverage_class = max_t(s16, dev->phy.coverage_class, 1625 phy2->coverage_class); 1626 1627 if (phy3) 1628 coverage_class = max_t(s16, coverage_class, 1629 phy3->coverage_class); 1630 1631 offset = 3 * coverage_class; 1632 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | 1633 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); 1634 1635 mt76_wr(dev, MT_TMAC_CDTR(band_idx), cck + reg_offset); 1636 mt76_wr(dev, MT_TMAC_ODTR(band_idx), ofdm + reg_offset); 1637 } 1638 1639 void mt7996_mac_enable_nf(struct mt7996_dev *dev, u8 band) 1640 { 1641 mt76_set(dev, MT_WF_PHYRX_CSD_BAND_RXTD12(band), 1642 MT_WF_PHYRX_CSD_BAND_RXTD12_IRPI_SW_CLR_ONLY | 1643 MT_WF_PHYRX_CSD_BAND_RXTD12_IRPI_SW_CLR); 1644 1645 mt76_set(dev, MT_WF_PHYRX_BAND_RX_CTRL1(band), 1646 FIELD_PREP(MT_WF_PHYRX_BAND_RX_CTRL1_IPI_EN, 0x5)); 1647 } 1648 1649 static u8 1650 mt7996_phy_get_nf(struct mt7996_phy *phy, u8 band_idx) 1651 { 1652 static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 }; 1653 struct mt7996_dev *dev = phy->dev; 1654 u32 val, sum = 0, n = 0; 1655 int ant, i; 1656 1657 for (ant = 0; ant < hweight8(phy->mt76->antenna_mask); ant++) { 1658 u32 reg = MT_WF_PHYRX_CSD_IRPI(band_idx, ant); 1659 1660 for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) { 1661 val = mt76_rr(dev, reg); 1662 sum += val * nf_power[i]; 1663 n += val; 1664 } 1665 } 1666 1667 return n ? sum / n : 0; 1668 } 1669 1670 void mt7996_update_channel(struct mt76_phy *mphy) 1671 { 1672 struct mt7996_phy *phy = mphy->priv; 1673 struct mt76_channel_state *state = mphy->chan_state; 1674 int nf; 1675 1676 mt7996_mcu_get_chan_mib_info(phy, false); 1677 1678 nf = mt7996_phy_get_nf(phy, mphy->band_idx); 1679 if (!phy->noise) 1680 phy->noise = nf << 4; 1681 else if (nf) 1682 phy->noise += nf - (phy->noise >> 4); 1683 1684 state->noise = -(phy->noise >> 4); 1685 } 1686 1687 static bool 1688 mt7996_wait_reset_state(struct mt7996_dev *dev, u32 state) 1689 { 1690 bool ret; 1691 1692 ret = wait_event_timeout(dev->reset_wait, 1693 (READ_ONCE(dev->recovery.state) & state), 1694 MT7996_RESET_TIMEOUT); 1695 1696 WARN(!ret, "Timeout waiting for MCU reset state %x\n", state); 1697 return ret; 1698 } 1699 1700 static void 1701 mt7996_update_vif_beacon(void *priv, u8 *mac, struct ieee80211_vif *vif) 1702 { 1703 struct ieee80211_hw *hw = priv; 1704 1705 switch (vif->type) { 1706 case NL80211_IFTYPE_MESH_POINT: 1707 case NL80211_IFTYPE_ADHOC: 1708 case NL80211_IFTYPE_AP: 1709 mt7996_mcu_add_beacon(hw, vif, &vif->bss_conf); 1710 break; 1711 default: 1712 break; 1713 } 1714 } 1715 1716 static void 1717 mt7996_update_beacons(struct mt7996_dev *dev) 1718 { 1719 struct mt76_phy *phy2, *phy3; 1720 1721 ieee80211_iterate_active_interfaces(dev->mt76.hw, 1722 IEEE80211_IFACE_ITER_RESUME_ALL, 1723 mt7996_update_vif_beacon, dev->mt76.hw); 1724 1725 phy2 = dev->mt76.phys[MT_BAND1]; 1726 if (!phy2) 1727 return; 1728 1729 ieee80211_iterate_active_interfaces(phy2->hw, 1730 IEEE80211_IFACE_ITER_RESUME_ALL, 1731 mt7996_update_vif_beacon, phy2->hw); 1732 1733 phy3 = dev->mt76.phys[MT_BAND2]; 1734 if (!phy3) 1735 return; 1736 1737 ieee80211_iterate_active_interfaces(phy3->hw, 1738 IEEE80211_IFACE_ITER_RESUME_ALL, 1739 mt7996_update_vif_beacon, phy3->hw); 1740 } 1741 1742 void mt7996_tx_token_put(struct mt7996_dev *dev) 1743 { 1744 struct mt76_txwi_cache *txwi; 1745 int id; 1746 1747 spin_lock_bh(&dev->mt76.token_lock); 1748 idr_for_each_entry(&dev->mt76.token, txwi, id) { 1749 mt7996_txwi_free(dev, txwi, NULL, NULL, NULL); 1750 dev->mt76.token_count--; 1751 } 1752 spin_unlock_bh(&dev->mt76.token_lock); 1753 idr_destroy(&dev->mt76.token); 1754 } 1755 1756 static int 1757 mt7996_mac_restart(struct mt7996_dev *dev) 1758 { 1759 struct mt7996_phy *phy2, *phy3; 1760 struct mt76_dev *mdev = &dev->mt76; 1761 int i, ret; 1762 1763 phy2 = mt7996_phy2(dev); 1764 phy3 = mt7996_phy3(dev); 1765 1766 if (dev->hif2) { 1767 mt76_wr(dev, MT_INT1_MASK_CSR, 0x0); 1768 mt76_wr(dev, MT_INT1_SOURCE_CSR, ~0); 1769 } 1770 1771 if (dev_is_pci(mdev->dev)) { 1772 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0); 1773 if (dev->hif2) 1774 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE, 0x0); 1775 } 1776 1777 set_bit(MT76_RESET, &dev->mphy.state); 1778 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1779 wake_up(&dev->mt76.mcu.wait); 1780 if (phy2) 1781 set_bit(MT76_RESET, &phy2->mt76->state); 1782 if (phy3) 1783 set_bit(MT76_RESET, &phy3->mt76->state); 1784 1785 /* lock/unlock all queues to ensure that no tx is pending */ 1786 mt76_txq_schedule_all(&dev->mphy); 1787 if (phy2) 1788 mt76_txq_schedule_all(phy2->mt76); 1789 if (phy3) 1790 mt76_txq_schedule_all(phy3->mt76); 1791 1792 /* disable all tx/rx napi */ 1793 mt76_worker_disable(&dev->mt76.tx_worker); 1794 mt76_for_each_q_rx(mdev, i) { 1795 if (mtk_wed_device_active(&dev->mt76.mmio.wed) && 1796 mt76_queue_is_wed_rro(&mdev->q_rx[i])) 1797 continue; 1798 1799 if (mdev->q_rx[i].ndesc) 1800 napi_disable(&dev->mt76.napi[i]); 1801 } 1802 napi_disable(&dev->mt76.tx_napi); 1803 1804 /* token reinit */ 1805 mt7996_tx_token_put(dev); 1806 idr_init(&dev->mt76.token); 1807 1808 mt7996_dma_reset(dev, true); 1809 1810 mt76_for_each_q_rx(mdev, i) { 1811 if (mtk_wed_device_active(&dev->mt76.mmio.wed) && 1812 mt76_queue_is_wed_rro(&mdev->q_rx[i])) 1813 continue; 1814 1815 if (mdev->q_rx[i].ndesc) { 1816 napi_enable(&dev->mt76.napi[i]); 1817 local_bh_disable(); 1818 napi_schedule(&dev->mt76.napi[i]); 1819 local_bh_enable(); 1820 } 1821 } 1822 clear_bit(MT76_MCU_RESET, &dev->mphy.state); 1823 clear_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state); 1824 1825 mt76_wr(dev, MT_INT_MASK_CSR, dev->mt76.mmio.irqmask); 1826 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 1827 if (dev->hif2) { 1828 mt76_wr(dev, MT_INT1_MASK_CSR, dev->mt76.mmio.irqmask); 1829 mt76_wr(dev, MT_INT1_SOURCE_CSR, ~0); 1830 } 1831 if (dev_is_pci(mdev->dev)) { 1832 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff); 1833 if (dev->hif2) 1834 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE, 0xff); 1835 } 1836 1837 /* load firmware */ 1838 ret = mt7996_mcu_init_firmware(dev); 1839 if (ret) 1840 goto out; 1841 1842 /* set the necessary init items */ 1843 ret = mt7996_mcu_set_eeprom(dev); 1844 if (ret) 1845 goto out; 1846 1847 mt7996_mac_init(dev); 1848 mt7996_init_txpower(&dev->phy); 1849 mt7996_init_txpower(phy2); 1850 mt7996_init_txpower(phy3); 1851 ret = mt7996_txbf_init(dev); 1852 1853 if (test_bit(MT76_STATE_RUNNING, &dev->mphy.state)) { 1854 ret = mt7996_run(&dev->phy); 1855 if (ret) 1856 goto out; 1857 } 1858 1859 if (phy2 && test_bit(MT76_STATE_RUNNING, &phy2->mt76->state)) { 1860 ret = mt7996_run(phy2); 1861 if (ret) 1862 goto out; 1863 } 1864 1865 if (phy3 && test_bit(MT76_STATE_RUNNING, &phy3->mt76->state)) { 1866 ret = mt7996_run(phy3); 1867 if (ret) 1868 goto out; 1869 } 1870 1871 out: 1872 /* reset done */ 1873 clear_bit(MT76_RESET, &dev->mphy.state); 1874 if (phy2) 1875 clear_bit(MT76_RESET, &phy2->mt76->state); 1876 if (phy3) 1877 clear_bit(MT76_RESET, &phy3->mt76->state); 1878 1879 napi_enable(&dev->mt76.tx_napi); 1880 local_bh_disable(); 1881 napi_schedule(&dev->mt76.tx_napi); 1882 local_bh_enable(); 1883 1884 mt76_worker_enable(&dev->mt76.tx_worker); 1885 return ret; 1886 } 1887 1888 static void 1889 mt7996_mac_full_reset(struct mt7996_dev *dev) 1890 { 1891 struct mt7996_phy *phy2, *phy3; 1892 int i; 1893 1894 phy2 = mt7996_phy2(dev); 1895 phy3 = mt7996_phy3(dev); 1896 dev->recovery.hw_full_reset = true; 1897 1898 wake_up(&dev->mt76.mcu.wait); 1899 ieee80211_stop_queues(mt76_hw(dev)); 1900 if (phy2) 1901 ieee80211_stop_queues(phy2->mt76->hw); 1902 if (phy3) 1903 ieee80211_stop_queues(phy3->mt76->hw); 1904 1905 cancel_work_sync(&dev->wed_rro.work); 1906 cancel_delayed_work_sync(&dev->mphy.mac_work); 1907 if (phy2) 1908 cancel_delayed_work_sync(&phy2->mt76->mac_work); 1909 if (phy3) 1910 cancel_delayed_work_sync(&phy3->mt76->mac_work); 1911 1912 mutex_lock(&dev->mt76.mutex); 1913 for (i = 0; i < 10; i++) { 1914 if (!mt7996_mac_restart(dev)) 1915 break; 1916 } 1917 mutex_unlock(&dev->mt76.mutex); 1918 1919 if (i == 10) 1920 dev_err(dev->mt76.dev, "chip full reset failed\n"); 1921 1922 ieee80211_restart_hw(mt76_hw(dev)); 1923 if (phy2) 1924 ieee80211_restart_hw(phy2->mt76->hw); 1925 if (phy3) 1926 ieee80211_restart_hw(phy3->mt76->hw); 1927 1928 ieee80211_wake_queues(mt76_hw(dev)); 1929 if (phy2) 1930 ieee80211_wake_queues(phy2->mt76->hw); 1931 if (phy3) 1932 ieee80211_wake_queues(phy3->mt76->hw); 1933 1934 dev->recovery.hw_full_reset = false; 1935 ieee80211_queue_delayed_work(mt76_hw(dev), 1936 &dev->mphy.mac_work, 1937 MT7996_WATCHDOG_TIME); 1938 if (phy2) 1939 ieee80211_queue_delayed_work(phy2->mt76->hw, 1940 &phy2->mt76->mac_work, 1941 MT7996_WATCHDOG_TIME); 1942 if (phy3) 1943 ieee80211_queue_delayed_work(phy3->mt76->hw, 1944 &phy3->mt76->mac_work, 1945 MT7996_WATCHDOG_TIME); 1946 } 1947 1948 void mt7996_mac_reset_work(struct work_struct *work) 1949 { 1950 struct mt7996_phy *phy2, *phy3; 1951 struct mt7996_dev *dev; 1952 int i; 1953 1954 dev = container_of(work, struct mt7996_dev, reset_work); 1955 phy2 = mt7996_phy2(dev); 1956 phy3 = mt7996_phy3(dev); 1957 1958 /* chip full reset */ 1959 if (dev->recovery.restart) { 1960 /* disable WA/WM WDT */ 1961 mt76_clear(dev, MT_WFDMA0_MCU_HOST_INT_ENA, 1962 MT_MCU_CMD_WDT_MASK); 1963 1964 if (READ_ONCE(dev->recovery.state) & MT_MCU_CMD_WA_WDT) 1965 dev->recovery.wa_reset_count++; 1966 else 1967 dev->recovery.wm_reset_count++; 1968 1969 mt7996_mac_full_reset(dev); 1970 1971 /* enable mcu irq */ 1972 mt7996_irq_enable(dev, MT_INT_MCU_CMD); 1973 mt7996_irq_disable(dev, 0); 1974 1975 /* enable WA/WM WDT */ 1976 mt76_set(dev, MT_WFDMA0_MCU_HOST_INT_ENA, MT_MCU_CMD_WDT_MASK); 1977 1978 dev->recovery.state = MT_MCU_CMD_NORMAL_STATE; 1979 dev->recovery.restart = false; 1980 return; 1981 } 1982 1983 if (!(READ_ONCE(dev->recovery.state) & MT_MCU_CMD_STOP_DMA)) 1984 return; 1985 1986 dev_info(dev->mt76.dev,"\n%s L1 SER recovery start.", 1987 wiphy_name(dev->mt76.hw->wiphy)); 1988 1989 if (mtk_wed_device_active(&dev->mt76.mmio.wed_hif2)) 1990 mtk_wed_device_stop(&dev->mt76.mmio.wed_hif2); 1991 1992 if (mtk_wed_device_active(&dev->mt76.mmio.wed)) 1993 mtk_wed_device_stop(&dev->mt76.mmio.wed); 1994 1995 ieee80211_stop_queues(mt76_hw(dev)); 1996 if (phy2) 1997 ieee80211_stop_queues(phy2->mt76->hw); 1998 if (phy3) 1999 ieee80211_stop_queues(phy3->mt76->hw); 2000 2001 set_bit(MT76_RESET, &dev->mphy.state); 2002 set_bit(MT76_MCU_RESET, &dev->mphy.state); 2003 wake_up(&dev->mt76.mcu.wait); 2004 2005 cancel_work_sync(&dev->wed_rro.work); 2006 cancel_delayed_work_sync(&dev->mphy.mac_work); 2007 if (phy2) { 2008 set_bit(MT76_RESET, &phy2->mt76->state); 2009 cancel_delayed_work_sync(&phy2->mt76->mac_work); 2010 } 2011 if (phy3) { 2012 set_bit(MT76_RESET, &phy3->mt76->state); 2013 cancel_delayed_work_sync(&phy3->mt76->mac_work); 2014 } 2015 mt76_worker_disable(&dev->mt76.tx_worker); 2016 mt76_for_each_q_rx(&dev->mt76, i) { 2017 if (mtk_wed_device_active(&dev->mt76.mmio.wed) && 2018 mt76_queue_is_wed_rro(&dev->mt76.q_rx[i])) 2019 continue; 2020 2021 napi_disable(&dev->mt76.napi[i]); 2022 } 2023 napi_disable(&dev->mt76.tx_napi); 2024 2025 mutex_lock(&dev->mt76.mutex); 2026 2027 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_STOPPED); 2028 2029 if (mt7996_wait_reset_state(dev, MT_MCU_CMD_RESET_DONE)) { 2030 mt7996_dma_reset(dev, false); 2031 2032 mt7996_tx_token_put(dev); 2033 idr_init(&dev->mt76.token); 2034 2035 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_INIT); 2036 mt7996_wait_reset_state(dev, MT_MCU_CMD_RECOVERY_DONE); 2037 } 2038 2039 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_RESET_DONE); 2040 mt7996_wait_reset_state(dev, MT_MCU_CMD_NORMAL_STATE); 2041 2042 /* enable DMA Tx/Tx and interrupt */ 2043 mt7996_dma_start(dev, false, false); 2044 2045 if (mtk_wed_device_active(&dev->mt76.mmio.wed)) { 2046 u32 wed_irq_mask = MT_INT_RRO_RX_DONE | MT_INT_TX_DONE_BAND2 | 2047 dev->mt76.mmio.irqmask; 2048 2049 if (mtk_wed_get_rx_capa(&dev->mt76.mmio.wed)) 2050 wed_irq_mask &= ~MT_INT_RX_DONE_RRO_IND; 2051 2052 mt76_wr(dev, MT_INT_MASK_CSR, wed_irq_mask); 2053 2054 mtk_wed_device_start_hw_rro(&dev->mt76.mmio.wed, wed_irq_mask, 2055 true); 2056 mt7996_irq_enable(dev, wed_irq_mask); 2057 mt7996_irq_disable(dev, 0); 2058 } 2059 2060 if (mtk_wed_device_active(&dev->mt76.mmio.wed_hif2)) { 2061 mt76_wr(dev, MT_INT_PCIE1_MASK_CSR, MT_INT_TX_RX_DONE_EXT); 2062 mtk_wed_device_start(&dev->mt76.mmio.wed_hif2, 2063 MT_INT_TX_RX_DONE_EXT); 2064 } 2065 2066 clear_bit(MT76_MCU_RESET, &dev->mphy.state); 2067 clear_bit(MT76_RESET, &dev->mphy.state); 2068 if (phy2) 2069 clear_bit(MT76_RESET, &phy2->mt76->state); 2070 if (phy3) 2071 clear_bit(MT76_RESET, &phy3->mt76->state); 2072 2073 mt76_for_each_q_rx(&dev->mt76, i) { 2074 if (mtk_wed_device_active(&dev->mt76.mmio.wed) && 2075 mt76_queue_is_wed_rro(&dev->mt76.q_rx[i])) 2076 continue; 2077 2078 napi_enable(&dev->mt76.napi[i]); 2079 local_bh_disable(); 2080 napi_schedule(&dev->mt76.napi[i]); 2081 local_bh_enable(); 2082 } 2083 2084 tasklet_schedule(&dev->mt76.irq_tasklet); 2085 2086 mt76_worker_enable(&dev->mt76.tx_worker); 2087 2088 napi_enable(&dev->mt76.tx_napi); 2089 local_bh_disable(); 2090 napi_schedule(&dev->mt76.tx_napi); 2091 local_bh_enable(); 2092 2093 ieee80211_wake_queues(mt76_hw(dev)); 2094 if (phy2) 2095 ieee80211_wake_queues(phy2->mt76->hw); 2096 if (phy3) 2097 ieee80211_wake_queues(phy3->mt76->hw); 2098 2099 mutex_unlock(&dev->mt76.mutex); 2100 2101 mt7996_update_beacons(dev); 2102 2103 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work, 2104 MT7996_WATCHDOG_TIME); 2105 if (phy2) 2106 ieee80211_queue_delayed_work(phy2->mt76->hw, 2107 &phy2->mt76->mac_work, 2108 MT7996_WATCHDOG_TIME); 2109 if (phy3) 2110 ieee80211_queue_delayed_work(phy3->mt76->hw, 2111 &phy3->mt76->mac_work, 2112 MT7996_WATCHDOG_TIME); 2113 dev_info(dev->mt76.dev,"\n%s L1 SER recovery completed.", 2114 wiphy_name(dev->mt76.hw->wiphy)); 2115 } 2116 2117 /* firmware coredump */ 2118 void mt7996_mac_dump_work(struct work_struct *work) 2119 { 2120 const struct mt7996_mem_region *mem_region; 2121 struct mt7996_crash_data *crash_data; 2122 struct mt7996_dev *dev; 2123 struct mt7996_mem_hdr *hdr; 2124 size_t buf_len; 2125 int i; 2126 u32 num; 2127 u8 *buf; 2128 2129 dev = container_of(work, struct mt7996_dev, dump_work); 2130 2131 mutex_lock(&dev->dump_mutex); 2132 2133 crash_data = mt7996_coredump_new(dev); 2134 if (!crash_data) { 2135 mutex_unlock(&dev->dump_mutex); 2136 goto skip_coredump; 2137 } 2138 2139 mem_region = mt7996_coredump_get_mem_layout(dev, &num); 2140 if (!mem_region || !crash_data->memdump_buf_len) { 2141 mutex_unlock(&dev->dump_mutex); 2142 goto skip_memdump; 2143 } 2144 2145 buf = crash_data->memdump_buf; 2146 buf_len = crash_data->memdump_buf_len; 2147 2148 /* dumping memory content... */ 2149 memset(buf, 0, buf_len); 2150 for (i = 0; i < num; i++) { 2151 if (mem_region->len > buf_len) { 2152 dev_warn(dev->mt76.dev, "%s len %zu is too large\n", 2153 mem_region->name, mem_region->len); 2154 break; 2155 } 2156 2157 /* reserve space for the header */ 2158 hdr = (void *)buf; 2159 buf += sizeof(*hdr); 2160 buf_len -= sizeof(*hdr); 2161 2162 mt7996_memcpy_fromio(dev, buf, mem_region->start, 2163 mem_region->len); 2164 2165 hdr->start = mem_region->start; 2166 hdr->len = mem_region->len; 2167 2168 if (!mem_region->len) 2169 /* note: the header remains, just with zero length */ 2170 break; 2171 2172 buf += mem_region->len; 2173 buf_len -= mem_region->len; 2174 2175 mem_region++; 2176 } 2177 2178 mutex_unlock(&dev->dump_mutex); 2179 2180 skip_memdump: 2181 mt7996_coredump_submit(dev); 2182 skip_coredump: 2183 queue_work(dev->mt76.wq, &dev->reset_work); 2184 } 2185 2186 void mt7996_reset(struct mt7996_dev *dev) 2187 { 2188 if (!dev->recovery.hw_init_done) 2189 return; 2190 2191 if (dev->recovery.hw_full_reset) 2192 return; 2193 2194 /* wm/wa exception: do full recovery */ 2195 if (READ_ONCE(dev->recovery.state) & MT_MCU_CMD_WDT_MASK) { 2196 dev->recovery.restart = true; 2197 dev_info(dev->mt76.dev, 2198 "%s indicated firmware crash, attempting recovery\n", 2199 wiphy_name(dev->mt76.hw->wiphy)); 2200 2201 mt7996_irq_disable(dev, MT_INT_MCU_CMD); 2202 queue_work(dev->mt76.wq, &dev->dump_work); 2203 return; 2204 } 2205 2206 queue_work(dev->mt76.wq, &dev->reset_work); 2207 wake_up(&dev->reset_wait); 2208 } 2209 2210 void mt7996_mac_update_stats(struct mt7996_phy *phy) 2211 { 2212 struct mt76_mib_stats *mib = &phy->mib; 2213 struct mt7996_dev *dev = phy->dev; 2214 u8 band_idx = phy->mt76->band_idx; 2215 u32 cnt; 2216 int i; 2217 2218 cnt = mt76_rr(dev, MT_MIB_RSCR1(band_idx)); 2219 mib->fcs_err_cnt += cnt; 2220 2221 cnt = mt76_rr(dev, MT_MIB_RSCR33(band_idx)); 2222 mib->rx_fifo_full_cnt += cnt; 2223 2224 cnt = mt76_rr(dev, MT_MIB_RSCR31(band_idx)); 2225 mib->rx_mpdu_cnt += cnt; 2226 2227 cnt = mt76_rr(dev, MT_MIB_SDR6(band_idx)); 2228 mib->channel_idle_cnt += FIELD_GET(MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK, cnt); 2229 2230 cnt = mt76_rr(dev, MT_MIB_RVSR0(band_idx)); 2231 mib->rx_vector_mismatch_cnt += cnt; 2232 2233 cnt = mt76_rr(dev, MT_MIB_RSCR35(band_idx)); 2234 mib->rx_delimiter_fail_cnt += cnt; 2235 2236 cnt = mt76_rr(dev, MT_MIB_RSCR36(band_idx)); 2237 mib->rx_len_mismatch_cnt += cnt; 2238 2239 cnt = mt76_rr(dev, MT_MIB_TSCR0(band_idx)); 2240 mib->tx_ampdu_cnt += cnt; 2241 2242 cnt = mt76_rr(dev, MT_MIB_TSCR2(band_idx)); 2243 mib->tx_stop_q_empty_cnt += cnt; 2244 2245 cnt = mt76_rr(dev, MT_MIB_TSCR3(band_idx)); 2246 mib->tx_mpdu_attempts_cnt += cnt; 2247 2248 cnt = mt76_rr(dev, MT_MIB_TSCR4(band_idx)); 2249 mib->tx_mpdu_success_cnt += cnt; 2250 2251 cnt = mt76_rr(dev, MT_MIB_RSCR27(band_idx)); 2252 mib->rx_ampdu_cnt += cnt; 2253 2254 cnt = mt76_rr(dev, MT_MIB_RSCR28(band_idx)); 2255 mib->rx_ampdu_bytes_cnt += cnt; 2256 2257 cnt = mt76_rr(dev, MT_MIB_RSCR29(band_idx)); 2258 mib->rx_ampdu_valid_subframe_cnt += cnt; 2259 2260 cnt = mt76_rr(dev, MT_MIB_RSCR30(band_idx)); 2261 mib->rx_ampdu_valid_subframe_bytes_cnt += cnt; 2262 2263 cnt = mt76_rr(dev, MT_MIB_SDR27(band_idx)); 2264 mib->tx_rwp_fail_cnt += FIELD_GET(MT_MIB_SDR27_TX_RWP_FAIL_CNT, cnt); 2265 2266 cnt = mt76_rr(dev, MT_MIB_SDR28(band_idx)); 2267 mib->tx_rwp_need_cnt += FIELD_GET(MT_MIB_SDR28_TX_RWP_NEED_CNT, cnt); 2268 2269 cnt = mt76_rr(dev, MT_UMIB_RPDCR(band_idx)); 2270 mib->rx_pfdrop_cnt += cnt; 2271 2272 cnt = mt76_rr(dev, MT_MIB_RVSR1(band_idx)); 2273 mib->rx_vec_queue_overflow_drop_cnt += cnt; 2274 2275 cnt = mt76_rr(dev, MT_MIB_TSCR1(band_idx)); 2276 mib->rx_ba_cnt += cnt; 2277 2278 cnt = mt76_rr(dev, MT_MIB_BSCR0(band_idx)); 2279 mib->tx_bf_ebf_ppdu_cnt += cnt; 2280 2281 cnt = mt76_rr(dev, MT_MIB_BSCR1(band_idx)); 2282 mib->tx_bf_ibf_ppdu_cnt += cnt; 2283 2284 cnt = mt76_rr(dev, MT_MIB_BSCR2(band_idx)); 2285 mib->tx_mu_bf_cnt += cnt; 2286 2287 cnt = mt76_rr(dev, MT_MIB_TSCR5(band_idx)); 2288 mib->tx_mu_mpdu_cnt += cnt; 2289 2290 cnt = mt76_rr(dev, MT_MIB_TSCR6(band_idx)); 2291 mib->tx_mu_acked_mpdu_cnt += cnt; 2292 2293 cnt = mt76_rr(dev, MT_MIB_TSCR7(band_idx)); 2294 mib->tx_su_acked_mpdu_cnt += cnt; 2295 2296 cnt = mt76_rr(dev, MT_MIB_BSCR3(band_idx)); 2297 mib->tx_bf_rx_fb_ht_cnt += cnt; 2298 mib->tx_bf_rx_fb_all_cnt += cnt; 2299 2300 cnt = mt76_rr(dev, MT_MIB_BSCR4(band_idx)); 2301 mib->tx_bf_rx_fb_vht_cnt += cnt; 2302 mib->tx_bf_rx_fb_all_cnt += cnt; 2303 2304 cnt = mt76_rr(dev, MT_MIB_BSCR5(band_idx)); 2305 mib->tx_bf_rx_fb_he_cnt += cnt; 2306 mib->tx_bf_rx_fb_all_cnt += cnt; 2307 2308 cnt = mt76_rr(dev, MT_MIB_BSCR6(band_idx)); 2309 mib->tx_bf_rx_fb_eht_cnt += cnt; 2310 mib->tx_bf_rx_fb_all_cnt += cnt; 2311 2312 cnt = mt76_rr(dev, MT_ETBF_RX_FB_CONT(band_idx)); 2313 mib->tx_bf_rx_fb_bw = FIELD_GET(MT_ETBF_RX_FB_BW, cnt); 2314 mib->tx_bf_rx_fb_nc_cnt += FIELD_GET(MT_ETBF_RX_FB_NC, cnt); 2315 mib->tx_bf_rx_fb_nr_cnt += FIELD_GET(MT_ETBF_RX_FB_NR, cnt); 2316 2317 cnt = mt76_rr(dev, MT_MIB_BSCR7(band_idx)); 2318 mib->tx_bf_fb_trig_cnt += cnt; 2319 2320 cnt = mt76_rr(dev, MT_MIB_BSCR17(band_idx)); 2321 mib->tx_bf_fb_cpl_cnt += cnt; 2322 2323 for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) { 2324 cnt = mt76_rr(dev, MT_PLE_AMSDU_PACK_MSDU_CNT(i)); 2325 mib->tx_amsdu[i] += cnt; 2326 mib->tx_amsdu_cnt += cnt; 2327 } 2328 2329 /* rts count */ 2330 cnt = mt76_rr(dev, MT_MIB_BTSCR5(band_idx)); 2331 mib->rts_cnt += cnt; 2332 2333 /* rts retry count */ 2334 cnt = mt76_rr(dev, MT_MIB_BTSCR6(band_idx)); 2335 mib->rts_retries_cnt += cnt; 2336 2337 /* ba miss count */ 2338 cnt = mt76_rr(dev, MT_MIB_BTSCR0(band_idx)); 2339 mib->ba_miss_cnt += cnt; 2340 2341 /* ack fail count */ 2342 cnt = mt76_rr(dev, MT_MIB_BFTFCR(band_idx)); 2343 mib->ack_fail_cnt += cnt; 2344 2345 for (i = 0; i < 16; i++) { 2346 cnt = mt76_rr(dev, MT_TX_AGG_CNT(band_idx, i)); 2347 phy->mt76->aggr_stats[i] += cnt; 2348 } 2349 } 2350 2351 void mt7996_mac_sta_rc_work(struct work_struct *work) 2352 { 2353 struct mt7996_dev *dev = container_of(work, struct mt7996_dev, rc_work); 2354 struct ieee80211_bss_conf *link_conf; 2355 struct ieee80211_link_sta *link_sta; 2356 struct mt7996_sta_link *msta_link; 2357 struct mt7996_vif_link *link; 2358 struct mt76_vif_link *mlink; 2359 struct ieee80211_sta *sta; 2360 struct ieee80211_vif *vif; 2361 struct mt7996_sta *msta; 2362 struct mt7996_vif *mvif; 2363 LIST_HEAD(list); 2364 u32 changed; 2365 u8 link_id; 2366 2367 rcu_read_lock(); 2368 spin_lock_bh(&dev->mt76.sta_poll_lock); 2369 list_splice_init(&dev->sta_rc_list, &list); 2370 2371 while (!list_empty(&list)) { 2372 msta_link = list_first_entry(&list, struct mt7996_sta_link, 2373 rc_list); 2374 list_del_init(&msta_link->rc_list); 2375 2376 changed = msta_link->changed; 2377 msta_link->changed = 0; 2378 2379 sta = wcid_to_sta(&msta_link->wcid); 2380 link_id = msta_link->wcid.link_id; 2381 msta = msta_link->sta; 2382 mvif = msta->vif; 2383 vif = container_of((void *)mvif, struct ieee80211_vif, drv_priv); 2384 2385 mlink = rcu_dereference(mvif->mt76.link[link_id]); 2386 if (!mlink) 2387 continue; 2388 2389 link_sta = rcu_dereference(sta->link[link_id]); 2390 if (!link_sta) 2391 continue; 2392 2393 link_conf = rcu_dereference(vif->link_conf[link_id]); 2394 if (!link_conf) 2395 continue; 2396 2397 spin_unlock_bh(&dev->mt76.sta_poll_lock); 2398 2399 link = (struct mt7996_vif_link *)mlink; 2400 2401 if (changed & (IEEE80211_RC_SUPP_RATES_CHANGED | 2402 IEEE80211_RC_NSS_CHANGED | 2403 IEEE80211_RC_BW_CHANGED)) 2404 mt7996_mcu_add_rate_ctrl(dev, vif, link_conf, 2405 link_sta, link, msta_link, 2406 true); 2407 2408 if (changed & IEEE80211_RC_SMPS_CHANGED) 2409 mt7996_mcu_set_fixed_field(dev, link_sta, link, 2410 msta_link, NULL, 2411 RATE_PARAM_MMPS_UPDATE); 2412 2413 spin_lock_bh(&dev->mt76.sta_poll_lock); 2414 } 2415 2416 spin_unlock_bh(&dev->mt76.sta_poll_lock); 2417 rcu_read_unlock(); 2418 } 2419 2420 void mt7996_mac_work(struct work_struct *work) 2421 { 2422 struct mt7996_phy *phy; 2423 struct mt76_phy *mphy; 2424 2425 mphy = (struct mt76_phy *)container_of(work, struct mt76_phy, 2426 mac_work.work); 2427 phy = mphy->priv; 2428 2429 mutex_lock(&mphy->dev->mutex); 2430 2431 mt76_update_survey(mphy); 2432 if (++mphy->mac_work_count == 5) { 2433 mphy->mac_work_count = 0; 2434 2435 mt7996_mac_update_stats(phy); 2436 2437 mt7996_mcu_get_all_sta_info(phy, UNI_ALL_STA_TXRX_RATE); 2438 if (mtk_wed_device_active(&phy->dev->mt76.mmio.wed)) { 2439 mt7996_mcu_get_all_sta_info(phy, UNI_ALL_STA_TXRX_ADM_STAT); 2440 mt7996_mcu_get_all_sta_info(phy, UNI_ALL_STA_TXRX_MSDU_COUNT); 2441 } 2442 } 2443 2444 mutex_unlock(&mphy->dev->mutex); 2445 2446 mt76_tx_status_check(mphy->dev, false); 2447 2448 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, 2449 MT7996_WATCHDOG_TIME); 2450 } 2451 2452 static void mt7996_dfs_stop_radar_detector(struct mt7996_phy *phy) 2453 { 2454 struct mt7996_dev *dev = phy->dev; 2455 int rdd_idx = mt7996_get_rdd_idx(phy, false); 2456 2457 if (rdd_idx < 0) 2458 return; 2459 2460 mt7996_mcu_rdd_cmd(dev, RDD_STOP, rdd_idx, 0); 2461 } 2462 2463 static int mt7996_dfs_start_rdd(struct mt7996_dev *dev, int rdd_idx) 2464 { 2465 int err, region; 2466 2467 switch (dev->mt76.region) { 2468 case NL80211_DFS_ETSI: 2469 region = 0; 2470 break; 2471 case NL80211_DFS_JP: 2472 region = 2; 2473 break; 2474 case NL80211_DFS_FCC: 2475 default: 2476 region = 1; 2477 break; 2478 } 2479 2480 err = mt7996_mcu_rdd_cmd(dev, RDD_START, rdd_idx, region); 2481 if (err < 0) 2482 return err; 2483 2484 return mt7996_mcu_rdd_cmd(dev, RDD_DET_MODE, rdd_idx, 1); 2485 } 2486 2487 static int mt7996_dfs_start_radar_detector(struct mt7996_phy *phy) 2488 { 2489 struct mt7996_dev *dev = phy->dev; 2490 int err, rdd_idx; 2491 2492 rdd_idx = mt7996_get_rdd_idx(phy, false); 2493 if (rdd_idx < 0) 2494 return -EINVAL; 2495 2496 /* start CAC */ 2497 err = mt7996_mcu_rdd_cmd(dev, RDD_CAC_START, rdd_idx, 0); 2498 if (err < 0) 2499 return err; 2500 2501 err = mt7996_dfs_start_rdd(dev, rdd_idx); 2502 2503 return err; 2504 } 2505 2506 static int 2507 mt7996_dfs_init_radar_specs(struct mt7996_phy *phy) 2508 { 2509 const struct mt7996_dfs_radar_spec *radar_specs; 2510 struct mt7996_dev *dev = phy->dev; 2511 int err, i; 2512 2513 switch (dev->mt76.region) { 2514 case NL80211_DFS_FCC: 2515 radar_specs = &fcc_radar_specs; 2516 err = mt7996_mcu_set_fcc5_lpn(dev, 8); 2517 if (err < 0) 2518 return err; 2519 break; 2520 case NL80211_DFS_ETSI: 2521 radar_specs = &etsi_radar_specs; 2522 break; 2523 case NL80211_DFS_JP: 2524 radar_specs = &jp_radar_specs; 2525 break; 2526 default: 2527 return -EINVAL; 2528 } 2529 2530 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) { 2531 err = mt7996_mcu_set_radar_th(dev, i, 2532 &radar_specs->radar_pattern[i]); 2533 if (err < 0) 2534 return err; 2535 } 2536 2537 return mt7996_mcu_set_pulse_th(dev, &radar_specs->pulse_th); 2538 } 2539 2540 int mt7996_dfs_init_radar_detector(struct mt7996_phy *phy) 2541 { 2542 struct mt7996_dev *dev = phy->dev; 2543 enum mt76_dfs_state dfs_state, prev_state; 2544 int err, rdd_idx = mt7996_get_rdd_idx(phy, false); 2545 2546 prev_state = phy->mt76->dfs_state; 2547 dfs_state = mt76_phy_dfs_state(phy->mt76); 2548 2549 if (prev_state == dfs_state || rdd_idx < 0) 2550 return 0; 2551 2552 if (prev_state == MT_DFS_STATE_UNKNOWN) 2553 mt7996_dfs_stop_radar_detector(phy); 2554 2555 if (dfs_state == MT_DFS_STATE_DISABLED) 2556 goto stop; 2557 2558 if (prev_state <= MT_DFS_STATE_DISABLED) { 2559 err = mt7996_dfs_init_radar_specs(phy); 2560 if (err < 0) 2561 return err; 2562 2563 err = mt7996_dfs_start_radar_detector(phy); 2564 if (err < 0) 2565 return err; 2566 2567 phy->mt76->dfs_state = MT_DFS_STATE_CAC; 2568 } 2569 2570 if (dfs_state == MT_DFS_STATE_CAC) 2571 return 0; 2572 2573 err = mt7996_mcu_rdd_cmd(dev, RDD_CAC_END, rdd_idx, 0); 2574 if (err < 0) { 2575 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN; 2576 return err; 2577 } 2578 2579 phy->mt76->dfs_state = MT_DFS_STATE_ACTIVE; 2580 return 0; 2581 2582 stop: 2583 err = mt7996_mcu_rdd_cmd(dev, RDD_NORMAL_START, rdd_idx, 0); 2584 if (err < 0) 2585 return err; 2586 2587 mt7996_dfs_stop_radar_detector(phy); 2588 phy->mt76->dfs_state = MT_DFS_STATE_DISABLED; 2589 2590 return 0; 2591 } 2592 2593 static int 2594 mt7996_mac_twt_duration_align(int duration) 2595 { 2596 return duration << 8; 2597 } 2598 2599 static u64 2600 mt7996_mac_twt_sched_list_add(struct mt7996_dev *dev, 2601 struct mt7996_twt_flow *flow) 2602 { 2603 struct mt7996_twt_flow *iter, *iter_next; 2604 u32 duration = flow->duration << 8; 2605 u64 start_tsf; 2606 2607 iter = list_first_entry_or_null(&dev->twt_list, 2608 struct mt7996_twt_flow, list); 2609 if (!iter || !iter->sched || iter->start_tsf > duration) { 2610 /* add flow as first entry in the list */ 2611 list_add(&flow->list, &dev->twt_list); 2612 return 0; 2613 } 2614 2615 list_for_each_entry_safe(iter, iter_next, &dev->twt_list, list) { 2616 start_tsf = iter->start_tsf + 2617 mt7996_mac_twt_duration_align(iter->duration); 2618 if (list_is_last(&iter->list, &dev->twt_list)) 2619 break; 2620 2621 if (!iter_next->sched || 2622 iter_next->start_tsf > start_tsf + duration) { 2623 list_add(&flow->list, &iter->list); 2624 goto out; 2625 } 2626 } 2627 2628 /* add flow as last entry in the list */ 2629 list_add_tail(&flow->list, &dev->twt_list); 2630 out: 2631 return start_tsf; 2632 } 2633 2634 static int mt7996_mac_check_twt_req(struct ieee80211_twt_setup *twt) 2635 { 2636 struct ieee80211_twt_params *twt_agrt; 2637 u64 interval, duration; 2638 u16 mantissa; 2639 u8 exp; 2640 2641 /* only individual agreement supported */ 2642 if (twt->control & IEEE80211_TWT_CONTROL_NEG_TYPE_BROADCAST) 2643 return -EOPNOTSUPP; 2644 2645 /* only 256us unit supported */ 2646 if (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT) 2647 return -EOPNOTSUPP; 2648 2649 twt_agrt = (struct ieee80211_twt_params *)twt->params; 2650 2651 /* explicit agreement not supported */ 2652 if (!(twt_agrt->req_type & cpu_to_le16(IEEE80211_TWT_REQTYPE_IMPLICIT))) 2653 return -EOPNOTSUPP; 2654 2655 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, 2656 le16_to_cpu(twt_agrt->req_type)); 2657 mantissa = le16_to_cpu(twt_agrt->mantissa); 2658 duration = twt_agrt->min_twt_dur << 8; 2659 2660 interval = (u64)mantissa << exp; 2661 if (interval < duration) 2662 return -EOPNOTSUPP; 2663 2664 return 0; 2665 } 2666 2667 static bool 2668 mt7996_mac_twt_param_equal(struct mt7996_sta_link *msta_link, 2669 struct ieee80211_twt_params *twt_agrt) 2670 { 2671 u16 type = le16_to_cpu(twt_agrt->req_type); 2672 u8 exp; 2673 int i; 2674 2675 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, type); 2676 for (i = 0; i < MT7996_MAX_STA_TWT_AGRT; i++) { 2677 struct mt7996_twt_flow *f; 2678 2679 if (!(msta_link->twt.flowid_mask & BIT(i))) 2680 continue; 2681 2682 f = &msta_link->twt.flow[i]; 2683 if (f->duration == twt_agrt->min_twt_dur && 2684 f->mantissa == twt_agrt->mantissa && 2685 f->exp == exp && 2686 f->protection == !!(type & IEEE80211_TWT_REQTYPE_PROTECTION) && 2687 f->flowtype == !!(type & IEEE80211_TWT_REQTYPE_FLOWTYPE) && 2688 f->trigger == !!(type & IEEE80211_TWT_REQTYPE_TRIGGER)) 2689 return true; 2690 } 2691 2692 return false; 2693 } 2694 2695 void mt7996_mac_add_twt_setup(struct ieee80211_hw *hw, 2696 struct ieee80211_sta *sta, 2697 struct ieee80211_twt_setup *twt) 2698 { 2699 enum ieee80211_twt_setup_cmd setup_cmd = TWT_SETUP_CMD_REJECT; 2700 struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv; 2701 struct ieee80211_twt_params *twt_agrt = (void *)twt->params; 2702 struct mt7996_sta_link *msta_link = &msta->deflink; 2703 u16 req_type = le16_to_cpu(twt_agrt->req_type); 2704 enum ieee80211_twt_setup_cmd sta_setup_cmd; 2705 struct mt7996_dev *dev = mt7996_hw_dev(hw); 2706 struct mt7996_twt_flow *flow; 2707 u8 flowid, table_id, exp; 2708 2709 if (mt7996_mac_check_twt_req(twt)) 2710 goto out; 2711 2712 mutex_lock(&dev->mt76.mutex); 2713 2714 if (dev->twt.n_agrt == MT7996_MAX_TWT_AGRT) 2715 goto unlock; 2716 2717 if (hweight8(msta_link->twt.flowid_mask) == 2718 ARRAY_SIZE(msta_link->twt.flow)) 2719 goto unlock; 2720 2721 if (twt_agrt->min_twt_dur < MT7996_MIN_TWT_DUR) { 2722 setup_cmd = TWT_SETUP_CMD_DICTATE; 2723 twt_agrt->min_twt_dur = MT7996_MIN_TWT_DUR; 2724 goto unlock; 2725 } 2726 2727 if (mt7996_mac_twt_param_equal(msta_link, twt_agrt)) 2728 goto unlock; 2729 2730 flowid = ffs(~msta_link->twt.flowid_mask) - 1; 2731 twt_agrt->req_type &= ~cpu_to_le16(IEEE80211_TWT_REQTYPE_FLOWID); 2732 twt_agrt->req_type |= le16_encode_bits(flowid, 2733 IEEE80211_TWT_REQTYPE_FLOWID); 2734 2735 table_id = ffs(~dev->twt.table_mask) - 1; 2736 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, req_type); 2737 sta_setup_cmd = FIELD_GET(IEEE80211_TWT_REQTYPE_SETUP_CMD, req_type); 2738 2739 flow = &msta_link->twt.flow[flowid]; 2740 memset(flow, 0, sizeof(*flow)); 2741 INIT_LIST_HEAD(&flow->list); 2742 flow->wcid = msta_link->wcid.idx; 2743 flow->table_id = table_id; 2744 flow->id = flowid; 2745 flow->duration = twt_agrt->min_twt_dur; 2746 flow->mantissa = twt_agrt->mantissa; 2747 flow->exp = exp; 2748 flow->protection = !!(req_type & IEEE80211_TWT_REQTYPE_PROTECTION); 2749 flow->flowtype = !!(req_type & IEEE80211_TWT_REQTYPE_FLOWTYPE); 2750 flow->trigger = !!(req_type & IEEE80211_TWT_REQTYPE_TRIGGER); 2751 2752 if (sta_setup_cmd == TWT_SETUP_CMD_REQUEST || 2753 sta_setup_cmd == TWT_SETUP_CMD_SUGGEST) { 2754 u64 interval = (u64)le16_to_cpu(twt_agrt->mantissa) << exp; 2755 u64 flow_tsf, curr_tsf; 2756 u32 rem; 2757 2758 flow->sched = true; 2759 flow->start_tsf = mt7996_mac_twt_sched_list_add(dev, flow); 2760 curr_tsf = __mt7996_get_tsf(hw, &msta->vif->deflink); 2761 div_u64_rem(curr_tsf - flow->start_tsf, interval, &rem); 2762 flow_tsf = curr_tsf + interval - rem; 2763 twt_agrt->twt = cpu_to_le64(flow_tsf); 2764 } else { 2765 list_add_tail(&flow->list, &dev->twt_list); 2766 } 2767 flow->tsf = le64_to_cpu(twt_agrt->twt); 2768 2769 if (mt7996_mcu_twt_agrt_update(dev, &msta->vif->deflink, flow, 2770 MCU_TWT_AGRT_ADD)) 2771 goto unlock; 2772 2773 setup_cmd = TWT_SETUP_CMD_ACCEPT; 2774 dev->twt.table_mask |= BIT(table_id); 2775 msta_link->twt.flowid_mask |= BIT(flowid); 2776 dev->twt.n_agrt++; 2777 2778 unlock: 2779 mutex_unlock(&dev->mt76.mutex); 2780 out: 2781 twt_agrt->req_type &= ~cpu_to_le16(IEEE80211_TWT_REQTYPE_SETUP_CMD); 2782 twt_agrt->req_type |= 2783 le16_encode_bits(setup_cmd, IEEE80211_TWT_REQTYPE_SETUP_CMD); 2784 twt->control = twt->control & IEEE80211_TWT_CONTROL_RX_DISABLED; 2785 } 2786 2787 void mt7996_mac_twt_teardown_flow(struct mt7996_dev *dev, 2788 struct mt7996_vif_link *link, 2789 struct mt7996_sta_link *msta_link, 2790 u8 flowid) 2791 { 2792 struct mt7996_twt_flow *flow; 2793 2794 lockdep_assert_held(&dev->mt76.mutex); 2795 2796 if (flowid >= ARRAY_SIZE(msta_link->twt.flow)) 2797 return; 2798 2799 if (!(msta_link->twt.flowid_mask & BIT(flowid))) 2800 return; 2801 2802 flow = &msta_link->twt.flow[flowid]; 2803 if (mt7996_mcu_twt_agrt_update(dev, link, flow, MCU_TWT_AGRT_DELETE)) 2804 return; 2805 2806 list_del_init(&flow->list); 2807 msta_link->twt.flowid_mask &= ~BIT(flowid); 2808 dev->twt.table_mask &= ~BIT(flow->table_id); 2809 dev->twt.n_agrt--; 2810 } 2811