1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #include <linux/etherdevice.h> 7 #include <linux/of.h> 8 #include <linux/hwmon.h> 9 #include <linux/hwmon-sysfs.h> 10 #include <linux/thermal.h> 11 #include "mt7996.h" 12 #include "mac.h" 13 #include "mcu.h" 14 #include "coredump.h" 15 #include "eeprom.h" 16 17 static const struct ieee80211_iface_limit if_limits_global = { 18 .max = MT7996_MAX_INTERFACES * MT7996_MAX_RADIOS, 19 .types = BIT(NL80211_IFTYPE_STATION) 20 | BIT(NL80211_IFTYPE_ADHOC) 21 | BIT(NL80211_IFTYPE_AP) 22 #ifdef CONFIG_MAC80211_MESH 23 | BIT(NL80211_IFTYPE_MESH_POINT) 24 #endif 25 }; 26 27 static const struct ieee80211_iface_combination if_comb_global = { 28 .limits = &if_limits_global, 29 .n_limits = 1, 30 .max_interfaces = MT7996_MAX_INTERFACES * MT7996_MAX_RADIOS, 31 .num_different_channels = MT7996_MAX_RADIOS, 32 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 33 BIT(NL80211_CHAN_WIDTH_20) | 34 BIT(NL80211_CHAN_WIDTH_40) | 35 BIT(NL80211_CHAN_WIDTH_80) | 36 BIT(NL80211_CHAN_WIDTH_160), 37 }; 38 39 static const struct ieee80211_iface_limit if_limits[] = { 40 { 41 .max = 16, 42 .types = BIT(NL80211_IFTYPE_AP) 43 #ifdef CONFIG_MAC80211_MESH 44 | BIT(NL80211_IFTYPE_MESH_POINT) 45 #endif 46 }, { 47 .max = MT7996_MAX_INTERFACES, 48 .types = BIT(NL80211_IFTYPE_STATION) 49 } 50 }; 51 52 static const struct ieee80211_iface_combination if_comb = { 53 .limits = if_limits, 54 .n_limits = ARRAY_SIZE(if_limits), 55 .max_interfaces = MT7996_MAX_INTERFACES, 56 .num_different_channels = 1, 57 .beacon_int_infra_match = true, 58 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 59 BIT(NL80211_CHAN_WIDTH_20) | 60 BIT(NL80211_CHAN_WIDTH_40) | 61 BIT(NL80211_CHAN_WIDTH_80) | 62 BIT(NL80211_CHAN_WIDTH_160), 63 .beacon_int_min_gcd = 100, 64 }; 65 66 static const u8 if_types_ext_capa_ap[] = { 67 [0] = WLAN_EXT_CAPA1_EXT_CHANNEL_SWITCHING, 68 [2] = WLAN_EXT_CAPA3_MULTI_BSSID_SUPPORT, 69 [7] = WLAN_EXT_CAPA8_OPMODE_NOTIF, 70 }; 71 72 static const struct wiphy_iftype_ext_capab iftypes_ext_capa[] = { 73 { 74 .iftype = NL80211_IFTYPE_AP, 75 .extended_capabilities = if_types_ext_capa_ap, 76 .extended_capabilities_mask = if_types_ext_capa_ap, 77 .extended_capabilities_len = sizeof(if_types_ext_capa_ap), 78 .eml_capabilities = IEEE80211_EML_CAP_EMLSR_SUPP, 79 .mld_capa_and_ops = 80 FIELD_PREP_CONST(IEEE80211_MLD_CAP_OP_MAX_SIMUL_LINKS, 81 MT7996_MAX_RADIOS - 1), 82 }, { 83 .iftype = NL80211_IFTYPE_STATION, 84 .extended_capabilities = if_types_ext_capa_ap, 85 .extended_capabilities_mask = if_types_ext_capa_ap, 86 .extended_capabilities_len = sizeof(if_types_ext_capa_ap), 87 .mld_capa_and_ops = 88 FIELD_PREP_CONST(IEEE80211_MLD_CAP_OP_MAX_SIMUL_LINKS, 89 MT7996_MAX_RADIOS - 1), 90 }, 91 }; 92 93 static ssize_t mt7996_thermal_temp_show(struct device *dev, 94 struct device_attribute *attr, 95 char *buf) 96 { 97 struct mt7996_phy *phy = dev_get_drvdata(dev); 98 int i = to_sensor_dev_attr(attr)->index; 99 int temperature; 100 101 switch (i) { 102 case 0: 103 temperature = mt7996_mcu_get_temperature(phy); 104 if (temperature < 0) 105 return temperature; 106 /* display in millidegree celcius */ 107 return sprintf(buf, "%u\n", temperature * 1000); 108 case 1: 109 case 2: 110 return sprintf(buf, "%u\n", 111 phy->throttle_temp[i - 1] * 1000); 112 case 3: 113 return sprintf(buf, "%hhu\n", phy->throttle_state); 114 default: 115 return -EINVAL; 116 } 117 } 118 119 static ssize_t mt7996_thermal_temp_store(struct device *dev, 120 struct device_attribute *attr, 121 const char *buf, size_t count) 122 { 123 struct mt7996_phy *phy = dev_get_drvdata(dev); 124 int ret, i = to_sensor_dev_attr(attr)->index; 125 long val; 126 127 ret = kstrtol(buf, 10, &val); 128 if (ret < 0) 129 return ret; 130 131 mutex_lock(&phy->dev->mt76.mutex); 132 val = DIV_ROUND_CLOSEST(clamp_val(val, 40 * 1000, 130 * 1000), 1000); 133 134 /* add a safety margin ~10 */ 135 if ((i - 1 == MT7996_CRIT_TEMP_IDX && 136 val > phy->throttle_temp[MT7996_MAX_TEMP_IDX] - 10) || 137 (i - 1 == MT7996_MAX_TEMP_IDX && 138 val - 10 < phy->throttle_temp[MT7996_CRIT_TEMP_IDX])) { 139 dev_err(phy->dev->mt76.dev, 140 "temp1_max shall be 10 degrees higher than temp1_crit."); 141 mutex_unlock(&phy->dev->mt76.mutex); 142 return -EINVAL; 143 } 144 145 phy->throttle_temp[i - 1] = val; 146 mutex_unlock(&phy->dev->mt76.mutex); 147 148 ret = mt7996_mcu_set_thermal_protect(phy, true); 149 if (ret) 150 return ret; 151 152 return count; 153 } 154 155 static SENSOR_DEVICE_ATTR_RO(temp1_input, mt7996_thermal_temp, 0); 156 static SENSOR_DEVICE_ATTR_RW(temp1_crit, mt7996_thermal_temp, 1); 157 static SENSOR_DEVICE_ATTR_RW(temp1_max, mt7996_thermal_temp, 2); 158 static SENSOR_DEVICE_ATTR_RO(throttle1, mt7996_thermal_temp, 3); 159 160 static struct attribute *mt7996_hwmon_attrs[] = { 161 &sensor_dev_attr_temp1_input.dev_attr.attr, 162 &sensor_dev_attr_temp1_crit.dev_attr.attr, 163 &sensor_dev_attr_temp1_max.dev_attr.attr, 164 &sensor_dev_attr_throttle1.dev_attr.attr, 165 NULL, 166 }; 167 ATTRIBUTE_GROUPS(mt7996_hwmon); 168 169 static int 170 mt7996_thermal_get_max_throttle_state(struct thermal_cooling_device *cdev, 171 unsigned long *state) 172 { 173 *state = MT7996_CDEV_THROTTLE_MAX; 174 175 return 0; 176 } 177 178 static int 179 mt7996_thermal_get_cur_throttle_state(struct thermal_cooling_device *cdev, 180 unsigned long *state) 181 { 182 struct mt7996_phy *phy = cdev->devdata; 183 184 *state = phy->cdev_state; 185 186 return 0; 187 } 188 189 static int 190 mt7996_thermal_set_cur_throttle_state(struct thermal_cooling_device *cdev, 191 unsigned long state) 192 { 193 struct mt7996_phy *phy = cdev->devdata; 194 u8 throttling = MT7996_THERMAL_THROTTLE_MAX - state; 195 int ret; 196 197 if (state > MT7996_CDEV_THROTTLE_MAX) { 198 dev_err(phy->dev->mt76.dev, 199 "please specify a valid throttling state\n"); 200 return -EINVAL; 201 } 202 203 if (state == phy->cdev_state) 204 return 0; 205 206 /* cooling_device convention: 0 = no cooling, more = more cooling 207 * mcu convention: 1 = max cooling, more = less cooling 208 */ 209 ret = mt7996_mcu_set_thermal_throttling(phy, throttling); 210 if (ret) 211 return ret; 212 213 phy->cdev_state = state; 214 215 return 0; 216 } 217 218 static const struct thermal_cooling_device_ops mt7996_thermal_ops = { 219 .get_max_state = mt7996_thermal_get_max_throttle_state, 220 .get_cur_state = mt7996_thermal_get_cur_throttle_state, 221 .set_cur_state = mt7996_thermal_set_cur_throttle_state, 222 }; 223 224 static void mt7996_unregister_thermal(struct mt7996_phy *phy) 225 { 226 struct wiphy *wiphy = phy->mt76->hw->wiphy; 227 char name[sizeof("cooling_deviceXXX")]; 228 229 if (!phy->cdev) 230 return; 231 232 snprintf(name, sizeof(name), "cooling_device%d", phy->mt76->band_idx); 233 sysfs_remove_link(&wiphy->dev.kobj, name); 234 thermal_cooling_device_unregister(phy->cdev); 235 } 236 237 static int mt7996_thermal_init(struct mt7996_phy *phy) 238 { 239 struct wiphy *wiphy = phy->mt76->hw->wiphy; 240 char cname[sizeof("cooling_deviceXXX")]; 241 struct thermal_cooling_device *cdev; 242 struct device *hwmon; 243 const char *name; 244 245 name = devm_kasprintf(&wiphy->dev, GFP_KERNEL, "mt7996_%s.%d", 246 wiphy_name(wiphy), phy->mt76->band_idx); 247 if (!name) 248 return -ENOMEM; 249 250 snprintf(cname, sizeof(cname), "cooling_device%d", phy->mt76->band_idx); 251 252 cdev = thermal_cooling_device_register(name, phy, &mt7996_thermal_ops); 253 if (!IS_ERR(cdev)) { 254 if (sysfs_create_link(&wiphy->dev.kobj, &cdev->device.kobj, 255 cname) < 0) 256 thermal_cooling_device_unregister(cdev); 257 else 258 phy->cdev = cdev; 259 } 260 261 /* initialize critical/maximum high temperature */ 262 phy->throttle_temp[MT7996_CRIT_TEMP_IDX] = MT7996_CRIT_TEMP; 263 phy->throttle_temp[MT7996_MAX_TEMP_IDX] = MT7996_MAX_TEMP; 264 265 if (!IS_REACHABLE(CONFIG_HWMON)) 266 return 0; 267 268 hwmon = devm_hwmon_device_register_with_groups(&wiphy->dev, name, phy, 269 mt7996_hwmon_groups); 270 271 if (IS_ERR(hwmon)) 272 return PTR_ERR(hwmon); 273 274 return 0; 275 } 276 277 static void mt7996_led_set_config(struct led_classdev *led_cdev, 278 u8 delay_on, u8 delay_off) 279 { 280 struct mt7996_dev *dev; 281 struct mt76_phy *mphy; 282 u32 val; 283 284 mphy = container_of(led_cdev, struct mt76_phy, leds.cdev); 285 dev = container_of(mphy->dev, struct mt7996_dev, mt76); 286 287 /* select TX blink mode, 2: only data frames */ 288 mt76_rmw_field(dev, MT_TMAC_TCR0(mphy->band_idx), MT_TMAC_TCR0_TX_BLINK, 2); 289 290 /* enable LED */ 291 mt76_wr(dev, MT_LED_EN(mphy->band_idx), 1); 292 293 /* set LED Tx blink on/off time */ 294 val = FIELD_PREP(MT_LED_TX_BLINK_ON_MASK, delay_on) | 295 FIELD_PREP(MT_LED_TX_BLINK_OFF_MASK, delay_off); 296 mt76_wr(dev, MT_LED_TX_BLINK(mphy->band_idx), val); 297 298 /* turn LED off */ 299 if (delay_off == 0xff && delay_on == 0x0) { 300 val = MT_LED_CTRL_POLARITY | MT_LED_CTRL_KICK; 301 } else { 302 /* control LED */ 303 val = MT_LED_CTRL_BLINK_MODE | MT_LED_CTRL_KICK; 304 if (mphy->band_idx == MT_BAND1) 305 val |= MT_LED_CTRL_BLINK_BAND_SEL; 306 } 307 308 if (mphy->leds.al) 309 val |= MT_LED_CTRL_POLARITY; 310 311 mt76_wr(dev, MT_LED_CTRL(mphy->band_idx), val); 312 mt76_clear(dev, MT_LED_CTRL(mphy->band_idx), MT_LED_CTRL_KICK); 313 } 314 315 static int mt7996_led_set_blink(struct led_classdev *led_cdev, 316 unsigned long *delay_on, 317 unsigned long *delay_off) 318 { 319 u16 delta_on = 0, delta_off = 0; 320 321 #define HW_TICK 10 322 #define TO_HW_TICK(_t) (((_t) > HW_TICK) ? ((_t) / HW_TICK) : HW_TICK) 323 324 if (*delay_on) 325 delta_on = TO_HW_TICK(*delay_on); 326 if (*delay_off) 327 delta_off = TO_HW_TICK(*delay_off); 328 329 mt7996_led_set_config(led_cdev, delta_on, delta_off); 330 331 return 0; 332 } 333 334 static void mt7996_led_set_brightness(struct led_classdev *led_cdev, 335 enum led_brightness brightness) 336 { 337 if (!brightness) 338 mt7996_led_set_config(led_cdev, 0, 0xff); 339 else 340 mt7996_led_set_config(led_cdev, 0xff, 0); 341 } 342 343 static void __mt7996_init_txpower(struct mt7996_phy *phy, 344 struct ieee80211_supported_band *sband) 345 { 346 struct mt7996_dev *dev = phy->dev; 347 int i, n_chains = hweight16(phy->mt76->chainmask); 348 int path_delta = mt76_tx_power_path_delta(n_chains); 349 int pwr_delta = mt7996_eeprom_get_power_delta(dev, sband->band); 350 struct mt76_power_limits limits; 351 352 for (i = 0; i < sband->n_channels; i++) { 353 struct ieee80211_channel *chan = &sband->channels[i]; 354 int target_power = mt7996_eeprom_get_target_power(dev, chan); 355 356 target_power += pwr_delta; 357 target_power = mt76_get_rate_power_limits(phy->mt76, chan, 358 &limits, 359 target_power); 360 target_power += path_delta; 361 target_power = DIV_ROUND_UP(target_power, 2); 362 chan->max_power = min_t(int, chan->max_reg_power, 363 target_power); 364 chan->orig_mpwr = target_power; 365 } 366 } 367 368 void mt7996_init_txpower(struct mt7996_phy *phy) 369 { 370 if (!phy) 371 return; 372 373 if (phy->mt76->cap.has_2ghz) 374 __mt7996_init_txpower(phy, &phy->mt76->sband_2g.sband); 375 if (phy->mt76->cap.has_5ghz) 376 __mt7996_init_txpower(phy, &phy->mt76->sband_5g.sband); 377 if (phy->mt76->cap.has_6ghz) 378 __mt7996_init_txpower(phy, &phy->mt76->sband_6g.sband); 379 } 380 381 static void 382 mt7996_regd_notifier(struct wiphy *wiphy, 383 struct regulatory_request *request) 384 { 385 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 386 struct mt7996_dev *dev = mt7996_hw_dev(hw); 387 struct mt7996_phy *phy; 388 389 memcpy(dev->mt76.alpha2, request->alpha2, sizeof(dev->mt76.alpha2)); 390 dev->mt76.region = request->dfs_region; 391 392 mt7996_for_each_phy(dev, phy) { 393 if (dev->mt76.region == NL80211_DFS_UNSET) 394 mt7996_mcu_rdd_background_enable(phy, NULL); 395 396 mt7996_init_txpower(phy); 397 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN; 398 mt7996_dfs_init_radar_detector(phy); 399 } 400 } 401 402 static void 403 mt7996_init_wiphy_band(struct ieee80211_hw *hw, struct mt7996_phy *phy) 404 { 405 struct mt7996_dev *dev = phy->dev; 406 struct wiphy *wiphy = hw->wiphy; 407 int n_radios = hw->wiphy->n_radio; 408 struct wiphy_radio_freq_range *freq = &dev->radio_freqs[n_radios]; 409 struct wiphy_radio *radio = &dev->radios[n_radios]; 410 411 phy->slottime = 9; 412 phy->beacon_rate = -1; 413 phy->rxfilter = MT_WF_RFCR_DROP_OTHER_UC; 414 415 if (phy->mt76->cap.has_2ghz) { 416 phy->mt76->sband_2g.sband.ht_cap.cap |= 417 IEEE80211_HT_CAP_LDPC_CODING | 418 IEEE80211_HT_CAP_MAX_AMSDU; 419 phy->mt76->sband_2g.sband.ht_cap.ampdu_density = 420 IEEE80211_HT_MPDU_DENSITY_2; 421 freq->start_freq = 2400000; 422 freq->end_freq = 2500000; 423 } else if (phy->mt76->cap.has_5ghz) { 424 phy->mt76->sband_5g.sband.ht_cap.cap |= 425 IEEE80211_HT_CAP_LDPC_CODING | 426 IEEE80211_HT_CAP_MAX_AMSDU; 427 428 phy->mt76->sband_5g.sband.vht_cap.cap |= 429 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 430 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 431 IEEE80211_VHT_CAP_SHORT_GI_160 | 432 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ; 433 phy->mt76->sband_5g.sband.ht_cap.ampdu_density = 434 IEEE80211_HT_MPDU_DENSITY_1; 435 436 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 437 freq->start_freq = 5000000; 438 freq->end_freq = 5900000; 439 } else if (phy->mt76->cap.has_6ghz) { 440 freq->start_freq = 5900000; 441 freq->end_freq = 7200000; 442 } else { 443 return; 444 } 445 446 dev->radio_phy[n_radios] = phy; 447 radio->freq_range = freq; 448 radio->n_freq_range = 1; 449 radio->iface_combinations = &if_comb; 450 radio->n_iface_combinations = 1; 451 hw->wiphy->n_radio++; 452 453 wiphy->available_antennas_rx |= phy->mt76->chainmask; 454 wiphy->available_antennas_tx |= phy->mt76->chainmask; 455 456 mt76_set_stream_caps(phy->mt76, true); 457 mt7996_set_stream_vht_txbf_caps(phy); 458 mt7996_set_stream_he_eht_caps(phy); 459 mt7996_init_txpower(phy); 460 } 461 462 static void 463 mt7996_init_wiphy(struct ieee80211_hw *hw, struct mtk_wed_device *wed) 464 { 465 struct mt7996_dev *dev = mt7996_hw_dev(hw); 466 struct mt76_dev *mdev = &dev->mt76; 467 struct wiphy *wiphy = hw->wiphy; 468 u16 max_subframes = dev->has_eht ? IEEE80211_MAX_AMPDU_BUF_EHT : 469 IEEE80211_MAX_AMPDU_BUF_HE; 470 471 hw->queues = 4; 472 hw->max_rx_aggregation_subframes = max_subframes; 473 hw->max_tx_aggregation_subframes = max_subframes; 474 if (is_mt7990(mdev) && dev->has_eht) 475 hw->max_tx_aggregation_subframes = 512; 476 477 hw->netdev_features = NETIF_F_RXCSUM; 478 if (mtk_wed_device_active(wed) || mt76_npu_device_active(mdev)) 479 hw->netdev_features |= NETIF_F_HW_TC; 480 481 hw->radiotap_timestamp.units_pos = 482 IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US; 483 484 hw->sta_data_size = sizeof(struct mt7996_sta); 485 hw->vif_data_size = sizeof(struct mt7996_vif); 486 hw->chanctx_data_size = sizeof(struct mt76_chanctx); 487 488 wiphy->iface_combinations = &if_comb_global; 489 wiphy->n_iface_combinations = 1; 490 491 wiphy->radio = dev->radios; 492 493 wiphy->reg_notifier = mt7996_regd_notifier; 494 wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH | 495 WIPHY_FLAG_SUPPORTS_MLO; 496 wiphy->mbssid_max_interfaces = 16; 497 wiphy->iftype_ext_capab = iftypes_ext_capa; 498 wiphy->num_iftype_ext_capab = ARRAY_SIZE(iftypes_ext_capa); 499 500 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR); 501 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS); 502 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_LEGACY); 503 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HT); 504 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_VHT); 505 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HE); 506 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP); 507 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_FILS_DISCOVERY); 508 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT); 509 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 510 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_MU_MIMO_AIR_SNIFFER); 511 512 if (mt7996_eeprom_has_background_radar(dev) && 513 (!mdev->dev->of_node || 514 !of_property_read_bool(mdev->dev->of_node, 515 "mediatek,disable-radar-background"))) 516 wiphy_ext_feature_set(wiphy, 517 NL80211_EXT_FEATURE_RADAR_BACKGROUND); 518 519 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 520 ieee80211_hw_set(hw, SUPPORTS_TX_ENCAP_OFFLOAD); 521 ieee80211_hw_set(hw, SUPPORTS_RX_DECAP_OFFLOAD); 522 ieee80211_hw_set(hw, NO_VIRTUAL_MONITOR); 523 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 524 525 hw->max_tx_fragments = 4; 526 527 /* init led callbacks */ 528 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 529 dev->mphy.leds.cdev.brightness_set = mt7996_led_set_brightness; 530 dev->mphy.leds.cdev.blink_set = mt7996_led_set_blink; 531 } 532 533 wiphy->max_scan_ssids = 4; 534 wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN; 535 536 mt7996_init_wiphy_band(hw, &dev->phy); 537 } 538 539 static void 540 mt7996_mac_init_band(struct mt7996_dev *dev, u8 band) 541 { 542 u32 mask, set; 543 544 /* clear estimated value of EIFS for Rx duration & OBSS time */ 545 mt76_wr(dev, MT_WF_RMAC_RSVD0(band), MT_WF_RMAC_RSVD0_EIFS_CLR); 546 547 /* clear backoff time for Rx duration */ 548 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME1(band), 549 MT_WF_RMAC_MIB_NONQOSD_BACKOFF); 550 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME3(band), 551 MT_WF_RMAC_MIB_QOS01_BACKOFF); 552 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME4(band), 553 MT_WF_RMAC_MIB_QOS23_BACKOFF); 554 555 /* clear backoff time for Tx duration */ 556 mt76_clear(dev, MT_WTBLOFF_ACR(band), 557 MT_WTBLOFF_ADM_BACKOFFTIME); 558 559 /* clear backoff time and set software compensation for OBSS time */ 560 mask = MT_WF_RMAC_MIB_OBSS_BACKOFF | MT_WF_RMAC_MIB_ED_OFFSET; 561 set = FIELD_PREP(MT_WF_RMAC_MIB_OBSS_BACKOFF, 0) | 562 FIELD_PREP(MT_WF_RMAC_MIB_ED_OFFSET, 4); 563 mt76_rmw(dev, MT_WF_RMAC_MIB_AIRTIME0(band), mask, set); 564 565 /* filter out non-resp frames and get instanstaeous signal reporting */ 566 mask = MT_WTBLOFF_RSCR_RCPI_MODE | MT_WTBLOFF_RSCR_RCPI_PARAM; 567 set = FIELD_PREP(MT_WTBLOFF_RSCR_RCPI_MODE, 0) | 568 FIELD_PREP(MT_WTBLOFF_RSCR_RCPI_PARAM, 0x3); 569 mt76_rmw(dev, MT_WTBLOFF_RSCR(band), mask, set); 570 571 /* MT_TXD5_TX_STATUS_HOST (MPDU format) has higher priority than 572 * MT_AGG_ACR_PPDU_TXS2H (PPDU format) even though ACR bit is set. 573 */ 574 mt76_set(dev, MT_AGG_ACR4(band), MT_AGG_ACR_PPDU_TXS2H); 575 } 576 577 static void mt7996_mac_init_basic_rates(struct mt7996_dev *dev) 578 { 579 int i; 580 581 for (i = 0; i < ARRAY_SIZE(mt76_rates); i++) { 582 u16 rate = mt76_rates[i].hw_value; 583 /* odd index for driver, even index for firmware */ 584 u16 idx = MT7996_BASIC_RATES_TBL + 2 * i; 585 586 rate = FIELD_PREP(MT_TX_RATE_MODE, rate >> 8) | 587 FIELD_PREP(MT_TX_RATE_IDX, rate & GENMASK(7, 0)); 588 mt7996_mcu_set_fixed_rate_table(&dev->phy, idx, rate, false); 589 } 590 } 591 592 void mt7996_mac_init(struct mt7996_dev *dev) 593 { 594 #define HIF_TXD_V2_1 0x21 595 int i; 596 597 mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT); 598 599 for (i = 0; i < mt7996_wtbl_size(dev); i++) 600 mt7996_mac_wtbl_update(dev, i, 601 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 602 603 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 604 i = dev->mphy.leds.pin ? MT_LED_GPIO_MUX3 : MT_LED_GPIO_MUX2; 605 mt76_rmw_field(dev, i, MT_LED_GPIO_SEL_MASK, 4); 606 } 607 608 /* rro module init */ 609 if (dev->hif2) 610 mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 611 is_mt7996(&dev->mt76) ? 2 : 7); 612 else 613 mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 0); 614 615 if (mt7996_has_hwrro(dev)) { 616 u16 timeout; 617 618 timeout = mt76_rr(dev, MT_HW_REV) == MT_HW_REV1 ? 512 : 128; 619 mt7996_mcu_set_rro(dev, UNI_RRO_SET_FLUSH_TIMEOUT, timeout); 620 mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 621 is_mt7996(&dev->mt76) ? 1 : 2); 622 mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 623 !is_mt7996(&dev->mt76)); 624 } else { 625 mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 3); 626 mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 1); 627 } 628 629 mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), 630 MCU_WA_PARAM_HW_PATH_HIF_VER, 631 HIF_TXD_V2_1, 0); 632 633 for (i = MT_BAND0; i <= MT_BAND2; i++) 634 mt7996_mac_init_band(dev, i); 635 636 mt7996_mac_init_basic_rates(dev); 637 } 638 639 int mt7996_txbf_init(struct mt7996_dev *dev) 640 { 641 int ret; 642 643 if (mt7996_band_valid(dev, MT_BAND1) || 644 mt7996_band_valid(dev, MT_BAND2)) { 645 ret = mt7996_mcu_set_txbf(dev, BF_MOD_EN_CTRL); 646 if (ret) 647 return ret; 648 } 649 650 /* trigger sounding packets */ 651 ret = mt7996_mcu_set_txbf(dev, BF_SOUNDING_ON); 652 if (ret) 653 return ret; 654 655 /* enable eBF */ 656 return mt7996_mcu_set_txbf(dev, BF_HW_EN_UPDATE); 657 } 658 659 static int mt7996_register_phy(struct mt7996_dev *dev, enum mt76_band_id band) 660 { 661 struct mt7996_phy *phy; 662 struct mt76_phy *mphy; 663 u32 mac_ofs, hif1_ofs = 0; 664 int ret; 665 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 666 667 if (!mt7996_band_valid(dev, band)) 668 return 0; 669 670 if (dev->hif2 && 671 ((is_mt7996(&dev->mt76) && band == MT_BAND2) || 672 (is_mt7992(&dev->mt76) && band == MT_BAND1))) { 673 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); 674 wed = &dev->mt76.mmio.wed_hif2; 675 } 676 677 mphy = mt76_alloc_radio_phy(&dev->mt76, sizeof(*phy), band); 678 if (!mphy) 679 return -ENOMEM; 680 681 phy = mphy->priv; 682 phy->dev = dev; 683 phy->mt76 = mphy; 684 mphy->dev->phys[band] = mphy; 685 686 INIT_DELAYED_WORK(&mphy->mac_work, mt7996_mac_work); 687 688 ret = mt7996_eeprom_parse_hw_cap(dev, phy); 689 if (ret) 690 goto error; 691 692 mac_ofs = band == MT_BAND2 ? MT_EE_MAC_ADDR3 : MT_EE_MAC_ADDR2; 693 memcpy(mphy->macaddr, dev->mt76.eeprom.data + mac_ofs, ETH_ALEN); 694 /* Make the extra PHY MAC address local without overlapping with 695 * the usual MAC address allocation scheme on multiple virtual interfaces 696 */ 697 if (!is_valid_ether_addr(mphy->macaddr)) { 698 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR, 699 ETH_ALEN); 700 mphy->macaddr[0] |= 2; 701 mphy->macaddr[0] ^= BIT(7); 702 if (band == MT_BAND2) 703 mphy->macaddr[0] ^= BIT(6); 704 } 705 ret = mt76_eeprom_override(mphy); 706 if (ret) 707 goto error; 708 709 /* init wiphy according to mphy and phy */ 710 mt7996_init_wiphy_band(mphy->hw, phy); 711 712 if (is_mt7996(&dev->mt76) && !dev->hif2 && band == MT_BAND1) { 713 int i; 714 715 for (i = 0; i <= MT_TXQ_PSD; i++) 716 mphy->q_tx[i] = dev->mt76.phys[MT_BAND0]->q_tx[0]; 717 } else { 718 ret = mt7996_init_tx_queues(mphy->priv, MT_TXQ_ID(band), 719 MT7996_TX_RING_SIZE, 720 MT_TXQ_RING_BASE(band) + hif1_ofs, 721 wed); 722 if (ret) 723 goto error; 724 } 725 726 ret = mt76_register_phy(mphy, true, mt76_rates, 727 ARRAY_SIZE(mt76_rates)); 728 if (ret) 729 goto error; 730 731 if (wed == &dev->mt76.mmio.wed_hif2 && mtk_wed_device_active(wed)) { 732 mt76_wr(dev, MT_INT_PCIE1_MASK_CSR, MT_INT_TX_RX_DONE_EXT); 733 mtk_wed_device_start(&dev->mt76.mmio.wed_hif2, 734 MT_INT_TX_RX_DONE_EXT); 735 } 736 737 return 0; 738 739 error: 740 mphy->dev->phys[band] = NULL; 741 return ret; 742 } 743 744 static void 745 mt7996_unregister_phy(struct mt7996_phy *phy) 746 { 747 if (phy) 748 mt7996_unregister_thermal(phy); 749 } 750 751 static void mt7996_init_work(struct work_struct *work) 752 { 753 struct mt7996_dev *dev = container_of(work, struct mt7996_dev, 754 init_work); 755 756 mt7996_mcu_set_eeprom(dev); 757 mt7996_mac_init(dev); 758 mt7996_txbf_init(dev); 759 } 760 761 void mt7996_wfsys_reset(struct mt7996_dev *dev) 762 { 763 mt76_set(dev, MT_WF_SUBSYS_RST, 0x1); 764 msleep(20); 765 766 mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1); 767 msleep(20); 768 } 769 770 static void mt7996_rro_hw_init_v3(struct mt7996_dev *dev) 771 { 772 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 773 u32 session_id; 774 775 if (dev->mt76.hwrro_mode == MT76_HWRRO_V3_1) 776 return; 777 778 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 779 if (mtk_wed_device_active(wed) && mtk_wed_get_rx_capa(wed)) { 780 wed->wlan.ind_cmd.win_size = 781 ffs(MT7996_RRO_WINDOW_MAX_LEN) - 6; 782 if (is_mt7996(&dev->mt76)) 783 wed->wlan.ind_cmd.particular_sid = 784 MT7996_RRO_MAX_SESSION; 785 else 786 wed->wlan.ind_cmd.particular_sid = 1; 787 wed->wlan.ind_cmd.particular_se_phys = 788 dev->wed_rro.session.phy_addr; 789 wed->wlan.ind_cmd.se_group_nums = MT7996_RRO_ADDR_ELEM_LEN; 790 wed->wlan.ind_cmd.ack_sn_addr = MT_RRO_ACK_SN_CTRL; 791 } 792 #endif /* CONFIG_NET_MEDIATEK_SOC_WED */ 793 794 if (mtk_wed_device_active(wed) && mtk_wed_get_rx_capa(wed)) { 795 mt76_wr(dev, MT_RRO_IND_CMD_SIGNATURE_BASE0, 0x15010e00); 796 mt76_set(dev, MT_RRO_IND_CMD_SIGNATURE_BASE1, 797 MT_RRO_IND_CMD_SIGNATURE_BASE1_EN); 798 } else { 799 mt76_wr(dev, MT_RRO_IND_CMD_SIGNATURE_BASE0, 0); 800 mt76_wr(dev, MT_RRO_IND_CMD_SIGNATURE_BASE1, 0); 801 } 802 803 /* particular session configure */ 804 /* use max session idx + 1 as particular session id */ 805 mt76_wr(dev, MT_RRO_PARTICULAR_CFG0, dev->wed_rro.session.phy_addr); 806 807 session_id = is_mt7996(&dev->mt76) ? MT7996_RRO_MAX_SESSION : 1; 808 mt76_wr(dev, MT_RRO_PARTICULAR_CFG1, 809 MT_RRO_PARTICULAR_CONFG_EN | 810 FIELD_PREP(MT_RRO_PARTICULAR_SID, session_id)); 811 } 812 813 void mt7996_rro_hw_init(struct mt7996_dev *dev) 814 { 815 u32 reg = MT_RRO_ADDR_ELEM_SEG_ADDR0; 816 int i; 817 818 if (!mt7996_has_hwrro(dev)) 819 return; 820 821 INIT_LIST_HEAD(&dev->wed_rro.page_cache); 822 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.page_map); i++) 823 INIT_LIST_HEAD(&dev->wed_rro.page_map[i]); 824 825 if (!is_mt7996(&dev->mt76)) { 826 reg = MT_RRO_MSDU_PG_SEG_ADDR0; 827 828 if (dev->mt76.hwrro_mode == MT76_HWRRO_V3_1) { 829 mt76_clear(dev, MT_RRO_3_0_EMU_CONF, 830 MT_RRO_3_0_EMU_CONF_EN_MASK); 831 mt76_set(dev, MT_RRO_3_1_GLOBAL_CONFIG, 832 MT_RRO_3_1_GLOBAL_CONFIG_RXDMAD_SEL); 833 if (!mtk_wed_device_active(&dev->mt76.mmio.wed) && 834 !mt76_npu_device_active(&dev->mt76)) { 835 mt76_set(dev, MT_RRO_3_1_GLOBAL_CONFIG, 836 MT_RRO_3_1_GLOBAL_CONFIG_RX_DIDX_WR_EN | 837 MT_RRO_3_1_GLOBAL_CONFIG_RX_CIDX_RD_EN); 838 mt76_wr(dev, MT_RRO_RX_RING_AP_CIDX_ADDR, 839 dev->wed_rro.emi_rings_cpu.phy_addr >> 4); 840 mt76_wr(dev, MT_RRO_RX_RING_AP_DIDX_ADDR, 841 dev->wed_rro.emi_rings_dma.phy_addr >> 4); 842 } 843 } else { 844 /* set emul 3.0 function */ 845 mt76_wr(dev, MT_RRO_3_0_EMU_CONF, 846 MT_RRO_3_0_EMU_CONF_EN_MASK); 847 848 mt76_wr(dev, MT_RRO_ADDR_ARRAY_BASE0, 849 dev->wed_rro.addr_elem[0].phy_addr); 850 } 851 852 mt76_set(dev, MT_RRO_3_1_GLOBAL_CONFIG, 853 MT_RRO_3_1_GLOBAL_CONFIG_INTERLEAVE_EN); 854 855 /* setup Msdu page address */ 856 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.msdu_pg); i++) { 857 mt76_wr(dev, reg, 858 dev->wed_rro.msdu_pg[i].phy_addr >> 4); 859 reg += 4; 860 } 861 } else { 862 /* TODO: remove line after WM has set */ 863 mt76_clear(dev, WF_RRO_AXI_MST_CFG, 864 WF_RRO_AXI_MST_CFG_DIDX_OK); 865 866 /* setup BA bitmap cache address */ 867 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE0, 868 dev->wed_rro.ba_bitmap[0].phy_addr); 869 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE1, 0); 870 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE_EXT0, 871 dev->wed_rro.ba_bitmap[1].phy_addr); 872 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE_EXT1, 0); 873 874 /* Setup Address element address */ 875 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) { 876 mt76_wr(dev, reg, 877 dev->wed_rro.addr_elem[i].phy_addr >> 4); 878 reg += 4; 879 } 880 881 /* Setup Address element address - separate address segment 882 * mode. 883 */ 884 mt76_wr(dev, MT_RRO_ADDR_ARRAY_BASE1, 885 MT_RRO_ADDR_ARRAY_ELEM_ADDR_SEG_MODE); 886 } 887 888 mt7996_rro_hw_init_v3(dev); 889 890 /* interrupt enable */ 891 mt76_wr(dev, MT_RRO_HOST_INT_ENA, 892 MT_RRO_HOST_INT_ENA_HOST_RRO_DONE_ENA); 893 } 894 895 static int mt7996_wed_rro_init(struct mt7996_dev *dev) 896 { 897 u32 val = FIELD_PREP(WED_RRO_ADDR_SIGNATURE_MASK, 0xff); 898 struct mt7996_wed_rro_addr *addr; 899 void *ptr; 900 int i; 901 902 if (!mt7996_has_hwrro(dev)) 903 return 0; 904 905 if (dev->mt76.hwrro_mode == MT76_HWRRO_V3) { 906 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.ba_bitmap); i++) { 907 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 908 MT7996_RRO_BA_BITMAP_CR_SIZE, 909 &dev->wed_rro.ba_bitmap[i].phy_addr, 910 GFP_KERNEL); 911 if (!ptr) 912 return -ENOMEM; 913 914 dev->wed_rro.ba_bitmap[i].ptr = ptr; 915 } 916 } 917 918 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) { 919 int j; 920 921 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 922 MT7996_RRO_WINDOW_MAX_SIZE * sizeof(*addr), 923 &dev->wed_rro.addr_elem[i].phy_addr, 924 GFP_KERNEL); 925 if (!ptr) 926 return -ENOMEM; 927 928 dev->wed_rro.addr_elem[i].ptr = ptr; 929 memset(dev->wed_rro.addr_elem[i].ptr, 0, 930 MT7996_RRO_WINDOW_MAX_SIZE * sizeof(*addr)); 931 932 addr = dev->wed_rro.addr_elem[i].ptr; 933 for (j = 0; j < MT7996_RRO_WINDOW_MAX_SIZE; j++) { 934 addr->data = cpu_to_le32(val); 935 addr++; 936 } 937 938 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 939 if (mtk_wed_device_active(&dev->mt76.mmio.wed) && 940 mtk_wed_get_rx_capa(&dev->mt76.mmio.wed)) { 941 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 942 943 wed->wlan.ind_cmd.addr_elem_phys[i] = 944 dev->wed_rro.addr_elem[i].phy_addr; 945 } 946 #endif /* CONFIG_NET_MEDIATEK_SOC_WED */ 947 } 948 949 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.msdu_pg); i++) { 950 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 951 MT7996_RRO_MSDU_PG_SIZE_PER_CR, 952 &dev->wed_rro.msdu_pg[i].phy_addr, 953 GFP_KERNEL); 954 if (!ptr) 955 return -ENOMEM; 956 957 dev->wed_rro.msdu_pg[i].ptr = ptr; 958 959 memset(dev->wed_rro.msdu_pg[i].ptr, 0, 960 MT7996_RRO_MSDU_PG_SIZE_PER_CR); 961 } 962 963 if (!mtk_wed_device_active(&dev->mt76.mmio.wed) && 964 dev->mt76.hwrro_mode == MT76_HWRRO_V3_1) { 965 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 966 sizeof(*dev->wed_rro.emi_rings_cpu.ptr), 967 &dev->wed_rro.emi_rings_cpu.phy_addr, 968 GFP_KERNEL); 969 if (!ptr) 970 return -ENOMEM; 971 972 dev->wed_rro.emi_rings_cpu.ptr = ptr; 973 974 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 975 sizeof(*dev->wed_rro.emi_rings_dma.ptr), 976 &dev->wed_rro.emi_rings_dma.phy_addr, 977 GFP_KERNEL); 978 if (!ptr) 979 return -ENOMEM; 980 981 dev->wed_rro.emi_rings_dma.ptr = ptr; 982 } 983 984 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 985 MT7996_RRO_WINDOW_MAX_LEN * sizeof(*addr), 986 &dev->wed_rro.session.phy_addr, 987 GFP_KERNEL); 988 if (!ptr) 989 return -ENOMEM; 990 991 dev->wed_rro.session.ptr = ptr; 992 addr = dev->wed_rro.session.ptr; 993 for (i = 0; i < MT7996_RRO_WINDOW_MAX_LEN; i++) { 994 addr->data = cpu_to_le32(val); 995 addr++; 996 } 997 998 mt7996_rro_hw_init(dev); 999 1000 return mt7996_dma_rro_init(dev); 1001 } 1002 1003 static void mt7996_wed_rro_free(struct mt7996_dev *dev) 1004 { 1005 int i; 1006 1007 if (!mt7996_has_hwrro(dev)) 1008 return; 1009 1010 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.ba_bitmap); i++) { 1011 if (!dev->wed_rro.ba_bitmap[i].ptr) 1012 continue; 1013 1014 dmam_free_coherent(dev->mt76.dma_dev, 1015 MT7996_RRO_BA_BITMAP_CR_SIZE, 1016 dev->wed_rro.ba_bitmap[i].ptr, 1017 dev->wed_rro.ba_bitmap[i].phy_addr); 1018 } 1019 1020 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) { 1021 if (!dev->wed_rro.addr_elem[i].ptr) 1022 continue; 1023 1024 dmam_free_coherent(dev->mt76.dma_dev, 1025 MT7996_RRO_WINDOW_MAX_SIZE * 1026 sizeof(struct mt7996_wed_rro_addr), 1027 dev->wed_rro.addr_elem[i].ptr, 1028 dev->wed_rro.addr_elem[i].phy_addr); 1029 } 1030 1031 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.msdu_pg); i++) { 1032 if (!dev->wed_rro.msdu_pg[i].ptr) 1033 continue; 1034 1035 dmam_free_coherent(dev->mt76.dma_dev, 1036 MT7996_RRO_MSDU_PG_SIZE_PER_CR, 1037 dev->wed_rro.msdu_pg[i].ptr, 1038 dev->wed_rro.msdu_pg[i].phy_addr); 1039 } 1040 1041 if (dev->wed_rro.emi_rings_cpu.ptr) 1042 dmam_free_coherent(dev->mt76.dma_dev, 1043 sizeof(*dev->wed_rro.emi_rings_cpu.ptr), 1044 dev->wed_rro.emi_rings_cpu.ptr, 1045 dev->wed_rro.emi_rings_cpu.phy_addr); 1046 1047 if (dev->wed_rro.emi_rings_dma.ptr) 1048 dmam_free_coherent(dev->mt76.dma_dev, 1049 sizeof(*dev->wed_rro.emi_rings_dma.ptr), 1050 dev->wed_rro.emi_rings_dma.ptr, 1051 dev->wed_rro.emi_rings_dma.phy_addr); 1052 1053 if (!dev->wed_rro.session.ptr) 1054 return; 1055 1056 dmam_free_coherent(dev->mt76.dma_dev, 1057 MT7996_RRO_WINDOW_MAX_LEN * 1058 sizeof(struct mt7996_wed_rro_addr), 1059 dev->wed_rro.session.ptr, 1060 dev->wed_rro.session.phy_addr); 1061 } 1062 1063 static void mt7996_wed_rro_work(struct work_struct *work) 1064 { 1065 u32 val = FIELD_PREP(WED_RRO_ADDR_SIGNATURE_MASK, 0xff); 1066 struct mt7996_dev *dev; 1067 LIST_HEAD(list); 1068 1069 dev = (struct mt7996_dev *)container_of(work, struct mt7996_dev, 1070 wed_rro.work); 1071 1072 spin_lock_bh(&dev->wed_rro.lock); 1073 list_splice_init(&dev->wed_rro.poll_list, &list); 1074 spin_unlock_bh(&dev->wed_rro.lock); 1075 1076 while (!list_empty(&list)) { 1077 struct mt7996_wed_rro_session_id *e; 1078 int i; 1079 1080 e = list_first_entry(&list, struct mt7996_wed_rro_session_id, 1081 list); 1082 list_del_init(&e->list); 1083 1084 if (mt76_npu_device_active(&dev->mt76)) 1085 goto reset_session; 1086 1087 for (i = 0; i < MT7996_RRO_WINDOW_MAX_LEN; i++) { 1088 void *ptr = dev->wed_rro.session.ptr; 1089 struct mt7996_wed_rro_addr *elem; 1090 u32 idx, elem_id = i; 1091 1092 if (e->id == MT7996_RRO_MAX_SESSION) 1093 goto reset; 1094 1095 idx = e->id / MT7996_RRO_BA_BITMAP_SESSION_SIZE; 1096 if (idx >= ARRAY_SIZE(dev->wed_rro.addr_elem)) 1097 goto out; 1098 1099 ptr = dev->wed_rro.addr_elem[idx].ptr; 1100 elem_id += 1101 (e->id % MT7996_RRO_BA_BITMAP_SESSION_SIZE) * 1102 MT7996_RRO_WINDOW_MAX_LEN; 1103 reset: 1104 elem = ptr + elem_id * sizeof(*elem); 1105 elem->data |= cpu_to_le32(val); 1106 } 1107 reset_session: 1108 mt7996_mcu_wed_rro_reset_sessions(dev, e->id); 1109 out: 1110 kfree(e); 1111 } 1112 } 1113 1114 static int mt7996_variant_type_init(struct mt7996_dev *dev) 1115 { 1116 u32 val = mt76_rr(dev, MT_PAD_GPIO); 1117 u8 var_type; 1118 1119 switch (mt76_chip(&dev->mt76)) { 1120 case MT7996_DEVICE_ID: 1121 if (val & MT_PAD_GPIO_2ADIE_TBTC) 1122 var_type = MT7996_VAR_TYPE_233; 1123 else 1124 var_type = MT7996_VAR_TYPE_444; 1125 break; 1126 case MT7992_DEVICE_ID: 1127 if (val & MT_PAD_GPIO_ADIE_SINGLE) 1128 var_type = MT7992_VAR_TYPE_23; 1129 else if (u32_get_bits(val, MT_PAD_GPIO_ADIE_COMB_7992)) 1130 var_type = MT7992_VAR_TYPE_44; 1131 else 1132 return -EINVAL; 1133 break; 1134 case MT7990_DEVICE_ID: 1135 var_type = MT7990_VAR_TYPE_23; 1136 break; 1137 default: 1138 return -EINVAL; 1139 } 1140 1141 dev->var.type = var_type; 1142 return 0; 1143 } 1144 1145 static int mt7996_variant_fem_init(struct mt7996_dev *dev) 1146 { 1147 #define MT7976C_EFUSE_OFFSET 0x470 1148 u8 buf[MT7996_EEPROM_BLOCK_SIZE], idx, adie_idx, adie_comb; 1149 u32 regval, val = mt76_rr(dev, MT_PAD_GPIO); 1150 u16 adie_id, adie_ver; 1151 bool is_7976c; 1152 int ret; 1153 1154 if (is_mt7992(&dev->mt76)) { 1155 adie_idx = (val & MT_PAD_GPIO_ADIE_SINGLE) ? 0 : 1; 1156 adie_comb = u32_get_bits(val, MT_PAD_GPIO_ADIE_COMB_7992); 1157 } else { 1158 adie_idx = 0; 1159 adie_comb = u32_get_bits(val, MT_PAD_GPIO_ADIE_COMB); 1160 } 1161 1162 ret = mt7996_mcu_rf_regval(dev, MT_ADIE_CHIP_ID(adie_idx), ®val, false); 1163 if (ret) 1164 return ret; 1165 1166 ret = mt7996_mcu_get_eeprom(dev, MT7976C_EFUSE_OFFSET, buf, sizeof(buf)); 1167 if (ret && ret != -EINVAL) 1168 return ret; 1169 1170 adie_ver = u32_get_bits(regval, MT_ADIE_VERSION_MASK); 1171 idx = MT7976C_EFUSE_OFFSET % MT7996_EEPROM_BLOCK_SIZE; 1172 is_7976c = adie_ver == 0x8a10 || adie_ver == 0x8b00 || 1173 adie_ver == 0x8c10 || buf[idx] == 0xc; 1174 1175 adie_id = u32_get_bits(regval, MT_ADIE_CHIP_ID_MASK); 1176 if (adie_id == 0x7975 || adie_id == 0x7979 || 1177 (adie_id == 0x7976 && is_7976c)) 1178 dev->var.fem = MT7996_FEM_INT; 1179 else if (adie_id == 0x7977 && adie_comb == 1) 1180 dev->var.fem = MT7996_FEM_MIX; 1181 else 1182 dev->var.fem = MT7996_FEM_EXT; 1183 1184 return 0; 1185 } 1186 1187 static int mt7996_init_hardware(struct mt7996_dev *dev) 1188 { 1189 int ret, idx; 1190 1191 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 1192 if (is_mt7992(&dev->mt76)) { 1193 mt76_rmw(dev, MT_AFE_CTL_BAND_PLL_03(MT_BAND0), MT_AFE_CTL_BAND_PLL_03_MSB_EN, 0); 1194 mt76_rmw(dev, MT_AFE_CTL_BAND_PLL_03(MT_BAND1), MT_AFE_CTL_BAND_PLL_03_MSB_EN, 0); 1195 } 1196 1197 INIT_WORK(&dev->init_work, mt7996_init_work); 1198 INIT_WORK(&dev->wed_rro.work, mt7996_wed_rro_work); 1199 INIT_LIST_HEAD(&dev->wed_rro.poll_list); 1200 spin_lock_init(&dev->wed_rro.lock); 1201 1202 ret = mt7996_variant_type_init(dev); 1203 if (ret) 1204 return ret; 1205 1206 ret = mt7996_dma_init(dev); 1207 if (ret) 1208 return ret; 1209 1210 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state); 1211 1212 ret = mt7996_mcu_init(dev); 1213 if (ret) 1214 return ret; 1215 1216 ret = mt7996_wed_rro_init(dev); 1217 if (ret) 1218 return ret; 1219 1220 ret = mt7996_variant_fem_init(dev); 1221 if (ret) 1222 return ret; 1223 1224 ret = mt7996_eeprom_init(dev); 1225 if (ret < 0) 1226 return ret; 1227 1228 /* Beacon and mgmt frames should occupy wcid 0 */ 1229 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7996_WTBL_STA); 1230 if (idx) 1231 return -ENOSPC; 1232 1233 dev->mt76.global_wcid.idx = idx; 1234 dev->mt76.global_wcid.hw_key_idx = -1; 1235 dev->mt76.global_wcid.tx_info |= MT_WCID_TX_INFO_SET; 1236 rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid); 1237 1238 return 0; 1239 } 1240 1241 void mt7996_set_stream_vht_txbf_caps(struct mt7996_phy *phy) 1242 { 1243 int sts; 1244 u32 *cap; 1245 1246 if (!phy->mt76->cap.has_5ghz) 1247 return; 1248 1249 sts = hweight16(phy->mt76->chainmask); 1250 cap = &phy->mt76->sband_5g.sband.vht_cap.cap; 1251 1252 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | 1253 IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE; 1254 1255 if (is_mt7992(phy->mt76->dev)) 1256 *cap |= FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, 4); 1257 else 1258 *cap |= FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, 3); 1259 1260 *cap &= ~(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK | 1261 IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 1262 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE); 1263 1264 if (sts < 2) 1265 return; 1266 1267 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 1268 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE | 1269 FIELD_PREP(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, sts - 1); 1270 } 1271 1272 static void 1273 mt7996_set_stream_he_txbf_caps(struct mt7996_phy *phy, 1274 struct ieee80211_sta_he_cap *he_cap, int vif, 1275 enum nl80211_band band) 1276 { 1277 struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem; 1278 int sts = hweight16(phy->mt76->chainmask); 1279 bool non_2g = band != NL80211_BAND_2GHZ; 1280 u8 c; 1281 1282 #ifdef CONFIG_MAC80211_MESH 1283 if (vif == NL80211_IFTYPE_MESH_POINT) 1284 return; 1285 #endif 1286 1287 elem->phy_cap_info[3] &= ~IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 1288 elem->phy_cap_info[4] &= ~IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 1289 1290 c = IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK | 1291 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK; 1292 elem->phy_cap_info[5] &= ~c; 1293 1294 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 1295 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 1296 elem->phy_cap_info[6] &= ~c; 1297 1298 elem->phy_cap_info[7] &= ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK; 1299 1300 c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 1301 IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO; 1302 elem->phy_cap_info[2] |= c; 1303 1304 c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE; 1305 1306 if (is_mt7992(phy->mt76->dev)) 1307 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_5 | 1308 (IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_5 * non_2g); 1309 else 1310 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4 | 1311 (IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4 * non_2g); 1312 1313 elem->phy_cap_info[4] |= c; 1314 1315 /* do not support NG16 due to spec D4.0 changes subcarrier idx */ 1316 c = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 1317 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU; 1318 1319 if (vif == NL80211_IFTYPE_STATION) 1320 c |= IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO; 1321 1322 elem->phy_cap_info[6] |= c; 1323 1324 if (sts < 2) 1325 return; 1326 1327 /* the maximum cap is 4 x 3, (Nr, Nc) = (3, 2) */ 1328 elem->phy_cap_info[7] |= min_t(int, sts - 1, 2) << 3; 1329 1330 if (!(vif == NL80211_IFTYPE_AP || vif == NL80211_IFTYPE_STATION)) 1331 return; 1332 1333 elem->phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 1334 1335 c = FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 1336 sts - 1) | 1337 (FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK, 1338 sts - 1) * non_2g); 1339 1340 elem->phy_cap_info[5] |= c; 1341 1342 if (vif != NL80211_IFTYPE_AP) 1343 return; 1344 1345 elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 1346 1347 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 1348 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 1349 elem->phy_cap_info[6] |= c; 1350 1351 c = 0; 1352 if (non_2g) 1353 c |= IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ | 1354 IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ; 1355 elem->phy_cap_info[7] |= c; 1356 } 1357 1358 static void 1359 mt7996_init_he_caps(struct mt7996_phy *phy, enum nl80211_band band, 1360 struct ieee80211_sband_iftype_data *data, 1361 enum nl80211_iftype iftype) 1362 { 1363 struct ieee80211_sta_he_cap *he_cap = &data->he_cap; 1364 struct ieee80211_he_cap_elem *he_cap_elem = &he_cap->he_cap_elem; 1365 struct ieee80211_he_mcs_nss_supp *he_mcs = &he_cap->he_mcs_nss_supp; 1366 int i, nss = hweight8(phy->mt76->antenna_mask); 1367 u16 mcs_map = 0; 1368 1369 for (i = 0; i < 8; i++) { 1370 if (i < nss) 1371 mcs_map |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 1372 else 1373 mcs_map |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 1374 } 1375 1376 he_cap->has_he = true; 1377 1378 he_cap_elem->mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE; 1379 he_cap_elem->mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 1380 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3; 1381 he_cap_elem->mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 1382 1383 if (band == NL80211_BAND_2GHZ) 1384 he_cap_elem->phy_cap_info[0] = 1385 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 1386 else 1387 he_cap_elem->phy_cap_info[0] = 1388 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 1389 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 1390 1391 he_cap_elem->phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD; 1392 he_cap_elem->phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 1393 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ; 1394 1395 he_cap_elem->phy_cap_info[7] = 1396 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI; 1397 1398 switch (iftype) { 1399 case NL80211_IFTYPE_AP: 1400 he_cap_elem->mac_cap_info[0] |= IEEE80211_HE_MAC_CAP0_TWT_RES; 1401 he_cap_elem->mac_cap_info[2] |= IEEE80211_HE_MAC_CAP2_BSR; 1402 he_cap_elem->mac_cap_info[4] |= IEEE80211_HE_MAC_CAP4_BQR; 1403 he_cap_elem->mac_cap_info[5] |= 1404 IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX; 1405 he_cap_elem->phy_cap_info[3] |= 1406 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1407 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1408 he_cap_elem->phy_cap_info[6] |= 1409 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1410 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1411 he_cap_elem->phy_cap_info[9] |= 1412 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1413 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU; 1414 break; 1415 case NL80211_IFTYPE_STATION: 1416 he_cap_elem->mac_cap_info[1] |= 1417 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 1418 1419 if (band == NL80211_BAND_2GHZ) 1420 he_cap_elem->phy_cap_info[0] |= 1421 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G; 1422 else 1423 he_cap_elem->phy_cap_info[0] |= 1424 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G; 1425 1426 he_cap_elem->phy_cap_info[1] |= 1427 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 1428 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 1429 he_cap_elem->phy_cap_info[3] |= 1430 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1431 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1432 he_cap_elem->phy_cap_info[6] |= 1433 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB | 1434 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1435 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1436 he_cap_elem->phy_cap_info[7] |= 1437 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP; 1438 he_cap_elem->phy_cap_info[8] |= 1439 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 1440 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 1441 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU | 1442 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_484; 1443 he_cap_elem->phy_cap_info[9] |= 1444 IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 1445 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK | 1446 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1447 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 1448 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 1449 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB; 1450 break; 1451 default: 1452 break; 1453 } 1454 1455 he_mcs->rx_mcs_80 = cpu_to_le16(mcs_map); 1456 he_mcs->tx_mcs_80 = cpu_to_le16(mcs_map); 1457 he_mcs->rx_mcs_160 = cpu_to_le16(mcs_map); 1458 he_mcs->tx_mcs_160 = cpu_to_le16(mcs_map); 1459 1460 mt7996_set_stream_he_txbf_caps(phy, he_cap, iftype, band); 1461 1462 memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres)); 1463 if (he_cap_elem->phy_cap_info[6] & 1464 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) { 1465 mt76_connac_gen_ppe_thresh(he_cap->ppe_thres, nss, band); 1466 } else { 1467 he_cap_elem->phy_cap_info[9] |= 1468 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 1469 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 1470 } 1471 1472 if (band == NL80211_BAND_6GHZ) { 1473 u16 cap = IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS | 1474 IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS; 1475 1476 cap |= u16_encode_bits(IEEE80211_HT_MPDU_DENSITY_0_5, 1477 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 1478 u16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 1479 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 1480 u16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 1481 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 1482 1483 data->he_6ghz_capa.capa = cpu_to_le16(cap); 1484 } 1485 } 1486 1487 static void 1488 mt7996_init_eht_caps(struct mt7996_phy *phy, enum nl80211_band band, 1489 struct ieee80211_sband_iftype_data *data, 1490 enum nl80211_iftype iftype) 1491 { 1492 struct ieee80211_sta_eht_cap *eht_cap = &data->eht_cap; 1493 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem = &eht_cap->eht_cap_elem; 1494 struct ieee80211_eht_mcs_nss_supp *eht_nss = &eht_cap->eht_mcs_nss_supp; 1495 enum nl80211_chan_width width = phy->mt76->chandef.width; 1496 int nss = hweight8(phy->mt76->antenna_mask); 1497 int sts = hweight16(phy->mt76->chainmask); 1498 u8 val; 1499 1500 if (!phy->dev->has_eht) 1501 return; 1502 1503 eht_cap->has_eht = true; 1504 1505 eht_cap_elem->mac_cap_info[0] = 1506 IEEE80211_EHT_MAC_CAP0_OM_CONTROL | 1507 u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_11454, 1508 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK); 1509 1510 eht_cap_elem->mac_cap_info[1] |= 1511 IEEE80211_EHT_MAC_CAP1_MAX_AMPDU_LEN_MASK; 1512 1513 eht_cap_elem->phy_cap_info[0] = 1514 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI | 1515 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMER | 1516 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE; 1517 1518 /* Set the maximum capability regardless of the antenna configuration. */ 1519 val = is_mt7992(phy->mt76->dev) ? 4 : 3; 1520 eht_cap_elem->phy_cap_info[0] |= 1521 u8_encode_bits(u8_get_bits(val, BIT(0)), 1522 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK); 1523 1524 eht_cap_elem->phy_cap_info[1] = 1525 u8_encode_bits(u8_get_bits(val, GENMASK(2, 1)), 1526 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK); 1527 1528 eht_cap_elem->phy_cap_info[2] = 1529 u8_encode_bits(sts - 1, IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_80MHZ_MASK); 1530 1531 if (band != NL80211_BAND_2GHZ) { 1532 eht_cap_elem->phy_cap_info[1] |= 1533 u8_encode_bits(val, 1534 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK); 1535 1536 eht_cap_elem->phy_cap_info[2] |= 1537 u8_encode_bits(sts - 1, 1538 IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_160MHZ_MASK); 1539 } 1540 1541 if (band == NL80211_BAND_6GHZ) { 1542 eht_cap_elem->phy_cap_info[0] |= 1543 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ; 1544 1545 eht_cap_elem->phy_cap_info[1] |= 1546 u8_encode_bits(val, 1547 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK); 1548 1549 eht_cap_elem->phy_cap_info[2] |= 1550 u8_encode_bits(sts - 1, 1551 IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_320MHZ_MASK); 1552 } 1553 1554 eht_cap_elem->phy_cap_info[3] = 1555 IEEE80211_EHT_PHY_CAP3_NG_16_SU_FEEDBACK | 1556 IEEE80211_EHT_PHY_CAP3_NG_16_MU_FEEDBACK | 1557 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK | 1558 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK; 1559 1560 eht_cap_elem->phy_cap_info[4] = 1561 IEEE80211_EHT_PHY_CAP4_EHT_MU_PPDU_4_EHT_LTF_08_GI | 1562 u8_encode_bits(min_t(int, sts - 1, 2), 1563 IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK); 1564 1565 eht_cap_elem->phy_cap_info[5] = 1566 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_16US, 1567 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK) | 1568 u8_encode_bits(u8_get_bits(1, GENMASK(1, 0)), 1569 IEEE80211_EHT_PHY_CAP5_MAX_NUM_SUPP_EHT_LTF_MASK); 1570 1571 val = width == NL80211_CHAN_WIDTH_320 ? 0xf : 1572 width == NL80211_CHAN_WIDTH_160 ? 0x7 : 1573 width == NL80211_CHAN_WIDTH_80 ? 0x3 : 0x1; 1574 eht_cap_elem->phy_cap_info[6] = 1575 u8_encode_bits(val, IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_MASK); 1576 1577 val = u8_encode_bits(nss, IEEE80211_EHT_MCS_NSS_RX) | 1578 u8_encode_bits(nss, IEEE80211_EHT_MCS_NSS_TX); 1579 #define SET_EHT_MAX_NSS(_bw, _val) do { \ 1580 eht_nss->bw._##_bw.rx_tx_mcs9_max_nss = _val; \ 1581 eht_nss->bw._##_bw.rx_tx_mcs11_max_nss = _val; \ 1582 eht_nss->bw._##_bw.rx_tx_mcs13_max_nss = _val; \ 1583 } while (0) 1584 1585 SET_EHT_MAX_NSS(80, val); 1586 SET_EHT_MAX_NSS(160, val); 1587 if (band == NL80211_BAND_6GHZ) 1588 SET_EHT_MAX_NSS(320, val); 1589 #undef SET_EHT_MAX_NSS 1590 1591 if (iftype != NL80211_IFTYPE_AP) 1592 return; 1593 1594 eht_cap_elem->phy_cap_info[3] |= 1595 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK | 1596 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK; 1597 1598 eht_cap_elem->phy_cap_info[7] = 1599 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_80MHZ | 1600 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_80MHZ; 1601 1602 if (band == NL80211_BAND_2GHZ) 1603 return; 1604 1605 eht_cap_elem->phy_cap_info[7] |= 1606 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_160MHZ | 1607 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_160MHZ; 1608 1609 if (band != NL80211_BAND_6GHZ) 1610 return; 1611 1612 eht_cap_elem->phy_cap_info[7] |= 1613 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_320MHZ | 1614 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_320MHZ; 1615 } 1616 1617 static void 1618 __mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy, 1619 struct ieee80211_supported_band *sband, 1620 enum nl80211_band band) 1621 { 1622 struct ieee80211_sband_iftype_data *data = phy->iftype[band]; 1623 int i, n = 0; 1624 1625 for (i = 0; i < NUM_NL80211_IFTYPES; i++) { 1626 switch (i) { 1627 case NL80211_IFTYPE_STATION: 1628 case NL80211_IFTYPE_AP: 1629 #ifdef CONFIG_MAC80211_MESH 1630 case NL80211_IFTYPE_MESH_POINT: 1631 #endif 1632 break; 1633 default: 1634 continue; 1635 } 1636 1637 data[n].types_mask = BIT(i); 1638 mt7996_init_he_caps(phy, band, &data[n], i); 1639 mt7996_init_eht_caps(phy, band, &data[n], i); 1640 1641 n++; 1642 } 1643 1644 _ieee80211_set_sband_iftype_data(sband, data, n); 1645 } 1646 1647 void mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy) 1648 { 1649 if (phy->mt76->cap.has_2ghz) 1650 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_2g.sband, 1651 NL80211_BAND_2GHZ); 1652 1653 if (phy->mt76->cap.has_5ghz) 1654 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_5g.sband, 1655 NL80211_BAND_5GHZ); 1656 1657 if (phy->mt76->cap.has_6ghz) 1658 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_6g.sband, 1659 NL80211_BAND_6GHZ); 1660 } 1661 1662 int mt7996_register_device(struct mt7996_dev *dev) 1663 { 1664 struct ieee80211_hw *hw = mt76_hw(dev); 1665 struct mt7996_phy *phy; 1666 int ret; 1667 1668 dev->phy.dev = dev; 1669 dev->phy.mt76 = &dev->mt76.phy; 1670 dev->mt76.phy.priv = &dev->phy; 1671 INIT_WORK(&dev->rc_work, mt7996_mac_sta_rc_work); 1672 INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7996_mac_work); 1673 INIT_LIST_HEAD(&dev->sta_rc_list); 1674 INIT_LIST_HEAD(&dev->twt_list); 1675 1676 init_waitqueue_head(&dev->reset_wait); 1677 INIT_WORK(&dev->reset_work, mt7996_mac_reset_work); 1678 INIT_WORK(&dev->dump_work, mt7996_mac_dump_work); 1679 mutex_init(&dev->dump_mutex); 1680 1681 ret = mt7996_init_hardware(dev); 1682 if (ret) 1683 return ret; 1684 1685 mt7996_init_wiphy(hw, &dev->mt76.mmio.wed); 1686 1687 ret = mt7996_register_phy(dev, MT_BAND1); 1688 if (ret) 1689 return ret; 1690 1691 ret = mt7996_register_phy(dev, MT_BAND2); 1692 if (ret) 1693 return ret; 1694 1695 ret = mt7996_npu_hw_init(dev); 1696 if (ret) 1697 return ret; 1698 1699 ret = mt76_register_device(&dev->mt76, true, mt76_rates, 1700 ARRAY_SIZE(mt76_rates)); 1701 if (ret) 1702 return ret; 1703 1704 mt7996_for_each_phy(dev, phy) 1705 mt7996_thermal_init(phy); 1706 1707 ieee80211_queue_work(mt76_hw(dev), &dev->init_work); 1708 1709 dev->recovery.hw_init_done = true; 1710 1711 ret = mt7996_init_debugfs(dev); 1712 if (ret) 1713 goto error; 1714 1715 ret = mt7996_coredump_register(dev); 1716 if (ret) 1717 goto error; 1718 1719 return 0; 1720 1721 error: 1722 cancel_work_sync(&dev->init_work); 1723 1724 return ret; 1725 } 1726 1727 void mt7996_unregister_device(struct mt7996_dev *dev) 1728 { 1729 cancel_work_sync(&dev->wed_rro.work); 1730 mt7996_unregister_phy(mt7996_phy3(dev)); 1731 mt7996_unregister_phy(mt7996_phy2(dev)); 1732 mt7996_unregister_thermal(&dev->phy); 1733 mt7996_coredump_unregister(dev); 1734 mt76_unregister_device(&dev->mt76); 1735 mt7996_wed_rro_free(dev); 1736 mt7996_mcu_exit(dev); 1737 mt7996_tx_token_put(dev); 1738 mt7996_dma_cleanup(dev); 1739 if (mt7996_has_hwrro(dev) && 1740 !mtk_wed_device_active(&dev->mt76.mmio.wed)) 1741 mt7996_rro_msdu_page_map_free(dev); 1742 tasklet_disable(&dev->mt76.irq_tasklet); 1743 1744 mt76_free_device(&dev->mt76); 1745 } 1746