1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #include <linux/etherdevice.h> 7 #include <linux/of.h> 8 #include <linux/hwmon.h> 9 #include <linux/hwmon-sysfs.h> 10 #include <linux/thermal.h> 11 #include "mt7996.h" 12 #include "mac.h" 13 #include "mcu.h" 14 #include "coredump.h" 15 #include "eeprom.h" 16 17 static const struct ieee80211_iface_limit if_limits[] = { 18 { 19 .max = 16, 20 .types = BIT(NL80211_IFTYPE_AP) 21 #ifdef CONFIG_MAC80211_MESH 22 | BIT(NL80211_IFTYPE_MESH_POINT) 23 #endif 24 }, { 25 .max = MT7996_MAX_INTERFACES, 26 .types = BIT(NL80211_IFTYPE_STATION) 27 } 28 }; 29 30 static const struct ieee80211_iface_combination if_comb[] = { 31 { 32 .limits = if_limits, 33 .n_limits = ARRAY_SIZE(if_limits), 34 .max_interfaces = MT7996_MAX_INTERFACES, 35 .num_different_channels = 1, 36 .beacon_int_infra_match = true, 37 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 38 BIT(NL80211_CHAN_WIDTH_20) | 39 BIT(NL80211_CHAN_WIDTH_40) | 40 BIT(NL80211_CHAN_WIDTH_80) | 41 BIT(NL80211_CHAN_WIDTH_160), 42 .beacon_int_min_gcd = 100, 43 } 44 }; 45 46 static ssize_t mt7996_thermal_temp_show(struct device *dev, 47 struct device_attribute *attr, 48 char *buf) 49 { 50 struct mt7996_phy *phy = dev_get_drvdata(dev); 51 int i = to_sensor_dev_attr(attr)->index; 52 int temperature; 53 54 switch (i) { 55 case 0: 56 temperature = mt7996_mcu_get_temperature(phy); 57 if (temperature < 0) 58 return temperature; 59 /* display in millidegree celcius */ 60 return sprintf(buf, "%u\n", temperature * 1000); 61 case 1: 62 case 2: 63 return sprintf(buf, "%u\n", 64 phy->throttle_temp[i - 1] * 1000); 65 case 3: 66 return sprintf(buf, "%hhu\n", phy->throttle_state); 67 default: 68 return -EINVAL; 69 } 70 } 71 72 static ssize_t mt7996_thermal_temp_store(struct device *dev, 73 struct device_attribute *attr, 74 const char *buf, size_t count) 75 { 76 struct mt7996_phy *phy = dev_get_drvdata(dev); 77 int ret, i = to_sensor_dev_attr(attr)->index; 78 long val; 79 80 ret = kstrtol(buf, 10, &val); 81 if (ret < 0) 82 return ret; 83 84 mutex_lock(&phy->dev->mt76.mutex); 85 val = DIV_ROUND_CLOSEST(clamp_val(val, 40 * 1000, 130 * 1000), 1000); 86 87 /* add a safety margin ~10 */ 88 if ((i - 1 == MT7996_CRIT_TEMP_IDX && 89 val > phy->throttle_temp[MT7996_MAX_TEMP_IDX] - 10) || 90 (i - 1 == MT7996_MAX_TEMP_IDX && 91 val - 10 < phy->throttle_temp[MT7996_CRIT_TEMP_IDX])) { 92 dev_err(phy->dev->mt76.dev, 93 "temp1_max shall be 10 degrees higher than temp1_crit."); 94 mutex_unlock(&phy->dev->mt76.mutex); 95 return -EINVAL; 96 } 97 98 phy->throttle_temp[i - 1] = val; 99 mutex_unlock(&phy->dev->mt76.mutex); 100 101 ret = mt7996_mcu_set_thermal_protect(phy, true); 102 if (ret) 103 return ret; 104 105 return count; 106 } 107 108 static SENSOR_DEVICE_ATTR_RO(temp1_input, mt7996_thermal_temp, 0); 109 static SENSOR_DEVICE_ATTR_RW(temp1_crit, mt7996_thermal_temp, 1); 110 static SENSOR_DEVICE_ATTR_RW(temp1_max, mt7996_thermal_temp, 2); 111 static SENSOR_DEVICE_ATTR_RO(throttle1, mt7996_thermal_temp, 3); 112 113 static struct attribute *mt7996_hwmon_attrs[] = { 114 &sensor_dev_attr_temp1_input.dev_attr.attr, 115 &sensor_dev_attr_temp1_crit.dev_attr.attr, 116 &sensor_dev_attr_temp1_max.dev_attr.attr, 117 &sensor_dev_attr_throttle1.dev_attr.attr, 118 NULL, 119 }; 120 ATTRIBUTE_GROUPS(mt7996_hwmon); 121 122 static int 123 mt7996_thermal_get_max_throttle_state(struct thermal_cooling_device *cdev, 124 unsigned long *state) 125 { 126 *state = MT7996_CDEV_THROTTLE_MAX; 127 128 return 0; 129 } 130 131 static int 132 mt7996_thermal_get_cur_throttle_state(struct thermal_cooling_device *cdev, 133 unsigned long *state) 134 { 135 struct mt7996_phy *phy = cdev->devdata; 136 137 *state = phy->cdev_state; 138 139 return 0; 140 } 141 142 static int 143 mt7996_thermal_set_cur_throttle_state(struct thermal_cooling_device *cdev, 144 unsigned long state) 145 { 146 struct mt7996_phy *phy = cdev->devdata; 147 u8 throttling = MT7996_THERMAL_THROTTLE_MAX - state; 148 int ret; 149 150 if (state > MT7996_CDEV_THROTTLE_MAX) { 151 dev_err(phy->dev->mt76.dev, 152 "please specify a valid throttling state\n"); 153 return -EINVAL; 154 } 155 156 if (state == phy->cdev_state) 157 return 0; 158 159 /* cooling_device convention: 0 = no cooling, more = more cooling 160 * mcu convention: 1 = max cooling, more = less cooling 161 */ 162 ret = mt7996_mcu_set_thermal_throttling(phy, throttling); 163 if (ret) 164 return ret; 165 166 phy->cdev_state = state; 167 168 return 0; 169 } 170 171 static const struct thermal_cooling_device_ops mt7996_thermal_ops = { 172 .get_max_state = mt7996_thermal_get_max_throttle_state, 173 .get_cur_state = mt7996_thermal_get_cur_throttle_state, 174 .set_cur_state = mt7996_thermal_set_cur_throttle_state, 175 }; 176 177 static void mt7996_unregister_thermal(struct mt7996_phy *phy) 178 { 179 struct wiphy *wiphy = phy->mt76->hw->wiphy; 180 181 if (!phy->cdev) 182 return; 183 184 sysfs_remove_link(&wiphy->dev.kobj, "cooling_device"); 185 thermal_cooling_device_unregister(phy->cdev); 186 } 187 188 static int mt7996_thermal_init(struct mt7996_phy *phy) 189 { 190 struct wiphy *wiphy = phy->mt76->hw->wiphy; 191 struct thermal_cooling_device *cdev; 192 struct device *hwmon; 193 const char *name; 194 195 name = devm_kasprintf(&wiphy->dev, GFP_KERNEL, "mt7996_%s", 196 wiphy_name(wiphy)); 197 198 cdev = thermal_cooling_device_register(name, phy, &mt7996_thermal_ops); 199 if (!IS_ERR(cdev)) { 200 if (sysfs_create_link(&wiphy->dev.kobj, &cdev->device.kobj, 201 "cooling_device") < 0) 202 thermal_cooling_device_unregister(cdev); 203 else 204 phy->cdev = cdev; 205 } 206 207 /* initialize critical/maximum high temperature */ 208 phy->throttle_temp[MT7996_CRIT_TEMP_IDX] = MT7996_CRIT_TEMP; 209 phy->throttle_temp[MT7996_MAX_TEMP_IDX] = MT7996_MAX_TEMP; 210 211 if (!IS_REACHABLE(CONFIG_HWMON)) 212 return 0; 213 214 hwmon = devm_hwmon_device_register_with_groups(&wiphy->dev, name, phy, 215 mt7996_hwmon_groups); 216 217 if (IS_ERR(hwmon)) 218 return PTR_ERR(hwmon); 219 220 return 0; 221 } 222 223 static void mt7996_led_set_config(struct led_classdev *led_cdev, 224 u8 delay_on, u8 delay_off) 225 { 226 struct mt7996_dev *dev; 227 struct mt76_phy *mphy; 228 u32 val; 229 230 mphy = container_of(led_cdev, struct mt76_phy, leds.cdev); 231 dev = container_of(mphy->dev, struct mt7996_dev, mt76); 232 233 /* select TX blink mode, 2: only data frames */ 234 mt76_rmw_field(dev, MT_TMAC_TCR0(mphy->band_idx), MT_TMAC_TCR0_TX_BLINK, 2); 235 236 /* enable LED */ 237 mt76_wr(dev, MT_LED_EN(mphy->band_idx), 1); 238 239 /* set LED Tx blink on/off time */ 240 val = FIELD_PREP(MT_LED_TX_BLINK_ON_MASK, delay_on) | 241 FIELD_PREP(MT_LED_TX_BLINK_OFF_MASK, delay_off); 242 mt76_wr(dev, MT_LED_TX_BLINK(mphy->band_idx), val); 243 244 /* turn LED off */ 245 if (delay_off == 0xff && delay_on == 0x0) { 246 val = MT_LED_CTRL_POLARITY | MT_LED_CTRL_KICK; 247 } else { 248 /* control LED */ 249 val = MT_LED_CTRL_BLINK_MODE | MT_LED_CTRL_KICK; 250 if (mphy->band_idx == MT_BAND1) 251 val |= MT_LED_CTRL_BLINK_BAND_SEL; 252 } 253 254 if (mphy->leds.al) 255 val |= MT_LED_CTRL_POLARITY; 256 257 mt76_wr(dev, MT_LED_CTRL(mphy->band_idx), val); 258 mt76_clear(dev, MT_LED_CTRL(mphy->band_idx), MT_LED_CTRL_KICK); 259 } 260 261 static int mt7996_led_set_blink(struct led_classdev *led_cdev, 262 unsigned long *delay_on, 263 unsigned long *delay_off) 264 { 265 u16 delta_on = 0, delta_off = 0; 266 267 #define HW_TICK 10 268 #define TO_HW_TICK(_t) (((_t) > HW_TICK) ? ((_t) / HW_TICK) : HW_TICK) 269 270 if (*delay_on) 271 delta_on = TO_HW_TICK(*delay_on); 272 if (*delay_off) 273 delta_off = TO_HW_TICK(*delay_off); 274 275 mt7996_led_set_config(led_cdev, delta_on, delta_off); 276 277 return 0; 278 } 279 280 static void mt7996_led_set_brightness(struct led_classdev *led_cdev, 281 enum led_brightness brightness) 282 { 283 if (!brightness) 284 mt7996_led_set_config(led_cdev, 0, 0xff); 285 else 286 mt7996_led_set_config(led_cdev, 0xff, 0); 287 } 288 289 static void __mt7996_init_txpower(struct mt7996_phy *phy, 290 struct ieee80211_supported_band *sband) 291 { 292 struct mt7996_dev *dev = phy->dev; 293 int i, nss = hweight16(phy->mt76->chainmask); 294 int nss_delta = mt76_tx_power_nss_delta(nss); 295 int pwr_delta = mt7996_eeprom_get_power_delta(dev, sband->band); 296 struct mt76_power_limits limits; 297 298 for (i = 0; i < sband->n_channels; i++) { 299 struct ieee80211_channel *chan = &sband->channels[i]; 300 int target_power = mt7996_eeprom_get_target_power(dev, chan); 301 302 target_power += pwr_delta; 303 target_power = mt76_get_rate_power_limits(phy->mt76, chan, 304 &limits, 305 target_power); 306 target_power += nss_delta; 307 target_power = DIV_ROUND_UP(target_power, 2); 308 chan->max_power = min_t(int, chan->max_reg_power, 309 target_power); 310 chan->orig_mpwr = target_power; 311 } 312 } 313 314 void mt7996_init_txpower(struct mt7996_phy *phy) 315 { 316 if (!phy) 317 return; 318 319 if (phy->mt76->cap.has_2ghz) 320 __mt7996_init_txpower(phy, &phy->mt76->sband_2g.sband); 321 if (phy->mt76->cap.has_5ghz) 322 __mt7996_init_txpower(phy, &phy->mt76->sband_5g.sband); 323 if (phy->mt76->cap.has_6ghz) 324 __mt7996_init_txpower(phy, &phy->mt76->sband_6g.sband); 325 } 326 327 static void 328 mt7996_regd_notifier(struct wiphy *wiphy, 329 struct regulatory_request *request) 330 { 331 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 332 struct mt7996_dev *dev = mt7996_hw_dev(hw); 333 struct mt7996_phy *phy = mt7996_hw_phy(hw); 334 335 memcpy(dev->mt76.alpha2, request->alpha2, sizeof(dev->mt76.alpha2)); 336 dev->mt76.region = request->dfs_region; 337 338 if (dev->mt76.region == NL80211_DFS_UNSET) 339 mt7996_mcu_rdd_background_enable(phy, NULL); 340 341 mt7996_init_txpower(phy); 342 343 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN; 344 mt7996_dfs_init_radar_detector(phy); 345 } 346 347 static void 348 mt7996_init_wiphy(struct ieee80211_hw *hw, struct mtk_wed_device *wed) 349 { 350 struct mt7996_phy *phy = mt7996_hw_phy(hw); 351 struct mt76_dev *mdev = &phy->dev->mt76; 352 struct wiphy *wiphy = hw->wiphy; 353 u16 max_subframes = phy->dev->has_eht ? IEEE80211_MAX_AMPDU_BUF_EHT : 354 IEEE80211_MAX_AMPDU_BUF_HE; 355 356 hw->queues = 4; 357 hw->max_rx_aggregation_subframes = max_subframes; 358 hw->max_tx_aggregation_subframes = max_subframes; 359 hw->netdev_features = NETIF_F_RXCSUM; 360 if (mtk_wed_device_active(wed)) 361 hw->netdev_features |= NETIF_F_HW_TC; 362 363 hw->radiotap_timestamp.units_pos = 364 IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US; 365 366 phy->slottime = 9; 367 phy->beacon_rate = -1; 368 369 hw->sta_data_size = sizeof(struct mt7996_sta); 370 hw->vif_data_size = sizeof(struct mt7996_vif); 371 372 wiphy->iface_combinations = if_comb; 373 wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); 374 wiphy->reg_notifier = mt7996_regd_notifier; 375 wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; 376 wiphy->mbssid_max_interfaces = 16; 377 378 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR); 379 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS); 380 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_LEGACY); 381 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HT); 382 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_VHT); 383 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HE); 384 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP); 385 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_FILS_DISCOVERY); 386 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT); 387 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 388 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_MU_MIMO_AIR_SNIFFER); 389 390 if (mt7996_has_background_radar(phy->dev) && 391 (!mdev->dev->of_node || 392 !of_property_read_bool(mdev->dev->of_node, 393 "mediatek,disable-radar-background"))) 394 wiphy_ext_feature_set(wiphy, 395 NL80211_EXT_FEATURE_RADAR_BACKGROUND); 396 397 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 398 ieee80211_hw_set(hw, SUPPORTS_TX_ENCAP_OFFLOAD); 399 ieee80211_hw_set(hw, SUPPORTS_RX_DECAP_OFFLOAD); 400 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 401 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 402 403 hw->max_tx_fragments = 4; 404 405 if (phy->mt76->cap.has_2ghz) { 406 phy->mt76->sband_2g.sband.ht_cap.cap |= 407 IEEE80211_HT_CAP_LDPC_CODING | 408 IEEE80211_HT_CAP_MAX_AMSDU; 409 phy->mt76->sband_2g.sband.ht_cap.ampdu_density = 410 IEEE80211_HT_MPDU_DENSITY_2; 411 } 412 413 if (phy->mt76->cap.has_5ghz) { 414 phy->mt76->sband_5g.sband.ht_cap.cap |= 415 IEEE80211_HT_CAP_LDPC_CODING | 416 IEEE80211_HT_CAP_MAX_AMSDU; 417 418 phy->mt76->sband_5g.sband.vht_cap.cap |= 419 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 420 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 421 IEEE80211_VHT_CAP_SHORT_GI_160 | 422 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ; 423 phy->mt76->sband_5g.sband.ht_cap.ampdu_density = 424 IEEE80211_HT_MPDU_DENSITY_1; 425 426 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 427 } 428 429 /* init led callbacks */ 430 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 431 phy->mt76->leds.cdev.brightness_set = mt7996_led_set_brightness; 432 phy->mt76->leds.cdev.blink_set = mt7996_led_set_blink; 433 } 434 435 mt76_set_stream_caps(phy->mt76, true); 436 mt7996_set_stream_vht_txbf_caps(phy); 437 mt7996_set_stream_he_eht_caps(phy); 438 mt7996_init_txpower(phy); 439 440 wiphy->available_antennas_rx = phy->mt76->antenna_mask; 441 wiphy->available_antennas_tx = phy->mt76->antenna_mask; 442 443 wiphy->max_scan_ssids = 4; 444 wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN; 445 } 446 447 static void 448 mt7996_mac_init_band(struct mt7996_dev *dev, u8 band) 449 { 450 u32 mask, set; 451 452 /* clear estimated value of EIFS for Rx duration & OBSS time */ 453 mt76_wr(dev, MT_WF_RMAC_RSVD0(band), MT_WF_RMAC_RSVD0_EIFS_CLR); 454 455 /* clear backoff time for Rx duration */ 456 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME1(band), 457 MT_WF_RMAC_MIB_NONQOSD_BACKOFF); 458 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME3(band), 459 MT_WF_RMAC_MIB_QOS01_BACKOFF); 460 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME4(band), 461 MT_WF_RMAC_MIB_QOS23_BACKOFF); 462 463 /* clear backoff time for Tx duration */ 464 mt76_clear(dev, MT_WTBLOFF_ACR(band), 465 MT_WTBLOFF_ADM_BACKOFFTIME); 466 467 /* clear backoff time and set software compensation for OBSS time */ 468 mask = MT_WF_RMAC_MIB_OBSS_BACKOFF | MT_WF_RMAC_MIB_ED_OFFSET; 469 set = FIELD_PREP(MT_WF_RMAC_MIB_OBSS_BACKOFF, 0) | 470 FIELD_PREP(MT_WF_RMAC_MIB_ED_OFFSET, 4); 471 mt76_rmw(dev, MT_WF_RMAC_MIB_AIRTIME0(band), mask, set); 472 473 /* filter out non-resp frames and get instanstaeous signal reporting */ 474 mask = MT_WTBLOFF_RSCR_RCPI_MODE | MT_WTBLOFF_RSCR_RCPI_PARAM; 475 set = FIELD_PREP(MT_WTBLOFF_RSCR_RCPI_MODE, 0) | 476 FIELD_PREP(MT_WTBLOFF_RSCR_RCPI_PARAM, 0x3); 477 mt76_rmw(dev, MT_WTBLOFF_RSCR(band), mask, set); 478 479 /* MT_TXD5_TX_STATUS_HOST (MPDU format) has higher priority than 480 * MT_AGG_ACR_PPDU_TXS2H (PPDU format) even though ACR bit is set. 481 */ 482 mt76_set(dev, MT_AGG_ACR4(band), MT_AGG_ACR_PPDU_TXS2H); 483 } 484 485 static void mt7996_mac_init_basic_rates(struct mt7996_dev *dev) 486 { 487 int i; 488 489 for (i = 0; i < ARRAY_SIZE(mt76_rates); i++) { 490 u16 rate = mt76_rates[i].hw_value; 491 /* odd index for driver, even index for firmware */ 492 u16 idx = MT7996_BASIC_RATES_TBL + 2 * i; 493 494 rate = FIELD_PREP(MT_TX_RATE_MODE, rate >> 8) | 495 FIELD_PREP(MT_TX_RATE_IDX, rate & GENMASK(7, 0)); 496 mt7996_mcu_set_fixed_rate_table(&dev->phy, idx, rate, false); 497 } 498 } 499 500 void mt7996_mac_init(struct mt7996_dev *dev) 501 { 502 #define HIF_TXD_V2_1 0x21 503 int i; 504 505 mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT); 506 507 for (i = 0; i < mt7996_wtbl_size(dev); i++) 508 mt7996_mac_wtbl_update(dev, i, 509 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 510 511 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 512 i = dev->mphy.leds.pin ? MT_LED_GPIO_MUX3 : MT_LED_GPIO_MUX2; 513 mt76_rmw_field(dev, i, MT_LED_GPIO_SEL_MASK, 4); 514 } 515 516 /* rro module init */ 517 if (is_mt7996(&dev->mt76)) 518 mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 2); 519 else 520 mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 521 dev->hif2 ? 7 : 0); 522 523 if (dev->has_rro) { 524 u16 timeout; 525 526 timeout = mt76_rr(dev, MT_HW_REV) == MT_HW_REV1 ? 512 : 128; 527 mt7996_mcu_set_rro(dev, UNI_RRO_SET_FLUSH_TIMEOUT, timeout); 528 mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 1); 529 mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 0); 530 } else { 531 mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 3); 532 mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 1); 533 } 534 535 mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), 536 MCU_WA_PARAM_HW_PATH_HIF_VER, 537 HIF_TXD_V2_1, 0); 538 539 for (i = MT_BAND0; i <= MT_BAND2; i++) 540 mt7996_mac_init_band(dev, i); 541 542 mt7996_mac_init_basic_rates(dev); 543 } 544 545 int mt7996_txbf_init(struct mt7996_dev *dev) 546 { 547 int ret; 548 549 if (mt7996_band_valid(dev, MT_BAND1) || 550 mt7996_band_valid(dev, MT_BAND2)) { 551 ret = mt7996_mcu_set_txbf(dev, BF_MOD_EN_CTRL); 552 if (ret) 553 return ret; 554 } 555 556 /* trigger sounding packets */ 557 ret = mt7996_mcu_set_txbf(dev, BF_SOUNDING_ON); 558 if (ret) 559 return ret; 560 561 /* enable eBF */ 562 return mt7996_mcu_set_txbf(dev, BF_HW_EN_UPDATE); 563 } 564 565 static int mt7996_register_phy(struct mt7996_dev *dev, struct mt7996_phy *phy, 566 enum mt76_band_id band) 567 { 568 struct mt76_phy *mphy; 569 u32 mac_ofs, hif1_ofs = 0; 570 int ret; 571 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 572 573 if (!mt7996_band_valid(dev, band) || band == MT_BAND0) 574 return 0; 575 576 if (phy) 577 return 0; 578 579 if (is_mt7996(&dev->mt76) && band == MT_BAND2 && dev->hif2) { 580 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); 581 wed = &dev->mt76.mmio.wed_hif2; 582 } 583 584 mphy = mt76_alloc_phy(&dev->mt76, sizeof(*phy), &mt7996_ops, band); 585 if (!mphy) 586 return -ENOMEM; 587 588 phy = mphy->priv; 589 phy->dev = dev; 590 phy->mt76 = mphy; 591 mphy->dev->phys[band] = mphy; 592 593 INIT_DELAYED_WORK(&mphy->mac_work, mt7996_mac_work); 594 595 ret = mt7996_eeprom_parse_hw_cap(dev, phy); 596 if (ret) 597 goto error; 598 599 mac_ofs = band == MT_BAND2 ? MT_EE_MAC_ADDR3 : MT_EE_MAC_ADDR2; 600 memcpy(mphy->macaddr, dev->mt76.eeprom.data + mac_ofs, ETH_ALEN); 601 /* Make the extra PHY MAC address local without overlapping with 602 * the usual MAC address allocation scheme on multiple virtual interfaces 603 */ 604 if (!is_valid_ether_addr(mphy->macaddr)) { 605 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR, 606 ETH_ALEN); 607 mphy->macaddr[0] |= 2; 608 mphy->macaddr[0] ^= BIT(7); 609 if (band == MT_BAND2) 610 mphy->macaddr[0] ^= BIT(6); 611 } 612 mt76_eeprom_override(mphy); 613 614 /* init wiphy according to mphy and phy */ 615 mt7996_init_wiphy(mphy->hw, wed); 616 ret = mt7996_init_tx_queues(mphy->priv, 617 MT_TXQ_ID(band), 618 MT7996_TX_RING_SIZE, 619 MT_TXQ_RING_BASE(band) + hif1_ofs, 620 wed); 621 if (ret) 622 goto error; 623 624 ret = mt76_register_phy(mphy, true, mt76_rates, 625 ARRAY_SIZE(mt76_rates)); 626 if (ret) 627 goto error; 628 629 ret = mt7996_thermal_init(phy); 630 if (ret) 631 goto error; 632 633 ret = mt7996_init_debugfs(phy); 634 if (ret) 635 goto error; 636 637 if (wed == &dev->mt76.mmio.wed_hif2 && mtk_wed_device_active(wed)) { 638 u32 irq_mask = dev->mt76.mmio.irqmask | MT_INT_TX_DONE_BAND2; 639 640 mt76_wr(dev, MT_INT1_MASK_CSR, irq_mask); 641 mtk_wed_device_start(&dev->mt76.mmio.wed_hif2, irq_mask); 642 } 643 644 return 0; 645 646 error: 647 mphy->dev->phys[band] = NULL; 648 ieee80211_free_hw(mphy->hw); 649 return ret; 650 } 651 652 static void 653 mt7996_unregister_phy(struct mt7996_phy *phy, enum mt76_band_id band) 654 { 655 struct mt76_phy *mphy; 656 657 if (!phy) 658 return; 659 660 mt7996_unregister_thermal(phy); 661 662 mphy = phy->dev->mt76.phys[band]; 663 mt76_unregister_phy(mphy); 664 ieee80211_free_hw(mphy->hw); 665 phy->dev->mt76.phys[band] = NULL; 666 } 667 668 static void mt7996_init_work(struct work_struct *work) 669 { 670 struct mt7996_dev *dev = container_of(work, struct mt7996_dev, 671 init_work); 672 673 mt7996_mcu_set_eeprom(dev); 674 mt7996_mac_init(dev); 675 mt7996_txbf_init(dev); 676 } 677 678 void mt7996_wfsys_reset(struct mt7996_dev *dev) 679 { 680 mt76_set(dev, MT_WF_SUBSYS_RST, 0x1); 681 msleep(20); 682 683 mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1); 684 msleep(20); 685 } 686 687 static int mt7996_wed_rro_init(struct mt7996_dev *dev) 688 { 689 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 690 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 691 u32 reg = MT_RRO_ADDR_ELEM_SEG_ADDR0; 692 struct mt7996_wed_rro_addr *addr; 693 void *ptr; 694 int i; 695 696 if (!dev->has_rro) 697 return 0; 698 699 if (!mtk_wed_device_active(wed)) 700 return 0; 701 702 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.ba_bitmap); i++) { 703 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 704 MT7996_RRO_BA_BITMAP_CR_SIZE, 705 &dev->wed_rro.ba_bitmap[i].phy_addr, 706 GFP_KERNEL); 707 if (!ptr) 708 return -ENOMEM; 709 710 dev->wed_rro.ba_bitmap[i].ptr = ptr; 711 } 712 713 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) { 714 int j; 715 716 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 717 MT7996_RRO_WINDOW_MAX_SIZE * sizeof(*addr), 718 &dev->wed_rro.addr_elem[i].phy_addr, 719 GFP_KERNEL); 720 if (!ptr) 721 return -ENOMEM; 722 723 dev->wed_rro.addr_elem[i].ptr = ptr; 724 memset(dev->wed_rro.addr_elem[i].ptr, 0, 725 MT7996_RRO_WINDOW_MAX_SIZE * sizeof(*addr)); 726 727 addr = dev->wed_rro.addr_elem[i].ptr; 728 for (j = 0; j < MT7996_RRO_WINDOW_MAX_SIZE; j++) { 729 addr->signature = 0xff; 730 addr++; 731 } 732 733 wed->wlan.ind_cmd.addr_elem_phys[i] = 734 dev->wed_rro.addr_elem[i].phy_addr; 735 } 736 737 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 738 MT7996_RRO_WINDOW_MAX_LEN * sizeof(*addr), 739 &dev->wed_rro.session.phy_addr, 740 GFP_KERNEL); 741 if (!ptr) 742 return -ENOMEM; 743 744 dev->wed_rro.session.ptr = ptr; 745 addr = dev->wed_rro.session.ptr; 746 for (i = 0; i < MT7996_RRO_WINDOW_MAX_LEN; i++) { 747 addr->signature = 0xff; 748 addr++; 749 } 750 751 /* rro hw init */ 752 /* TODO: remove line after WM has set */ 753 mt76_clear(dev, WF_RRO_AXI_MST_CFG, WF_RRO_AXI_MST_CFG_DIDX_OK); 754 755 /* setup BA bitmap cache address */ 756 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE0, 757 dev->wed_rro.ba_bitmap[0].phy_addr); 758 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE1, 0); 759 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE_EXT0, 760 dev->wed_rro.ba_bitmap[1].phy_addr); 761 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE_EXT1, 0); 762 763 /* setup Address element address */ 764 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) { 765 mt76_wr(dev, reg, dev->wed_rro.addr_elem[i].phy_addr >> 4); 766 reg += 4; 767 } 768 769 /* setup Address element address - separate address segment mode */ 770 mt76_wr(dev, MT_RRO_ADDR_ARRAY_BASE1, 771 MT_RRO_ADDR_ARRAY_ELEM_ADDR_SEG_MODE); 772 773 wed->wlan.ind_cmd.win_size = ffs(MT7996_RRO_WINDOW_MAX_LEN) - 6; 774 wed->wlan.ind_cmd.particular_sid = MT7996_RRO_MAX_SESSION; 775 wed->wlan.ind_cmd.particular_se_phys = dev->wed_rro.session.phy_addr; 776 wed->wlan.ind_cmd.se_group_nums = MT7996_RRO_ADDR_ELEM_LEN; 777 wed->wlan.ind_cmd.ack_sn_addr = MT_RRO_ACK_SN_CTRL; 778 779 mt76_wr(dev, MT_RRO_IND_CMD_SIGNATURE_BASE0, 0x15010e00); 780 mt76_set(dev, MT_RRO_IND_CMD_SIGNATURE_BASE1, 781 MT_RRO_IND_CMD_SIGNATURE_BASE1_EN); 782 783 /* particular session configure */ 784 /* use max session idx + 1 as particular session id */ 785 mt76_wr(dev, MT_RRO_PARTICULAR_CFG0, dev->wed_rro.session.phy_addr); 786 mt76_wr(dev, MT_RRO_PARTICULAR_CFG1, 787 MT_RRO_PARTICULAR_CONFG_EN | 788 FIELD_PREP(MT_RRO_PARTICULAR_SID, MT7996_RRO_MAX_SESSION)); 789 790 /* interrupt enable */ 791 mt76_wr(dev, MT_RRO_HOST_INT_ENA, 792 MT_RRO_HOST_INT_ENA_HOST_RRO_DONE_ENA); 793 794 /* rro ind cmd queue init */ 795 return mt7996_dma_rro_init(dev); 796 #else 797 return 0; 798 #endif 799 } 800 801 static void mt7996_wed_rro_free(struct mt7996_dev *dev) 802 { 803 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 804 int i; 805 806 if (!dev->has_rro) 807 return; 808 809 if (!mtk_wed_device_active(&dev->mt76.mmio.wed)) 810 return; 811 812 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.ba_bitmap); i++) { 813 if (!dev->wed_rro.ba_bitmap[i].ptr) 814 continue; 815 816 dmam_free_coherent(dev->mt76.dma_dev, 817 MT7996_RRO_BA_BITMAP_CR_SIZE, 818 dev->wed_rro.ba_bitmap[i].ptr, 819 dev->wed_rro.ba_bitmap[i].phy_addr); 820 } 821 822 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) { 823 if (!dev->wed_rro.addr_elem[i].ptr) 824 continue; 825 826 dmam_free_coherent(dev->mt76.dma_dev, 827 MT7996_RRO_WINDOW_MAX_SIZE * 828 sizeof(struct mt7996_wed_rro_addr), 829 dev->wed_rro.addr_elem[i].ptr, 830 dev->wed_rro.addr_elem[i].phy_addr); 831 } 832 833 if (!dev->wed_rro.session.ptr) 834 return; 835 836 dmam_free_coherent(dev->mt76.dma_dev, 837 MT7996_RRO_WINDOW_MAX_LEN * 838 sizeof(struct mt7996_wed_rro_addr), 839 dev->wed_rro.session.ptr, 840 dev->wed_rro.session.phy_addr); 841 #endif 842 } 843 844 static void mt7996_wed_rro_work(struct work_struct *work) 845 { 846 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 847 struct mt7996_dev *dev; 848 LIST_HEAD(list); 849 850 dev = (struct mt7996_dev *)container_of(work, struct mt7996_dev, 851 wed_rro.work); 852 853 spin_lock_bh(&dev->wed_rro.lock); 854 list_splice_init(&dev->wed_rro.poll_list, &list); 855 spin_unlock_bh(&dev->wed_rro.lock); 856 857 while (!list_empty(&list)) { 858 struct mt7996_wed_rro_session_id *e; 859 int i; 860 861 e = list_first_entry(&list, struct mt7996_wed_rro_session_id, 862 list); 863 list_del_init(&e->list); 864 865 for (i = 0; i < MT7996_RRO_WINDOW_MAX_LEN; i++) { 866 void *ptr = dev->wed_rro.session.ptr; 867 struct mt7996_wed_rro_addr *elem; 868 u32 idx, elem_id = i; 869 870 if (e->id == MT7996_RRO_MAX_SESSION) 871 goto reset; 872 873 idx = e->id / MT7996_RRO_BA_BITMAP_SESSION_SIZE; 874 if (idx >= ARRAY_SIZE(dev->wed_rro.addr_elem)) 875 goto out; 876 877 ptr = dev->wed_rro.addr_elem[idx].ptr; 878 elem_id += 879 (e->id % MT7996_RRO_BA_BITMAP_SESSION_SIZE) * 880 MT7996_RRO_WINDOW_MAX_LEN; 881 reset: 882 elem = ptr + elem_id * sizeof(*elem); 883 elem->signature = 0xff; 884 } 885 mt7996_mcu_wed_rro_reset_sessions(dev, e->id); 886 out: 887 kfree(e); 888 } 889 #endif 890 } 891 892 static int mt7996_variant_type_init(struct mt7996_dev *dev) 893 { 894 u32 val = mt76_rr(dev, MT_PAD_GPIO); 895 u8 var_type; 896 897 switch (mt76_chip(&dev->mt76)) { 898 case 0x7990: 899 if (val & MT_PAD_GPIO_2ADIE_TBTC) 900 var_type = MT7996_VAR_TYPE_233; 901 else 902 var_type = MT7996_VAR_TYPE_444; 903 break; 904 case 0x7992: 905 if (val & MT_PAD_GPIO_ADIE_SINGLE) 906 var_type = MT7992_VAR_TYPE_23; 907 else if (u32_get_bits(val, MT_PAD_GPIO_ADIE_COMB_7992)) 908 var_type = MT7992_VAR_TYPE_44; 909 else 910 return -EINVAL; 911 break; 912 default: 913 return -EINVAL; 914 } 915 916 dev->var.type = var_type; 917 return 0; 918 } 919 920 static int mt7996_variant_fem_init(struct mt7996_dev *dev) 921 { 922 #define MT7976C_EFUSE_OFFSET 0x470 923 u8 buf[MT7996_EEPROM_BLOCK_SIZE], idx, adie_idx, adie_comb; 924 u32 regval, val = mt76_rr(dev, MT_PAD_GPIO); 925 u16 adie_id, adie_ver; 926 bool is_7976c; 927 int ret; 928 929 if (is_mt7992(&dev->mt76)) { 930 adie_idx = (val & MT_PAD_GPIO_ADIE_SINGLE) ? 0 : 1; 931 adie_comb = u32_get_bits(val, MT_PAD_GPIO_ADIE_COMB_7992); 932 } else { 933 adie_idx = 0; 934 adie_comb = u32_get_bits(val, MT_PAD_GPIO_ADIE_COMB); 935 } 936 937 ret = mt7996_mcu_rf_regval(dev, MT_ADIE_CHIP_ID(adie_idx), ®val, false); 938 if (ret) 939 return ret; 940 941 ret = mt7996_mcu_get_eeprom(dev, MT7976C_EFUSE_OFFSET, buf, sizeof(buf)); 942 if (ret && ret != -EINVAL) 943 return ret; 944 945 adie_ver = u32_get_bits(regval, MT_ADIE_VERSION_MASK); 946 idx = MT7976C_EFUSE_OFFSET % MT7996_EEPROM_BLOCK_SIZE; 947 is_7976c = adie_ver == 0x8a10 || adie_ver == 0x8b00 || 948 adie_ver == 0x8c10 || buf[idx] == 0xc; 949 950 adie_id = u32_get_bits(regval, MT_ADIE_CHIP_ID_MASK); 951 if (adie_id == 0x7975 || adie_id == 0x7979 || 952 (adie_id == 0x7976 && is_7976c)) 953 dev->var.fem = MT7996_FEM_INT; 954 else if (adie_id == 0x7977 && adie_comb == 1) 955 dev->var.fem = MT7996_FEM_MIX; 956 else 957 dev->var.fem = MT7996_FEM_EXT; 958 959 return 0; 960 } 961 962 static int mt7996_init_hardware(struct mt7996_dev *dev) 963 { 964 int ret, idx; 965 966 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 967 if (is_mt7992(&dev->mt76)) { 968 mt76_rmw(dev, MT_AFE_CTL_BAND_PLL_03(MT_BAND0), MT_AFE_CTL_BAND_PLL_03_MSB_EN, 0); 969 mt76_rmw(dev, MT_AFE_CTL_BAND_PLL_03(MT_BAND1), MT_AFE_CTL_BAND_PLL_03_MSB_EN, 0); 970 } 971 972 INIT_WORK(&dev->init_work, mt7996_init_work); 973 INIT_WORK(&dev->wed_rro.work, mt7996_wed_rro_work); 974 INIT_LIST_HEAD(&dev->wed_rro.poll_list); 975 spin_lock_init(&dev->wed_rro.lock); 976 977 ret = mt7996_variant_type_init(dev); 978 if (ret) 979 return ret; 980 981 ret = mt7996_dma_init(dev); 982 if (ret) 983 return ret; 984 985 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state); 986 987 ret = mt7996_mcu_init(dev); 988 if (ret) 989 return ret; 990 991 ret = mt7996_wed_rro_init(dev); 992 if (ret) 993 return ret; 994 995 ret = mt7996_variant_fem_init(dev); 996 if (ret) 997 return ret; 998 999 ret = mt7996_eeprom_init(dev); 1000 if (ret < 0) 1001 return ret; 1002 1003 /* Beacon and mgmt frames should occupy wcid 0 */ 1004 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7996_WTBL_STA); 1005 if (idx) 1006 return -ENOSPC; 1007 1008 dev->mt76.global_wcid.idx = idx; 1009 dev->mt76.global_wcid.hw_key_idx = -1; 1010 dev->mt76.global_wcid.tx_info |= MT_WCID_TX_INFO_SET; 1011 rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid); 1012 1013 return 0; 1014 } 1015 1016 void mt7996_set_stream_vht_txbf_caps(struct mt7996_phy *phy) 1017 { 1018 int sts; 1019 u32 *cap; 1020 1021 if (!phy->mt76->cap.has_5ghz) 1022 return; 1023 1024 sts = hweight16(phy->mt76->chainmask); 1025 cap = &phy->mt76->sband_5g.sband.vht_cap.cap; 1026 1027 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | 1028 IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE; 1029 1030 if (is_mt7996(phy->mt76->dev)) 1031 *cap |= FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, 3); 1032 else 1033 *cap |= FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, 4); 1034 1035 *cap &= ~(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK | 1036 IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 1037 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE); 1038 1039 if (sts < 2) 1040 return; 1041 1042 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 1043 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE | 1044 FIELD_PREP(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, sts - 1); 1045 } 1046 1047 static void 1048 mt7996_set_stream_he_txbf_caps(struct mt7996_phy *phy, 1049 struct ieee80211_sta_he_cap *he_cap, int vif) 1050 { 1051 struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem; 1052 int sts = hweight16(phy->mt76->chainmask); 1053 u8 c; 1054 1055 #ifdef CONFIG_MAC80211_MESH 1056 if (vif == NL80211_IFTYPE_MESH_POINT) 1057 return; 1058 #endif 1059 1060 elem->phy_cap_info[3] &= ~IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 1061 elem->phy_cap_info[4] &= ~IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 1062 1063 c = IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK | 1064 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK; 1065 elem->phy_cap_info[5] &= ~c; 1066 1067 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 1068 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 1069 elem->phy_cap_info[6] &= ~c; 1070 1071 elem->phy_cap_info[7] &= ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK; 1072 1073 c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 1074 IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO | 1075 IEEE80211_HE_PHY_CAP2_UL_MU_PARTIAL_MU_MIMO; 1076 elem->phy_cap_info[2] |= c; 1077 1078 c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE; 1079 1080 if (is_mt7996(phy->mt76->dev)) 1081 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4 | 1082 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 1083 else 1084 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_5 | 1085 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_5; 1086 1087 elem->phy_cap_info[4] |= c; 1088 1089 /* do not support NG16 due to spec D4.0 changes subcarrier idx */ 1090 c = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 1091 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU; 1092 1093 if (vif == NL80211_IFTYPE_STATION) 1094 c |= IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO; 1095 1096 elem->phy_cap_info[6] |= c; 1097 1098 if (sts < 2) 1099 return; 1100 1101 /* the maximum cap is 4 x 3, (Nr, Nc) = (3, 2) */ 1102 elem->phy_cap_info[7] |= min_t(int, sts - 1, 2) << 3; 1103 1104 if (!(vif == NL80211_IFTYPE_AP || vif == NL80211_IFTYPE_STATION)) 1105 return; 1106 1107 elem->phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 1108 1109 c = FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 1110 sts - 1) | 1111 FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK, 1112 sts - 1); 1113 elem->phy_cap_info[5] |= c; 1114 1115 if (vif != NL80211_IFTYPE_AP) 1116 return; 1117 1118 elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 1119 1120 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 1121 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 1122 elem->phy_cap_info[6] |= c; 1123 1124 c = IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ | 1125 IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ; 1126 elem->phy_cap_info[7] |= c; 1127 } 1128 1129 static void 1130 mt7996_init_he_caps(struct mt7996_phy *phy, enum nl80211_band band, 1131 struct ieee80211_sband_iftype_data *data, 1132 enum nl80211_iftype iftype) 1133 { 1134 struct ieee80211_sta_he_cap *he_cap = &data->he_cap; 1135 struct ieee80211_he_cap_elem *he_cap_elem = &he_cap->he_cap_elem; 1136 struct ieee80211_he_mcs_nss_supp *he_mcs = &he_cap->he_mcs_nss_supp; 1137 int i, nss = hweight8(phy->mt76->antenna_mask); 1138 u16 mcs_map = 0; 1139 1140 for (i = 0; i < 8; i++) { 1141 if (i < nss) 1142 mcs_map |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 1143 else 1144 mcs_map |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 1145 } 1146 1147 he_cap->has_he = true; 1148 1149 he_cap_elem->mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE; 1150 he_cap_elem->mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 1151 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3; 1152 he_cap_elem->mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 1153 1154 if (band == NL80211_BAND_2GHZ) 1155 he_cap_elem->phy_cap_info[0] = 1156 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 1157 else 1158 he_cap_elem->phy_cap_info[0] = 1159 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 1160 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 1161 1162 he_cap_elem->phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD; 1163 he_cap_elem->phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 1164 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ; 1165 1166 switch (iftype) { 1167 case NL80211_IFTYPE_AP: 1168 he_cap_elem->mac_cap_info[0] |= IEEE80211_HE_MAC_CAP0_TWT_RES; 1169 he_cap_elem->mac_cap_info[2] |= IEEE80211_HE_MAC_CAP2_BSR; 1170 he_cap_elem->mac_cap_info[4] |= IEEE80211_HE_MAC_CAP4_BQR; 1171 he_cap_elem->mac_cap_info[5] |= 1172 IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX; 1173 he_cap_elem->phy_cap_info[3] |= 1174 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1175 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1176 he_cap_elem->phy_cap_info[6] |= 1177 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1178 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1179 he_cap_elem->phy_cap_info[9] |= 1180 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1181 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU; 1182 break; 1183 case NL80211_IFTYPE_STATION: 1184 he_cap_elem->mac_cap_info[1] |= 1185 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 1186 1187 if (band == NL80211_BAND_2GHZ) 1188 he_cap_elem->phy_cap_info[0] |= 1189 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G; 1190 else 1191 he_cap_elem->phy_cap_info[0] |= 1192 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G; 1193 1194 he_cap_elem->phy_cap_info[1] |= 1195 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 1196 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 1197 he_cap_elem->phy_cap_info[3] |= 1198 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1199 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1200 he_cap_elem->phy_cap_info[6] |= 1201 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB | 1202 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1203 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1204 he_cap_elem->phy_cap_info[7] |= 1205 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 1206 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI; 1207 he_cap_elem->phy_cap_info[8] |= 1208 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 1209 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 1210 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU | 1211 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_484; 1212 he_cap_elem->phy_cap_info[9] |= 1213 IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 1214 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK | 1215 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1216 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 1217 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 1218 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB; 1219 break; 1220 default: 1221 break; 1222 } 1223 1224 he_mcs->rx_mcs_80 = cpu_to_le16(mcs_map); 1225 he_mcs->tx_mcs_80 = cpu_to_le16(mcs_map); 1226 he_mcs->rx_mcs_160 = cpu_to_le16(mcs_map); 1227 he_mcs->tx_mcs_160 = cpu_to_le16(mcs_map); 1228 1229 mt7996_set_stream_he_txbf_caps(phy, he_cap, iftype); 1230 1231 memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres)); 1232 if (he_cap_elem->phy_cap_info[6] & 1233 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) { 1234 mt76_connac_gen_ppe_thresh(he_cap->ppe_thres, nss); 1235 } else { 1236 he_cap_elem->phy_cap_info[9] |= 1237 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 1238 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 1239 } 1240 1241 if (band == NL80211_BAND_6GHZ) { 1242 u16 cap = IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS | 1243 IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS; 1244 1245 cap |= u16_encode_bits(IEEE80211_HT_MPDU_DENSITY_0_5, 1246 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 1247 u16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 1248 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 1249 u16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 1250 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 1251 1252 data->he_6ghz_capa.capa = cpu_to_le16(cap); 1253 } 1254 } 1255 1256 static void 1257 mt7996_init_eht_caps(struct mt7996_phy *phy, enum nl80211_band band, 1258 struct ieee80211_sband_iftype_data *data, 1259 enum nl80211_iftype iftype) 1260 { 1261 struct ieee80211_sta_eht_cap *eht_cap = &data->eht_cap; 1262 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem = &eht_cap->eht_cap_elem; 1263 struct ieee80211_eht_mcs_nss_supp *eht_nss = &eht_cap->eht_mcs_nss_supp; 1264 enum nl80211_chan_width width = phy->mt76->chandef.width; 1265 int nss = hweight8(phy->mt76->antenna_mask); 1266 int sts = hweight16(phy->mt76->chainmask); 1267 u8 val; 1268 1269 if (!phy->dev->has_eht) 1270 return; 1271 1272 eht_cap->has_eht = true; 1273 1274 eht_cap_elem->mac_cap_info[0] = 1275 IEEE80211_EHT_MAC_CAP0_EPCS_PRIO_ACCESS | 1276 IEEE80211_EHT_MAC_CAP0_OM_CONTROL; 1277 1278 eht_cap_elem->phy_cap_info[0] = 1279 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI | 1280 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMER | 1281 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE; 1282 1283 /* Set the maximum capability regardless of the antenna configuration. */ 1284 val = is_mt7992(phy->mt76->dev) ? 4 : 3; 1285 eht_cap_elem->phy_cap_info[0] |= 1286 u8_encode_bits(u8_get_bits(val, BIT(0)), 1287 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK); 1288 1289 eht_cap_elem->phy_cap_info[1] = 1290 u8_encode_bits(u8_get_bits(val, GENMASK(2, 1)), 1291 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK) | 1292 u8_encode_bits(val, 1293 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK); 1294 1295 eht_cap_elem->phy_cap_info[2] = 1296 u8_encode_bits(sts - 1, IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_80MHZ_MASK) | 1297 u8_encode_bits(sts - 1, IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_160MHZ_MASK); 1298 1299 if (band == NL80211_BAND_6GHZ) { 1300 eht_cap_elem->phy_cap_info[0] |= 1301 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ; 1302 1303 eht_cap_elem->phy_cap_info[1] |= 1304 u8_encode_bits(val, 1305 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK); 1306 1307 eht_cap_elem->phy_cap_info[2] |= 1308 u8_encode_bits(sts - 1, 1309 IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_320MHZ_MASK); 1310 } 1311 1312 eht_cap_elem->phy_cap_info[3] = 1313 IEEE80211_EHT_PHY_CAP3_NG_16_SU_FEEDBACK | 1314 IEEE80211_EHT_PHY_CAP3_NG_16_MU_FEEDBACK | 1315 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK | 1316 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK; 1317 1318 eht_cap_elem->phy_cap_info[4] = 1319 u8_encode_bits(min_t(int, sts - 1, 2), 1320 IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK); 1321 1322 eht_cap_elem->phy_cap_info[5] = 1323 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_16US, 1324 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK) | 1325 u8_encode_bits(u8_get_bits(0x11, GENMASK(1, 0)), 1326 IEEE80211_EHT_PHY_CAP5_MAX_NUM_SUPP_EHT_LTF_MASK); 1327 1328 val = width == NL80211_CHAN_WIDTH_320 ? 0xf : 1329 width == NL80211_CHAN_WIDTH_160 ? 0x7 : 1330 width == NL80211_CHAN_WIDTH_80 ? 0x3 : 0x1; 1331 eht_cap_elem->phy_cap_info[6] = 1332 u8_encode_bits(u8_get_bits(0x11, GENMASK(4, 2)), 1333 IEEE80211_EHT_PHY_CAP6_MAX_NUM_SUPP_EHT_LTF_MASK) | 1334 u8_encode_bits(val, IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_MASK); 1335 1336 val = u8_encode_bits(nss, IEEE80211_EHT_MCS_NSS_RX) | 1337 u8_encode_bits(nss, IEEE80211_EHT_MCS_NSS_TX); 1338 #define SET_EHT_MAX_NSS(_bw, _val) do { \ 1339 eht_nss->bw._##_bw.rx_tx_mcs9_max_nss = _val; \ 1340 eht_nss->bw._##_bw.rx_tx_mcs11_max_nss = _val; \ 1341 eht_nss->bw._##_bw.rx_tx_mcs13_max_nss = _val; \ 1342 } while (0) 1343 1344 SET_EHT_MAX_NSS(80, val); 1345 SET_EHT_MAX_NSS(160, val); 1346 if (band == NL80211_BAND_6GHZ) 1347 SET_EHT_MAX_NSS(320, val); 1348 #undef SET_EHT_MAX_NSS 1349 1350 if (iftype != NL80211_IFTYPE_AP) 1351 return; 1352 1353 eht_cap_elem->phy_cap_info[3] |= 1354 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK | 1355 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK; 1356 1357 eht_cap_elem->phy_cap_info[7] = 1358 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_80MHZ | 1359 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_160MHZ | 1360 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_80MHZ | 1361 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_160MHZ; 1362 1363 if (band != NL80211_BAND_6GHZ) 1364 return; 1365 1366 eht_cap_elem->phy_cap_info[7] |= 1367 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_320MHZ | 1368 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_320MHZ; 1369 } 1370 1371 static void 1372 __mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy, 1373 struct ieee80211_supported_band *sband, 1374 enum nl80211_band band) 1375 { 1376 struct ieee80211_sband_iftype_data *data = phy->iftype[band]; 1377 int i, n = 0; 1378 1379 for (i = 0; i < NUM_NL80211_IFTYPES; i++) { 1380 switch (i) { 1381 case NL80211_IFTYPE_STATION: 1382 case NL80211_IFTYPE_AP: 1383 #ifdef CONFIG_MAC80211_MESH 1384 case NL80211_IFTYPE_MESH_POINT: 1385 #endif 1386 break; 1387 default: 1388 continue; 1389 } 1390 1391 data[n].types_mask = BIT(i); 1392 mt7996_init_he_caps(phy, band, &data[n], i); 1393 mt7996_init_eht_caps(phy, band, &data[n], i); 1394 1395 n++; 1396 } 1397 1398 _ieee80211_set_sband_iftype_data(sband, data, n); 1399 } 1400 1401 void mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy) 1402 { 1403 if (phy->mt76->cap.has_2ghz) 1404 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_2g.sband, 1405 NL80211_BAND_2GHZ); 1406 1407 if (phy->mt76->cap.has_5ghz) 1408 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_5g.sband, 1409 NL80211_BAND_5GHZ); 1410 1411 if (phy->mt76->cap.has_6ghz) 1412 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_6g.sband, 1413 NL80211_BAND_6GHZ); 1414 } 1415 1416 int mt7996_register_device(struct mt7996_dev *dev) 1417 { 1418 struct ieee80211_hw *hw = mt76_hw(dev); 1419 int ret; 1420 1421 dev->phy.dev = dev; 1422 dev->phy.mt76 = &dev->mt76.phy; 1423 dev->mt76.phy.priv = &dev->phy; 1424 INIT_WORK(&dev->rc_work, mt7996_mac_sta_rc_work); 1425 INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7996_mac_work); 1426 INIT_LIST_HEAD(&dev->sta_rc_list); 1427 INIT_LIST_HEAD(&dev->twt_list); 1428 1429 init_waitqueue_head(&dev->reset_wait); 1430 INIT_WORK(&dev->reset_work, mt7996_mac_reset_work); 1431 INIT_WORK(&dev->dump_work, mt7996_mac_dump_work); 1432 mutex_init(&dev->dump_mutex); 1433 1434 ret = mt7996_init_hardware(dev); 1435 if (ret) 1436 return ret; 1437 1438 mt7996_init_wiphy(hw, &dev->mt76.mmio.wed); 1439 1440 ret = mt76_register_device(&dev->mt76, true, mt76_rates, 1441 ARRAY_SIZE(mt76_rates)); 1442 if (ret) 1443 return ret; 1444 1445 ret = mt7996_thermal_init(&dev->phy); 1446 if (ret) 1447 return ret; 1448 1449 ret = mt7996_register_phy(dev, mt7996_phy2(dev), MT_BAND1); 1450 if (ret) 1451 return ret; 1452 1453 ret = mt7996_register_phy(dev, mt7996_phy3(dev), MT_BAND2); 1454 if (ret) 1455 return ret; 1456 1457 ieee80211_queue_work(mt76_hw(dev), &dev->init_work); 1458 1459 dev->recovery.hw_init_done = true; 1460 1461 ret = mt7996_init_debugfs(&dev->phy); 1462 if (ret) 1463 goto error; 1464 1465 ret = mt7996_coredump_register(dev); 1466 if (ret) 1467 goto error; 1468 1469 return 0; 1470 1471 error: 1472 cancel_work_sync(&dev->init_work); 1473 1474 return ret; 1475 } 1476 1477 void mt7996_unregister_device(struct mt7996_dev *dev) 1478 { 1479 cancel_work_sync(&dev->wed_rro.work); 1480 mt7996_unregister_phy(mt7996_phy3(dev), MT_BAND2); 1481 mt7996_unregister_phy(mt7996_phy2(dev), MT_BAND1); 1482 mt7996_unregister_thermal(&dev->phy); 1483 mt7996_coredump_unregister(dev); 1484 mt76_unregister_device(&dev->mt76); 1485 mt7996_wed_rro_free(dev); 1486 mt7996_mcu_exit(dev); 1487 mt7996_tx_token_put(dev); 1488 mt7996_dma_cleanup(dev); 1489 tasklet_disable(&dev->mt76.irq_tasklet); 1490 1491 mt76_free_device(&dev->mt76); 1492 } 1493