1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #include <linux/etherdevice.h> 7 #include <linux/of.h> 8 #include <linux/hwmon.h> 9 #include <linux/hwmon-sysfs.h> 10 #include <linux/thermal.h> 11 #include "mt7996.h" 12 #include "mac.h" 13 #include "mcu.h" 14 #include "coredump.h" 15 #include "eeprom.h" 16 17 static const struct ieee80211_iface_limit if_limits[] = { 18 { 19 .max = 1, 20 .types = BIT(NL80211_IFTYPE_ADHOC) 21 }, { 22 .max = 16, 23 .types = BIT(NL80211_IFTYPE_AP) 24 #ifdef CONFIG_MAC80211_MESH 25 | BIT(NL80211_IFTYPE_MESH_POINT) 26 #endif 27 }, { 28 .max = MT7996_MAX_INTERFACES, 29 .types = BIT(NL80211_IFTYPE_STATION) 30 } 31 }; 32 33 static const struct ieee80211_iface_combination if_comb[] = { 34 { 35 .limits = if_limits, 36 .n_limits = ARRAY_SIZE(if_limits), 37 .max_interfaces = MT7996_MAX_INTERFACES, 38 .num_different_channels = 1, 39 .beacon_int_infra_match = true, 40 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 41 BIT(NL80211_CHAN_WIDTH_20) | 42 BIT(NL80211_CHAN_WIDTH_40) | 43 BIT(NL80211_CHAN_WIDTH_80) | 44 BIT(NL80211_CHAN_WIDTH_160), 45 } 46 }; 47 48 static ssize_t mt7996_thermal_temp_show(struct device *dev, 49 struct device_attribute *attr, 50 char *buf) 51 { 52 struct mt7996_phy *phy = dev_get_drvdata(dev); 53 int i = to_sensor_dev_attr(attr)->index; 54 int temperature; 55 56 switch (i) { 57 case 0: 58 temperature = mt7996_mcu_get_temperature(phy); 59 if (temperature < 0) 60 return temperature; 61 /* display in millidegree celcius */ 62 return sprintf(buf, "%u\n", temperature * 1000); 63 case 1: 64 case 2: 65 return sprintf(buf, "%u\n", 66 phy->throttle_temp[i - 1] * 1000); 67 case 3: 68 return sprintf(buf, "%hhu\n", phy->throttle_state); 69 default: 70 return -EINVAL; 71 } 72 } 73 74 static ssize_t mt7996_thermal_temp_store(struct device *dev, 75 struct device_attribute *attr, 76 const char *buf, size_t count) 77 { 78 struct mt7996_phy *phy = dev_get_drvdata(dev); 79 int ret, i = to_sensor_dev_attr(attr)->index; 80 long val; 81 82 ret = kstrtol(buf, 10, &val); 83 if (ret < 0) 84 return ret; 85 86 mutex_lock(&phy->dev->mt76.mutex); 87 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 40, 130); 88 89 /* add a safety margin ~10 */ 90 if ((i - 1 == MT7996_CRIT_TEMP_IDX && 91 val > phy->throttle_temp[MT7996_MAX_TEMP_IDX] - 10) || 92 (i - 1 == MT7996_MAX_TEMP_IDX && 93 val - 10 < phy->throttle_temp[MT7996_CRIT_TEMP_IDX])) { 94 dev_err(phy->dev->mt76.dev, 95 "temp1_max shall be 10 degrees higher than temp1_crit."); 96 mutex_unlock(&phy->dev->mt76.mutex); 97 return -EINVAL; 98 } 99 100 phy->throttle_temp[i - 1] = val; 101 mutex_unlock(&phy->dev->mt76.mutex); 102 103 ret = mt7996_mcu_set_thermal_protect(phy, true); 104 if (ret) 105 return ret; 106 107 return count; 108 } 109 110 static SENSOR_DEVICE_ATTR_RO(temp1_input, mt7996_thermal_temp, 0); 111 static SENSOR_DEVICE_ATTR_RW(temp1_crit, mt7996_thermal_temp, 1); 112 static SENSOR_DEVICE_ATTR_RW(temp1_max, mt7996_thermal_temp, 2); 113 static SENSOR_DEVICE_ATTR_RO(throttle1, mt7996_thermal_temp, 3); 114 115 static struct attribute *mt7996_hwmon_attrs[] = { 116 &sensor_dev_attr_temp1_input.dev_attr.attr, 117 &sensor_dev_attr_temp1_crit.dev_attr.attr, 118 &sensor_dev_attr_temp1_max.dev_attr.attr, 119 &sensor_dev_attr_throttle1.dev_attr.attr, 120 NULL, 121 }; 122 ATTRIBUTE_GROUPS(mt7996_hwmon); 123 124 static int 125 mt7996_thermal_get_max_throttle_state(struct thermal_cooling_device *cdev, 126 unsigned long *state) 127 { 128 *state = MT7996_CDEV_THROTTLE_MAX; 129 130 return 0; 131 } 132 133 static int 134 mt7996_thermal_get_cur_throttle_state(struct thermal_cooling_device *cdev, 135 unsigned long *state) 136 { 137 struct mt7996_phy *phy = cdev->devdata; 138 139 *state = phy->cdev_state; 140 141 return 0; 142 } 143 144 static int 145 mt7996_thermal_set_cur_throttle_state(struct thermal_cooling_device *cdev, 146 unsigned long state) 147 { 148 struct mt7996_phy *phy = cdev->devdata; 149 u8 throttling = MT7996_THERMAL_THROTTLE_MAX - state; 150 int ret; 151 152 if (state > MT7996_CDEV_THROTTLE_MAX) { 153 dev_err(phy->dev->mt76.dev, 154 "please specify a valid throttling state\n"); 155 return -EINVAL; 156 } 157 158 if (state == phy->cdev_state) 159 return 0; 160 161 /* cooling_device convention: 0 = no cooling, more = more cooling 162 * mcu convention: 1 = max cooling, more = less cooling 163 */ 164 ret = mt7996_mcu_set_thermal_throttling(phy, throttling); 165 if (ret) 166 return ret; 167 168 phy->cdev_state = state; 169 170 return 0; 171 } 172 173 static const struct thermal_cooling_device_ops mt7996_thermal_ops = { 174 .get_max_state = mt7996_thermal_get_max_throttle_state, 175 .get_cur_state = mt7996_thermal_get_cur_throttle_state, 176 .set_cur_state = mt7996_thermal_set_cur_throttle_state, 177 }; 178 179 static void mt7996_unregister_thermal(struct mt7996_phy *phy) 180 { 181 struct wiphy *wiphy = phy->mt76->hw->wiphy; 182 183 if (!phy->cdev) 184 return; 185 186 sysfs_remove_link(&wiphy->dev.kobj, "cooling_device"); 187 thermal_cooling_device_unregister(phy->cdev); 188 } 189 190 static int mt7996_thermal_init(struct mt7996_phy *phy) 191 { 192 struct wiphy *wiphy = phy->mt76->hw->wiphy; 193 struct thermal_cooling_device *cdev; 194 struct device *hwmon; 195 const char *name; 196 197 name = devm_kasprintf(&wiphy->dev, GFP_KERNEL, "mt7996_%s", 198 wiphy_name(wiphy)); 199 200 cdev = thermal_cooling_device_register(name, phy, &mt7996_thermal_ops); 201 if (!IS_ERR(cdev)) { 202 if (sysfs_create_link(&wiphy->dev.kobj, &cdev->device.kobj, 203 "cooling_device") < 0) 204 thermal_cooling_device_unregister(cdev); 205 else 206 phy->cdev = cdev; 207 } 208 209 /* initialize critical/maximum high temperature */ 210 phy->throttle_temp[MT7996_CRIT_TEMP_IDX] = MT7996_CRIT_TEMP; 211 phy->throttle_temp[MT7996_MAX_TEMP_IDX] = MT7996_MAX_TEMP; 212 213 if (!IS_REACHABLE(CONFIG_HWMON)) 214 return 0; 215 216 hwmon = devm_hwmon_device_register_with_groups(&wiphy->dev, name, phy, 217 mt7996_hwmon_groups); 218 219 if (IS_ERR(hwmon)) 220 return PTR_ERR(hwmon); 221 222 return 0; 223 } 224 225 static void mt7996_led_set_config(struct led_classdev *led_cdev, 226 u8 delay_on, u8 delay_off) 227 { 228 struct mt7996_dev *dev; 229 struct mt76_phy *mphy; 230 u32 val; 231 232 mphy = container_of(led_cdev, struct mt76_phy, leds.cdev); 233 dev = container_of(mphy->dev, struct mt7996_dev, mt76); 234 235 /* select TX blink mode, 2: only data frames */ 236 mt76_rmw_field(dev, MT_TMAC_TCR0(mphy->band_idx), MT_TMAC_TCR0_TX_BLINK, 2); 237 238 /* enable LED */ 239 mt76_wr(dev, MT_LED_EN(mphy->band_idx), 1); 240 241 /* set LED Tx blink on/off time */ 242 val = FIELD_PREP(MT_LED_TX_BLINK_ON_MASK, delay_on) | 243 FIELD_PREP(MT_LED_TX_BLINK_OFF_MASK, delay_off); 244 mt76_wr(dev, MT_LED_TX_BLINK(mphy->band_idx), val); 245 246 /* turn LED off */ 247 if (delay_off == 0xff && delay_on == 0x0) { 248 val = MT_LED_CTRL_POLARITY | MT_LED_CTRL_KICK; 249 } else { 250 /* control LED */ 251 val = MT_LED_CTRL_BLINK_MODE | MT_LED_CTRL_KICK; 252 if (mphy->band_idx == MT_BAND1) 253 val |= MT_LED_CTRL_BLINK_BAND_SEL; 254 } 255 256 if (mphy->leds.al) 257 val |= MT_LED_CTRL_POLARITY; 258 259 mt76_wr(dev, MT_LED_CTRL(mphy->band_idx), val); 260 mt76_clear(dev, MT_LED_CTRL(mphy->band_idx), MT_LED_CTRL_KICK); 261 } 262 263 static int mt7996_led_set_blink(struct led_classdev *led_cdev, 264 unsigned long *delay_on, 265 unsigned long *delay_off) 266 { 267 u16 delta_on = 0, delta_off = 0; 268 269 #define HW_TICK 10 270 #define TO_HW_TICK(_t) (((_t) > HW_TICK) ? ((_t) / HW_TICK) : HW_TICK) 271 272 if (*delay_on) 273 delta_on = TO_HW_TICK(*delay_on); 274 if (*delay_off) 275 delta_off = TO_HW_TICK(*delay_off); 276 277 mt7996_led_set_config(led_cdev, delta_on, delta_off); 278 279 return 0; 280 } 281 282 static void mt7996_led_set_brightness(struct led_classdev *led_cdev, 283 enum led_brightness brightness) 284 { 285 if (!brightness) 286 mt7996_led_set_config(led_cdev, 0, 0xff); 287 else 288 mt7996_led_set_config(led_cdev, 0xff, 0); 289 } 290 291 static void __mt7996_init_txpower(struct mt7996_phy *phy, 292 struct ieee80211_supported_band *sband) 293 { 294 struct mt7996_dev *dev = phy->dev; 295 int i, nss = hweight16(phy->mt76->chainmask); 296 int nss_delta = mt76_tx_power_nss_delta(nss); 297 int pwr_delta = mt7996_eeprom_get_power_delta(dev, sband->band); 298 struct mt76_power_limits limits; 299 300 for (i = 0; i < sband->n_channels; i++) { 301 struct ieee80211_channel *chan = &sband->channels[i]; 302 int target_power = mt7996_eeprom_get_target_power(dev, chan); 303 304 target_power += pwr_delta; 305 target_power = mt76_get_rate_power_limits(phy->mt76, chan, 306 &limits, 307 target_power); 308 target_power += nss_delta; 309 target_power = DIV_ROUND_UP(target_power, 2); 310 chan->max_power = min_t(int, chan->max_reg_power, 311 target_power); 312 chan->orig_mpwr = target_power; 313 } 314 } 315 316 void mt7996_init_txpower(struct mt7996_phy *phy) 317 { 318 if (!phy) 319 return; 320 321 if (phy->mt76->cap.has_2ghz) 322 __mt7996_init_txpower(phy, &phy->mt76->sband_2g.sband); 323 if (phy->mt76->cap.has_5ghz) 324 __mt7996_init_txpower(phy, &phy->mt76->sband_5g.sband); 325 if (phy->mt76->cap.has_6ghz) 326 __mt7996_init_txpower(phy, &phy->mt76->sband_6g.sband); 327 } 328 329 static void 330 mt7996_regd_notifier(struct wiphy *wiphy, 331 struct regulatory_request *request) 332 { 333 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 334 struct mt7996_dev *dev = mt7996_hw_dev(hw); 335 struct mt7996_phy *phy = mt7996_hw_phy(hw); 336 337 memcpy(dev->mt76.alpha2, request->alpha2, sizeof(dev->mt76.alpha2)); 338 dev->mt76.region = request->dfs_region; 339 340 if (dev->mt76.region == NL80211_DFS_UNSET) 341 mt7996_mcu_rdd_background_enable(phy, NULL); 342 343 mt7996_init_txpower(phy); 344 345 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN; 346 mt7996_dfs_init_radar_detector(phy); 347 } 348 349 static void 350 mt7996_init_wiphy(struct ieee80211_hw *hw, struct mtk_wed_device *wed) 351 { 352 struct mt7996_phy *phy = mt7996_hw_phy(hw); 353 struct mt76_dev *mdev = &phy->dev->mt76; 354 struct wiphy *wiphy = hw->wiphy; 355 u16 max_subframes = phy->dev->has_eht ? IEEE80211_MAX_AMPDU_BUF_EHT : 356 IEEE80211_MAX_AMPDU_BUF_HE; 357 358 hw->queues = 4; 359 hw->max_rx_aggregation_subframes = max_subframes; 360 hw->max_tx_aggregation_subframes = max_subframes; 361 hw->netdev_features = NETIF_F_RXCSUM; 362 if (mtk_wed_device_active(wed)) 363 hw->netdev_features |= NETIF_F_HW_TC; 364 365 hw->radiotap_timestamp.units_pos = 366 IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US; 367 368 phy->slottime = 9; 369 phy->beacon_rate = -1; 370 371 hw->sta_data_size = sizeof(struct mt7996_sta); 372 hw->vif_data_size = sizeof(struct mt7996_vif); 373 374 wiphy->iface_combinations = if_comb; 375 wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); 376 wiphy->reg_notifier = mt7996_regd_notifier; 377 wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; 378 wiphy->mbssid_max_interfaces = 16; 379 380 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR); 381 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS); 382 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_LEGACY); 383 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HT); 384 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_VHT); 385 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HE); 386 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP); 387 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_FILS_DISCOVERY); 388 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT); 389 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 390 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_MU_MIMO_AIR_SNIFFER); 391 392 if (!mdev->dev->of_node || 393 !of_property_read_bool(mdev->dev->of_node, 394 "mediatek,disable-radar-background")) 395 wiphy_ext_feature_set(wiphy, 396 NL80211_EXT_FEATURE_RADAR_BACKGROUND); 397 398 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 399 ieee80211_hw_set(hw, SUPPORTS_TX_ENCAP_OFFLOAD); 400 ieee80211_hw_set(hw, SUPPORTS_RX_DECAP_OFFLOAD); 401 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 402 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 403 404 hw->max_tx_fragments = 4; 405 406 if (phy->mt76->cap.has_2ghz) { 407 phy->mt76->sband_2g.sband.ht_cap.cap |= 408 IEEE80211_HT_CAP_LDPC_CODING | 409 IEEE80211_HT_CAP_MAX_AMSDU; 410 phy->mt76->sband_2g.sband.ht_cap.ampdu_density = 411 IEEE80211_HT_MPDU_DENSITY_2; 412 } 413 414 if (phy->mt76->cap.has_5ghz) { 415 phy->mt76->sband_5g.sband.ht_cap.cap |= 416 IEEE80211_HT_CAP_LDPC_CODING | 417 IEEE80211_HT_CAP_MAX_AMSDU; 418 419 phy->mt76->sband_5g.sband.vht_cap.cap |= 420 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 421 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 422 IEEE80211_VHT_CAP_SHORT_GI_160 | 423 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ; 424 phy->mt76->sband_5g.sband.ht_cap.ampdu_density = 425 IEEE80211_HT_MPDU_DENSITY_1; 426 427 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 428 } 429 430 /* init led callbacks */ 431 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 432 phy->mt76->leds.cdev.brightness_set = mt7996_led_set_brightness; 433 phy->mt76->leds.cdev.blink_set = mt7996_led_set_blink; 434 } 435 436 mt76_set_stream_caps(phy->mt76, true); 437 mt7996_set_stream_vht_txbf_caps(phy); 438 mt7996_set_stream_he_eht_caps(phy); 439 mt7996_init_txpower(phy); 440 441 wiphy->available_antennas_rx = phy->mt76->antenna_mask; 442 wiphy->available_antennas_tx = phy->mt76->antenna_mask; 443 } 444 445 static void 446 mt7996_mac_init_band(struct mt7996_dev *dev, u8 band) 447 { 448 u32 mask, set; 449 450 /* clear estimated value of EIFS for Rx duration & OBSS time */ 451 mt76_wr(dev, MT_WF_RMAC_RSVD0(band), MT_WF_RMAC_RSVD0_EIFS_CLR); 452 453 /* clear backoff time for Rx duration */ 454 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME1(band), 455 MT_WF_RMAC_MIB_NONQOSD_BACKOFF); 456 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME3(band), 457 MT_WF_RMAC_MIB_QOS01_BACKOFF); 458 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME4(band), 459 MT_WF_RMAC_MIB_QOS23_BACKOFF); 460 461 /* clear backoff time and set software compensation for OBSS time */ 462 mask = MT_WF_RMAC_MIB_OBSS_BACKOFF | MT_WF_RMAC_MIB_ED_OFFSET; 463 set = FIELD_PREP(MT_WF_RMAC_MIB_OBSS_BACKOFF, 0) | 464 FIELD_PREP(MT_WF_RMAC_MIB_ED_OFFSET, 4); 465 mt76_rmw(dev, MT_WF_RMAC_MIB_AIRTIME0(band), mask, set); 466 467 /* filter out non-resp frames and get instanstaeous signal reporting */ 468 mask = MT_WTBLOFF_RSCR_RCPI_MODE | MT_WTBLOFF_RSCR_RCPI_PARAM; 469 set = FIELD_PREP(MT_WTBLOFF_RSCR_RCPI_MODE, 0) | 470 FIELD_PREP(MT_WTBLOFF_RSCR_RCPI_PARAM, 0x3); 471 mt76_rmw(dev, MT_WTBLOFF_RSCR(band), mask, set); 472 473 /* MT_TXD5_TX_STATUS_HOST (MPDU format) has higher priority than 474 * MT_AGG_ACR_PPDU_TXS2H (PPDU format) even though ACR bit is set. 475 */ 476 mt76_set(dev, MT_AGG_ACR4(band), MT_AGG_ACR_PPDU_TXS2H); 477 } 478 479 static void mt7996_mac_init_basic_rates(struct mt7996_dev *dev) 480 { 481 int i; 482 483 for (i = 0; i < ARRAY_SIZE(mt76_rates); i++) { 484 u16 rate = mt76_rates[i].hw_value; 485 /* odd index for driver, even index for firmware */ 486 u16 idx = MT7996_BASIC_RATES_TBL + 2 * i; 487 488 rate = FIELD_PREP(MT_TX_RATE_MODE, rate >> 8) | 489 FIELD_PREP(MT_TX_RATE_IDX, rate & GENMASK(7, 0)); 490 mt7996_mcu_set_fixed_rate_table(&dev->phy, idx, rate, false); 491 } 492 } 493 494 void mt7996_mac_init(struct mt7996_dev *dev) 495 { 496 #define HIF_TXD_V2_1 4 497 int i; 498 499 mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT); 500 501 for (i = 0; i < mt7996_wtbl_size(dev); i++) 502 mt7996_mac_wtbl_update(dev, i, 503 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 504 505 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 506 i = dev->mphy.leds.pin ? MT_LED_GPIO_MUX3 : MT_LED_GPIO_MUX2; 507 mt76_rmw_field(dev, i, MT_LED_GPIO_SEL_MASK, 4); 508 } 509 510 /* txs report queue */ 511 mt76_rmw_field(dev, MT_DMA_TCRF1(0), MT_DMA_TCRF1_QIDX, 0); 512 mt76_rmw_field(dev, MT_DMA_TCRF1(1), MT_DMA_TCRF1_QIDX, 6); 513 mt76_rmw_field(dev, MT_DMA_TCRF1(2), MT_DMA_TCRF1_QIDX, 0); 514 515 /* rro module init */ 516 if (is_mt7996(&dev->mt76)) 517 mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 2); 518 else 519 mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 520 dev->hif2 ? 7 : 0); 521 522 if (dev->has_rro) { 523 u16 timeout; 524 525 timeout = mt76_rr(dev, MT_HW_REV) == MT_HW_REV1 ? 512 : 128; 526 mt7996_mcu_set_rro(dev, UNI_RRO_SET_FLUSH_TIMEOUT, timeout); 527 mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 1); 528 mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 0); 529 } else { 530 mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 3); 531 mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 1); 532 } 533 534 mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), 535 MCU_WA_PARAM_HW_PATH_HIF_VER, 536 HIF_TXD_V2_1, 0); 537 538 for (i = MT_BAND0; i <= MT_BAND2; i++) 539 mt7996_mac_init_band(dev, i); 540 541 mt7996_mac_init_basic_rates(dev); 542 } 543 544 int mt7996_txbf_init(struct mt7996_dev *dev) 545 { 546 int ret; 547 548 if (mt7996_band_valid(dev, MT_BAND1) || 549 mt7996_band_valid(dev, MT_BAND2)) { 550 ret = mt7996_mcu_set_txbf(dev, BF_MOD_EN_CTRL); 551 if (ret) 552 return ret; 553 } 554 555 /* trigger sounding packets */ 556 ret = mt7996_mcu_set_txbf(dev, BF_SOUNDING_ON); 557 if (ret) 558 return ret; 559 560 /* enable eBF */ 561 return mt7996_mcu_set_txbf(dev, BF_HW_EN_UPDATE); 562 } 563 564 static int mt7996_register_phy(struct mt7996_dev *dev, struct mt7996_phy *phy, 565 enum mt76_band_id band) 566 { 567 struct mt76_phy *mphy; 568 u32 mac_ofs, hif1_ofs = 0; 569 int ret; 570 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 571 572 if (!mt7996_band_valid(dev, band) || band == MT_BAND0) 573 return 0; 574 575 if (phy) 576 return 0; 577 578 if (is_mt7996(&dev->mt76) && band == MT_BAND2 && dev->hif2) { 579 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); 580 wed = &dev->mt76.mmio.wed_hif2; 581 } 582 583 mphy = mt76_alloc_phy(&dev->mt76, sizeof(*phy), &mt7996_ops, band); 584 if (!mphy) 585 return -ENOMEM; 586 587 phy = mphy->priv; 588 phy->dev = dev; 589 phy->mt76 = mphy; 590 mphy->dev->phys[band] = mphy; 591 592 INIT_DELAYED_WORK(&mphy->mac_work, mt7996_mac_work); 593 594 ret = mt7996_eeprom_parse_hw_cap(dev, phy); 595 if (ret) 596 goto error; 597 598 mac_ofs = band == MT_BAND2 ? MT_EE_MAC_ADDR3 : MT_EE_MAC_ADDR2; 599 memcpy(mphy->macaddr, dev->mt76.eeprom.data + mac_ofs, ETH_ALEN); 600 /* Make the extra PHY MAC address local without overlapping with 601 * the usual MAC address allocation scheme on multiple virtual interfaces 602 */ 603 if (!is_valid_ether_addr(mphy->macaddr)) { 604 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR, 605 ETH_ALEN); 606 mphy->macaddr[0] |= 2; 607 mphy->macaddr[0] ^= BIT(7); 608 if (band == MT_BAND2) 609 mphy->macaddr[0] ^= BIT(6); 610 } 611 mt76_eeprom_override(mphy); 612 613 /* init wiphy according to mphy and phy */ 614 mt7996_init_wiphy(mphy->hw, wed); 615 ret = mt7996_init_tx_queues(mphy->priv, 616 MT_TXQ_ID(band), 617 MT7996_TX_RING_SIZE, 618 MT_TXQ_RING_BASE(band) + hif1_ofs, 619 wed); 620 if (ret) 621 goto error; 622 623 ret = mt76_register_phy(mphy, true, mt76_rates, 624 ARRAY_SIZE(mt76_rates)); 625 if (ret) 626 goto error; 627 628 ret = mt7996_thermal_init(phy); 629 if (ret) 630 goto error; 631 632 ret = mt7996_init_debugfs(phy); 633 if (ret) 634 goto error; 635 636 if (wed == &dev->mt76.mmio.wed_hif2 && mtk_wed_device_active(wed)) { 637 u32 irq_mask = dev->mt76.mmio.irqmask | MT_INT_TX_DONE_BAND2; 638 639 mt76_wr(dev, MT_INT1_MASK_CSR, irq_mask); 640 mtk_wed_device_start(&dev->mt76.mmio.wed_hif2, irq_mask); 641 } 642 643 return 0; 644 645 error: 646 mphy->dev->phys[band] = NULL; 647 ieee80211_free_hw(mphy->hw); 648 return ret; 649 } 650 651 static void 652 mt7996_unregister_phy(struct mt7996_phy *phy, enum mt76_band_id band) 653 { 654 struct mt76_phy *mphy; 655 656 if (!phy) 657 return; 658 659 mt7996_unregister_thermal(phy); 660 661 mphy = phy->dev->mt76.phys[band]; 662 mt76_unregister_phy(mphy); 663 ieee80211_free_hw(mphy->hw); 664 phy->dev->mt76.phys[band] = NULL; 665 } 666 667 static void mt7996_init_work(struct work_struct *work) 668 { 669 struct mt7996_dev *dev = container_of(work, struct mt7996_dev, 670 init_work); 671 672 mt7996_mcu_set_eeprom(dev); 673 mt7996_mac_init(dev); 674 mt7996_txbf_init(dev); 675 } 676 677 void mt7996_wfsys_reset(struct mt7996_dev *dev) 678 { 679 mt76_set(dev, MT_WF_SUBSYS_RST, 0x1); 680 msleep(20); 681 682 mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1); 683 msleep(20); 684 } 685 686 static int mt7996_wed_rro_init(struct mt7996_dev *dev) 687 { 688 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 689 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 690 u32 reg = MT_RRO_ADDR_ELEM_SEG_ADDR0; 691 struct mt7996_wed_rro_addr *addr; 692 void *ptr; 693 int i; 694 695 if (!dev->has_rro) 696 return 0; 697 698 if (!mtk_wed_device_active(wed)) 699 return 0; 700 701 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.ba_bitmap); i++) { 702 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 703 MT7996_RRO_BA_BITMAP_CR_SIZE, 704 &dev->wed_rro.ba_bitmap[i].phy_addr, 705 GFP_KERNEL); 706 if (!ptr) 707 return -ENOMEM; 708 709 dev->wed_rro.ba_bitmap[i].ptr = ptr; 710 } 711 712 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) { 713 int j; 714 715 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 716 MT7996_RRO_WINDOW_MAX_SIZE * sizeof(*addr), 717 &dev->wed_rro.addr_elem[i].phy_addr, 718 GFP_KERNEL); 719 if (!ptr) 720 return -ENOMEM; 721 722 dev->wed_rro.addr_elem[i].ptr = ptr; 723 memset(dev->wed_rro.addr_elem[i].ptr, 0, 724 MT7996_RRO_WINDOW_MAX_SIZE * sizeof(*addr)); 725 726 addr = dev->wed_rro.addr_elem[i].ptr; 727 for (j = 0; j < MT7996_RRO_WINDOW_MAX_SIZE; j++) { 728 addr->signature = 0xff; 729 addr++; 730 } 731 732 wed->wlan.ind_cmd.addr_elem_phys[i] = 733 dev->wed_rro.addr_elem[i].phy_addr; 734 } 735 736 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 737 MT7996_RRO_WINDOW_MAX_LEN * sizeof(*addr), 738 &dev->wed_rro.session.phy_addr, 739 GFP_KERNEL); 740 if (!ptr) 741 return -ENOMEM; 742 743 dev->wed_rro.session.ptr = ptr; 744 addr = dev->wed_rro.session.ptr; 745 for (i = 0; i < MT7996_RRO_WINDOW_MAX_LEN; i++) { 746 addr->signature = 0xff; 747 addr++; 748 } 749 750 /* rro hw init */ 751 /* TODO: remove line after WM has set */ 752 mt76_clear(dev, WF_RRO_AXI_MST_CFG, WF_RRO_AXI_MST_CFG_DIDX_OK); 753 754 /* setup BA bitmap cache address */ 755 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE0, 756 dev->wed_rro.ba_bitmap[0].phy_addr); 757 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE1, 0); 758 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE_EXT0, 759 dev->wed_rro.ba_bitmap[1].phy_addr); 760 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE_EXT1, 0); 761 762 /* setup Address element address */ 763 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) { 764 mt76_wr(dev, reg, dev->wed_rro.addr_elem[i].phy_addr >> 4); 765 reg += 4; 766 } 767 768 /* setup Address element address - separate address segment mode */ 769 mt76_wr(dev, MT_RRO_ADDR_ARRAY_BASE1, 770 MT_RRO_ADDR_ARRAY_ELEM_ADDR_SEG_MODE); 771 772 wed->wlan.ind_cmd.win_size = ffs(MT7996_RRO_WINDOW_MAX_LEN) - 6; 773 wed->wlan.ind_cmd.particular_sid = MT7996_RRO_MAX_SESSION; 774 wed->wlan.ind_cmd.particular_se_phys = dev->wed_rro.session.phy_addr; 775 wed->wlan.ind_cmd.se_group_nums = MT7996_RRO_ADDR_ELEM_LEN; 776 wed->wlan.ind_cmd.ack_sn_addr = MT_RRO_ACK_SN_CTRL; 777 778 mt76_wr(dev, MT_RRO_IND_CMD_SIGNATURE_BASE0, 0x15010e00); 779 mt76_set(dev, MT_RRO_IND_CMD_SIGNATURE_BASE1, 780 MT_RRO_IND_CMD_SIGNATURE_BASE1_EN); 781 782 /* particular session configure */ 783 /* use max session idx + 1 as particular session id */ 784 mt76_wr(dev, MT_RRO_PARTICULAR_CFG0, dev->wed_rro.session.phy_addr); 785 mt76_wr(dev, MT_RRO_PARTICULAR_CFG1, 786 MT_RRO_PARTICULAR_CONFG_EN | 787 FIELD_PREP(MT_RRO_PARTICULAR_SID, MT7996_RRO_MAX_SESSION)); 788 789 /* interrupt enable */ 790 mt76_wr(dev, MT_RRO_HOST_INT_ENA, 791 MT_RRO_HOST_INT_ENA_HOST_RRO_DONE_ENA); 792 793 /* rro ind cmd queue init */ 794 return mt7996_dma_rro_init(dev); 795 #else 796 return 0; 797 #endif 798 } 799 800 static void mt7996_wed_rro_free(struct mt7996_dev *dev) 801 { 802 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 803 int i; 804 805 if (!dev->has_rro) 806 return; 807 808 if (!mtk_wed_device_active(&dev->mt76.mmio.wed)) 809 return; 810 811 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.ba_bitmap); i++) { 812 if (!dev->wed_rro.ba_bitmap[i].ptr) 813 continue; 814 815 dmam_free_coherent(dev->mt76.dma_dev, 816 MT7996_RRO_BA_BITMAP_CR_SIZE, 817 dev->wed_rro.ba_bitmap[i].ptr, 818 dev->wed_rro.ba_bitmap[i].phy_addr); 819 } 820 821 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) { 822 if (!dev->wed_rro.addr_elem[i].ptr) 823 continue; 824 825 dmam_free_coherent(dev->mt76.dma_dev, 826 MT7996_RRO_WINDOW_MAX_SIZE * 827 sizeof(struct mt7996_wed_rro_addr), 828 dev->wed_rro.addr_elem[i].ptr, 829 dev->wed_rro.addr_elem[i].phy_addr); 830 } 831 832 if (!dev->wed_rro.session.ptr) 833 return; 834 835 dmam_free_coherent(dev->mt76.dma_dev, 836 MT7996_RRO_WINDOW_MAX_LEN * 837 sizeof(struct mt7996_wed_rro_addr), 838 dev->wed_rro.session.ptr, 839 dev->wed_rro.session.phy_addr); 840 #endif 841 } 842 843 static void mt7996_wed_rro_work(struct work_struct *work) 844 { 845 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 846 struct mt7996_dev *dev; 847 LIST_HEAD(list); 848 849 dev = (struct mt7996_dev *)container_of(work, struct mt7996_dev, 850 wed_rro.work); 851 852 spin_lock_bh(&dev->wed_rro.lock); 853 list_splice_init(&dev->wed_rro.poll_list, &list); 854 spin_unlock_bh(&dev->wed_rro.lock); 855 856 while (!list_empty(&list)) { 857 struct mt7996_wed_rro_session_id *e; 858 int i; 859 860 e = list_first_entry(&list, struct mt7996_wed_rro_session_id, 861 list); 862 list_del_init(&e->list); 863 864 for (i = 0; i < MT7996_RRO_WINDOW_MAX_LEN; i++) { 865 void *ptr = dev->wed_rro.session.ptr; 866 struct mt7996_wed_rro_addr *elem; 867 u32 idx, elem_id = i; 868 869 if (e->id == MT7996_RRO_MAX_SESSION) 870 goto reset; 871 872 idx = e->id / MT7996_RRO_BA_BITMAP_SESSION_SIZE; 873 if (idx >= ARRAY_SIZE(dev->wed_rro.addr_elem)) 874 goto out; 875 876 ptr = dev->wed_rro.addr_elem[idx].ptr; 877 elem_id += 878 (e->id % MT7996_RRO_BA_BITMAP_SESSION_SIZE) * 879 MT7996_RRO_WINDOW_MAX_LEN; 880 reset: 881 elem = ptr + elem_id * sizeof(*elem); 882 elem->signature = 0xff; 883 } 884 mt7996_mcu_wed_rro_reset_sessions(dev, e->id); 885 out: 886 kfree(e); 887 } 888 #endif 889 } 890 891 static int mt7996_init_hardware(struct mt7996_dev *dev) 892 { 893 int ret, idx; 894 895 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 896 if (is_mt7992(&dev->mt76)) { 897 mt76_rmw(dev, MT_AFE_CTL_BAND_PLL_03(MT_BAND0), MT_AFE_CTL_BAND_PLL_03_MSB_EN, 0); 898 mt76_rmw(dev, MT_AFE_CTL_BAND_PLL_03(MT_BAND1), MT_AFE_CTL_BAND_PLL_03_MSB_EN, 0); 899 } 900 901 INIT_WORK(&dev->init_work, mt7996_init_work); 902 INIT_WORK(&dev->wed_rro.work, mt7996_wed_rro_work); 903 INIT_LIST_HEAD(&dev->wed_rro.poll_list); 904 spin_lock_init(&dev->wed_rro.lock); 905 906 ret = mt7996_dma_init(dev); 907 if (ret) 908 return ret; 909 910 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state); 911 912 ret = mt7996_mcu_init(dev); 913 if (ret) 914 return ret; 915 916 ret = mt7996_wed_rro_init(dev); 917 if (ret) 918 return ret; 919 920 ret = mt7996_eeprom_init(dev); 921 if (ret < 0) 922 return ret; 923 924 /* Beacon and mgmt frames should occupy wcid 0 */ 925 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7996_WTBL_STA); 926 if (idx) 927 return -ENOSPC; 928 929 dev->mt76.global_wcid.idx = idx; 930 dev->mt76.global_wcid.hw_key_idx = -1; 931 dev->mt76.global_wcid.tx_info |= MT_WCID_TX_INFO_SET; 932 rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid); 933 934 return 0; 935 } 936 937 void mt7996_set_stream_vht_txbf_caps(struct mt7996_phy *phy) 938 { 939 int sts; 940 u32 *cap; 941 942 if (!phy->mt76->cap.has_5ghz) 943 return; 944 945 sts = hweight16(phy->mt76->chainmask); 946 cap = &phy->mt76->sband_5g.sband.vht_cap.cap; 947 948 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | 949 IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 950 FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, sts - 1); 951 952 *cap &= ~(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK | 953 IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 954 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE); 955 956 if (sts < 2) 957 return; 958 959 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 960 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE | 961 FIELD_PREP(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, sts - 1); 962 } 963 964 static void 965 mt7996_set_stream_he_txbf_caps(struct mt7996_phy *phy, 966 struct ieee80211_sta_he_cap *he_cap, int vif) 967 { 968 struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem; 969 int sts = hweight16(phy->mt76->chainmask); 970 u8 c; 971 972 #ifdef CONFIG_MAC80211_MESH 973 if (vif == NL80211_IFTYPE_MESH_POINT) 974 return; 975 #endif 976 977 elem->phy_cap_info[3] &= ~IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 978 elem->phy_cap_info[4] &= ~IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 979 980 c = IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK | 981 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK; 982 elem->phy_cap_info[5] &= ~c; 983 984 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 985 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 986 elem->phy_cap_info[6] &= ~c; 987 988 elem->phy_cap_info[7] &= ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK; 989 990 c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 991 IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO | 992 IEEE80211_HE_PHY_CAP2_UL_MU_PARTIAL_MU_MIMO; 993 elem->phy_cap_info[2] |= c; 994 995 c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 996 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4 | 997 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 998 elem->phy_cap_info[4] |= c; 999 1000 /* do not support NG16 due to spec D4.0 changes subcarrier idx */ 1001 c = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 1002 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU; 1003 1004 if (vif == NL80211_IFTYPE_STATION) 1005 c |= IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO; 1006 1007 elem->phy_cap_info[6] |= c; 1008 1009 if (sts < 2) 1010 return; 1011 1012 /* the maximum cap is 4 x 3, (Nr, Nc) = (3, 2) */ 1013 elem->phy_cap_info[7] |= min_t(int, sts - 1, 2) << 3; 1014 1015 if (vif != NL80211_IFTYPE_AP) 1016 return; 1017 1018 elem->phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 1019 elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 1020 1021 c = FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 1022 sts - 1) | 1023 FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK, 1024 sts - 1); 1025 elem->phy_cap_info[5] |= c; 1026 1027 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 1028 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 1029 elem->phy_cap_info[6] |= c; 1030 1031 c = IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ | 1032 IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ; 1033 elem->phy_cap_info[7] |= c; 1034 } 1035 1036 static void 1037 mt7996_init_he_caps(struct mt7996_phy *phy, enum nl80211_band band, 1038 struct ieee80211_sband_iftype_data *data, 1039 enum nl80211_iftype iftype) 1040 { 1041 struct ieee80211_sta_he_cap *he_cap = &data->he_cap; 1042 struct ieee80211_he_cap_elem *he_cap_elem = &he_cap->he_cap_elem; 1043 struct ieee80211_he_mcs_nss_supp *he_mcs = &he_cap->he_mcs_nss_supp; 1044 int i, nss = hweight8(phy->mt76->antenna_mask); 1045 u16 mcs_map = 0; 1046 1047 for (i = 0; i < 8; i++) { 1048 if (i < nss) 1049 mcs_map |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 1050 else 1051 mcs_map |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 1052 } 1053 1054 he_cap->has_he = true; 1055 1056 he_cap_elem->mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE; 1057 he_cap_elem->mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 1058 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3; 1059 he_cap_elem->mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 1060 1061 if (band == NL80211_BAND_2GHZ) 1062 he_cap_elem->phy_cap_info[0] = 1063 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 1064 else 1065 he_cap_elem->phy_cap_info[0] = 1066 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 1067 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 1068 1069 he_cap_elem->phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD; 1070 he_cap_elem->phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 1071 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ; 1072 1073 switch (iftype) { 1074 case NL80211_IFTYPE_AP: 1075 he_cap_elem->mac_cap_info[0] |= IEEE80211_HE_MAC_CAP0_TWT_RES; 1076 he_cap_elem->mac_cap_info[2] |= IEEE80211_HE_MAC_CAP2_BSR; 1077 he_cap_elem->mac_cap_info[4] |= IEEE80211_HE_MAC_CAP4_BQR; 1078 he_cap_elem->mac_cap_info[5] |= 1079 IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX; 1080 he_cap_elem->phy_cap_info[3] |= 1081 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1082 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1083 he_cap_elem->phy_cap_info[6] |= 1084 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1085 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1086 he_cap_elem->phy_cap_info[9] |= 1087 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1088 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU; 1089 break; 1090 case NL80211_IFTYPE_STATION: 1091 he_cap_elem->mac_cap_info[1] |= 1092 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 1093 1094 if (band == NL80211_BAND_2GHZ) 1095 he_cap_elem->phy_cap_info[0] |= 1096 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G; 1097 else 1098 he_cap_elem->phy_cap_info[0] |= 1099 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G; 1100 1101 he_cap_elem->phy_cap_info[1] |= 1102 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 1103 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 1104 he_cap_elem->phy_cap_info[3] |= 1105 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1106 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1107 he_cap_elem->phy_cap_info[6] |= 1108 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB | 1109 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1110 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1111 he_cap_elem->phy_cap_info[7] |= 1112 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 1113 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI; 1114 he_cap_elem->phy_cap_info[8] |= 1115 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 1116 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 1117 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU | 1118 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_484; 1119 he_cap_elem->phy_cap_info[9] |= 1120 IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 1121 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK | 1122 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1123 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 1124 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 1125 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB; 1126 break; 1127 default: 1128 break; 1129 } 1130 1131 he_mcs->rx_mcs_80 = cpu_to_le16(mcs_map); 1132 he_mcs->tx_mcs_80 = cpu_to_le16(mcs_map); 1133 he_mcs->rx_mcs_160 = cpu_to_le16(mcs_map); 1134 he_mcs->tx_mcs_160 = cpu_to_le16(mcs_map); 1135 1136 mt7996_set_stream_he_txbf_caps(phy, he_cap, iftype); 1137 1138 memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres)); 1139 if (he_cap_elem->phy_cap_info[6] & 1140 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) { 1141 mt76_connac_gen_ppe_thresh(he_cap->ppe_thres, nss); 1142 } else { 1143 he_cap_elem->phy_cap_info[9] |= 1144 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 1145 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 1146 } 1147 1148 if (band == NL80211_BAND_6GHZ) { 1149 u16 cap = IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS | 1150 IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS; 1151 1152 cap |= u16_encode_bits(IEEE80211_HT_MPDU_DENSITY_0_5, 1153 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 1154 u16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 1155 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 1156 u16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 1157 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 1158 1159 data->he_6ghz_capa.capa = cpu_to_le16(cap); 1160 } 1161 } 1162 1163 static void 1164 mt7996_init_eht_caps(struct mt7996_phy *phy, enum nl80211_band band, 1165 struct ieee80211_sband_iftype_data *data, 1166 enum nl80211_iftype iftype) 1167 { 1168 struct ieee80211_sta_eht_cap *eht_cap = &data->eht_cap; 1169 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem = &eht_cap->eht_cap_elem; 1170 struct ieee80211_eht_mcs_nss_supp *eht_nss = &eht_cap->eht_mcs_nss_supp; 1171 enum nl80211_chan_width width = phy->mt76->chandef.width; 1172 int nss = hweight8(phy->mt76->antenna_mask); 1173 int sts = hweight16(phy->mt76->chainmask); 1174 u8 val; 1175 1176 if (!phy->dev->has_eht) 1177 return; 1178 1179 eht_cap->has_eht = true; 1180 1181 eht_cap_elem->mac_cap_info[0] = 1182 IEEE80211_EHT_MAC_CAP0_EPCS_PRIO_ACCESS | 1183 IEEE80211_EHT_MAC_CAP0_OM_CONTROL; 1184 1185 eht_cap_elem->phy_cap_info[0] = 1186 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ | 1187 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI | 1188 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMER | 1189 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE; 1190 1191 val = max_t(u8, sts - 1, 3); 1192 eht_cap_elem->phy_cap_info[0] |= 1193 u8_encode_bits(u8_get_bits(val, BIT(0)), 1194 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK); 1195 1196 eht_cap_elem->phy_cap_info[1] = 1197 u8_encode_bits(u8_get_bits(val, GENMASK(2, 1)), 1198 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK) | 1199 u8_encode_bits(val, 1200 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK) | 1201 u8_encode_bits(val, 1202 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK); 1203 1204 eht_cap_elem->phy_cap_info[2] = 1205 u8_encode_bits(sts - 1, IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_80MHZ_MASK) | 1206 u8_encode_bits(sts - 1, IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_160MHZ_MASK) | 1207 u8_encode_bits(sts - 1, IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_320MHZ_MASK); 1208 1209 eht_cap_elem->phy_cap_info[3] = 1210 IEEE80211_EHT_PHY_CAP3_NG_16_SU_FEEDBACK | 1211 IEEE80211_EHT_PHY_CAP3_NG_16_MU_FEEDBACK | 1212 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK | 1213 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK | 1214 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK | 1215 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK | 1216 IEEE80211_EHT_PHY_CAP3_TRIG_CQI_FDBK; 1217 1218 eht_cap_elem->phy_cap_info[4] = 1219 u8_encode_bits(min_t(int, sts - 1, 2), 1220 IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK); 1221 1222 eht_cap_elem->phy_cap_info[5] = 1223 IEEE80211_EHT_PHY_CAP5_NON_TRIG_CQI_FEEDBACK | 1224 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_16US, 1225 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK) | 1226 u8_encode_bits(u8_get_bits(0x11, GENMASK(1, 0)), 1227 IEEE80211_EHT_PHY_CAP5_MAX_NUM_SUPP_EHT_LTF_MASK); 1228 1229 val = width == NL80211_CHAN_WIDTH_320 ? 0xf : 1230 width == NL80211_CHAN_WIDTH_160 ? 0x7 : 1231 width == NL80211_CHAN_WIDTH_80 ? 0x3 : 0x1; 1232 eht_cap_elem->phy_cap_info[6] = 1233 u8_encode_bits(u8_get_bits(0x11, GENMASK(4, 2)), 1234 IEEE80211_EHT_PHY_CAP6_MAX_NUM_SUPP_EHT_LTF_MASK) | 1235 u8_encode_bits(val, IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_MASK); 1236 1237 eht_cap_elem->phy_cap_info[7] = 1238 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_80MHZ | 1239 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_160MHZ | 1240 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_320MHZ | 1241 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_80MHZ | 1242 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_160MHZ | 1243 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_320MHZ; 1244 1245 val = u8_encode_bits(nss, IEEE80211_EHT_MCS_NSS_RX) | 1246 u8_encode_bits(nss, IEEE80211_EHT_MCS_NSS_TX); 1247 #define SET_EHT_MAX_NSS(_bw, _val) do { \ 1248 eht_nss->bw._##_bw.rx_tx_mcs9_max_nss = _val; \ 1249 eht_nss->bw._##_bw.rx_tx_mcs11_max_nss = _val; \ 1250 eht_nss->bw._##_bw.rx_tx_mcs13_max_nss = _val; \ 1251 } while (0) 1252 1253 SET_EHT_MAX_NSS(80, val); 1254 SET_EHT_MAX_NSS(160, val); 1255 SET_EHT_MAX_NSS(320, val); 1256 #undef SET_EHT_MAX_NSS 1257 } 1258 1259 static void 1260 __mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy, 1261 struct ieee80211_supported_band *sband, 1262 enum nl80211_band band) 1263 { 1264 struct ieee80211_sband_iftype_data *data = phy->iftype[band]; 1265 int i, n = 0; 1266 1267 for (i = 0; i < NUM_NL80211_IFTYPES; i++) { 1268 switch (i) { 1269 case NL80211_IFTYPE_STATION: 1270 case NL80211_IFTYPE_AP: 1271 #ifdef CONFIG_MAC80211_MESH 1272 case NL80211_IFTYPE_MESH_POINT: 1273 #endif 1274 break; 1275 default: 1276 continue; 1277 } 1278 1279 data[n].types_mask = BIT(i); 1280 mt7996_init_he_caps(phy, band, &data[n], i); 1281 mt7996_init_eht_caps(phy, band, &data[n], i); 1282 1283 n++; 1284 } 1285 1286 _ieee80211_set_sband_iftype_data(sband, data, n); 1287 } 1288 1289 void mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy) 1290 { 1291 if (phy->mt76->cap.has_2ghz) 1292 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_2g.sband, 1293 NL80211_BAND_2GHZ); 1294 1295 if (phy->mt76->cap.has_5ghz) 1296 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_5g.sband, 1297 NL80211_BAND_5GHZ); 1298 1299 if (phy->mt76->cap.has_6ghz) 1300 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_6g.sband, 1301 NL80211_BAND_6GHZ); 1302 } 1303 1304 int mt7996_register_device(struct mt7996_dev *dev) 1305 { 1306 struct ieee80211_hw *hw = mt76_hw(dev); 1307 int ret; 1308 1309 dev->phy.dev = dev; 1310 dev->phy.mt76 = &dev->mt76.phy; 1311 dev->mt76.phy.priv = &dev->phy; 1312 INIT_WORK(&dev->rc_work, mt7996_mac_sta_rc_work); 1313 INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7996_mac_work); 1314 INIT_LIST_HEAD(&dev->sta_rc_list); 1315 INIT_LIST_HEAD(&dev->twt_list); 1316 1317 init_waitqueue_head(&dev->reset_wait); 1318 INIT_WORK(&dev->reset_work, mt7996_mac_reset_work); 1319 INIT_WORK(&dev->dump_work, mt7996_mac_dump_work); 1320 mutex_init(&dev->dump_mutex); 1321 1322 ret = mt7996_init_hardware(dev); 1323 if (ret) 1324 return ret; 1325 1326 mt7996_init_wiphy(hw, &dev->mt76.mmio.wed); 1327 1328 ret = mt76_register_device(&dev->mt76, true, mt76_rates, 1329 ARRAY_SIZE(mt76_rates)); 1330 if (ret) 1331 return ret; 1332 1333 ret = mt7996_thermal_init(&dev->phy); 1334 if (ret) 1335 return ret; 1336 1337 ret = mt7996_register_phy(dev, mt7996_phy2(dev), MT_BAND1); 1338 if (ret) 1339 return ret; 1340 1341 ret = mt7996_register_phy(dev, mt7996_phy3(dev), MT_BAND2); 1342 if (ret) 1343 return ret; 1344 1345 ieee80211_queue_work(mt76_hw(dev), &dev->init_work); 1346 1347 dev->recovery.hw_init_done = true; 1348 1349 ret = mt7996_init_debugfs(&dev->phy); 1350 if (ret) 1351 goto error; 1352 1353 ret = mt7996_coredump_register(dev); 1354 if (ret) 1355 goto error; 1356 1357 return 0; 1358 1359 error: 1360 cancel_work_sync(&dev->init_work); 1361 1362 return ret; 1363 } 1364 1365 void mt7996_unregister_device(struct mt7996_dev *dev) 1366 { 1367 cancel_work_sync(&dev->wed_rro.work); 1368 mt7996_unregister_phy(mt7996_phy3(dev), MT_BAND2); 1369 mt7996_unregister_phy(mt7996_phy2(dev), MT_BAND1); 1370 mt7996_unregister_thermal(&dev->phy); 1371 mt7996_coredump_unregister(dev); 1372 mt76_unregister_device(&dev->mt76); 1373 mt7996_wed_rro_free(dev); 1374 mt7996_mcu_exit(dev); 1375 mt7996_tx_token_put(dev); 1376 mt7996_dma_cleanup(dev); 1377 tasklet_disable(&dev->mt76.irq_tasklet); 1378 1379 mt76_free_device(&dev->mt76); 1380 } 1381