1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #include <linux/etherdevice.h> 7 #include <linux/of.h> 8 #include <linux/thermal.h> 9 #include "mt7996.h" 10 #include "mac.h" 11 #include "mcu.h" 12 #include "coredump.h" 13 #include "eeprom.h" 14 15 static const struct ieee80211_iface_limit if_limits[] = { 16 { 17 .max = 1, 18 .types = BIT(NL80211_IFTYPE_ADHOC) 19 }, { 20 .max = 16, 21 .types = BIT(NL80211_IFTYPE_AP) 22 #ifdef CONFIG_MAC80211_MESH 23 | BIT(NL80211_IFTYPE_MESH_POINT) 24 #endif 25 }, { 26 .max = MT7996_MAX_INTERFACES, 27 .types = BIT(NL80211_IFTYPE_STATION) 28 } 29 }; 30 31 static const struct ieee80211_iface_combination if_comb[] = { 32 { 33 .limits = if_limits, 34 .n_limits = ARRAY_SIZE(if_limits), 35 .max_interfaces = MT7996_MAX_INTERFACES, 36 .num_different_channels = 1, 37 .beacon_int_infra_match = true, 38 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 39 BIT(NL80211_CHAN_WIDTH_20) | 40 BIT(NL80211_CHAN_WIDTH_40) | 41 BIT(NL80211_CHAN_WIDTH_80) | 42 BIT(NL80211_CHAN_WIDTH_160), 43 } 44 }; 45 46 static void mt7996_led_set_config(struct led_classdev *led_cdev, 47 u8 delay_on, u8 delay_off) 48 { 49 struct mt7996_dev *dev; 50 struct mt76_phy *mphy; 51 u32 val; 52 53 mphy = container_of(led_cdev, struct mt76_phy, leds.cdev); 54 dev = container_of(mphy->dev, struct mt7996_dev, mt76); 55 56 /* select TX blink mode, 2: only data frames */ 57 mt76_rmw_field(dev, MT_TMAC_TCR0(mphy->band_idx), MT_TMAC_TCR0_TX_BLINK, 2); 58 59 /* enable LED */ 60 mt76_wr(dev, MT_LED_EN(mphy->band_idx), 1); 61 62 /* set LED Tx blink on/off time */ 63 val = FIELD_PREP(MT_LED_TX_BLINK_ON_MASK, delay_on) | 64 FIELD_PREP(MT_LED_TX_BLINK_OFF_MASK, delay_off); 65 mt76_wr(dev, MT_LED_TX_BLINK(mphy->band_idx), val); 66 67 /* turn LED off */ 68 if (delay_off == 0xff && delay_on == 0x0) { 69 val = MT_LED_CTRL_POLARITY | MT_LED_CTRL_KICK; 70 } else { 71 /* control LED */ 72 val = MT_LED_CTRL_BLINK_MODE | MT_LED_CTRL_KICK; 73 if (mphy->band_idx == MT_BAND1) 74 val |= MT_LED_CTRL_BLINK_BAND_SEL; 75 } 76 77 if (mphy->leds.al) 78 val |= MT_LED_CTRL_POLARITY; 79 80 mt76_wr(dev, MT_LED_CTRL(mphy->band_idx), val); 81 mt76_clear(dev, MT_LED_CTRL(mphy->band_idx), MT_LED_CTRL_KICK); 82 } 83 84 static int mt7996_led_set_blink(struct led_classdev *led_cdev, 85 unsigned long *delay_on, 86 unsigned long *delay_off) 87 { 88 u16 delta_on = 0, delta_off = 0; 89 90 #define HW_TICK 10 91 #define TO_HW_TICK(_t) (((_t) > HW_TICK) ? ((_t) / HW_TICK) : HW_TICK) 92 93 if (*delay_on) 94 delta_on = TO_HW_TICK(*delay_on); 95 if (*delay_off) 96 delta_off = TO_HW_TICK(*delay_off); 97 98 mt7996_led_set_config(led_cdev, delta_on, delta_off); 99 100 return 0; 101 } 102 103 static void mt7996_led_set_brightness(struct led_classdev *led_cdev, 104 enum led_brightness brightness) 105 { 106 if (!brightness) 107 mt7996_led_set_config(led_cdev, 0, 0xff); 108 else 109 mt7996_led_set_config(led_cdev, 0xff, 0); 110 } 111 112 void mt7996_init_txpower(struct mt7996_dev *dev, 113 struct ieee80211_supported_band *sband) 114 { 115 int i, nss = hweight8(dev->mphy.antenna_mask); 116 int nss_delta = mt76_tx_power_nss_delta(nss); 117 int pwr_delta = mt7996_eeprom_get_power_delta(dev, sband->band); 118 struct mt76_power_limits limits; 119 120 for (i = 0; i < sband->n_channels; i++) { 121 struct ieee80211_channel *chan = &sband->channels[i]; 122 int target_power = mt7996_eeprom_get_target_power(dev, chan); 123 124 target_power += pwr_delta; 125 target_power = mt76_get_rate_power_limits(&dev->mphy, chan, 126 &limits, 127 target_power); 128 target_power += nss_delta; 129 target_power = DIV_ROUND_UP(target_power, 2); 130 chan->max_power = min_t(int, chan->max_reg_power, 131 target_power); 132 chan->orig_mpwr = target_power; 133 } 134 } 135 136 static void 137 mt7996_regd_notifier(struct wiphy *wiphy, 138 struct regulatory_request *request) 139 { 140 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 141 struct mt7996_dev *dev = mt7996_hw_dev(hw); 142 struct mt7996_phy *phy = mt7996_hw_phy(hw); 143 144 memcpy(dev->mt76.alpha2, request->alpha2, sizeof(dev->mt76.alpha2)); 145 dev->mt76.region = request->dfs_region; 146 147 if (dev->mt76.region == NL80211_DFS_UNSET) 148 mt7996_mcu_rdd_background_enable(phy, NULL); 149 150 mt7996_init_txpower(dev, &phy->mt76->sband_2g.sband); 151 mt7996_init_txpower(dev, &phy->mt76->sband_5g.sband); 152 mt7996_init_txpower(dev, &phy->mt76->sband_6g.sband); 153 154 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN; 155 mt7996_dfs_init_radar_detector(phy); 156 } 157 158 static void 159 mt7996_init_wiphy(struct ieee80211_hw *hw) 160 { 161 struct mt7996_phy *phy = mt7996_hw_phy(hw); 162 struct mt76_dev *mdev = &phy->dev->mt76; 163 struct wiphy *wiphy = hw->wiphy; 164 u16 max_subframes = phy->dev->has_eht ? IEEE80211_MAX_AMPDU_BUF_EHT : 165 IEEE80211_MAX_AMPDU_BUF_HE; 166 167 hw->queues = 4; 168 hw->max_rx_aggregation_subframes = max_subframes; 169 hw->max_tx_aggregation_subframes = max_subframes; 170 hw->netdev_features = NETIF_F_RXCSUM; 171 172 hw->radiotap_timestamp.units_pos = 173 IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US; 174 175 phy->slottime = 9; 176 177 hw->sta_data_size = sizeof(struct mt7996_sta); 178 hw->vif_data_size = sizeof(struct mt7996_vif); 179 180 wiphy->iface_combinations = if_comb; 181 wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); 182 wiphy->reg_notifier = mt7996_regd_notifier; 183 wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; 184 wiphy->mbssid_max_interfaces = 16; 185 186 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR); 187 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS); 188 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_LEGACY); 189 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HT); 190 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_VHT); 191 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HE); 192 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP); 193 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_FILS_DISCOVERY); 194 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT); 195 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 196 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_MU_MIMO_AIR_SNIFFER); 197 198 if (!mdev->dev->of_node || 199 !of_property_read_bool(mdev->dev->of_node, 200 "mediatek,disable-radar-background")) 201 wiphy_ext_feature_set(wiphy, 202 NL80211_EXT_FEATURE_RADAR_BACKGROUND); 203 204 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 205 ieee80211_hw_set(hw, SUPPORTS_TX_ENCAP_OFFLOAD); 206 ieee80211_hw_set(hw, SUPPORTS_RX_DECAP_OFFLOAD); 207 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 208 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 209 210 hw->max_tx_fragments = 4; 211 212 if (phy->mt76->cap.has_2ghz) { 213 phy->mt76->sband_2g.sband.ht_cap.cap |= 214 IEEE80211_HT_CAP_LDPC_CODING | 215 IEEE80211_HT_CAP_MAX_AMSDU; 216 phy->mt76->sband_2g.sband.ht_cap.ampdu_density = 217 IEEE80211_HT_MPDU_DENSITY_2; 218 } 219 220 if (phy->mt76->cap.has_5ghz) { 221 phy->mt76->sband_5g.sband.ht_cap.cap |= 222 IEEE80211_HT_CAP_LDPC_CODING | 223 IEEE80211_HT_CAP_MAX_AMSDU; 224 225 phy->mt76->sband_5g.sband.vht_cap.cap |= 226 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 227 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 228 IEEE80211_VHT_CAP_SHORT_GI_160 | 229 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ; 230 phy->mt76->sband_5g.sband.ht_cap.ampdu_density = 231 IEEE80211_HT_MPDU_DENSITY_1; 232 233 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 234 } 235 236 /* init led callbacks */ 237 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 238 phy->mt76->leds.cdev.brightness_set = mt7996_led_set_brightness; 239 phy->mt76->leds.cdev.blink_set = mt7996_led_set_blink; 240 } 241 242 mt76_set_stream_caps(phy->mt76, true); 243 mt7996_set_stream_vht_txbf_caps(phy); 244 mt7996_set_stream_he_eht_caps(phy); 245 246 wiphy->available_antennas_rx = phy->mt76->antenna_mask; 247 wiphy->available_antennas_tx = phy->mt76->antenna_mask; 248 } 249 250 static void 251 mt7996_mac_init_band(struct mt7996_dev *dev, u8 band) 252 { 253 u32 mask, set; 254 255 /* clear estimated value of EIFS for Rx duration & OBSS time */ 256 mt76_wr(dev, MT_WF_RMAC_RSVD0(band), MT_WF_RMAC_RSVD0_EIFS_CLR); 257 258 /* clear backoff time for Rx duration */ 259 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME1(band), 260 MT_WF_RMAC_MIB_NONQOSD_BACKOFF); 261 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME3(band), 262 MT_WF_RMAC_MIB_QOS01_BACKOFF); 263 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME4(band), 264 MT_WF_RMAC_MIB_QOS23_BACKOFF); 265 266 /* clear backoff time and set software compensation for OBSS time */ 267 mask = MT_WF_RMAC_MIB_OBSS_BACKOFF | MT_WF_RMAC_MIB_ED_OFFSET; 268 set = FIELD_PREP(MT_WF_RMAC_MIB_OBSS_BACKOFF, 0) | 269 FIELD_PREP(MT_WF_RMAC_MIB_ED_OFFSET, 4); 270 mt76_rmw(dev, MT_WF_RMAC_MIB_AIRTIME0(band), mask, set); 271 272 /* filter out non-resp frames and get instanstaeous signal reporting */ 273 mask = MT_WTBLOFF_RSCR_RCPI_MODE | MT_WTBLOFF_RSCR_RCPI_PARAM; 274 set = FIELD_PREP(MT_WTBLOFF_RSCR_RCPI_MODE, 0) | 275 FIELD_PREP(MT_WTBLOFF_RSCR_RCPI_PARAM, 0x3); 276 mt76_rmw(dev, MT_WTBLOFF_RSCR(band), mask, set); 277 278 /* MT_TXD5_TX_STATUS_HOST (MPDU format) has higher priority than 279 * MT_AGG_ACR_PPDU_TXS2H (PPDU format) even though ACR bit is set. 280 */ 281 mt76_set(dev, MT_AGG_ACR4(band), MT_AGG_ACR_PPDU_TXS2H); 282 } 283 284 static void mt7996_mac_init_basic_rates(struct mt7996_dev *dev) 285 { 286 int i; 287 288 for (i = 0; i < ARRAY_SIZE(mt76_rates); i++) { 289 u16 rate = mt76_rates[i].hw_value; 290 u16 idx = MT7996_BASIC_RATES_TBL + i; 291 292 rate = FIELD_PREP(MT_TX_RATE_MODE, rate >> 8) | 293 FIELD_PREP(MT_TX_RATE_IDX, rate & GENMASK(7, 0)); 294 mt7996_mac_set_fixed_rate_table(dev, idx, rate); 295 } 296 } 297 298 void mt7996_mac_init(struct mt7996_dev *dev) 299 { 300 #define HIF_TXD_V2_1 4 301 int i; 302 303 mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT); 304 305 for (i = 0; i < mt7996_wtbl_size(dev); i++) 306 mt7996_mac_wtbl_update(dev, i, 307 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 308 309 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 310 i = dev->mphy.leds.pin ? MT_LED_GPIO_MUX3 : MT_LED_GPIO_MUX2; 311 mt76_rmw_field(dev, i, MT_LED_GPIO_SEL_MASK, 4); 312 } 313 314 /* txs report queue */ 315 mt76_rmw_field(dev, MT_DMA_TCRF1(0), MT_DMA_TCRF1_QIDX, 0); 316 mt76_rmw_field(dev, MT_DMA_TCRF1(1), MT_DMA_TCRF1_QIDX, 6); 317 mt76_rmw_field(dev, MT_DMA_TCRF1(2), MT_DMA_TCRF1_QIDX, 0); 318 319 /* rro module init */ 320 mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 2); 321 mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 3); 322 mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 1); 323 324 mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), 325 MCU_WA_PARAM_HW_PATH_HIF_VER, 326 HIF_TXD_V2_1, 0); 327 328 for (i = MT_BAND0; i <= MT_BAND2; i++) 329 mt7996_mac_init_band(dev, i); 330 331 mt7996_mac_init_basic_rates(dev); 332 } 333 334 int mt7996_txbf_init(struct mt7996_dev *dev) 335 { 336 int ret; 337 338 if (dev->dbdc_support) { 339 ret = mt7996_mcu_set_txbf(dev, BF_MOD_EN_CTRL); 340 if (ret) 341 return ret; 342 } 343 344 /* trigger sounding packets */ 345 ret = mt7996_mcu_set_txbf(dev, BF_SOUNDING_ON); 346 if (ret) 347 return ret; 348 349 /* enable eBF */ 350 return mt7996_mcu_set_txbf(dev, BF_HW_EN_UPDATE); 351 } 352 353 static int mt7996_register_phy(struct mt7996_dev *dev, struct mt7996_phy *phy, 354 enum mt76_band_id band) 355 { 356 struct mt76_phy *mphy; 357 u32 mac_ofs, hif1_ofs = 0; 358 int ret; 359 360 if (band != MT_BAND1 && band != MT_BAND2) 361 return 0; 362 363 if ((band == MT_BAND1 && !dev->dbdc_support) || 364 (band == MT_BAND2 && !dev->tbtc_support)) 365 return 0; 366 367 if (phy) 368 return 0; 369 370 if (band == MT_BAND2 && dev->hif2) 371 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); 372 373 mphy = mt76_alloc_phy(&dev->mt76, sizeof(*phy), &mt7996_ops, band); 374 if (!mphy) 375 return -ENOMEM; 376 377 phy = mphy->priv; 378 phy->dev = dev; 379 phy->mt76 = mphy; 380 mphy->dev->phys[band] = mphy; 381 382 INIT_DELAYED_WORK(&mphy->mac_work, mt7996_mac_work); 383 384 ret = mt7996_eeprom_parse_hw_cap(dev, phy); 385 if (ret) 386 goto error; 387 388 mac_ofs = band == MT_BAND2 ? MT_EE_MAC_ADDR3 : MT_EE_MAC_ADDR2; 389 memcpy(mphy->macaddr, dev->mt76.eeprom.data + mac_ofs, ETH_ALEN); 390 /* Make the extra PHY MAC address local without overlapping with 391 * the usual MAC address allocation scheme on multiple virtual interfaces 392 */ 393 if (!is_valid_ether_addr(mphy->macaddr)) { 394 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR, 395 ETH_ALEN); 396 mphy->macaddr[0] |= 2; 397 mphy->macaddr[0] ^= BIT(7); 398 if (band == MT_BAND2) 399 mphy->macaddr[0] ^= BIT(6); 400 } 401 mt76_eeprom_override(mphy); 402 403 /* init wiphy according to mphy and phy */ 404 mt7996_init_wiphy(mphy->hw); 405 ret = mt76_connac_init_tx_queues(phy->mt76, 406 MT_TXQ_ID(band), 407 MT7996_TX_RING_SIZE, 408 MT_TXQ_RING_BASE(band) + hif1_ofs, 0); 409 if (ret) 410 goto error; 411 412 ret = mt76_register_phy(mphy, true, mt76_rates, 413 ARRAY_SIZE(mt76_rates)); 414 if (ret) 415 goto error; 416 417 ret = mt7996_init_debugfs(phy); 418 if (ret) 419 goto error; 420 421 return 0; 422 423 error: 424 mphy->dev->phys[band] = NULL; 425 ieee80211_free_hw(mphy->hw); 426 return ret; 427 } 428 429 static void 430 mt7996_unregister_phy(struct mt7996_phy *phy, enum mt76_band_id band) 431 { 432 struct mt76_phy *mphy; 433 434 if (!phy) 435 return; 436 437 mphy = phy->dev->mt76.phys[band]; 438 mt76_unregister_phy(mphy); 439 ieee80211_free_hw(mphy->hw); 440 phy->dev->mt76.phys[band] = NULL; 441 } 442 443 static void mt7996_init_work(struct work_struct *work) 444 { 445 struct mt7996_dev *dev = container_of(work, struct mt7996_dev, 446 init_work); 447 448 mt7996_mcu_set_eeprom(dev); 449 mt7996_mac_init(dev); 450 mt7996_init_txpower(dev, &dev->mphy.sband_2g.sband); 451 mt7996_init_txpower(dev, &dev->mphy.sband_5g.sband); 452 mt7996_init_txpower(dev, &dev->mphy.sband_6g.sband); 453 mt7996_txbf_init(dev); 454 } 455 456 void mt7996_wfsys_reset(struct mt7996_dev *dev) 457 { 458 mt76_set(dev, MT_WF_SUBSYS_RST, 0x1); 459 msleep(20); 460 461 mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1); 462 msleep(20); 463 } 464 465 static int mt7996_init_hardware(struct mt7996_dev *dev) 466 { 467 int ret, idx; 468 469 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 470 471 INIT_WORK(&dev->init_work, mt7996_init_work); 472 473 dev->dbdc_support = true; 474 dev->tbtc_support = true; 475 476 ret = mt7996_dma_init(dev); 477 if (ret) 478 return ret; 479 480 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state); 481 482 ret = mt7996_mcu_init(dev); 483 if (ret) 484 return ret; 485 486 ret = mt7996_eeprom_init(dev); 487 if (ret < 0) 488 return ret; 489 490 /* Beacon and mgmt frames should occupy wcid 0 */ 491 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7996_WTBL_STA); 492 if (idx) 493 return -ENOSPC; 494 495 dev->mt76.global_wcid.idx = idx; 496 dev->mt76.global_wcid.hw_key_idx = -1; 497 dev->mt76.global_wcid.tx_info |= MT_WCID_TX_INFO_SET; 498 rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid); 499 500 return 0; 501 } 502 503 void mt7996_set_stream_vht_txbf_caps(struct mt7996_phy *phy) 504 { 505 int sts; 506 u32 *cap; 507 508 if (!phy->mt76->cap.has_5ghz) 509 return; 510 511 sts = hweight16(phy->mt76->chainmask); 512 cap = &phy->mt76->sband_5g.sband.vht_cap.cap; 513 514 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | 515 IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 516 FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, sts - 1); 517 518 *cap &= ~(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK | 519 IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 520 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE); 521 522 if (sts < 2) 523 return; 524 525 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 526 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE | 527 FIELD_PREP(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, sts - 1); 528 } 529 530 static void 531 mt7996_set_stream_he_txbf_caps(struct mt7996_phy *phy, 532 struct ieee80211_sta_he_cap *he_cap, int vif) 533 { 534 struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem; 535 int sts = hweight16(phy->mt76->chainmask); 536 u8 c; 537 538 #ifdef CONFIG_MAC80211_MESH 539 if (vif == NL80211_IFTYPE_MESH_POINT) 540 return; 541 #endif 542 543 elem->phy_cap_info[3] &= ~IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 544 elem->phy_cap_info[4] &= ~IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 545 546 c = IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK | 547 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK; 548 elem->phy_cap_info[5] &= ~c; 549 550 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 551 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 552 elem->phy_cap_info[6] &= ~c; 553 554 elem->phy_cap_info[7] &= ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK; 555 556 c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 557 IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO | 558 IEEE80211_HE_PHY_CAP2_UL_MU_PARTIAL_MU_MIMO; 559 elem->phy_cap_info[2] |= c; 560 561 c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 562 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4 | 563 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 564 elem->phy_cap_info[4] |= c; 565 566 /* do not support NG16 due to spec D4.0 changes subcarrier idx */ 567 c = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 568 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU; 569 570 if (vif == NL80211_IFTYPE_STATION) 571 c |= IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO; 572 573 elem->phy_cap_info[6] |= c; 574 575 if (sts < 2) 576 return; 577 578 /* the maximum cap is 4 x 3, (Nr, Nc) = (3, 2) */ 579 elem->phy_cap_info[7] |= min_t(int, sts - 1, 2) << 3; 580 581 if (vif != NL80211_IFTYPE_AP) 582 return; 583 584 elem->phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 585 elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 586 587 c = FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 588 sts - 1) | 589 FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK, 590 sts - 1); 591 elem->phy_cap_info[5] |= c; 592 593 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 594 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 595 elem->phy_cap_info[6] |= c; 596 597 c = IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ | 598 IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ; 599 elem->phy_cap_info[7] |= c; 600 } 601 602 static void 603 mt7996_init_he_caps(struct mt7996_phy *phy, enum nl80211_band band, 604 struct ieee80211_sband_iftype_data *data, 605 enum nl80211_iftype iftype) 606 { 607 struct ieee80211_sta_he_cap *he_cap = &data->he_cap; 608 struct ieee80211_he_cap_elem *he_cap_elem = &he_cap->he_cap_elem; 609 struct ieee80211_he_mcs_nss_supp *he_mcs = &he_cap->he_mcs_nss_supp; 610 int i, nss = hweight8(phy->mt76->antenna_mask); 611 u16 mcs_map = 0; 612 613 for (i = 0; i < 8; i++) { 614 if (i < nss) 615 mcs_map |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 616 else 617 mcs_map |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 618 } 619 620 he_cap->has_he = true; 621 622 he_cap_elem->mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE; 623 he_cap_elem->mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 624 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3; 625 he_cap_elem->mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 626 627 if (band == NL80211_BAND_2GHZ) 628 he_cap_elem->phy_cap_info[0] = 629 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 630 else 631 he_cap_elem->phy_cap_info[0] = 632 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 633 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 634 635 he_cap_elem->phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD; 636 he_cap_elem->phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 637 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ; 638 639 switch (iftype) { 640 case NL80211_IFTYPE_AP: 641 he_cap_elem->mac_cap_info[0] |= IEEE80211_HE_MAC_CAP0_TWT_RES; 642 he_cap_elem->mac_cap_info[2] |= IEEE80211_HE_MAC_CAP2_BSR; 643 he_cap_elem->mac_cap_info[4] |= IEEE80211_HE_MAC_CAP4_BQR; 644 he_cap_elem->mac_cap_info[5] |= 645 IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX; 646 he_cap_elem->phy_cap_info[3] |= 647 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 648 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 649 he_cap_elem->phy_cap_info[6] |= 650 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 651 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 652 he_cap_elem->phy_cap_info[9] |= 653 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 654 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU; 655 break; 656 case NL80211_IFTYPE_STATION: 657 he_cap_elem->mac_cap_info[1] |= 658 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 659 660 if (band == NL80211_BAND_2GHZ) 661 he_cap_elem->phy_cap_info[0] |= 662 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G; 663 else 664 he_cap_elem->phy_cap_info[0] |= 665 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G; 666 667 he_cap_elem->phy_cap_info[1] |= 668 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 669 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 670 he_cap_elem->phy_cap_info[3] |= 671 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 672 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 673 he_cap_elem->phy_cap_info[6] |= 674 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB | 675 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 676 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 677 he_cap_elem->phy_cap_info[7] |= 678 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 679 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI; 680 he_cap_elem->phy_cap_info[8] |= 681 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 682 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 683 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU | 684 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_484; 685 he_cap_elem->phy_cap_info[9] |= 686 IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 687 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK | 688 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 689 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 690 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 691 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB; 692 break; 693 default: 694 break; 695 } 696 697 he_mcs->rx_mcs_80 = cpu_to_le16(mcs_map); 698 he_mcs->tx_mcs_80 = cpu_to_le16(mcs_map); 699 he_mcs->rx_mcs_160 = cpu_to_le16(mcs_map); 700 he_mcs->tx_mcs_160 = cpu_to_le16(mcs_map); 701 702 mt7996_set_stream_he_txbf_caps(phy, he_cap, iftype); 703 704 memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres)); 705 if (he_cap_elem->phy_cap_info[6] & 706 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) { 707 mt76_connac_gen_ppe_thresh(he_cap->ppe_thres, nss); 708 } else { 709 he_cap_elem->phy_cap_info[9] |= 710 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 711 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 712 } 713 714 if (band == NL80211_BAND_6GHZ) { 715 u16 cap = IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS | 716 IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS; 717 718 cap |= u16_encode_bits(IEEE80211_HT_MPDU_DENSITY_0_5, 719 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 720 u16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 721 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 722 u16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 723 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 724 725 data->he_6ghz_capa.capa = cpu_to_le16(cap); 726 } 727 } 728 729 static void 730 mt7996_init_eht_caps(struct mt7996_phy *phy, enum nl80211_band band, 731 struct ieee80211_sband_iftype_data *data, 732 enum nl80211_iftype iftype) 733 { 734 struct ieee80211_sta_eht_cap *eht_cap = &data->eht_cap; 735 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem = &eht_cap->eht_cap_elem; 736 struct ieee80211_eht_mcs_nss_supp *eht_nss = &eht_cap->eht_mcs_nss_supp; 737 enum nl80211_chan_width width = phy->mt76->chandef.width; 738 int nss = hweight8(phy->mt76->antenna_mask); 739 int sts = hweight16(phy->mt76->chainmask); 740 u8 val; 741 742 if (!phy->dev->has_eht) 743 return; 744 745 eht_cap->has_eht = true; 746 747 eht_cap_elem->mac_cap_info[0] = 748 IEEE80211_EHT_MAC_CAP0_EPCS_PRIO_ACCESS | 749 IEEE80211_EHT_MAC_CAP0_OM_CONTROL; 750 751 eht_cap_elem->phy_cap_info[0] = 752 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ | 753 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI | 754 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMER | 755 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE; 756 757 val = max_t(u8, sts - 1, 3); 758 eht_cap_elem->phy_cap_info[0] |= 759 u8_encode_bits(u8_get_bits(val, BIT(0)), 760 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK); 761 762 eht_cap_elem->phy_cap_info[1] = 763 u8_encode_bits(u8_get_bits(val, GENMASK(2, 1)), 764 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK) | 765 u8_encode_bits(val, 766 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK) | 767 u8_encode_bits(val, 768 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK); 769 770 eht_cap_elem->phy_cap_info[2] = 771 u8_encode_bits(sts - 1, IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_80MHZ_MASK) | 772 u8_encode_bits(sts - 1, IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_160MHZ_MASK) | 773 u8_encode_bits(sts - 1, IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_320MHZ_MASK); 774 775 eht_cap_elem->phy_cap_info[3] = 776 IEEE80211_EHT_PHY_CAP3_NG_16_SU_FEEDBACK | 777 IEEE80211_EHT_PHY_CAP3_NG_16_MU_FEEDBACK | 778 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK | 779 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK | 780 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK | 781 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK | 782 IEEE80211_EHT_PHY_CAP3_TRIG_CQI_FDBK; 783 784 eht_cap_elem->phy_cap_info[4] = 785 u8_encode_bits(min_t(int, sts - 1, 2), 786 IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK); 787 788 eht_cap_elem->phy_cap_info[5] = 789 IEEE80211_EHT_PHY_CAP5_NON_TRIG_CQI_FEEDBACK | 790 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_16US, 791 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK) | 792 u8_encode_bits(u8_get_bits(0x11, GENMASK(1, 0)), 793 IEEE80211_EHT_PHY_CAP5_MAX_NUM_SUPP_EHT_LTF_MASK); 794 795 val = width == NL80211_CHAN_WIDTH_320 ? 0xf : 796 width == NL80211_CHAN_WIDTH_160 ? 0x7 : 797 width == NL80211_CHAN_WIDTH_80 ? 0x3 : 0x1; 798 eht_cap_elem->phy_cap_info[6] = 799 u8_encode_bits(u8_get_bits(0x11, GENMASK(4, 2)), 800 IEEE80211_EHT_PHY_CAP6_MAX_NUM_SUPP_EHT_LTF_MASK) | 801 u8_encode_bits(val, IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_MASK); 802 803 eht_cap_elem->phy_cap_info[7] = 804 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_80MHZ | 805 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_160MHZ | 806 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_320MHZ | 807 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_80MHZ | 808 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_160MHZ | 809 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_320MHZ; 810 811 val = u8_encode_bits(nss, IEEE80211_EHT_MCS_NSS_RX) | 812 u8_encode_bits(nss, IEEE80211_EHT_MCS_NSS_TX); 813 #define SET_EHT_MAX_NSS(_bw, _val) do { \ 814 eht_nss->bw._##_bw.rx_tx_mcs9_max_nss = _val; \ 815 eht_nss->bw._##_bw.rx_tx_mcs11_max_nss = _val; \ 816 eht_nss->bw._##_bw.rx_tx_mcs13_max_nss = _val; \ 817 } while (0) 818 819 SET_EHT_MAX_NSS(80, val); 820 SET_EHT_MAX_NSS(160, val); 821 SET_EHT_MAX_NSS(320, val); 822 #undef SET_EHT_MAX_NSS 823 } 824 825 static void 826 __mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy, 827 struct ieee80211_supported_band *sband, 828 enum nl80211_band band) 829 { 830 struct ieee80211_sband_iftype_data *data = phy->iftype[band]; 831 int i, n = 0; 832 833 for (i = 0; i < NUM_NL80211_IFTYPES; i++) { 834 switch (i) { 835 case NL80211_IFTYPE_STATION: 836 case NL80211_IFTYPE_AP: 837 #ifdef CONFIG_MAC80211_MESH 838 case NL80211_IFTYPE_MESH_POINT: 839 #endif 840 break; 841 default: 842 continue; 843 } 844 845 data[n].types_mask = BIT(i); 846 mt7996_init_he_caps(phy, band, &data[n], i); 847 mt7996_init_eht_caps(phy, band, &data[n], i); 848 849 n++; 850 } 851 852 _ieee80211_set_sband_iftype_data(sband, data, n); 853 } 854 855 void mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy) 856 { 857 if (phy->mt76->cap.has_2ghz) 858 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_2g.sband, 859 NL80211_BAND_2GHZ); 860 861 if (phy->mt76->cap.has_5ghz) 862 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_5g.sband, 863 NL80211_BAND_5GHZ); 864 865 if (phy->mt76->cap.has_6ghz) 866 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_6g.sband, 867 NL80211_BAND_6GHZ); 868 } 869 870 int mt7996_register_device(struct mt7996_dev *dev) 871 { 872 struct ieee80211_hw *hw = mt76_hw(dev); 873 int ret; 874 875 dev->phy.dev = dev; 876 dev->phy.mt76 = &dev->mt76.phy; 877 dev->mt76.phy.priv = &dev->phy; 878 INIT_WORK(&dev->rc_work, mt7996_mac_sta_rc_work); 879 INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7996_mac_work); 880 INIT_LIST_HEAD(&dev->sta_rc_list); 881 INIT_LIST_HEAD(&dev->twt_list); 882 883 init_waitqueue_head(&dev->reset_wait); 884 INIT_WORK(&dev->reset_work, mt7996_mac_reset_work); 885 INIT_WORK(&dev->dump_work, mt7996_mac_dump_work); 886 mutex_init(&dev->dump_mutex); 887 888 ret = mt7996_init_hardware(dev); 889 if (ret) 890 return ret; 891 892 mt7996_init_wiphy(hw); 893 894 ret = mt76_register_device(&dev->mt76, true, mt76_rates, 895 ARRAY_SIZE(mt76_rates)); 896 if (ret) 897 return ret; 898 899 ieee80211_queue_work(mt76_hw(dev), &dev->init_work); 900 901 ret = mt7996_register_phy(dev, mt7996_phy2(dev), MT_BAND1); 902 if (ret) 903 return ret; 904 905 ret = mt7996_register_phy(dev, mt7996_phy3(dev), MT_BAND2); 906 if (ret) 907 return ret; 908 909 dev->recovery.hw_init_done = true; 910 911 ret = mt7996_init_debugfs(&dev->phy); 912 if (ret) 913 return ret; 914 915 return mt7996_coredump_register(dev); 916 } 917 918 void mt7996_unregister_device(struct mt7996_dev *dev) 919 { 920 mt7996_unregister_phy(mt7996_phy3(dev), MT_BAND2); 921 mt7996_unregister_phy(mt7996_phy2(dev), MT_BAND1); 922 mt7996_coredump_unregister(dev); 923 mt76_unregister_device(&dev->mt76); 924 mt7996_mcu_exit(dev); 925 mt7996_tx_token_put(dev); 926 mt7996_dma_cleanup(dev); 927 tasklet_disable(&dev->mt76.irq_tasklet); 928 929 mt76_free_device(&dev->mt76); 930 } 931