1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #include <linux/etherdevice.h> 7 #include <linux/of.h> 8 #include <linux/hwmon.h> 9 #include <linux/hwmon-sysfs.h> 10 #include <linux/thermal.h> 11 #include "mt7996.h" 12 #include "mac.h" 13 #include "mcu.h" 14 #include "coredump.h" 15 #include "eeprom.h" 16 17 static const struct ieee80211_iface_limit if_limits_global = { 18 .max = MT7996_MAX_INTERFACES * MT7996_MAX_RADIOS, 19 .types = BIT(NL80211_IFTYPE_STATION) 20 | BIT(NL80211_IFTYPE_ADHOC) 21 | BIT(NL80211_IFTYPE_AP) 22 #ifdef CONFIG_MAC80211_MESH 23 | BIT(NL80211_IFTYPE_MESH_POINT) 24 #endif 25 }; 26 27 static const struct ieee80211_iface_combination if_comb_global = { 28 .limits = &if_limits_global, 29 .n_limits = 1, 30 .max_interfaces = MT7996_MAX_INTERFACES * MT7996_MAX_RADIOS, 31 .num_different_channels = MT7996_MAX_RADIOS, 32 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 33 BIT(NL80211_CHAN_WIDTH_20) | 34 BIT(NL80211_CHAN_WIDTH_40) | 35 BIT(NL80211_CHAN_WIDTH_80) | 36 BIT(NL80211_CHAN_WIDTH_160), 37 }; 38 39 static const struct ieee80211_iface_limit if_limits[] = { 40 { 41 .max = 16, 42 .types = BIT(NL80211_IFTYPE_AP) 43 #ifdef CONFIG_MAC80211_MESH 44 | BIT(NL80211_IFTYPE_MESH_POINT) 45 #endif 46 }, { 47 .max = MT7996_MAX_INTERFACES, 48 .types = BIT(NL80211_IFTYPE_STATION) 49 } 50 }; 51 52 static const struct ieee80211_iface_combination if_comb = { 53 .limits = if_limits, 54 .n_limits = ARRAY_SIZE(if_limits), 55 .max_interfaces = MT7996_MAX_INTERFACES, 56 .num_different_channels = 1, 57 .beacon_int_infra_match = true, 58 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 59 BIT(NL80211_CHAN_WIDTH_20) | 60 BIT(NL80211_CHAN_WIDTH_40) | 61 BIT(NL80211_CHAN_WIDTH_80) | 62 BIT(NL80211_CHAN_WIDTH_160), 63 .beacon_int_min_gcd = 100, 64 }; 65 66 static ssize_t mt7996_thermal_temp_show(struct device *dev, 67 struct device_attribute *attr, 68 char *buf) 69 { 70 struct mt7996_phy *phy = dev_get_drvdata(dev); 71 int i = to_sensor_dev_attr(attr)->index; 72 int temperature; 73 74 switch (i) { 75 case 0: 76 temperature = mt7996_mcu_get_temperature(phy); 77 if (temperature < 0) 78 return temperature; 79 /* display in millidegree celcius */ 80 return sprintf(buf, "%u\n", temperature * 1000); 81 case 1: 82 case 2: 83 return sprintf(buf, "%u\n", 84 phy->throttle_temp[i - 1] * 1000); 85 case 3: 86 return sprintf(buf, "%hhu\n", phy->throttle_state); 87 default: 88 return -EINVAL; 89 } 90 } 91 92 static ssize_t mt7996_thermal_temp_store(struct device *dev, 93 struct device_attribute *attr, 94 const char *buf, size_t count) 95 { 96 struct mt7996_phy *phy = dev_get_drvdata(dev); 97 int ret, i = to_sensor_dev_attr(attr)->index; 98 long val; 99 100 ret = kstrtol(buf, 10, &val); 101 if (ret < 0) 102 return ret; 103 104 mutex_lock(&phy->dev->mt76.mutex); 105 val = DIV_ROUND_CLOSEST(clamp_val(val, 40 * 1000, 130 * 1000), 1000); 106 107 /* add a safety margin ~10 */ 108 if ((i - 1 == MT7996_CRIT_TEMP_IDX && 109 val > phy->throttle_temp[MT7996_MAX_TEMP_IDX] - 10) || 110 (i - 1 == MT7996_MAX_TEMP_IDX && 111 val - 10 < phy->throttle_temp[MT7996_CRIT_TEMP_IDX])) { 112 dev_err(phy->dev->mt76.dev, 113 "temp1_max shall be 10 degrees higher than temp1_crit."); 114 mutex_unlock(&phy->dev->mt76.mutex); 115 return -EINVAL; 116 } 117 118 phy->throttle_temp[i - 1] = val; 119 mutex_unlock(&phy->dev->mt76.mutex); 120 121 ret = mt7996_mcu_set_thermal_protect(phy, true); 122 if (ret) 123 return ret; 124 125 return count; 126 } 127 128 static SENSOR_DEVICE_ATTR_RO(temp1_input, mt7996_thermal_temp, 0); 129 static SENSOR_DEVICE_ATTR_RW(temp1_crit, mt7996_thermal_temp, 1); 130 static SENSOR_DEVICE_ATTR_RW(temp1_max, mt7996_thermal_temp, 2); 131 static SENSOR_DEVICE_ATTR_RO(throttle1, mt7996_thermal_temp, 3); 132 133 static struct attribute *mt7996_hwmon_attrs[] = { 134 &sensor_dev_attr_temp1_input.dev_attr.attr, 135 &sensor_dev_attr_temp1_crit.dev_attr.attr, 136 &sensor_dev_attr_temp1_max.dev_attr.attr, 137 &sensor_dev_attr_throttle1.dev_attr.attr, 138 NULL, 139 }; 140 ATTRIBUTE_GROUPS(mt7996_hwmon); 141 142 static int 143 mt7996_thermal_get_max_throttle_state(struct thermal_cooling_device *cdev, 144 unsigned long *state) 145 { 146 *state = MT7996_CDEV_THROTTLE_MAX; 147 148 return 0; 149 } 150 151 static int 152 mt7996_thermal_get_cur_throttle_state(struct thermal_cooling_device *cdev, 153 unsigned long *state) 154 { 155 struct mt7996_phy *phy = cdev->devdata; 156 157 *state = phy->cdev_state; 158 159 return 0; 160 } 161 162 static int 163 mt7996_thermal_set_cur_throttle_state(struct thermal_cooling_device *cdev, 164 unsigned long state) 165 { 166 struct mt7996_phy *phy = cdev->devdata; 167 u8 throttling = MT7996_THERMAL_THROTTLE_MAX - state; 168 int ret; 169 170 if (state > MT7996_CDEV_THROTTLE_MAX) { 171 dev_err(phy->dev->mt76.dev, 172 "please specify a valid throttling state\n"); 173 return -EINVAL; 174 } 175 176 if (state == phy->cdev_state) 177 return 0; 178 179 /* cooling_device convention: 0 = no cooling, more = more cooling 180 * mcu convention: 1 = max cooling, more = less cooling 181 */ 182 ret = mt7996_mcu_set_thermal_throttling(phy, throttling); 183 if (ret) 184 return ret; 185 186 phy->cdev_state = state; 187 188 return 0; 189 } 190 191 static const struct thermal_cooling_device_ops mt7996_thermal_ops = { 192 .get_max_state = mt7996_thermal_get_max_throttle_state, 193 .get_cur_state = mt7996_thermal_get_cur_throttle_state, 194 .set_cur_state = mt7996_thermal_set_cur_throttle_state, 195 }; 196 197 static void mt7996_unregister_thermal(struct mt7996_phy *phy) 198 { 199 struct wiphy *wiphy = phy->mt76->hw->wiphy; 200 char name[sizeof("cooling_deviceXXX")]; 201 202 if (!phy->cdev) 203 return; 204 205 snprintf(name, sizeof(name), "cooling_device%d", phy->mt76->band_idx); 206 sysfs_remove_link(&wiphy->dev.kobj, name); 207 thermal_cooling_device_unregister(phy->cdev); 208 } 209 210 static int mt7996_thermal_init(struct mt7996_phy *phy) 211 { 212 struct wiphy *wiphy = phy->mt76->hw->wiphy; 213 char cname[sizeof("cooling_deviceXXX")]; 214 struct thermal_cooling_device *cdev; 215 struct device *hwmon; 216 const char *name; 217 218 name = devm_kasprintf(&wiphy->dev, GFP_KERNEL, "mt7996_%s.%d", 219 wiphy_name(wiphy), phy->mt76->band_idx); 220 snprintf(cname, sizeof(cname), "cooling_device%d", phy->mt76->band_idx); 221 222 cdev = thermal_cooling_device_register(name, phy, &mt7996_thermal_ops); 223 if (!IS_ERR(cdev)) { 224 if (sysfs_create_link(&wiphy->dev.kobj, &cdev->device.kobj, 225 cname) < 0) 226 thermal_cooling_device_unregister(cdev); 227 else 228 phy->cdev = cdev; 229 } 230 231 /* initialize critical/maximum high temperature */ 232 phy->throttle_temp[MT7996_CRIT_TEMP_IDX] = MT7996_CRIT_TEMP; 233 phy->throttle_temp[MT7996_MAX_TEMP_IDX] = MT7996_MAX_TEMP; 234 235 if (!IS_REACHABLE(CONFIG_HWMON)) 236 return 0; 237 238 hwmon = devm_hwmon_device_register_with_groups(&wiphy->dev, name, phy, 239 mt7996_hwmon_groups); 240 241 if (IS_ERR(hwmon)) 242 return PTR_ERR(hwmon); 243 244 return 0; 245 } 246 247 static void mt7996_led_set_config(struct led_classdev *led_cdev, 248 u8 delay_on, u8 delay_off) 249 { 250 struct mt7996_dev *dev; 251 struct mt76_phy *mphy; 252 u32 val; 253 254 mphy = container_of(led_cdev, struct mt76_phy, leds.cdev); 255 dev = container_of(mphy->dev, struct mt7996_dev, mt76); 256 257 /* select TX blink mode, 2: only data frames */ 258 mt76_rmw_field(dev, MT_TMAC_TCR0(mphy->band_idx), MT_TMAC_TCR0_TX_BLINK, 2); 259 260 /* enable LED */ 261 mt76_wr(dev, MT_LED_EN(mphy->band_idx), 1); 262 263 /* set LED Tx blink on/off time */ 264 val = FIELD_PREP(MT_LED_TX_BLINK_ON_MASK, delay_on) | 265 FIELD_PREP(MT_LED_TX_BLINK_OFF_MASK, delay_off); 266 mt76_wr(dev, MT_LED_TX_BLINK(mphy->band_idx), val); 267 268 /* turn LED off */ 269 if (delay_off == 0xff && delay_on == 0x0) { 270 val = MT_LED_CTRL_POLARITY | MT_LED_CTRL_KICK; 271 } else { 272 /* control LED */ 273 val = MT_LED_CTRL_BLINK_MODE | MT_LED_CTRL_KICK; 274 if (mphy->band_idx == MT_BAND1) 275 val |= MT_LED_CTRL_BLINK_BAND_SEL; 276 } 277 278 if (mphy->leds.al) 279 val |= MT_LED_CTRL_POLARITY; 280 281 mt76_wr(dev, MT_LED_CTRL(mphy->band_idx), val); 282 mt76_clear(dev, MT_LED_CTRL(mphy->band_idx), MT_LED_CTRL_KICK); 283 } 284 285 static int mt7996_led_set_blink(struct led_classdev *led_cdev, 286 unsigned long *delay_on, 287 unsigned long *delay_off) 288 { 289 u16 delta_on = 0, delta_off = 0; 290 291 #define HW_TICK 10 292 #define TO_HW_TICK(_t) (((_t) > HW_TICK) ? ((_t) / HW_TICK) : HW_TICK) 293 294 if (*delay_on) 295 delta_on = TO_HW_TICK(*delay_on); 296 if (*delay_off) 297 delta_off = TO_HW_TICK(*delay_off); 298 299 mt7996_led_set_config(led_cdev, delta_on, delta_off); 300 301 return 0; 302 } 303 304 static void mt7996_led_set_brightness(struct led_classdev *led_cdev, 305 enum led_brightness brightness) 306 { 307 if (!brightness) 308 mt7996_led_set_config(led_cdev, 0, 0xff); 309 else 310 mt7996_led_set_config(led_cdev, 0xff, 0); 311 } 312 313 static void __mt7996_init_txpower(struct mt7996_phy *phy, 314 struct ieee80211_supported_band *sband) 315 { 316 struct mt7996_dev *dev = phy->dev; 317 int i, nss = hweight16(phy->mt76->chainmask); 318 int nss_delta = mt76_tx_power_nss_delta(nss); 319 int pwr_delta = mt7996_eeprom_get_power_delta(dev, sband->band); 320 struct mt76_power_limits limits; 321 322 for (i = 0; i < sband->n_channels; i++) { 323 struct ieee80211_channel *chan = &sband->channels[i]; 324 int target_power = mt7996_eeprom_get_target_power(dev, chan); 325 326 target_power += pwr_delta; 327 target_power = mt76_get_rate_power_limits(phy->mt76, chan, 328 &limits, 329 target_power); 330 target_power += nss_delta; 331 target_power = DIV_ROUND_UP(target_power, 2); 332 chan->max_power = min_t(int, chan->max_reg_power, 333 target_power); 334 chan->orig_mpwr = target_power; 335 } 336 } 337 338 void mt7996_init_txpower(struct mt7996_phy *phy) 339 { 340 if (!phy) 341 return; 342 343 if (phy->mt76->cap.has_2ghz) 344 __mt7996_init_txpower(phy, &phy->mt76->sband_2g.sband); 345 if (phy->mt76->cap.has_5ghz) 346 __mt7996_init_txpower(phy, &phy->mt76->sband_5g.sband); 347 if (phy->mt76->cap.has_6ghz) 348 __mt7996_init_txpower(phy, &phy->mt76->sband_6g.sband); 349 } 350 351 static void 352 mt7996_regd_notifier(struct wiphy *wiphy, 353 struct regulatory_request *request) 354 { 355 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 356 struct mt7996_dev *dev = mt7996_hw_dev(hw); 357 struct mt7996_phy *phy; 358 359 memcpy(dev->mt76.alpha2, request->alpha2, sizeof(dev->mt76.alpha2)); 360 dev->mt76.region = request->dfs_region; 361 362 mt7996_for_each_phy(dev, phy) { 363 if (dev->mt76.region == NL80211_DFS_UNSET) 364 mt7996_mcu_rdd_background_enable(phy, NULL); 365 366 mt7996_init_txpower(phy); 367 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN; 368 mt7996_dfs_init_radar_detector(phy); 369 } 370 } 371 372 static void 373 mt7996_init_wiphy_band(struct ieee80211_hw *hw, struct mt7996_phy *phy) 374 { 375 struct mt7996_dev *dev = phy->dev; 376 struct wiphy *wiphy = hw->wiphy; 377 int n_radios = hw->wiphy->n_radio; 378 struct wiphy_radio_freq_range *freq = &dev->radio_freqs[n_radios]; 379 struct wiphy_radio *radio = &dev->radios[n_radios]; 380 381 phy->slottime = 9; 382 phy->beacon_rate = -1; 383 384 if (phy->mt76->cap.has_2ghz) { 385 phy->mt76->sband_2g.sband.ht_cap.cap |= 386 IEEE80211_HT_CAP_LDPC_CODING | 387 IEEE80211_HT_CAP_MAX_AMSDU; 388 phy->mt76->sband_2g.sband.ht_cap.ampdu_density = 389 IEEE80211_HT_MPDU_DENSITY_2; 390 freq->start_freq = 2400000; 391 freq->end_freq = 2500000; 392 } else if (phy->mt76->cap.has_5ghz) { 393 phy->mt76->sband_5g.sband.ht_cap.cap |= 394 IEEE80211_HT_CAP_LDPC_CODING | 395 IEEE80211_HT_CAP_MAX_AMSDU; 396 397 phy->mt76->sband_5g.sband.vht_cap.cap |= 398 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 399 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 400 IEEE80211_VHT_CAP_SHORT_GI_160 | 401 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ; 402 phy->mt76->sband_5g.sband.ht_cap.ampdu_density = 403 IEEE80211_HT_MPDU_DENSITY_1; 404 405 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 406 freq->start_freq = 5000000; 407 freq->end_freq = 5900000; 408 } else if (phy->mt76->cap.has_6ghz) { 409 freq->start_freq = 5900000; 410 freq->end_freq = 7200000; 411 } else { 412 return; 413 } 414 415 dev->radio_phy[n_radios] = phy; 416 radio->freq_range = freq; 417 radio->n_freq_range = 1; 418 radio->iface_combinations = &if_comb; 419 radio->n_iface_combinations = 1; 420 hw->wiphy->n_radio++; 421 422 wiphy->available_antennas_rx |= phy->mt76->chainmask; 423 wiphy->available_antennas_tx |= phy->mt76->chainmask; 424 425 mt76_set_stream_caps(phy->mt76, true); 426 mt7996_set_stream_vht_txbf_caps(phy); 427 mt7996_set_stream_he_eht_caps(phy); 428 mt7996_init_txpower(phy); 429 } 430 431 static void 432 mt7996_init_wiphy(struct ieee80211_hw *hw, struct mtk_wed_device *wed) 433 { 434 struct mt7996_dev *dev = mt7996_hw_dev(hw); 435 struct mt76_dev *mdev = &dev->mt76; 436 struct wiphy *wiphy = hw->wiphy; 437 u16 max_subframes = dev->has_eht ? IEEE80211_MAX_AMPDU_BUF_EHT : 438 IEEE80211_MAX_AMPDU_BUF_HE; 439 440 hw->queues = 4; 441 hw->max_rx_aggregation_subframes = max_subframes; 442 hw->max_tx_aggregation_subframes = max_subframes; 443 hw->netdev_features = NETIF_F_RXCSUM; 444 if (mtk_wed_device_active(wed)) 445 hw->netdev_features |= NETIF_F_HW_TC; 446 447 hw->radiotap_timestamp.units_pos = 448 IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US; 449 450 hw->sta_data_size = sizeof(struct mt7996_sta); 451 hw->vif_data_size = sizeof(struct mt7996_vif); 452 hw->chanctx_data_size = sizeof(struct mt76_chanctx); 453 454 wiphy->iface_combinations = &if_comb_global; 455 wiphy->n_iface_combinations = 1; 456 457 wiphy->radio = dev->radios; 458 459 wiphy->reg_notifier = mt7996_regd_notifier; 460 wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; 461 wiphy->mbssid_max_interfaces = 16; 462 463 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR); 464 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS); 465 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_LEGACY); 466 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HT); 467 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_VHT); 468 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HE); 469 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP); 470 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_FILS_DISCOVERY); 471 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT); 472 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 473 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_MU_MIMO_AIR_SNIFFER); 474 475 if (mt7996_has_background_radar(dev) && 476 (!mdev->dev->of_node || 477 !of_property_read_bool(mdev->dev->of_node, 478 "mediatek,disable-radar-background"))) 479 wiphy_ext_feature_set(wiphy, 480 NL80211_EXT_FEATURE_RADAR_BACKGROUND); 481 482 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 483 ieee80211_hw_set(hw, SUPPORTS_TX_ENCAP_OFFLOAD); 484 ieee80211_hw_set(hw, SUPPORTS_RX_DECAP_OFFLOAD); 485 ieee80211_hw_set(hw, NO_VIRTUAL_MONITOR); 486 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 487 488 hw->max_tx_fragments = 4; 489 490 /* init led callbacks */ 491 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 492 dev->mphy.leds.cdev.brightness_set = mt7996_led_set_brightness; 493 dev->mphy.leds.cdev.blink_set = mt7996_led_set_blink; 494 } 495 496 wiphy->max_scan_ssids = 4; 497 wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN; 498 499 mt7996_init_wiphy_band(hw, &dev->phy); 500 } 501 502 static void 503 mt7996_mac_init_band(struct mt7996_dev *dev, u8 band) 504 { 505 u32 mask, set; 506 507 /* clear estimated value of EIFS for Rx duration & OBSS time */ 508 mt76_wr(dev, MT_WF_RMAC_RSVD0(band), MT_WF_RMAC_RSVD0_EIFS_CLR); 509 510 /* clear backoff time for Rx duration */ 511 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME1(band), 512 MT_WF_RMAC_MIB_NONQOSD_BACKOFF); 513 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME3(band), 514 MT_WF_RMAC_MIB_QOS01_BACKOFF); 515 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME4(band), 516 MT_WF_RMAC_MIB_QOS23_BACKOFF); 517 518 /* clear backoff time for Tx duration */ 519 mt76_clear(dev, MT_WTBLOFF_ACR(band), 520 MT_WTBLOFF_ADM_BACKOFFTIME); 521 522 /* clear backoff time and set software compensation for OBSS time */ 523 mask = MT_WF_RMAC_MIB_OBSS_BACKOFF | MT_WF_RMAC_MIB_ED_OFFSET; 524 set = FIELD_PREP(MT_WF_RMAC_MIB_OBSS_BACKOFF, 0) | 525 FIELD_PREP(MT_WF_RMAC_MIB_ED_OFFSET, 4); 526 mt76_rmw(dev, MT_WF_RMAC_MIB_AIRTIME0(band), mask, set); 527 528 /* filter out non-resp frames and get instanstaeous signal reporting */ 529 mask = MT_WTBLOFF_RSCR_RCPI_MODE | MT_WTBLOFF_RSCR_RCPI_PARAM; 530 set = FIELD_PREP(MT_WTBLOFF_RSCR_RCPI_MODE, 0) | 531 FIELD_PREP(MT_WTBLOFF_RSCR_RCPI_PARAM, 0x3); 532 mt76_rmw(dev, MT_WTBLOFF_RSCR(band), mask, set); 533 534 /* MT_TXD5_TX_STATUS_HOST (MPDU format) has higher priority than 535 * MT_AGG_ACR_PPDU_TXS2H (PPDU format) even though ACR bit is set. 536 */ 537 mt76_set(dev, MT_AGG_ACR4(band), MT_AGG_ACR_PPDU_TXS2H); 538 } 539 540 static void mt7996_mac_init_basic_rates(struct mt7996_dev *dev) 541 { 542 int i; 543 544 for (i = 0; i < ARRAY_SIZE(mt76_rates); i++) { 545 u16 rate = mt76_rates[i].hw_value; 546 /* odd index for driver, even index for firmware */ 547 u16 idx = MT7996_BASIC_RATES_TBL + 2 * i; 548 549 rate = FIELD_PREP(MT_TX_RATE_MODE, rate >> 8) | 550 FIELD_PREP(MT_TX_RATE_IDX, rate & GENMASK(7, 0)); 551 mt7996_mcu_set_fixed_rate_table(&dev->phy, idx, rate, false); 552 } 553 } 554 555 void mt7996_mac_init(struct mt7996_dev *dev) 556 { 557 #define HIF_TXD_V2_1 0x21 558 int i; 559 560 mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT); 561 562 for (i = 0; i < mt7996_wtbl_size(dev); i++) 563 mt7996_mac_wtbl_update(dev, i, 564 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 565 566 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 567 i = dev->mphy.leds.pin ? MT_LED_GPIO_MUX3 : MT_LED_GPIO_MUX2; 568 mt76_rmw_field(dev, i, MT_LED_GPIO_SEL_MASK, 4); 569 } 570 571 /* rro module init */ 572 if (is_mt7996(&dev->mt76)) 573 mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 2); 574 else 575 mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 576 dev->hif2 ? 7 : 0); 577 578 if (dev->has_rro) { 579 u16 timeout; 580 581 timeout = mt76_rr(dev, MT_HW_REV) == MT_HW_REV1 ? 512 : 128; 582 mt7996_mcu_set_rro(dev, UNI_RRO_SET_FLUSH_TIMEOUT, timeout); 583 mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 1); 584 mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 0); 585 } else { 586 mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 3); 587 mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 1); 588 } 589 590 mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), 591 MCU_WA_PARAM_HW_PATH_HIF_VER, 592 HIF_TXD_V2_1, 0); 593 594 for (i = MT_BAND0; i <= MT_BAND2; i++) 595 mt7996_mac_init_band(dev, i); 596 597 mt7996_mac_init_basic_rates(dev); 598 } 599 600 int mt7996_txbf_init(struct mt7996_dev *dev) 601 { 602 int ret; 603 604 if (mt7996_band_valid(dev, MT_BAND1) || 605 mt7996_band_valid(dev, MT_BAND2)) { 606 ret = mt7996_mcu_set_txbf(dev, BF_MOD_EN_CTRL); 607 if (ret) 608 return ret; 609 } 610 611 /* trigger sounding packets */ 612 ret = mt7996_mcu_set_txbf(dev, BF_SOUNDING_ON); 613 if (ret) 614 return ret; 615 616 /* enable eBF */ 617 return mt7996_mcu_set_txbf(dev, BF_HW_EN_UPDATE); 618 } 619 620 static int mt7996_register_phy(struct mt7996_dev *dev, enum mt76_band_id band) 621 { 622 struct mt7996_phy *phy; 623 struct mt76_phy *mphy; 624 u32 mac_ofs, hif1_ofs = 0; 625 int ret; 626 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 627 628 if (!mt7996_band_valid(dev, band)) 629 return 0; 630 631 if (is_mt7996(&dev->mt76) && band == MT_BAND2 && dev->hif2) { 632 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); 633 wed = &dev->mt76.mmio.wed_hif2; 634 } 635 636 mphy = mt76_alloc_radio_phy(&dev->mt76, sizeof(*phy), band); 637 if (!mphy) 638 return -ENOMEM; 639 640 phy = mphy->priv; 641 phy->dev = dev; 642 phy->mt76 = mphy; 643 mphy->dev->phys[band] = mphy; 644 645 INIT_DELAYED_WORK(&mphy->mac_work, mt7996_mac_work); 646 647 ret = mt7996_eeprom_parse_hw_cap(dev, phy); 648 if (ret) 649 goto error; 650 651 mac_ofs = band == MT_BAND2 ? MT_EE_MAC_ADDR3 : MT_EE_MAC_ADDR2; 652 memcpy(mphy->macaddr, dev->mt76.eeprom.data + mac_ofs, ETH_ALEN); 653 /* Make the extra PHY MAC address local without overlapping with 654 * the usual MAC address allocation scheme on multiple virtual interfaces 655 */ 656 if (!is_valid_ether_addr(mphy->macaddr)) { 657 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR, 658 ETH_ALEN); 659 mphy->macaddr[0] |= 2; 660 mphy->macaddr[0] ^= BIT(7); 661 if (band == MT_BAND2) 662 mphy->macaddr[0] ^= BIT(6); 663 } 664 mt76_eeprom_override(mphy); 665 666 /* init wiphy according to mphy and phy */ 667 mt7996_init_wiphy_band(mphy->hw, phy); 668 ret = mt7996_init_tx_queues(mphy->priv, 669 MT_TXQ_ID(band), 670 MT7996_TX_RING_SIZE, 671 MT_TXQ_RING_BASE(band) + hif1_ofs, 672 wed); 673 if (ret) 674 goto error; 675 676 ret = mt76_register_phy(mphy, true, mt76_rates, 677 ARRAY_SIZE(mt76_rates)); 678 if (ret) 679 goto error; 680 681 if (wed == &dev->mt76.mmio.wed_hif2 && mtk_wed_device_active(wed)) { 682 u32 irq_mask = dev->mt76.mmio.irqmask | MT_INT_TX_DONE_BAND2; 683 684 mt76_wr(dev, MT_INT1_MASK_CSR, irq_mask); 685 mtk_wed_device_start(&dev->mt76.mmio.wed_hif2, irq_mask); 686 } 687 688 return 0; 689 690 error: 691 mphy->dev->phys[band] = NULL; 692 return ret; 693 } 694 695 static void 696 mt7996_unregister_phy(struct mt7996_phy *phy) 697 { 698 if (phy) 699 mt7996_unregister_thermal(phy); 700 } 701 702 static void mt7996_init_work(struct work_struct *work) 703 { 704 struct mt7996_dev *dev = container_of(work, struct mt7996_dev, 705 init_work); 706 707 mt7996_mcu_set_eeprom(dev); 708 mt7996_mac_init(dev); 709 mt7996_txbf_init(dev); 710 } 711 712 void mt7996_wfsys_reset(struct mt7996_dev *dev) 713 { 714 mt76_set(dev, MT_WF_SUBSYS_RST, 0x1); 715 msleep(20); 716 717 mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1); 718 msleep(20); 719 } 720 721 static int mt7996_wed_rro_init(struct mt7996_dev *dev) 722 { 723 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 724 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 725 u32 reg = MT_RRO_ADDR_ELEM_SEG_ADDR0; 726 struct mt7996_wed_rro_addr *addr; 727 void *ptr; 728 int i; 729 730 if (!dev->has_rro) 731 return 0; 732 733 if (!mtk_wed_device_active(wed)) 734 return 0; 735 736 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.ba_bitmap); i++) { 737 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 738 MT7996_RRO_BA_BITMAP_CR_SIZE, 739 &dev->wed_rro.ba_bitmap[i].phy_addr, 740 GFP_KERNEL); 741 if (!ptr) 742 return -ENOMEM; 743 744 dev->wed_rro.ba_bitmap[i].ptr = ptr; 745 } 746 747 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) { 748 int j; 749 750 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 751 MT7996_RRO_WINDOW_MAX_SIZE * sizeof(*addr), 752 &dev->wed_rro.addr_elem[i].phy_addr, 753 GFP_KERNEL); 754 if (!ptr) 755 return -ENOMEM; 756 757 dev->wed_rro.addr_elem[i].ptr = ptr; 758 memset(dev->wed_rro.addr_elem[i].ptr, 0, 759 MT7996_RRO_WINDOW_MAX_SIZE * sizeof(*addr)); 760 761 addr = dev->wed_rro.addr_elem[i].ptr; 762 for (j = 0; j < MT7996_RRO_WINDOW_MAX_SIZE; j++) { 763 addr->signature = 0xff; 764 addr++; 765 } 766 767 wed->wlan.ind_cmd.addr_elem_phys[i] = 768 dev->wed_rro.addr_elem[i].phy_addr; 769 } 770 771 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 772 MT7996_RRO_WINDOW_MAX_LEN * sizeof(*addr), 773 &dev->wed_rro.session.phy_addr, 774 GFP_KERNEL); 775 if (!ptr) 776 return -ENOMEM; 777 778 dev->wed_rro.session.ptr = ptr; 779 addr = dev->wed_rro.session.ptr; 780 for (i = 0; i < MT7996_RRO_WINDOW_MAX_LEN; i++) { 781 addr->signature = 0xff; 782 addr++; 783 } 784 785 /* rro hw init */ 786 /* TODO: remove line after WM has set */ 787 mt76_clear(dev, WF_RRO_AXI_MST_CFG, WF_RRO_AXI_MST_CFG_DIDX_OK); 788 789 /* setup BA bitmap cache address */ 790 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE0, 791 dev->wed_rro.ba_bitmap[0].phy_addr); 792 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE1, 0); 793 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE_EXT0, 794 dev->wed_rro.ba_bitmap[1].phy_addr); 795 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE_EXT1, 0); 796 797 /* setup Address element address */ 798 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) { 799 mt76_wr(dev, reg, dev->wed_rro.addr_elem[i].phy_addr >> 4); 800 reg += 4; 801 } 802 803 /* setup Address element address - separate address segment mode */ 804 mt76_wr(dev, MT_RRO_ADDR_ARRAY_BASE1, 805 MT_RRO_ADDR_ARRAY_ELEM_ADDR_SEG_MODE); 806 807 wed->wlan.ind_cmd.win_size = ffs(MT7996_RRO_WINDOW_MAX_LEN) - 6; 808 wed->wlan.ind_cmd.particular_sid = MT7996_RRO_MAX_SESSION; 809 wed->wlan.ind_cmd.particular_se_phys = dev->wed_rro.session.phy_addr; 810 wed->wlan.ind_cmd.se_group_nums = MT7996_RRO_ADDR_ELEM_LEN; 811 wed->wlan.ind_cmd.ack_sn_addr = MT_RRO_ACK_SN_CTRL; 812 813 mt76_wr(dev, MT_RRO_IND_CMD_SIGNATURE_BASE0, 0x15010e00); 814 mt76_set(dev, MT_RRO_IND_CMD_SIGNATURE_BASE1, 815 MT_RRO_IND_CMD_SIGNATURE_BASE1_EN); 816 817 /* particular session configure */ 818 /* use max session idx + 1 as particular session id */ 819 mt76_wr(dev, MT_RRO_PARTICULAR_CFG0, dev->wed_rro.session.phy_addr); 820 mt76_wr(dev, MT_RRO_PARTICULAR_CFG1, 821 MT_RRO_PARTICULAR_CONFG_EN | 822 FIELD_PREP(MT_RRO_PARTICULAR_SID, MT7996_RRO_MAX_SESSION)); 823 824 /* interrupt enable */ 825 mt76_wr(dev, MT_RRO_HOST_INT_ENA, 826 MT_RRO_HOST_INT_ENA_HOST_RRO_DONE_ENA); 827 828 /* rro ind cmd queue init */ 829 return mt7996_dma_rro_init(dev); 830 #else 831 return 0; 832 #endif 833 } 834 835 static void mt7996_wed_rro_free(struct mt7996_dev *dev) 836 { 837 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 838 int i; 839 840 if (!dev->has_rro) 841 return; 842 843 if (!mtk_wed_device_active(&dev->mt76.mmio.wed)) 844 return; 845 846 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.ba_bitmap); i++) { 847 if (!dev->wed_rro.ba_bitmap[i].ptr) 848 continue; 849 850 dmam_free_coherent(dev->mt76.dma_dev, 851 MT7996_RRO_BA_BITMAP_CR_SIZE, 852 dev->wed_rro.ba_bitmap[i].ptr, 853 dev->wed_rro.ba_bitmap[i].phy_addr); 854 } 855 856 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) { 857 if (!dev->wed_rro.addr_elem[i].ptr) 858 continue; 859 860 dmam_free_coherent(dev->mt76.dma_dev, 861 MT7996_RRO_WINDOW_MAX_SIZE * 862 sizeof(struct mt7996_wed_rro_addr), 863 dev->wed_rro.addr_elem[i].ptr, 864 dev->wed_rro.addr_elem[i].phy_addr); 865 } 866 867 if (!dev->wed_rro.session.ptr) 868 return; 869 870 dmam_free_coherent(dev->mt76.dma_dev, 871 MT7996_RRO_WINDOW_MAX_LEN * 872 sizeof(struct mt7996_wed_rro_addr), 873 dev->wed_rro.session.ptr, 874 dev->wed_rro.session.phy_addr); 875 #endif 876 } 877 878 static void mt7996_wed_rro_work(struct work_struct *work) 879 { 880 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 881 struct mt7996_dev *dev; 882 LIST_HEAD(list); 883 884 dev = (struct mt7996_dev *)container_of(work, struct mt7996_dev, 885 wed_rro.work); 886 887 spin_lock_bh(&dev->wed_rro.lock); 888 list_splice_init(&dev->wed_rro.poll_list, &list); 889 spin_unlock_bh(&dev->wed_rro.lock); 890 891 while (!list_empty(&list)) { 892 struct mt7996_wed_rro_session_id *e; 893 int i; 894 895 e = list_first_entry(&list, struct mt7996_wed_rro_session_id, 896 list); 897 list_del_init(&e->list); 898 899 for (i = 0; i < MT7996_RRO_WINDOW_MAX_LEN; i++) { 900 void *ptr = dev->wed_rro.session.ptr; 901 struct mt7996_wed_rro_addr *elem; 902 u32 idx, elem_id = i; 903 904 if (e->id == MT7996_RRO_MAX_SESSION) 905 goto reset; 906 907 idx = e->id / MT7996_RRO_BA_BITMAP_SESSION_SIZE; 908 if (idx >= ARRAY_SIZE(dev->wed_rro.addr_elem)) 909 goto out; 910 911 ptr = dev->wed_rro.addr_elem[idx].ptr; 912 elem_id += 913 (e->id % MT7996_RRO_BA_BITMAP_SESSION_SIZE) * 914 MT7996_RRO_WINDOW_MAX_LEN; 915 reset: 916 elem = ptr + elem_id * sizeof(*elem); 917 elem->signature = 0xff; 918 } 919 mt7996_mcu_wed_rro_reset_sessions(dev, e->id); 920 out: 921 kfree(e); 922 } 923 #endif 924 } 925 926 static int mt7996_variant_type_init(struct mt7996_dev *dev) 927 { 928 u32 val = mt76_rr(dev, MT_PAD_GPIO); 929 u8 var_type; 930 931 switch (mt76_chip(&dev->mt76)) { 932 case 0x7990: 933 if (val & MT_PAD_GPIO_2ADIE_TBTC) 934 var_type = MT7996_VAR_TYPE_233; 935 else 936 var_type = MT7996_VAR_TYPE_444; 937 break; 938 case 0x7992: 939 if (val & MT_PAD_GPIO_ADIE_SINGLE) 940 var_type = MT7992_VAR_TYPE_23; 941 else if (u32_get_bits(val, MT_PAD_GPIO_ADIE_COMB_7992)) 942 var_type = MT7992_VAR_TYPE_44; 943 else 944 return -EINVAL; 945 break; 946 default: 947 return -EINVAL; 948 } 949 950 dev->var.type = var_type; 951 return 0; 952 } 953 954 static int mt7996_variant_fem_init(struct mt7996_dev *dev) 955 { 956 #define MT7976C_EFUSE_OFFSET 0x470 957 u8 buf[MT7996_EEPROM_BLOCK_SIZE], idx, adie_idx, adie_comb; 958 u32 regval, val = mt76_rr(dev, MT_PAD_GPIO); 959 u16 adie_id, adie_ver; 960 bool is_7976c; 961 int ret; 962 963 if (is_mt7992(&dev->mt76)) { 964 adie_idx = (val & MT_PAD_GPIO_ADIE_SINGLE) ? 0 : 1; 965 adie_comb = u32_get_bits(val, MT_PAD_GPIO_ADIE_COMB_7992); 966 } else { 967 adie_idx = 0; 968 adie_comb = u32_get_bits(val, MT_PAD_GPIO_ADIE_COMB); 969 } 970 971 ret = mt7996_mcu_rf_regval(dev, MT_ADIE_CHIP_ID(adie_idx), ®val, false); 972 if (ret) 973 return ret; 974 975 ret = mt7996_mcu_get_eeprom(dev, MT7976C_EFUSE_OFFSET, buf, sizeof(buf)); 976 if (ret && ret != -EINVAL) 977 return ret; 978 979 adie_ver = u32_get_bits(regval, MT_ADIE_VERSION_MASK); 980 idx = MT7976C_EFUSE_OFFSET % MT7996_EEPROM_BLOCK_SIZE; 981 is_7976c = adie_ver == 0x8a10 || adie_ver == 0x8b00 || 982 adie_ver == 0x8c10 || buf[idx] == 0xc; 983 984 adie_id = u32_get_bits(regval, MT_ADIE_CHIP_ID_MASK); 985 if (adie_id == 0x7975 || adie_id == 0x7979 || 986 (adie_id == 0x7976 && is_7976c)) 987 dev->var.fem = MT7996_FEM_INT; 988 else if (adie_id == 0x7977 && adie_comb == 1) 989 dev->var.fem = MT7996_FEM_MIX; 990 else 991 dev->var.fem = MT7996_FEM_EXT; 992 993 return 0; 994 } 995 996 static int mt7996_init_hardware(struct mt7996_dev *dev) 997 { 998 int ret, idx; 999 1000 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 1001 if (is_mt7992(&dev->mt76)) { 1002 mt76_rmw(dev, MT_AFE_CTL_BAND_PLL_03(MT_BAND0), MT_AFE_CTL_BAND_PLL_03_MSB_EN, 0); 1003 mt76_rmw(dev, MT_AFE_CTL_BAND_PLL_03(MT_BAND1), MT_AFE_CTL_BAND_PLL_03_MSB_EN, 0); 1004 } 1005 1006 INIT_WORK(&dev->init_work, mt7996_init_work); 1007 INIT_WORK(&dev->wed_rro.work, mt7996_wed_rro_work); 1008 INIT_LIST_HEAD(&dev->wed_rro.poll_list); 1009 spin_lock_init(&dev->wed_rro.lock); 1010 1011 ret = mt7996_variant_type_init(dev); 1012 if (ret) 1013 return ret; 1014 1015 ret = mt7996_dma_init(dev); 1016 if (ret) 1017 return ret; 1018 1019 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state); 1020 1021 ret = mt7996_mcu_init(dev); 1022 if (ret) 1023 return ret; 1024 1025 ret = mt7996_wed_rro_init(dev); 1026 if (ret) 1027 return ret; 1028 1029 ret = mt7996_variant_fem_init(dev); 1030 if (ret) 1031 return ret; 1032 1033 ret = mt7996_eeprom_init(dev); 1034 if (ret < 0) 1035 return ret; 1036 1037 /* Beacon and mgmt frames should occupy wcid 0 */ 1038 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7996_WTBL_STA); 1039 if (idx) 1040 return -ENOSPC; 1041 1042 dev->mt76.global_wcid.idx = idx; 1043 dev->mt76.global_wcid.hw_key_idx = -1; 1044 dev->mt76.global_wcid.tx_info |= MT_WCID_TX_INFO_SET; 1045 rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid); 1046 1047 return 0; 1048 } 1049 1050 void mt7996_set_stream_vht_txbf_caps(struct mt7996_phy *phy) 1051 { 1052 int sts; 1053 u32 *cap; 1054 1055 if (!phy->mt76->cap.has_5ghz) 1056 return; 1057 1058 sts = hweight16(phy->mt76->chainmask); 1059 cap = &phy->mt76->sband_5g.sband.vht_cap.cap; 1060 1061 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | 1062 IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE; 1063 1064 if (is_mt7996(phy->mt76->dev)) 1065 *cap |= FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, 3); 1066 else 1067 *cap |= FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, 4); 1068 1069 *cap &= ~(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK | 1070 IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 1071 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE); 1072 1073 if (sts < 2) 1074 return; 1075 1076 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 1077 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE | 1078 FIELD_PREP(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, sts - 1); 1079 } 1080 1081 static void 1082 mt7996_set_stream_he_txbf_caps(struct mt7996_phy *phy, 1083 struct ieee80211_sta_he_cap *he_cap, int vif) 1084 { 1085 struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem; 1086 int sts = hweight16(phy->mt76->chainmask); 1087 u8 c; 1088 1089 #ifdef CONFIG_MAC80211_MESH 1090 if (vif == NL80211_IFTYPE_MESH_POINT) 1091 return; 1092 #endif 1093 1094 elem->phy_cap_info[3] &= ~IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 1095 elem->phy_cap_info[4] &= ~IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 1096 1097 c = IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK | 1098 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK; 1099 elem->phy_cap_info[5] &= ~c; 1100 1101 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 1102 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 1103 elem->phy_cap_info[6] &= ~c; 1104 1105 elem->phy_cap_info[7] &= ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK; 1106 1107 c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 1108 IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO | 1109 IEEE80211_HE_PHY_CAP2_UL_MU_PARTIAL_MU_MIMO; 1110 elem->phy_cap_info[2] |= c; 1111 1112 c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE; 1113 1114 if (is_mt7996(phy->mt76->dev)) 1115 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4 | 1116 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 1117 else 1118 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_5 | 1119 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_5; 1120 1121 elem->phy_cap_info[4] |= c; 1122 1123 /* do not support NG16 due to spec D4.0 changes subcarrier idx */ 1124 c = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 1125 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU; 1126 1127 if (vif == NL80211_IFTYPE_STATION) 1128 c |= IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO; 1129 1130 elem->phy_cap_info[6] |= c; 1131 1132 if (sts < 2) 1133 return; 1134 1135 /* the maximum cap is 4 x 3, (Nr, Nc) = (3, 2) */ 1136 elem->phy_cap_info[7] |= min_t(int, sts - 1, 2) << 3; 1137 1138 if (!(vif == NL80211_IFTYPE_AP || vif == NL80211_IFTYPE_STATION)) 1139 return; 1140 1141 elem->phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 1142 1143 c = FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 1144 sts - 1) | 1145 FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK, 1146 sts - 1); 1147 elem->phy_cap_info[5] |= c; 1148 1149 if (vif != NL80211_IFTYPE_AP) 1150 return; 1151 1152 elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 1153 1154 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 1155 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 1156 elem->phy_cap_info[6] |= c; 1157 1158 c = IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ | 1159 IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ; 1160 elem->phy_cap_info[7] |= c; 1161 } 1162 1163 static void 1164 mt7996_init_he_caps(struct mt7996_phy *phy, enum nl80211_band band, 1165 struct ieee80211_sband_iftype_data *data, 1166 enum nl80211_iftype iftype) 1167 { 1168 struct ieee80211_sta_he_cap *he_cap = &data->he_cap; 1169 struct ieee80211_he_cap_elem *he_cap_elem = &he_cap->he_cap_elem; 1170 struct ieee80211_he_mcs_nss_supp *he_mcs = &he_cap->he_mcs_nss_supp; 1171 int i, nss = hweight8(phy->mt76->antenna_mask); 1172 u16 mcs_map = 0; 1173 1174 for (i = 0; i < 8; i++) { 1175 if (i < nss) 1176 mcs_map |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 1177 else 1178 mcs_map |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 1179 } 1180 1181 he_cap->has_he = true; 1182 1183 he_cap_elem->mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE; 1184 he_cap_elem->mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 1185 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3; 1186 he_cap_elem->mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 1187 1188 if (band == NL80211_BAND_2GHZ) 1189 he_cap_elem->phy_cap_info[0] = 1190 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 1191 else 1192 he_cap_elem->phy_cap_info[0] = 1193 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 1194 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 1195 1196 he_cap_elem->phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD; 1197 he_cap_elem->phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 1198 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ; 1199 1200 switch (iftype) { 1201 case NL80211_IFTYPE_AP: 1202 he_cap_elem->mac_cap_info[0] |= IEEE80211_HE_MAC_CAP0_TWT_RES; 1203 he_cap_elem->mac_cap_info[2] |= IEEE80211_HE_MAC_CAP2_BSR; 1204 he_cap_elem->mac_cap_info[4] |= IEEE80211_HE_MAC_CAP4_BQR; 1205 he_cap_elem->mac_cap_info[5] |= 1206 IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX; 1207 he_cap_elem->phy_cap_info[3] |= 1208 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1209 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1210 he_cap_elem->phy_cap_info[6] |= 1211 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1212 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1213 he_cap_elem->phy_cap_info[9] |= 1214 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1215 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU; 1216 break; 1217 case NL80211_IFTYPE_STATION: 1218 he_cap_elem->mac_cap_info[1] |= 1219 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 1220 1221 if (band == NL80211_BAND_2GHZ) 1222 he_cap_elem->phy_cap_info[0] |= 1223 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G; 1224 else 1225 he_cap_elem->phy_cap_info[0] |= 1226 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G; 1227 1228 he_cap_elem->phy_cap_info[1] |= 1229 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 1230 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 1231 he_cap_elem->phy_cap_info[3] |= 1232 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1233 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1234 he_cap_elem->phy_cap_info[6] |= 1235 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB | 1236 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1237 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1238 he_cap_elem->phy_cap_info[7] |= 1239 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 1240 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI; 1241 he_cap_elem->phy_cap_info[8] |= 1242 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 1243 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 1244 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU | 1245 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_484; 1246 he_cap_elem->phy_cap_info[9] |= 1247 IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 1248 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK | 1249 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1250 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 1251 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 1252 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB; 1253 break; 1254 default: 1255 break; 1256 } 1257 1258 he_mcs->rx_mcs_80 = cpu_to_le16(mcs_map); 1259 he_mcs->tx_mcs_80 = cpu_to_le16(mcs_map); 1260 he_mcs->rx_mcs_160 = cpu_to_le16(mcs_map); 1261 he_mcs->tx_mcs_160 = cpu_to_le16(mcs_map); 1262 1263 mt7996_set_stream_he_txbf_caps(phy, he_cap, iftype); 1264 1265 memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres)); 1266 if (he_cap_elem->phy_cap_info[6] & 1267 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) { 1268 mt76_connac_gen_ppe_thresh(he_cap->ppe_thres, nss); 1269 } else { 1270 he_cap_elem->phy_cap_info[9] |= 1271 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 1272 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 1273 } 1274 1275 if (band == NL80211_BAND_6GHZ) { 1276 u16 cap = IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS | 1277 IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS; 1278 1279 cap |= u16_encode_bits(IEEE80211_HT_MPDU_DENSITY_0_5, 1280 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 1281 u16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 1282 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 1283 u16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 1284 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 1285 1286 data->he_6ghz_capa.capa = cpu_to_le16(cap); 1287 } 1288 } 1289 1290 static void 1291 mt7996_init_eht_caps(struct mt7996_phy *phy, enum nl80211_band band, 1292 struct ieee80211_sband_iftype_data *data, 1293 enum nl80211_iftype iftype) 1294 { 1295 struct ieee80211_sta_eht_cap *eht_cap = &data->eht_cap; 1296 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem = &eht_cap->eht_cap_elem; 1297 struct ieee80211_eht_mcs_nss_supp *eht_nss = &eht_cap->eht_mcs_nss_supp; 1298 enum nl80211_chan_width width = phy->mt76->chandef.width; 1299 int nss = hweight8(phy->mt76->antenna_mask); 1300 int sts = hweight16(phy->mt76->chainmask); 1301 u8 val; 1302 1303 if (!phy->dev->has_eht) 1304 return; 1305 1306 eht_cap->has_eht = true; 1307 1308 eht_cap_elem->mac_cap_info[0] = 1309 IEEE80211_EHT_MAC_CAP0_EPCS_PRIO_ACCESS | 1310 IEEE80211_EHT_MAC_CAP0_OM_CONTROL; 1311 1312 eht_cap_elem->phy_cap_info[0] = 1313 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI | 1314 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMER | 1315 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE; 1316 1317 /* Set the maximum capability regardless of the antenna configuration. */ 1318 val = is_mt7992(phy->mt76->dev) ? 4 : 3; 1319 eht_cap_elem->phy_cap_info[0] |= 1320 u8_encode_bits(u8_get_bits(val, BIT(0)), 1321 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK); 1322 1323 eht_cap_elem->phy_cap_info[1] = 1324 u8_encode_bits(u8_get_bits(val, GENMASK(2, 1)), 1325 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK) | 1326 u8_encode_bits(val, 1327 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK); 1328 1329 eht_cap_elem->phy_cap_info[2] = 1330 u8_encode_bits(sts - 1, IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_80MHZ_MASK) | 1331 u8_encode_bits(sts - 1, IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_160MHZ_MASK); 1332 1333 if (band == NL80211_BAND_6GHZ) { 1334 eht_cap_elem->phy_cap_info[0] |= 1335 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ; 1336 1337 eht_cap_elem->phy_cap_info[1] |= 1338 u8_encode_bits(val, 1339 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK); 1340 1341 eht_cap_elem->phy_cap_info[2] |= 1342 u8_encode_bits(sts - 1, 1343 IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_320MHZ_MASK); 1344 } 1345 1346 eht_cap_elem->phy_cap_info[3] = 1347 IEEE80211_EHT_PHY_CAP3_NG_16_SU_FEEDBACK | 1348 IEEE80211_EHT_PHY_CAP3_NG_16_MU_FEEDBACK | 1349 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK | 1350 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK; 1351 1352 eht_cap_elem->phy_cap_info[4] = 1353 u8_encode_bits(min_t(int, sts - 1, 2), 1354 IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK); 1355 1356 eht_cap_elem->phy_cap_info[5] = 1357 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_16US, 1358 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK) | 1359 u8_encode_bits(u8_get_bits(0x11, GENMASK(1, 0)), 1360 IEEE80211_EHT_PHY_CAP5_MAX_NUM_SUPP_EHT_LTF_MASK); 1361 1362 val = width == NL80211_CHAN_WIDTH_320 ? 0xf : 1363 width == NL80211_CHAN_WIDTH_160 ? 0x7 : 1364 width == NL80211_CHAN_WIDTH_80 ? 0x3 : 0x1; 1365 eht_cap_elem->phy_cap_info[6] = 1366 u8_encode_bits(u8_get_bits(0x11, GENMASK(4, 2)), 1367 IEEE80211_EHT_PHY_CAP6_MAX_NUM_SUPP_EHT_LTF_MASK) | 1368 u8_encode_bits(val, IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_MASK); 1369 1370 val = u8_encode_bits(nss, IEEE80211_EHT_MCS_NSS_RX) | 1371 u8_encode_bits(nss, IEEE80211_EHT_MCS_NSS_TX); 1372 #define SET_EHT_MAX_NSS(_bw, _val) do { \ 1373 eht_nss->bw._##_bw.rx_tx_mcs9_max_nss = _val; \ 1374 eht_nss->bw._##_bw.rx_tx_mcs11_max_nss = _val; \ 1375 eht_nss->bw._##_bw.rx_tx_mcs13_max_nss = _val; \ 1376 } while (0) 1377 1378 SET_EHT_MAX_NSS(80, val); 1379 SET_EHT_MAX_NSS(160, val); 1380 if (band == NL80211_BAND_6GHZ) 1381 SET_EHT_MAX_NSS(320, val); 1382 #undef SET_EHT_MAX_NSS 1383 1384 if (iftype != NL80211_IFTYPE_AP) 1385 return; 1386 1387 eht_cap_elem->phy_cap_info[3] |= 1388 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK | 1389 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK; 1390 1391 eht_cap_elem->phy_cap_info[7] = 1392 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_80MHZ | 1393 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_160MHZ | 1394 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_80MHZ | 1395 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_160MHZ; 1396 1397 if (band != NL80211_BAND_6GHZ) 1398 return; 1399 1400 eht_cap_elem->phy_cap_info[7] |= 1401 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_320MHZ | 1402 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_320MHZ; 1403 } 1404 1405 static void 1406 __mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy, 1407 struct ieee80211_supported_band *sband, 1408 enum nl80211_band band) 1409 { 1410 struct ieee80211_sband_iftype_data *data = phy->iftype[band]; 1411 int i, n = 0; 1412 1413 for (i = 0; i < NUM_NL80211_IFTYPES; i++) { 1414 switch (i) { 1415 case NL80211_IFTYPE_STATION: 1416 case NL80211_IFTYPE_AP: 1417 #ifdef CONFIG_MAC80211_MESH 1418 case NL80211_IFTYPE_MESH_POINT: 1419 #endif 1420 break; 1421 default: 1422 continue; 1423 } 1424 1425 data[n].types_mask = BIT(i); 1426 mt7996_init_he_caps(phy, band, &data[n], i); 1427 mt7996_init_eht_caps(phy, band, &data[n], i); 1428 1429 n++; 1430 } 1431 1432 _ieee80211_set_sband_iftype_data(sband, data, n); 1433 } 1434 1435 void mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy) 1436 { 1437 if (phy->mt76->cap.has_2ghz) 1438 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_2g.sband, 1439 NL80211_BAND_2GHZ); 1440 1441 if (phy->mt76->cap.has_5ghz) 1442 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_5g.sband, 1443 NL80211_BAND_5GHZ); 1444 1445 if (phy->mt76->cap.has_6ghz) 1446 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_6g.sband, 1447 NL80211_BAND_6GHZ); 1448 } 1449 1450 int mt7996_register_device(struct mt7996_dev *dev) 1451 { 1452 struct ieee80211_hw *hw = mt76_hw(dev); 1453 struct mt7996_phy *phy; 1454 int ret; 1455 1456 dev->phy.dev = dev; 1457 dev->phy.mt76 = &dev->mt76.phy; 1458 dev->mt76.phy.priv = &dev->phy; 1459 INIT_WORK(&dev->rc_work, mt7996_mac_sta_rc_work); 1460 INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7996_mac_work); 1461 INIT_LIST_HEAD(&dev->sta_rc_list); 1462 INIT_LIST_HEAD(&dev->twt_list); 1463 1464 init_waitqueue_head(&dev->reset_wait); 1465 INIT_WORK(&dev->reset_work, mt7996_mac_reset_work); 1466 INIT_WORK(&dev->dump_work, mt7996_mac_dump_work); 1467 mutex_init(&dev->dump_mutex); 1468 1469 ret = mt7996_init_hardware(dev); 1470 if (ret) 1471 return ret; 1472 1473 mt7996_init_wiphy(hw, &dev->mt76.mmio.wed); 1474 1475 ret = mt7996_register_phy(dev, MT_BAND1); 1476 if (ret) 1477 return ret; 1478 1479 ret = mt7996_register_phy(dev, MT_BAND2); 1480 if (ret) 1481 return ret; 1482 1483 ret = mt76_register_device(&dev->mt76, true, mt76_rates, 1484 ARRAY_SIZE(mt76_rates)); 1485 if (ret) 1486 return ret; 1487 1488 mt7996_for_each_phy(dev, phy) 1489 mt7996_thermal_init(phy); 1490 1491 ieee80211_queue_work(mt76_hw(dev), &dev->init_work); 1492 1493 dev->recovery.hw_init_done = true; 1494 1495 ret = mt7996_init_debugfs(dev); 1496 if (ret) 1497 goto error; 1498 1499 ret = mt7996_coredump_register(dev); 1500 if (ret) 1501 goto error; 1502 1503 return 0; 1504 1505 error: 1506 cancel_work_sync(&dev->init_work); 1507 1508 return ret; 1509 } 1510 1511 void mt7996_unregister_device(struct mt7996_dev *dev) 1512 { 1513 cancel_work_sync(&dev->wed_rro.work); 1514 mt7996_unregister_phy(mt7996_phy3(dev)); 1515 mt7996_unregister_phy(mt7996_phy2(dev)); 1516 mt7996_unregister_thermal(&dev->phy); 1517 mt7996_coredump_unregister(dev); 1518 mt76_unregister_device(&dev->mt76); 1519 mt7996_wed_rro_free(dev); 1520 mt7996_mcu_exit(dev); 1521 mt7996_tx_token_put(dev); 1522 mt7996_dma_cleanup(dev); 1523 tasklet_disable(&dev->mt76.irq_tasklet); 1524 1525 mt76_free_device(&dev->mt76); 1526 } 1527