1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #include <linux/etherdevice.h> 7 #include <linux/thermal.h> 8 #include "mt7996.h" 9 #include "mac.h" 10 #include "mcu.h" 11 #include "coredump.h" 12 #include "eeprom.h" 13 14 static const struct ieee80211_iface_limit if_limits[] = { 15 { 16 .max = 1, 17 .types = BIT(NL80211_IFTYPE_ADHOC) 18 }, { 19 .max = 16, 20 .types = BIT(NL80211_IFTYPE_AP) 21 #ifdef CONFIG_MAC80211_MESH 22 | BIT(NL80211_IFTYPE_MESH_POINT) 23 #endif 24 }, { 25 .max = MT7996_MAX_INTERFACES, 26 .types = BIT(NL80211_IFTYPE_STATION) 27 } 28 }; 29 30 static const struct ieee80211_iface_combination if_comb[] = { 31 { 32 .limits = if_limits, 33 .n_limits = ARRAY_SIZE(if_limits), 34 .max_interfaces = MT7996_MAX_INTERFACES, 35 .num_different_channels = 1, 36 .beacon_int_infra_match = true, 37 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 38 BIT(NL80211_CHAN_WIDTH_20) | 39 BIT(NL80211_CHAN_WIDTH_40) | 40 BIT(NL80211_CHAN_WIDTH_80) | 41 BIT(NL80211_CHAN_WIDTH_160), 42 } 43 }; 44 45 static void mt7996_led_set_config(struct led_classdev *led_cdev, 46 u8 delay_on, u8 delay_off) 47 { 48 struct mt7996_dev *dev; 49 struct mt76_phy *mphy; 50 u32 val; 51 52 mphy = container_of(led_cdev, struct mt76_phy, leds.cdev); 53 dev = container_of(mphy->dev, struct mt7996_dev, mt76); 54 55 /* select TX blink mode, 2: only data frames */ 56 mt76_rmw_field(dev, MT_TMAC_TCR0(0), MT_TMAC_TCR0_TX_BLINK, 2); 57 58 /* enable LED */ 59 mt76_wr(dev, MT_LED_EN(0), 1); 60 61 /* set LED Tx blink on/off time */ 62 val = FIELD_PREP(MT_LED_TX_BLINK_ON_MASK, delay_on) | 63 FIELD_PREP(MT_LED_TX_BLINK_OFF_MASK, delay_off); 64 mt76_wr(dev, MT_LED_TX_BLINK(0), val); 65 66 /* control LED */ 67 val = MT_LED_CTRL_BLINK_MODE | MT_LED_CTRL_KICK; 68 if (mphy->leds.al) 69 val |= MT_LED_CTRL_POLARITY; 70 71 mt76_wr(dev, MT_LED_CTRL(0), val); 72 mt76_clear(dev, MT_LED_CTRL(0), MT_LED_CTRL_KICK); 73 } 74 75 static int mt7996_led_set_blink(struct led_classdev *led_cdev, 76 unsigned long *delay_on, 77 unsigned long *delay_off) 78 { 79 u16 delta_on = 0, delta_off = 0; 80 81 #define HW_TICK 10 82 #define TO_HW_TICK(_t) (((_t) > HW_TICK) ? ((_t) / HW_TICK) : HW_TICK) 83 84 if (*delay_on) 85 delta_on = TO_HW_TICK(*delay_on); 86 if (*delay_off) 87 delta_off = TO_HW_TICK(*delay_off); 88 89 mt7996_led_set_config(led_cdev, delta_on, delta_off); 90 91 return 0; 92 } 93 94 static void mt7996_led_set_brightness(struct led_classdev *led_cdev, 95 enum led_brightness brightness) 96 { 97 if (!brightness) 98 mt7996_led_set_config(led_cdev, 0, 0xff); 99 else 100 mt7996_led_set_config(led_cdev, 0xff, 0); 101 } 102 103 void mt7996_init_txpower(struct mt7996_dev *dev, 104 struct ieee80211_supported_band *sband) 105 { 106 int i, nss = hweight8(dev->mphy.antenna_mask); 107 int nss_delta = mt76_tx_power_nss_delta(nss); 108 int pwr_delta = mt7996_eeprom_get_power_delta(dev, sband->band); 109 struct mt76_power_limits limits; 110 111 for (i = 0; i < sband->n_channels; i++) { 112 struct ieee80211_channel *chan = &sband->channels[i]; 113 int target_power = mt7996_eeprom_get_target_power(dev, chan); 114 115 target_power += pwr_delta; 116 target_power = mt76_get_rate_power_limits(&dev->mphy, chan, 117 &limits, 118 target_power); 119 target_power += nss_delta; 120 target_power = DIV_ROUND_UP(target_power, 2); 121 chan->max_power = min_t(int, chan->max_reg_power, 122 target_power); 123 chan->orig_mpwr = target_power; 124 } 125 } 126 127 static void 128 mt7996_regd_notifier(struct wiphy *wiphy, 129 struct regulatory_request *request) 130 { 131 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 132 struct mt7996_dev *dev = mt7996_hw_dev(hw); 133 struct mt7996_phy *phy = mt7996_hw_phy(hw); 134 135 memcpy(dev->mt76.alpha2, request->alpha2, sizeof(dev->mt76.alpha2)); 136 dev->mt76.region = request->dfs_region; 137 138 if (dev->mt76.region == NL80211_DFS_UNSET) 139 mt7996_mcu_rdd_background_enable(phy, NULL); 140 141 mt7996_init_txpower(dev, &phy->mt76->sband_2g.sband); 142 mt7996_init_txpower(dev, &phy->mt76->sband_5g.sband); 143 mt7996_init_txpower(dev, &phy->mt76->sband_6g.sband); 144 145 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN; 146 mt7996_dfs_init_radar_detector(phy); 147 } 148 149 static void 150 mt7996_init_wiphy(struct ieee80211_hw *hw) 151 { 152 struct mt7996_phy *phy = mt7996_hw_phy(hw); 153 struct mt76_dev *mdev = &phy->dev->mt76; 154 struct wiphy *wiphy = hw->wiphy; 155 u16 max_subframes = phy->dev->has_eht ? IEEE80211_MAX_AMPDU_BUF_EHT : 156 IEEE80211_MAX_AMPDU_BUF_HE; 157 158 hw->queues = 4; 159 hw->max_rx_aggregation_subframes = max_subframes; 160 hw->max_tx_aggregation_subframes = max_subframes; 161 hw->netdev_features = NETIF_F_RXCSUM; 162 163 hw->radiotap_timestamp.units_pos = 164 IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US; 165 166 phy->slottime = 9; 167 168 hw->sta_data_size = sizeof(struct mt7996_sta); 169 hw->vif_data_size = sizeof(struct mt7996_vif); 170 171 wiphy->iface_combinations = if_comb; 172 wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); 173 wiphy->reg_notifier = mt7996_regd_notifier; 174 wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; 175 176 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR); 177 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS); 178 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_LEGACY); 179 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HT); 180 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_VHT); 181 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HE); 182 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP); 183 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_FILS_DISCOVERY); 184 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT); 185 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 186 187 if (!mdev->dev->of_node || 188 !of_property_read_bool(mdev->dev->of_node, 189 "mediatek,disable-radar-background")) 190 wiphy_ext_feature_set(wiphy, 191 NL80211_EXT_FEATURE_RADAR_BACKGROUND); 192 193 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 194 ieee80211_hw_set(hw, SUPPORTS_TX_ENCAP_OFFLOAD); 195 ieee80211_hw_set(hw, SUPPORTS_RX_DECAP_OFFLOAD); 196 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 197 198 hw->max_tx_fragments = 4; 199 200 if (phy->mt76->cap.has_2ghz) { 201 phy->mt76->sband_2g.sband.ht_cap.cap |= 202 IEEE80211_HT_CAP_LDPC_CODING | 203 IEEE80211_HT_CAP_MAX_AMSDU; 204 phy->mt76->sband_2g.sband.ht_cap.ampdu_density = 205 IEEE80211_HT_MPDU_DENSITY_2; 206 } 207 208 if (phy->mt76->cap.has_5ghz) { 209 phy->mt76->sband_5g.sband.ht_cap.cap |= 210 IEEE80211_HT_CAP_LDPC_CODING | 211 IEEE80211_HT_CAP_MAX_AMSDU; 212 213 phy->mt76->sband_5g.sband.vht_cap.cap |= 214 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 215 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 216 IEEE80211_VHT_CAP_SHORT_GI_160 | 217 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ; 218 phy->mt76->sband_5g.sband.ht_cap.ampdu_density = 219 IEEE80211_HT_MPDU_DENSITY_1; 220 } 221 222 mt76_set_stream_caps(phy->mt76, true); 223 mt7996_set_stream_vht_txbf_caps(phy); 224 mt7996_set_stream_he_eht_caps(phy); 225 226 wiphy->available_antennas_rx = phy->mt76->antenna_mask; 227 wiphy->available_antennas_tx = phy->mt76->antenna_mask; 228 } 229 230 static void 231 mt7996_mac_init_band(struct mt7996_dev *dev, u8 band) 232 { 233 u32 mask, set; 234 235 /* clear estimated value of EIFS for Rx duration & OBSS time */ 236 mt76_wr(dev, MT_WF_RMAC_RSVD0(band), MT_WF_RMAC_RSVD0_EIFS_CLR); 237 238 /* clear backoff time for Rx duration */ 239 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME1(band), 240 MT_WF_RMAC_MIB_NONQOSD_BACKOFF); 241 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME3(band), 242 MT_WF_RMAC_MIB_QOS01_BACKOFF); 243 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME4(band), 244 MT_WF_RMAC_MIB_QOS23_BACKOFF); 245 246 /* clear backoff time and set software compensation for OBSS time */ 247 mask = MT_WF_RMAC_MIB_OBSS_BACKOFF | MT_WF_RMAC_MIB_ED_OFFSET; 248 set = FIELD_PREP(MT_WF_RMAC_MIB_OBSS_BACKOFF, 0) | 249 FIELD_PREP(MT_WF_RMAC_MIB_ED_OFFSET, 4); 250 mt76_rmw(dev, MT_WF_RMAC_MIB_AIRTIME0(band), mask, set); 251 252 /* filter out non-resp frames and get instanstaeous signal reporting */ 253 mask = MT_WTBLOFF_RSCR_RCPI_MODE | MT_WTBLOFF_RSCR_RCPI_PARAM; 254 set = FIELD_PREP(MT_WTBLOFF_RSCR_RCPI_MODE, 0) | 255 FIELD_PREP(MT_WTBLOFF_RSCR_RCPI_PARAM, 0x3); 256 mt76_rmw(dev, MT_WTBLOFF_RSCR(band), mask, set); 257 } 258 259 static void mt7996_mac_init_basic_rates(struct mt7996_dev *dev) 260 { 261 int i; 262 263 for (i = 0; i < ARRAY_SIZE(mt76_rates); i++) { 264 u16 rate = mt76_rates[i].hw_value; 265 u16 idx = MT7996_BASIC_RATES_TBL + i; 266 267 rate = FIELD_PREP(MT_TX_RATE_MODE, rate >> 8) | 268 FIELD_PREP(MT_TX_RATE_IDX, rate & GENMASK(7, 0)); 269 mt7996_mac_set_fixed_rate_table(dev, idx, rate); 270 } 271 } 272 273 void mt7996_mac_init(struct mt7996_dev *dev) 274 { 275 #define HIF_TXD_V2_1 4 276 int i; 277 278 mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT); 279 280 for (i = 0; i < mt7996_wtbl_size(dev); i++) 281 mt7996_mac_wtbl_update(dev, i, 282 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 283 284 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 285 i = dev->mphy.leds.pin ? MT_LED_GPIO_MUX3 : MT_LED_GPIO_MUX2; 286 mt76_rmw_field(dev, i, MT_LED_GPIO_SEL_MASK, 4); 287 } 288 289 /* txs report queue */ 290 mt76_rmw_field(dev, MT_DMA_TCRF1(0), MT_DMA_TCRF1_QIDX, 0); 291 mt76_rmw_field(dev, MT_DMA_TCRF1(1), MT_DMA_TCRF1_QIDX, 6); 292 mt76_rmw_field(dev, MT_DMA_TCRF1(2), MT_DMA_TCRF1_QIDX, 0); 293 294 /* rro module init */ 295 mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 2); 296 mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 3); 297 mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 1); 298 299 mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), 300 MCU_WA_PARAM_HW_PATH_HIF_VER, 301 HIF_TXD_V2_1, 0); 302 303 for (i = MT_BAND0; i <= MT_BAND2; i++) 304 mt7996_mac_init_band(dev, i); 305 306 mt7996_mac_init_basic_rates(dev); 307 } 308 309 int mt7996_txbf_init(struct mt7996_dev *dev) 310 { 311 int ret; 312 313 if (dev->dbdc_support) { 314 ret = mt7996_mcu_set_txbf(dev, BF_MOD_EN_CTRL); 315 if (ret) 316 return ret; 317 } 318 319 /* trigger sounding packets */ 320 ret = mt7996_mcu_set_txbf(dev, BF_SOUNDING_ON); 321 if (ret) 322 return ret; 323 324 /* enable eBF */ 325 return mt7996_mcu_set_txbf(dev, BF_HW_EN_UPDATE); 326 } 327 328 static int mt7996_register_phy(struct mt7996_dev *dev, struct mt7996_phy *phy, 329 enum mt76_band_id band) 330 { 331 struct mt76_phy *mphy; 332 u32 mac_ofs, hif1_ofs = 0; 333 int ret; 334 335 if (band != MT_BAND1 && band != MT_BAND2) 336 return 0; 337 338 if ((band == MT_BAND1 && !dev->dbdc_support) || 339 (band == MT_BAND2 && !dev->tbtc_support)) 340 return 0; 341 342 if (phy) 343 return 0; 344 345 if (band == MT_BAND2 && dev->hif2) 346 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); 347 348 mphy = mt76_alloc_phy(&dev->mt76, sizeof(*phy), &mt7996_ops, band); 349 if (!mphy) 350 return -ENOMEM; 351 352 phy = mphy->priv; 353 phy->dev = dev; 354 phy->mt76 = mphy; 355 mphy->dev->phys[band] = mphy; 356 357 INIT_DELAYED_WORK(&mphy->mac_work, mt7996_mac_work); 358 359 ret = mt7996_eeprom_parse_hw_cap(dev, phy); 360 if (ret) 361 goto error; 362 363 mac_ofs = band == MT_BAND2 ? MT_EE_MAC_ADDR3 : MT_EE_MAC_ADDR2; 364 memcpy(mphy->macaddr, dev->mt76.eeprom.data + mac_ofs, ETH_ALEN); 365 /* Make the extra PHY MAC address local without overlapping with 366 * the usual MAC address allocation scheme on multiple virtual interfaces 367 */ 368 if (!is_valid_ether_addr(mphy->macaddr)) { 369 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR, 370 ETH_ALEN); 371 mphy->macaddr[0] |= 2; 372 mphy->macaddr[0] ^= BIT(7); 373 if (band == MT_BAND2) 374 mphy->macaddr[0] ^= BIT(6); 375 } 376 mt76_eeprom_override(mphy); 377 378 /* init wiphy according to mphy and phy */ 379 mt7996_init_wiphy(mphy->hw); 380 ret = mt76_connac_init_tx_queues(phy->mt76, 381 MT_TXQ_ID(band), 382 MT7996_TX_RING_SIZE, 383 MT_TXQ_RING_BASE(band) + hif1_ofs, 0); 384 if (ret) 385 goto error; 386 387 ret = mt76_register_phy(mphy, true, mt76_rates, 388 ARRAY_SIZE(mt76_rates)); 389 if (ret) 390 goto error; 391 392 ret = mt7996_init_debugfs(phy); 393 if (ret) 394 goto error; 395 396 return 0; 397 398 error: 399 mphy->dev->phys[band] = NULL; 400 ieee80211_free_hw(mphy->hw); 401 return ret; 402 } 403 404 static void 405 mt7996_unregister_phy(struct mt7996_phy *phy, enum mt76_band_id band) 406 { 407 struct mt76_phy *mphy; 408 409 if (!phy) 410 return; 411 412 mphy = phy->dev->mt76.phys[band]; 413 mt76_unregister_phy(mphy); 414 ieee80211_free_hw(mphy->hw); 415 phy->dev->mt76.phys[band] = NULL; 416 } 417 418 static void mt7996_init_work(struct work_struct *work) 419 { 420 struct mt7996_dev *dev = container_of(work, struct mt7996_dev, 421 init_work); 422 423 mt7996_mcu_set_eeprom(dev); 424 mt7996_mac_init(dev); 425 mt7996_init_txpower(dev, &dev->mphy.sband_2g.sband); 426 mt7996_init_txpower(dev, &dev->mphy.sband_5g.sband); 427 mt7996_init_txpower(dev, &dev->mphy.sband_6g.sband); 428 mt7996_txbf_init(dev); 429 } 430 431 void mt7996_wfsys_reset(struct mt7996_dev *dev) 432 { 433 mt76_set(dev, MT_WF_SUBSYS_RST, 0x1); 434 msleep(20); 435 436 mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1); 437 msleep(20); 438 } 439 440 static int mt7996_init_hardware(struct mt7996_dev *dev) 441 { 442 int ret, idx; 443 444 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 445 446 INIT_WORK(&dev->init_work, mt7996_init_work); 447 448 dev->dbdc_support = true; 449 dev->tbtc_support = true; 450 451 ret = mt7996_dma_init(dev); 452 if (ret) 453 return ret; 454 455 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state); 456 457 ret = mt7996_mcu_init(dev); 458 if (ret) 459 return ret; 460 461 ret = mt7996_eeprom_init(dev); 462 if (ret < 0) 463 return ret; 464 465 /* Beacon and mgmt frames should occupy wcid 0 */ 466 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7996_WTBL_STA); 467 if (idx) 468 return -ENOSPC; 469 470 dev->mt76.global_wcid.idx = idx; 471 dev->mt76.global_wcid.hw_key_idx = -1; 472 dev->mt76.global_wcid.tx_info |= MT_WCID_TX_INFO_SET; 473 rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid); 474 475 return 0; 476 } 477 478 void mt7996_set_stream_vht_txbf_caps(struct mt7996_phy *phy) 479 { 480 int sts; 481 u32 *cap; 482 483 if (!phy->mt76->cap.has_5ghz) 484 return; 485 486 sts = hweight16(phy->mt76->chainmask); 487 cap = &phy->mt76->sband_5g.sband.vht_cap.cap; 488 489 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | 490 IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 491 FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, sts - 1); 492 493 *cap &= ~(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK | 494 IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 495 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE); 496 497 if (sts < 2) 498 return; 499 500 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 501 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE | 502 FIELD_PREP(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, sts - 1); 503 } 504 505 static void 506 mt7996_set_stream_he_txbf_caps(struct mt7996_phy *phy, 507 struct ieee80211_sta_he_cap *he_cap, int vif) 508 { 509 struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem; 510 int sts = hweight16(phy->mt76->chainmask); 511 u8 c; 512 513 #ifdef CONFIG_MAC80211_MESH 514 if (vif == NL80211_IFTYPE_MESH_POINT) 515 return; 516 #endif 517 518 elem->phy_cap_info[3] &= ~IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 519 elem->phy_cap_info[4] &= ~IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 520 521 c = IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK | 522 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK; 523 elem->phy_cap_info[5] &= ~c; 524 525 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 526 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 527 elem->phy_cap_info[6] &= ~c; 528 529 elem->phy_cap_info[7] &= ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK; 530 531 c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 532 IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO | 533 IEEE80211_HE_PHY_CAP2_UL_MU_PARTIAL_MU_MIMO; 534 elem->phy_cap_info[2] |= c; 535 536 c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 537 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4 | 538 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 539 elem->phy_cap_info[4] |= c; 540 541 /* do not support NG16 due to spec D4.0 changes subcarrier idx */ 542 c = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 543 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU; 544 545 if (vif == NL80211_IFTYPE_STATION) 546 c |= IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO; 547 548 elem->phy_cap_info[6] |= c; 549 550 if (sts < 2) 551 return; 552 553 /* the maximum cap is 4 x 3, (Nr, Nc) = (3, 2) */ 554 elem->phy_cap_info[7] |= min_t(int, sts - 1, 2) << 3; 555 556 if (vif != NL80211_IFTYPE_AP) 557 return; 558 559 elem->phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 560 elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 561 562 c = FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 563 sts - 1) | 564 FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK, 565 sts - 1); 566 elem->phy_cap_info[5] |= c; 567 568 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 569 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 570 elem->phy_cap_info[6] |= c; 571 572 c = IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ | 573 IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ; 574 elem->phy_cap_info[7] |= c; 575 } 576 577 static void 578 mt7996_init_he_caps(struct mt7996_phy *phy, enum nl80211_band band, 579 struct ieee80211_sband_iftype_data *data, 580 enum nl80211_iftype iftype) 581 { 582 struct ieee80211_sta_he_cap *he_cap = &data->he_cap; 583 struct ieee80211_he_cap_elem *he_cap_elem = &he_cap->he_cap_elem; 584 struct ieee80211_he_mcs_nss_supp *he_mcs = &he_cap->he_mcs_nss_supp; 585 int i, nss = hweight8(phy->mt76->antenna_mask); 586 u16 mcs_map = 0; 587 588 for (i = 0; i < 8; i++) { 589 if (i < nss) 590 mcs_map |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 591 else 592 mcs_map |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 593 } 594 595 he_cap->has_he = true; 596 597 he_cap_elem->mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE; 598 he_cap_elem->mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 599 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3; 600 he_cap_elem->mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 601 602 if (band == NL80211_BAND_2GHZ) 603 he_cap_elem->phy_cap_info[0] = 604 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 605 else 606 he_cap_elem->phy_cap_info[0] = 607 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 608 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 609 610 he_cap_elem->phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD; 611 he_cap_elem->phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 612 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ; 613 614 switch (iftype) { 615 case NL80211_IFTYPE_AP: 616 he_cap_elem->mac_cap_info[0] |= IEEE80211_HE_MAC_CAP0_TWT_RES; 617 he_cap_elem->mac_cap_info[2] |= IEEE80211_HE_MAC_CAP2_BSR; 618 he_cap_elem->mac_cap_info[4] |= IEEE80211_HE_MAC_CAP4_BQR; 619 he_cap_elem->mac_cap_info[5] |= 620 IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX; 621 he_cap_elem->phy_cap_info[3] |= 622 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 623 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 624 he_cap_elem->phy_cap_info[6] |= 625 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 626 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 627 he_cap_elem->phy_cap_info[9] |= 628 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 629 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU; 630 break; 631 case NL80211_IFTYPE_STATION: 632 he_cap_elem->mac_cap_info[1] |= 633 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 634 635 if (band == NL80211_BAND_2GHZ) 636 he_cap_elem->phy_cap_info[0] |= 637 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G; 638 else 639 he_cap_elem->phy_cap_info[0] |= 640 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G; 641 642 he_cap_elem->phy_cap_info[1] |= 643 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 644 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 645 he_cap_elem->phy_cap_info[3] |= 646 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 647 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 648 he_cap_elem->phy_cap_info[6] |= 649 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB | 650 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 651 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 652 he_cap_elem->phy_cap_info[7] |= 653 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 654 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI; 655 he_cap_elem->phy_cap_info[8] |= 656 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 657 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 658 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU | 659 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_484; 660 he_cap_elem->phy_cap_info[9] |= 661 IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 662 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK | 663 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 664 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 665 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 666 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB; 667 break; 668 default: 669 break; 670 } 671 672 he_mcs->rx_mcs_80 = cpu_to_le16(mcs_map); 673 he_mcs->tx_mcs_80 = cpu_to_le16(mcs_map); 674 he_mcs->rx_mcs_160 = cpu_to_le16(mcs_map); 675 he_mcs->tx_mcs_160 = cpu_to_le16(mcs_map); 676 677 mt7996_set_stream_he_txbf_caps(phy, he_cap, iftype); 678 679 memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres)); 680 if (he_cap_elem->phy_cap_info[6] & 681 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) { 682 mt76_connac_gen_ppe_thresh(he_cap->ppe_thres, nss); 683 } else { 684 he_cap_elem->phy_cap_info[9] |= 685 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 686 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 687 } 688 689 if (band == NL80211_BAND_6GHZ) { 690 u16 cap = IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS | 691 IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS; 692 693 cap |= u16_encode_bits(IEEE80211_HT_MPDU_DENSITY_0_5, 694 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 695 u16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 696 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 697 u16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 698 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 699 700 data->he_6ghz_capa.capa = cpu_to_le16(cap); 701 } 702 } 703 704 static void 705 mt7996_init_eht_caps(struct mt7996_phy *phy, enum nl80211_band band, 706 struct ieee80211_sband_iftype_data *data, 707 enum nl80211_iftype iftype) 708 { 709 struct ieee80211_sta_eht_cap *eht_cap = &data->eht_cap; 710 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem = &eht_cap->eht_cap_elem; 711 struct ieee80211_eht_mcs_nss_supp *eht_nss = &eht_cap->eht_mcs_nss_supp; 712 enum nl80211_chan_width width = phy->mt76->chandef.width; 713 int nss = hweight8(phy->mt76->antenna_mask); 714 int sts = hweight16(phy->mt76->chainmask); 715 u8 val; 716 717 if (!phy->dev->has_eht) 718 return; 719 720 eht_cap->has_eht = true; 721 722 eht_cap_elem->mac_cap_info[0] = 723 IEEE80211_EHT_MAC_CAP0_EPCS_PRIO_ACCESS | 724 IEEE80211_EHT_MAC_CAP0_OM_CONTROL; 725 726 eht_cap_elem->phy_cap_info[0] = 727 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ | 728 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI | 729 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMER | 730 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE; 731 732 eht_cap_elem->phy_cap_info[0] |= 733 u8_encode_bits(u8_get_bits(sts - 1, BIT(0)), 734 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK); 735 736 eht_cap_elem->phy_cap_info[1] = 737 u8_encode_bits(u8_get_bits(sts - 1, GENMASK(2, 1)), 738 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK) | 739 u8_encode_bits(sts - 1, 740 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK) | 741 u8_encode_bits(sts - 1, 742 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK); 743 744 eht_cap_elem->phy_cap_info[2] = 745 u8_encode_bits(sts - 1, IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_80MHZ_MASK) | 746 u8_encode_bits(sts - 1, IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_160MHZ_MASK) | 747 u8_encode_bits(sts - 1, IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_320MHZ_MASK); 748 749 eht_cap_elem->phy_cap_info[3] = 750 IEEE80211_EHT_PHY_CAP3_NG_16_SU_FEEDBACK | 751 IEEE80211_EHT_PHY_CAP3_NG_16_MU_FEEDBACK | 752 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK | 753 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK | 754 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK | 755 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK | 756 IEEE80211_EHT_PHY_CAP3_TRIG_CQI_FDBK; 757 758 eht_cap_elem->phy_cap_info[4] = 759 u8_encode_bits(min_t(int, sts - 1, 2), 760 IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK); 761 762 eht_cap_elem->phy_cap_info[5] = 763 IEEE80211_EHT_PHY_CAP5_NON_TRIG_CQI_FEEDBACK | 764 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_16US, 765 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK) | 766 u8_encode_bits(u8_get_bits(0x11, GENMASK(1, 0)), 767 IEEE80211_EHT_PHY_CAP5_MAX_NUM_SUPP_EHT_LTF_MASK); 768 769 val = width == NL80211_CHAN_WIDTH_320 ? 0xf : 770 width == NL80211_CHAN_WIDTH_160 ? 0x7 : 771 width == NL80211_CHAN_WIDTH_80 ? 0x3 : 0x1; 772 eht_cap_elem->phy_cap_info[6] = 773 u8_encode_bits(u8_get_bits(0x11, GENMASK(4, 2)), 774 IEEE80211_EHT_PHY_CAP6_MAX_NUM_SUPP_EHT_LTF_MASK) | 775 u8_encode_bits(val, IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_MASK); 776 777 eht_cap_elem->phy_cap_info[7] = 778 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_80MHZ | 779 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_160MHZ | 780 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_320MHZ | 781 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_80MHZ | 782 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_160MHZ | 783 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_320MHZ; 784 785 val = u8_encode_bits(nss, IEEE80211_EHT_MCS_NSS_RX) | 786 u8_encode_bits(nss, IEEE80211_EHT_MCS_NSS_TX); 787 #define SET_EHT_MAX_NSS(_bw, _val) do { \ 788 eht_nss->bw._##_bw.rx_tx_mcs9_max_nss = _val; \ 789 eht_nss->bw._##_bw.rx_tx_mcs11_max_nss = _val; \ 790 eht_nss->bw._##_bw.rx_tx_mcs13_max_nss = _val; \ 791 } while (0) 792 793 SET_EHT_MAX_NSS(80, val); 794 SET_EHT_MAX_NSS(160, val); 795 SET_EHT_MAX_NSS(320, val); 796 #undef SET_EHT_MAX_NSS 797 } 798 799 static void 800 __mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy, 801 struct ieee80211_supported_band *sband, 802 enum nl80211_band band) 803 { 804 struct ieee80211_sband_iftype_data *data = phy->iftype[band]; 805 int i, n = 0; 806 807 for (i = 0; i < NUM_NL80211_IFTYPES; i++) { 808 switch (i) { 809 case NL80211_IFTYPE_STATION: 810 case NL80211_IFTYPE_AP: 811 #ifdef CONFIG_MAC80211_MESH 812 case NL80211_IFTYPE_MESH_POINT: 813 #endif 814 break; 815 default: 816 continue; 817 } 818 819 data[n].types_mask = BIT(i); 820 mt7996_init_he_caps(phy, band, &data[n], i); 821 mt7996_init_eht_caps(phy, band, &data[n], i); 822 823 n++; 824 } 825 826 sband->iftype_data = data; 827 sband->n_iftype_data = n; 828 } 829 830 void mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy) 831 { 832 if (phy->mt76->cap.has_2ghz) 833 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_2g.sband, 834 NL80211_BAND_2GHZ); 835 836 if (phy->mt76->cap.has_5ghz) 837 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_5g.sband, 838 NL80211_BAND_5GHZ); 839 840 if (phy->mt76->cap.has_6ghz) 841 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_6g.sband, 842 NL80211_BAND_6GHZ); 843 } 844 845 int mt7996_register_device(struct mt7996_dev *dev) 846 { 847 struct ieee80211_hw *hw = mt76_hw(dev); 848 int ret; 849 850 dev->phy.dev = dev; 851 dev->phy.mt76 = &dev->mt76.phy; 852 dev->mt76.phy.priv = &dev->phy; 853 INIT_WORK(&dev->rc_work, mt7996_mac_sta_rc_work); 854 INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7996_mac_work); 855 INIT_LIST_HEAD(&dev->sta_rc_list); 856 INIT_LIST_HEAD(&dev->sta_poll_list); 857 INIT_LIST_HEAD(&dev->twt_list); 858 spin_lock_init(&dev->sta_poll_lock); 859 860 init_waitqueue_head(&dev->reset_wait); 861 INIT_WORK(&dev->reset_work, mt7996_mac_reset_work); 862 INIT_WORK(&dev->dump_work, mt7996_mac_dump_work); 863 mutex_init(&dev->dump_mutex); 864 865 ret = mt7996_init_hardware(dev); 866 if (ret) 867 return ret; 868 869 mt7996_init_wiphy(hw); 870 871 /* init led callbacks */ 872 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 873 dev->mphy.leds.cdev.brightness_set = mt7996_led_set_brightness; 874 dev->mphy.leds.cdev.blink_set = mt7996_led_set_blink; 875 } 876 877 ret = mt76_register_device(&dev->mt76, true, mt76_rates, 878 ARRAY_SIZE(mt76_rates)); 879 if (ret) 880 return ret; 881 882 ieee80211_queue_work(mt76_hw(dev), &dev->init_work); 883 884 ret = mt7996_register_phy(dev, mt7996_phy2(dev), MT_BAND1); 885 if (ret) 886 return ret; 887 888 ret = mt7996_register_phy(dev, mt7996_phy3(dev), MT_BAND2); 889 if (ret) 890 return ret; 891 892 dev->recovery.hw_init_done = true; 893 894 ret = mt7996_init_debugfs(&dev->phy); 895 if (ret) 896 return ret; 897 898 return mt7996_coredump_register(dev); 899 } 900 901 void mt7996_unregister_device(struct mt7996_dev *dev) 902 { 903 mt7996_unregister_phy(mt7996_phy3(dev), MT_BAND2); 904 mt7996_unregister_phy(mt7996_phy2(dev), MT_BAND1); 905 mt7996_coredump_unregister(dev); 906 mt76_unregister_device(&dev->mt76); 907 mt7996_mcu_exit(dev); 908 mt7996_tx_token_put(dev); 909 mt7996_dma_cleanup(dev); 910 tasklet_disable(&dev->mt76.irq_tasklet); 911 912 mt76_free_device(&dev->mt76); 913 } 914