1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #include "mt7996.h" 7 #include "../dma.h" 8 #include "mac.h" 9 10 static int mt7996_poll_tx(struct napi_struct *napi, int budget) 11 { 12 struct mt7996_dev *dev; 13 14 dev = container_of(napi, struct mt7996_dev, mt76.tx_napi); 15 16 mt76_connac_tx_cleanup(&dev->mt76); 17 if (napi_complete_done(napi, 0)) 18 mt7996_irq_enable(dev, MT_INT_TX_DONE_MCU); 19 20 return 0; 21 } 22 23 static void mt7996_dma_config(struct mt7996_dev *dev) 24 { 25 #define Q_CONFIG(q, wfdma, int, id) do { \ 26 if (wfdma) \ 27 dev->q_wfdma_mask |= (1 << (q)); \ 28 dev->q_int_mask[(q)] = int; \ 29 dev->q_id[(q)] = id; \ 30 } while (0) 31 32 #define MCUQ_CONFIG(q, wfdma, int, id) Q_CONFIG(q, (wfdma), (int), (id)) 33 #define RXQ_CONFIG(q, wfdma, int, id) Q_CONFIG(__RXQ(q), (wfdma), (int), (id)) 34 #define TXQ_CONFIG(q, wfdma, int, id) Q_CONFIG(__TXQ(q), (wfdma), (int), (id)) 35 36 /* rx queue */ 37 RXQ_CONFIG(MT_RXQ_MCU, WFDMA0, MT_INT_RX_DONE_WM, MT7996_RXQ_MCU_WM); 38 RXQ_CONFIG(MT_RXQ_MCU_WA, WFDMA0, MT_INT_RX_DONE_WA, MT7996_RXQ_MCU_WA); 39 40 /* band0/band1 */ 41 RXQ_CONFIG(MT_RXQ_MAIN, WFDMA0, MT_INT_RX_DONE_BAND0, MT7996_RXQ_BAND0); 42 RXQ_CONFIG(MT_RXQ_MAIN_WA, WFDMA0, MT_INT_RX_DONE_WA_MAIN, MT7996_RXQ_MCU_WA_MAIN); 43 44 /* band2 */ 45 RXQ_CONFIG(MT_RXQ_BAND2, WFDMA0, MT_INT_RX_DONE_BAND2, MT7996_RXQ_BAND2); 46 RXQ_CONFIG(MT_RXQ_BAND2_WA, WFDMA0, MT_INT_RX_DONE_WA_TRI, MT7996_RXQ_MCU_WA_TRI); 47 48 /* data tx queue */ 49 TXQ_CONFIG(0, WFDMA0, MT_INT_TX_DONE_BAND0, MT7996_TXQ_BAND0); 50 TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, MT7996_TXQ_BAND1); 51 TXQ_CONFIG(2, WFDMA0, MT_INT_TX_DONE_BAND2, MT7996_TXQ_BAND2); 52 53 /* mcu tx queue */ 54 MCUQ_CONFIG(MT_MCUQ_WM, WFDMA0, MT_INT_TX_DONE_MCU_WM, MT7996_TXQ_MCU_WM); 55 MCUQ_CONFIG(MT_MCUQ_WA, WFDMA0, MT_INT_TX_DONE_MCU_WA, MT7996_TXQ_MCU_WA); 56 MCUQ_CONFIG(MT_MCUQ_FWDL, WFDMA0, MT_INT_TX_DONE_FWDL, MT7996_TXQ_FWDL); 57 } 58 59 static void __mt7996_dma_prefetch(struct mt7996_dev *dev, u32 ofs) 60 { 61 #define PREFETCH(_base, _depth) ((_base) << 16 | (_depth)) 62 /* prefetch SRAM wrapping boundary for tx/rx ring. */ 63 mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_FWDL) + ofs, PREFETCH(0x0, 0x2)); 64 mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WM) + ofs, PREFETCH(0x20, 0x2)); 65 mt76_wr(dev, MT_TXQ_EXT_CTRL(0) + ofs, PREFETCH(0x40, 0x4)); 66 mt76_wr(dev, MT_TXQ_EXT_CTRL(1) + ofs, PREFETCH(0x80, 0x4)); 67 mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WA) + ofs, PREFETCH(0xc0, 0x2)); 68 mt76_wr(dev, MT_TXQ_EXT_CTRL(2) + ofs, PREFETCH(0xe0, 0x4)); 69 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MCU) + ofs, PREFETCH(0x120, 0x2)); 70 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MCU_WA) + ofs, PREFETCH(0x140, 0x2)); 71 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MAIN_WA) + ofs, PREFETCH(0x160, 0x2)); 72 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND2_WA) + ofs, PREFETCH(0x180, 0x2)); 73 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MAIN) + ofs, PREFETCH(0x1a0, 0x10)); 74 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND2) + ofs, PREFETCH(0x2a0, 0x10)); 75 76 mt76_set(dev, WF_WFDMA0_GLO_CFG_EXT1 + ofs, WF_WFDMA0_GLO_CFG_EXT1_CALC_MODE); 77 } 78 79 void mt7996_dma_prefetch(struct mt7996_dev *dev) 80 { 81 __mt7996_dma_prefetch(dev, 0); 82 if (dev->hif2) 83 __mt7996_dma_prefetch(dev, MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0)); 84 } 85 86 static void mt7996_dma_disable(struct mt7996_dev *dev, bool reset) 87 { 88 u32 hif1_ofs = 0; 89 90 if (dev->hif2) 91 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); 92 93 if (reset) { 94 mt76_clear(dev, MT_WFDMA0_RST, 95 MT_WFDMA0_RST_DMASHDL_ALL_RST | 96 MT_WFDMA0_RST_LOGIC_RST); 97 98 mt76_set(dev, MT_WFDMA0_RST, 99 MT_WFDMA0_RST_DMASHDL_ALL_RST | 100 MT_WFDMA0_RST_LOGIC_RST); 101 102 if (dev->hif2) { 103 mt76_clear(dev, MT_WFDMA0_RST + hif1_ofs, 104 MT_WFDMA0_RST_DMASHDL_ALL_RST | 105 MT_WFDMA0_RST_LOGIC_RST); 106 107 mt76_set(dev, MT_WFDMA0_RST + hif1_ofs, 108 MT_WFDMA0_RST_DMASHDL_ALL_RST | 109 MT_WFDMA0_RST_LOGIC_RST); 110 } 111 } 112 113 /* disable */ 114 mt76_clear(dev, MT_WFDMA0_GLO_CFG, 115 MT_WFDMA0_GLO_CFG_TX_DMA_EN | 116 MT_WFDMA0_GLO_CFG_RX_DMA_EN | 117 MT_WFDMA0_GLO_CFG_OMIT_TX_INFO | 118 MT_WFDMA0_GLO_CFG_OMIT_RX_INFO | 119 MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2); 120 121 if (dev->hif2) { 122 mt76_clear(dev, MT_WFDMA0_GLO_CFG + hif1_ofs, 123 MT_WFDMA0_GLO_CFG_TX_DMA_EN | 124 MT_WFDMA0_GLO_CFG_RX_DMA_EN | 125 MT_WFDMA0_GLO_CFG_OMIT_TX_INFO | 126 MT_WFDMA0_GLO_CFG_OMIT_RX_INFO | 127 MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2); 128 } 129 } 130 131 void mt7996_dma_start(struct mt7996_dev *dev, bool reset) 132 { 133 u32 hif1_ofs = 0; 134 u32 irq_mask; 135 136 if (dev->hif2) 137 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); 138 139 /* enable WFDMA Tx/Rx */ 140 if (!reset) { 141 mt76_set(dev, MT_WFDMA0_GLO_CFG, 142 MT_WFDMA0_GLO_CFG_TX_DMA_EN | 143 MT_WFDMA0_GLO_CFG_RX_DMA_EN | 144 MT_WFDMA0_GLO_CFG_OMIT_TX_INFO | 145 MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2); 146 147 if (dev->hif2) 148 mt76_set(dev, MT_WFDMA0_GLO_CFG + hif1_ofs, 149 MT_WFDMA0_GLO_CFG_TX_DMA_EN | 150 MT_WFDMA0_GLO_CFG_RX_DMA_EN | 151 MT_WFDMA0_GLO_CFG_OMIT_TX_INFO | 152 MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2); 153 } 154 155 /* enable interrupts for TX/RX rings */ 156 irq_mask = MT_INT_MCU_CMD; 157 if (reset) 158 goto done; 159 160 irq_mask = MT_INT_RX_DONE_MCU | MT_INT_TX_DONE_MCU; 161 162 if (!dev->mphy.band_idx) 163 irq_mask |= MT_INT_BAND0_RX_DONE; 164 165 if (dev->dbdc_support) 166 irq_mask |= MT_INT_BAND1_RX_DONE; 167 168 if (dev->tbtc_support) 169 irq_mask |= MT_INT_BAND2_RX_DONE; 170 171 done: 172 mt7996_irq_enable(dev, irq_mask); 173 mt7996_irq_disable(dev, 0); 174 } 175 176 static void mt7996_dma_enable(struct mt7996_dev *dev, bool reset) 177 { 178 u32 hif1_ofs = 0; 179 180 if (dev->hif2) 181 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); 182 183 /* reset dma idx */ 184 mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR, ~0); 185 if (dev->hif2) 186 mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR + hif1_ofs, ~0); 187 188 /* configure delay interrupt off */ 189 mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0, 0); 190 mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG1, 0); 191 mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG2, 0); 192 193 if (dev->hif2) { 194 mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0 + hif1_ofs, 0); 195 mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG1 + hif1_ofs, 0); 196 mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG2 + hif1_ofs, 0); 197 } 198 199 /* configure perfetch settings */ 200 mt7996_dma_prefetch(dev); 201 202 /* hif wait WFDMA idle */ 203 mt76_set(dev, MT_WFDMA0_BUSY_ENA, 204 MT_WFDMA0_BUSY_ENA_TX_FIFO0 | 205 MT_WFDMA0_BUSY_ENA_TX_FIFO1 | 206 MT_WFDMA0_BUSY_ENA_RX_FIFO); 207 208 if (dev->hif2) 209 mt76_set(dev, MT_WFDMA0_BUSY_ENA + hif1_ofs, 210 MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 | 211 MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 | 212 MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO); 213 214 mt76_poll(dev, MT_WFDMA_EXT_CSR_HIF_MISC, 215 MT_WFDMA_EXT_CSR_HIF_MISC_BUSY, 0, 1000); 216 217 /* GLO_CFG_EXT0 */ 218 mt76_set(dev, WF_WFDMA0_GLO_CFG_EXT0, 219 WF_WFDMA0_GLO_CFG_EXT0_RX_WB_RXD | 220 WF_WFDMA0_GLO_CFG_EXT0_WED_MERGE_MODE); 221 222 /* GLO_CFG_EXT1 */ 223 mt76_set(dev, WF_WFDMA0_GLO_CFG_EXT1, 224 WF_WFDMA0_GLO_CFG_EXT1_TX_FCTRL_MODE); 225 226 if (dev->hif2) { 227 /* GLO_CFG_EXT0 */ 228 mt76_set(dev, WF_WFDMA0_GLO_CFG_EXT0 + hif1_ofs, 229 WF_WFDMA0_GLO_CFG_EXT0_RX_WB_RXD | 230 WF_WFDMA0_GLO_CFG_EXT0_WED_MERGE_MODE); 231 232 /* GLO_CFG_EXT1 */ 233 mt76_set(dev, WF_WFDMA0_GLO_CFG_EXT1 + hif1_ofs, 234 WF_WFDMA0_GLO_CFG_EXT1_TX_FCTRL_MODE); 235 236 mt76_set(dev, MT_WFDMA_HOST_CONFIG, 237 MT_WFDMA_HOST_CONFIG_PDMA_BAND); 238 } 239 240 if (dev->hif2) { 241 /* fix hardware limitation, pcie1's rx ring3 is not available 242 * so, redirect pcie0 rx ring3 interrupt to pcie1 243 */ 244 mt76_set(dev, MT_WFDMA0_RX_INT_PCIE_SEL, 245 MT_WFDMA0_RX_INT_SEL_RING3); 246 247 /* TODO: redirect rx ring6 interrupt to pcie0 for wed function */ 248 } 249 250 mt7996_dma_start(dev, reset); 251 } 252 253 int mt7996_dma_init(struct mt7996_dev *dev) 254 { 255 u32 hif1_ofs = 0; 256 int ret; 257 258 mt7996_dma_config(dev); 259 260 mt76_dma_attach(&dev->mt76); 261 262 if (dev->hif2) 263 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); 264 265 mt7996_dma_disable(dev, true); 266 267 /* init tx queue */ 268 ret = mt76_connac_init_tx_queues(dev->phy.mt76, 269 MT_TXQ_ID(dev->mphy.band_idx), 270 MT7996_TX_RING_SIZE, 271 MT_TXQ_RING_BASE(0), 0); 272 if (ret) 273 return ret; 274 275 /* command to WM */ 276 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, 277 MT_MCUQ_ID(MT_MCUQ_WM), 278 MT7996_TX_MCU_RING_SIZE, 279 MT_MCUQ_RING_BASE(MT_MCUQ_WM)); 280 if (ret) 281 return ret; 282 283 /* command to WA */ 284 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WA, 285 MT_MCUQ_ID(MT_MCUQ_WA), 286 MT7996_TX_MCU_RING_SIZE, 287 MT_MCUQ_RING_BASE(MT_MCUQ_WA)); 288 if (ret) 289 return ret; 290 291 /* firmware download */ 292 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL, 293 MT_MCUQ_ID(MT_MCUQ_FWDL), 294 MT7996_TX_FWDL_RING_SIZE, 295 MT_MCUQ_RING_BASE(MT_MCUQ_FWDL)); 296 if (ret) 297 return ret; 298 299 /* event from WM */ 300 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 301 MT_RXQ_ID(MT_RXQ_MCU), 302 MT7996_RX_MCU_RING_SIZE, 303 MT_RX_BUF_SIZE, 304 MT_RXQ_RING_BASE(MT_RXQ_MCU)); 305 if (ret) 306 return ret; 307 308 /* event from WA */ 309 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA], 310 MT_RXQ_ID(MT_RXQ_MCU_WA), 311 MT7996_RX_MCU_RING_SIZE_WA, 312 MT_RX_BUF_SIZE, 313 MT_RXQ_RING_BASE(MT_RXQ_MCU_WA)); 314 if (ret) 315 return ret; 316 317 /* rx data queue for band0 and band1 */ 318 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN], 319 MT_RXQ_ID(MT_RXQ_MAIN), 320 MT7996_RX_RING_SIZE, 321 MT_RX_BUF_SIZE, 322 MT_RXQ_RING_BASE(MT_RXQ_MAIN)); 323 if (ret) 324 return ret; 325 326 /* tx free notify event from WA for band0 */ 327 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN_WA], 328 MT_RXQ_ID(MT_RXQ_MAIN_WA), 329 MT7996_RX_MCU_RING_SIZE, 330 MT_RX_BUF_SIZE, 331 MT_RXQ_RING_BASE(MT_RXQ_MAIN_WA)); 332 if (ret) 333 return ret; 334 335 if (dev->tbtc_support || dev->mphy.band_idx == MT_BAND2) { 336 /* rx data queue for band2 */ 337 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND2], 338 MT_RXQ_ID(MT_RXQ_BAND2), 339 MT7996_RX_RING_SIZE, 340 MT_RX_BUF_SIZE, 341 MT_RXQ_RING_BASE(MT_RXQ_BAND2) + hif1_ofs); 342 if (ret) 343 return ret; 344 345 /* tx free notify event from WA for band2 346 * use pcie0's rx ring3, but, redirect pcie0 rx ring3 interrupt to pcie1 347 */ 348 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND2_WA], 349 MT_RXQ_ID(MT_RXQ_BAND2_WA), 350 MT7996_RX_MCU_RING_SIZE, 351 MT_RX_BUF_SIZE, 352 MT_RXQ_RING_BASE(MT_RXQ_BAND2_WA)); 353 if (ret) 354 return ret; 355 } 356 357 ret = mt76_init_queues(dev, mt76_dma_rx_poll); 358 if (ret < 0) 359 return ret; 360 361 netif_napi_add_tx(&dev->mt76.tx_napi_dev, &dev->mt76.tx_napi, 362 mt7996_poll_tx); 363 napi_enable(&dev->mt76.tx_napi); 364 365 mt7996_dma_enable(dev, false); 366 367 return 0; 368 } 369 370 void mt7996_dma_reset(struct mt7996_dev *dev, bool force) 371 { 372 struct mt76_phy *phy2 = dev->mt76.phys[MT_BAND1]; 373 struct mt76_phy *phy3 = dev->mt76.phys[MT_BAND2]; 374 u32 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); 375 int i; 376 377 mt76_clear(dev, MT_WFDMA0_GLO_CFG, 378 MT_WFDMA0_GLO_CFG_TX_DMA_EN | 379 MT_WFDMA0_GLO_CFG_RX_DMA_EN); 380 381 if (dev->hif2) 382 mt76_clear(dev, MT_WFDMA0_GLO_CFG + hif1_ofs, 383 MT_WFDMA0_GLO_CFG_TX_DMA_EN | 384 MT_WFDMA0_GLO_CFG_RX_DMA_EN); 385 386 usleep_range(1000, 2000); 387 388 for (i = 0; i < __MT_TXQ_MAX; i++) { 389 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true); 390 if (phy2) 391 mt76_queue_tx_cleanup(dev, phy2->q_tx[i], true); 392 if (phy3) 393 mt76_queue_tx_cleanup(dev, phy3->q_tx[i], true); 394 } 395 396 for (i = 0; i < __MT_MCUQ_MAX; i++) 397 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[i], true); 398 399 mt76_for_each_q_rx(&dev->mt76, i) 400 mt76_queue_rx_cleanup(dev, &dev->mt76.q_rx[i]); 401 402 mt76_tx_status_check(&dev->mt76, true); 403 404 /* reset wfsys */ 405 if (force) 406 mt7996_wfsys_reset(dev); 407 408 mt7996_dma_disable(dev, force); 409 410 /* reset hw queues */ 411 for (i = 0; i < __MT_TXQ_MAX; i++) { 412 mt76_queue_reset(dev, dev->mphy.q_tx[i]); 413 if (phy2) 414 mt76_queue_reset(dev, phy2->q_tx[i]); 415 if (phy3) 416 mt76_queue_reset(dev, phy3->q_tx[i]); 417 } 418 419 for (i = 0; i < __MT_MCUQ_MAX; i++) 420 mt76_queue_reset(dev, dev->mt76.q_mcu[i]); 421 422 mt76_for_each_q_rx(&dev->mt76, i) { 423 mt76_queue_reset(dev, &dev->mt76.q_rx[i]); 424 } 425 426 mt76_tx_status_check(&dev->mt76, true); 427 428 mt76_for_each_q_rx(&dev->mt76, i) 429 mt76_queue_rx_reset(dev, i); 430 431 mt7996_dma_enable(dev, !force); 432 } 433 434 void mt7996_dma_cleanup(struct mt7996_dev *dev) 435 { 436 mt7996_dma_disable(dev, true); 437 438 mt76_dma_cleanup(&dev->mt76); 439 } 440