1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #include <linux/relay.h> 7 #include "mt7996.h" 8 #include "eeprom.h" 9 #include "mcu.h" 10 #include "mac.h" 11 12 #define FW_BIN_LOG_MAGIC 0x44d9c99a 13 14 /** global debugfs **/ 15 16 struct hw_queue_map { 17 const char *name; 18 u8 index; 19 u8 pid; 20 u8 qid; 21 }; 22 23 static int 24 mt7996_implicit_txbf_set(void *data, u64 val) 25 { 26 struct mt7996_dev *dev = data; 27 28 /* The existing connected stations shall reconnect to apply 29 * new implicit txbf configuration. 30 */ 31 dev->ibf = !!val; 32 33 return mt7996_mcu_set_txbf(dev, BF_HW_EN_UPDATE); 34 } 35 36 static int 37 mt7996_implicit_txbf_get(void *data, u64 *val) 38 { 39 struct mt7996_dev *dev = data; 40 41 *val = dev->ibf; 42 43 return 0; 44 } 45 46 DEFINE_DEBUGFS_ATTRIBUTE(fops_implicit_txbf, mt7996_implicit_txbf_get, 47 mt7996_implicit_txbf_set, "%lld\n"); 48 49 /* test knob of system error recovery */ 50 static ssize_t 51 mt7996_sys_recovery_set(struct file *file, const char __user *user_buf, 52 size_t count, loff_t *ppos) 53 { 54 struct mt7996_dev *dev = file->private_data; 55 char buf[16], *sep; 56 int ret = 0; 57 u16 band, val; 58 59 if (count >= sizeof(buf)) 60 return -EINVAL; 61 62 if (copy_from_user(buf, user_buf, count)) 63 return -EFAULT; 64 65 if (count && buf[count - 1] == '\n') 66 buf[count - 1] = '\0'; 67 else 68 buf[count] = '\0'; 69 70 sep = strchr(buf, ','); 71 if (!sep) 72 return -EINVAL; 73 74 *sep = 0; 75 if (kstrtou16(buf, 0, &band) || kstrtou16(sep + 1, 0, &val)) 76 return -EINVAL; 77 78 switch (val) { 79 /* 80 * <band>,0: grab firmware current SER state. 81 * <band>,1: trigger & enable system error L1 recovery. 82 * <band>,2: trigger & enable system error L2 recovery. 83 * <band>,3: trigger & enable system error L3 rx abort. 84 * <band>,4: trigger & enable system error L3 tx abort 85 * <band>,5: trigger & enable system error L3 tx disable. 86 * <band>,6: trigger & enable system error L3 bf recovery. 87 * <band>,7: trigger & enable system error L4 mdp recovery. 88 * <band>,8: trigger & enable system error full recovery. 89 * <band>,9: trigger firmware crash. 90 */ 91 case UNI_CMD_SER_QUERY: 92 ret = mt7996_mcu_set_ser(dev, UNI_CMD_SER_QUERY, 0, band); 93 break; 94 case UNI_CMD_SER_SET_RECOVER_L1: 95 case UNI_CMD_SER_SET_RECOVER_L2: 96 case UNI_CMD_SER_SET_RECOVER_L3_RX_ABORT: 97 case UNI_CMD_SER_SET_RECOVER_L3_TX_ABORT: 98 case UNI_CMD_SER_SET_RECOVER_L3_TX_DISABLE: 99 case UNI_CMD_SER_SET_RECOVER_L3_BF: 100 case UNI_CMD_SER_SET_RECOVER_L4_MDP: 101 ret = mt7996_mcu_set_ser(dev, UNI_CMD_SER_SET, BIT(val), band); 102 if (ret) 103 return ret; 104 105 ret = mt7996_mcu_set_ser(dev, UNI_CMD_SER_TRIGGER, val, band); 106 break; 107 108 /* enable full chip reset */ 109 case UNI_CMD_SER_SET_RECOVER_FULL: 110 mt76_set(dev, MT_WFDMA0_MCU_HOST_INT_ENA, MT_MCU_CMD_WDT_MASK); 111 dev->recovery.state |= MT_MCU_CMD_WDT_MASK; 112 mt7996_reset(dev); 113 break; 114 115 /* WARNING: trigger firmware crash */ 116 case UNI_CMD_SER_SET_SYSTEM_ASSERT: 117 ret = mt7996_mcu_trigger_assert(dev); 118 if (ret) 119 return ret; 120 break; 121 default: 122 break; 123 } 124 125 return ret ? ret : count; 126 } 127 128 static ssize_t 129 mt7996_sys_recovery_get(struct file *file, char __user *user_buf, 130 size_t count, loff_t *ppos) 131 { 132 struct mt7996_dev *dev = file->private_data; 133 char *buff; 134 int desc = 0; 135 ssize_t ret; 136 static const size_t bufsz = 1024; 137 138 buff = kmalloc(bufsz, GFP_KERNEL); 139 if (!buff) 140 return -ENOMEM; 141 142 /* HELP */ 143 desc += scnprintf(buff + desc, bufsz - desc, 144 "Please echo the correct value ...\n"); 145 desc += scnprintf(buff + desc, bufsz - desc, 146 "<band>,0: grab firmware transient SER state\n"); 147 desc += scnprintf(buff + desc, bufsz - desc, 148 "<band>,1: trigger system error L1 recovery\n"); 149 desc += scnprintf(buff + desc, bufsz - desc, 150 "<band>,2: trigger system error L2 recovery\n"); 151 desc += scnprintf(buff + desc, bufsz - desc, 152 "<band>,3: trigger system error L3 rx abort\n"); 153 desc += scnprintf(buff + desc, bufsz - desc, 154 "<band>,4: trigger system error L3 tx abort\n"); 155 desc += scnprintf(buff + desc, bufsz - desc, 156 "<band>,5: trigger system error L3 tx disable\n"); 157 desc += scnprintf(buff + desc, bufsz - desc, 158 "<band>,6: trigger system error L3 bf recovery\n"); 159 desc += scnprintf(buff + desc, bufsz - desc, 160 "<band>,7: trigger system error L4 mdp recovery\n"); 161 desc += scnprintf(buff + desc, bufsz - desc, 162 "<band>,8: trigger system error full recovery\n"); 163 desc += scnprintf(buff + desc, bufsz - desc, 164 "<band>,9: trigger firmware crash\n"); 165 166 /* SER statistics */ 167 desc += scnprintf(buff + desc, bufsz - desc, 168 "\nlet's dump firmware SER statistics...\n"); 169 desc += scnprintf(buff + desc, bufsz - desc, 170 "::E R , SER_STATUS = 0x%08x\n", 171 mt76_rr(dev, MT_SWDEF_SER_STATS)); 172 desc += scnprintf(buff + desc, bufsz - desc, 173 "::E R , SER_PLE_ERR = 0x%08x\n", 174 mt76_rr(dev, MT_SWDEF_PLE_STATS)); 175 desc += scnprintf(buff + desc, bufsz - desc, 176 "::E R , SER_PLE_ERR_1 = 0x%08x\n", 177 mt76_rr(dev, MT_SWDEF_PLE1_STATS)); 178 desc += scnprintf(buff + desc, bufsz - desc, 179 "::E R , SER_PLE_ERR_AMSDU = 0x%08x\n", 180 mt76_rr(dev, MT_SWDEF_PLE_AMSDU_STATS)); 181 desc += scnprintf(buff + desc, bufsz - desc, 182 "::E R , SER_PSE_ERR = 0x%08x\n", 183 mt76_rr(dev, MT_SWDEF_PSE_STATS)); 184 desc += scnprintf(buff + desc, bufsz - desc, 185 "::E R , SER_PSE_ERR_1 = 0x%08x\n", 186 mt76_rr(dev, MT_SWDEF_PSE1_STATS)); 187 desc += scnprintf(buff + desc, bufsz - desc, 188 "::E R , SER_LMAC_WISR6_B0 = 0x%08x\n", 189 mt76_rr(dev, MT_SWDEF_LAMC_WISR6_BN0_STATS)); 190 desc += scnprintf(buff + desc, bufsz - desc, 191 "::E R , SER_LMAC_WISR6_B1 = 0x%08x\n", 192 mt76_rr(dev, MT_SWDEF_LAMC_WISR6_BN1_STATS)); 193 desc += scnprintf(buff + desc, bufsz - desc, 194 "::E R , SER_LMAC_WISR6_B2 = 0x%08x\n", 195 mt76_rr(dev, MT_SWDEF_LAMC_WISR6_BN2_STATS)); 196 desc += scnprintf(buff + desc, bufsz - desc, 197 "::E R , SER_LMAC_WISR7_B0 = 0x%08x\n", 198 mt76_rr(dev, MT_SWDEF_LAMC_WISR7_BN0_STATS)); 199 desc += scnprintf(buff + desc, bufsz - desc, 200 "::E R , SER_LMAC_WISR7_B1 = 0x%08x\n", 201 mt76_rr(dev, MT_SWDEF_LAMC_WISR7_BN1_STATS)); 202 desc += scnprintf(buff + desc, bufsz - desc, 203 "::E R , SER_LMAC_WISR7_B2 = 0x%08x\n", 204 mt76_rr(dev, MT_SWDEF_LAMC_WISR7_BN2_STATS)); 205 desc += scnprintf(buff + desc, bufsz - desc, 206 "\nSYS_RESET_COUNT: WM %d, WA %d\n", 207 dev->recovery.wm_reset_count, 208 dev->recovery.wa_reset_count); 209 210 ret = simple_read_from_buffer(user_buf, count, ppos, buff, desc); 211 kfree(buff); 212 return ret; 213 } 214 215 static const struct file_operations mt7996_sys_recovery_ops = { 216 .write = mt7996_sys_recovery_set, 217 .read = mt7996_sys_recovery_get, 218 .open = simple_open, 219 .llseek = default_llseek, 220 }; 221 222 static int 223 mt7996_radar_trigger(void *data, u64 val) 224 { 225 struct mt7996_dev *dev = data; 226 227 if (val > MT_RX_SEL2) 228 return -EINVAL; 229 230 if (val == MT_RX_SEL2 && !dev->rdd2_phy) { 231 dev_err(dev->mt76.dev, "Background radar is not enabled\n"); 232 return -EINVAL; 233 } 234 235 return mt7996_mcu_rdd_cmd(dev, RDD_RADAR_EMULATE, 236 val, 0, 0); 237 } 238 239 DEFINE_DEBUGFS_ATTRIBUTE(fops_radar_trigger, NULL, 240 mt7996_radar_trigger, "%lld\n"); 241 242 static int 243 mt7996_rdd_monitor(struct seq_file *s, void *data) 244 { 245 struct mt7996_dev *dev = dev_get_drvdata(s->private); 246 struct cfg80211_chan_def *chandef = &dev->rdd2_chandef; 247 const char *bw; 248 int ret = 0; 249 250 mutex_lock(&dev->mt76.mutex); 251 252 if (!cfg80211_chandef_valid(chandef)) { 253 ret = -EINVAL; 254 goto out; 255 } 256 257 if (!dev->rdd2_phy) { 258 seq_puts(s, "not running\n"); 259 goto out; 260 } 261 262 switch (chandef->width) { 263 case NL80211_CHAN_WIDTH_40: 264 bw = "40"; 265 break; 266 case NL80211_CHAN_WIDTH_80: 267 bw = "80"; 268 break; 269 case NL80211_CHAN_WIDTH_160: 270 bw = "160"; 271 break; 272 case NL80211_CHAN_WIDTH_80P80: 273 bw = "80P80"; 274 break; 275 default: 276 bw = "20"; 277 break; 278 } 279 280 seq_printf(s, "channel %d (%d MHz) width %s MHz center1: %d MHz\n", 281 chandef->chan->hw_value, chandef->chan->center_freq, 282 bw, chandef->center_freq1); 283 out: 284 mutex_unlock(&dev->mt76.mutex); 285 286 return ret; 287 } 288 289 static int 290 mt7996_fw_debug_wm_set(void *data, u64 val) 291 { 292 struct mt7996_dev *dev = data; 293 enum { 294 DEBUG_TXCMD = 62, 295 DEBUG_CMD_RPT_TX, 296 DEBUG_CMD_RPT_TRIG, 297 DEBUG_SPL, 298 DEBUG_RPT_RX, 299 DEBUG_RPT_RA = 68, 300 } debug; 301 bool tx, rx, en; 302 int ret; 303 304 dev->fw_debug_wm = val ? MCU_FW_LOG_TO_HOST : 0; 305 306 if (dev->fw_debug_bin) 307 val = MCU_FW_LOG_RELAY; 308 else 309 val = dev->fw_debug_wm; 310 311 tx = dev->fw_debug_wm || (dev->fw_debug_bin & BIT(1)); 312 rx = dev->fw_debug_wm || (dev->fw_debug_bin & BIT(2)); 313 en = dev->fw_debug_wm || (dev->fw_debug_bin & BIT(0)); 314 315 ret = mt7996_mcu_fw_log_2_host(dev, MCU_FW_LOG_WM, val); 316 if (ret) 317 return ret; 318 319 for (debug = DEBUG_TXCMD; debug <= DEBUG_RPT_RA; debug++) { 320 if (debug == 67) 321 continue; 322 323 if (debug == DEBUG_RPT_RX) 324 val = en && rx; 325 else 326 val = en && tx; 327 328 ret = mt7996_mcu_fw_dbg_ctrl(dev, debug, val); 329 if (ret) 330 return ret; 331 } 332 333 return 0; 334 } 335 336 static int 337 mt7996_fw_debug_wm_get(void *data, u64 *val) 338 { 339 struct mt7996_dev *dev = data; 340 341 *val = dev->fw_debug_wm; 342 343 return 0; 344 } 345 346 DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_wm, mt7996_fw_debug_wm_get, 347 mt7996_fw_debug_wm_set, "%lld\n"); 348 349 static int 350 mt7996_fw_debug_wa_set(void *data, u64 val) 351 { 352 struct mt7996_dev *dev = data; 353 int ret; 354 355 dev->fw_debug_wa = val ? MCU_FW_LOG_TO_HOST : 0; 356 357 ret = mt7996_mcu_fw_log_2_host(dev, MCU_FW_LOG_WA, dev->fw_debug_wa); 358 if (ret) 359 return ret; 360 361 return mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), MCU_WA_PARAM_PDMA_RX, 362 !!dev->fw_debug_wa, 0); 363 } 364 365 static int 366 mt7996_fw_debug_wa_get(void *data, u64 *val) 367 { 368 struct mt7996_dev *dev = data; 369 370 *val = dev->fw_debug_wa; 371 372 return 0; 373 } 374 375 DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_wa, mt7996_fw_debug_wa_get, 376 mt7996_fw_debug_wa_set, "%lld\n"); 377 378 static struct dentry * 379 create_buf_file_cb(const char *filename, struct dentry *parent, umode_t mode, 380 struct rchan_buf *buf, int *is_global) 381 { 382 struct dentry *f; 383 384 f = debugfs_create_file("fwlog_data", mode, parent, buf, 385 &relay_file_operations); 386 if (IS_ERR(f)) 387 return NULL; 388 389 *is_global = 1; 390 391 return f; 392 } 393 394 static int 395 remove_buf_file_cb(struct dentry *f) 396 { 397 debugfs_remove(f); 398 399 return 0; 400 } 401 402 static int 403 mt7996_fw_debug_bin_set(void *data, u64 val) 404 { 405 static struct rchan_callbacks relay_cb = { 406 .create_buf_file = create_buf_file_cb, 407 .remove_buf_file = remove_buf_file_cb, 408 }; 409 struct mt7996_dev *dev = data; 410 411 if (!dev->relay_fwlog) 412 dev->relay_fwlog = relay_open("fwlog_data", dev->debugfs_dir, 413 1500, 512, &relay_cb, NULL); 414 if (!dev->relay_fwlog) 415 return -ENOMEM; 416 417 dev->fw_debug_bin = val; 418 419 relay_reset(dev->relay_fwlog); 420 421 return mt7996_fw_debug_wm_set(dev, dev->fw_debug_wm); 422 } 423 424 static int 425 mt7996_fw_debug_bin_get(void *data, u64 *val) 426 { 427 struct mt7996_dev *dev = data; 428 429 *val = dev->fw_debug_bin; 430 431 return 0; 432 } 433 434 DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_bin, mt7996_fw_debug_bin_get, 435 mt7996_fw_debug_bin_set, "%lld\n"); 436 437 static int 438 mt7996_fw_util_wa_show(struct seq_file *file, void *data) 439 { 440 struct mt7996_dev *dev = file->private; 441 442 if (dev->fw_debug_wa) 443 return mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(QUERY), 444 MCU_WA_PARAM_CPU_UTIL, 0, 0); 445 446 return 0; 447 } 448 449 DEFINE_SHOW_ATTRIBUTE(mt7996_fw_util_wa); 450 451 static void 452 mt7996_ampdu_stat_read_phy(struct mt7996_phy *phy, struct seq_file *file) 453 { 454 struct mt7996_dev *dev = phy->dev; 455 int bound[15], range[8], i; 456 u8 band_idx = phy->mt76->band_idx; 457 458 /* Tx ampdu stat */ 459 for (i = 0; i < ARRAY_SIZE(range); i++) 460 range[i] = mt76_rr(dev, MT_MIB_ARNG(band_idx, i)); 461 462 for (i = 0; i < ARRAY_SIZE(bound); i++) 463 bound[i] = MT_MIB_ARNCR_RANGE(range[i / 2], i % 2) + 1; 464 465 seq_printf(file, "\nPhy %s, Phy band %d\n", 466 wiphy_name(phy->mt76->hw->wiphy), band_idx); 467 468 seq_printf(file, "Length: %8d | ", bound[0]); 469 for (i = 0; i < ARRAY_SIZE(bound) - 1; i++) 470 seq_printf(file, "%3d -%3d | ", 471 bound[i] + 1, bound[i + 1]); 472 473 seq_puts(file, "\nCount: "); 474 for (i = 0; i < ARRAY_SIZE(bound); i++) 475 seq_printf(file, "%8d | ", phy->mt76->aggr_stats[i]); 476 seq_puts(file, "\n"); 477 478 seq_printf(file, "BA miss count: %d\n", phy->mib.ba_miss_cnt); 479 } 480 481 static void 482 mt7996_txbf_stat_read_phy(struct mt7996_phy *phy, struct seq_file *s) 483 { 484 struct mt76_mib_stats *mib = &phy->mib; 485 static const char * const bw[] = { 486 "BW20", "BW40", "BW80", "BW160", "BW320" 487 }; 488 489 /* Tx Beamformer monitor */ 490 seq_puts(s, "\nTx Beamformer applied PPDU counts: "); 491 492 seq_printf(s, "iBF: %d, eBF: %d\n", 493 mib->tx_bf_ibf_ppdu_cnt, 494 mib->tx_bf_ebf_ppdu_cnt); 495 496 /* Tx Beamformer Rx feedback monitor */ 497 seq_puts(s, "Tx Beamformer Rx feedback statistics: "); 498 499 seq_printf(s, "All: %d, EHT: %d, HE: %d, VHT: %d, HT: %d, ", 500 mib->tx_bf_rx_fb_all_cnt, 501 mib->tx_bf_rx_fb_eht_cnt, 502 mib->tx_bf_rx_fb_he_cnt, 503 mib->tx_bf_rx_fb_vht_cnt, 504 mib->tx_bf_rx_fb_ht_cnt); 505 506 seq_printf(s, "%s, NC: %d, NR: %d\n", 507 bw[mib->tx_bf_rx_fb_bw], 508 mib->tx_bf_rx_fb_nc_cnt, 509 mib->tx_bf_rx_fb_nr_cnt); 510 511 /* Tx Beamformee Rx NDPA & Tx feedback report */ 512 seq_printf(s, "Tx Beamformee successful feedback frames: %d\n", 513 mib->tx_bf_fb_cpl_cnt); 514 seq_printf(s, "Tx Beamformee feedback triggered counts: %d\n", 515 mib->tx_bf_fb_trig_cnt); 516 517 /* Tx SU & MU counters */ 518 seq_printf(s, "Tx multi-user Beamforming counts: %d\n", 519 mib->tx_mu_bf_cnt); 520 seq_printf(s, "Tx multi-user MPDU counts: %d\n", mib->tx_mu_mpdu_cnt); 521 seq_printf(s, "Tx multi-user successful MPDU counts: %d\n", 522 mib->tx_mu_acked_mpdu_cnt); 523 seq_printf(s, "Tx single-user successful MPDU counts: %d\n", 524 mib->tx_su_acked_mpdu_cnt); 525 526 seq_puts(s, "\n"); 527 } 528 529 static void 530 mt7996_tx_stats_show_phy(struct seq_file *file, struct mt7996_phy *phy) 531 { 532 struct mt76_mib_stats *mib = &phy->mib; 533 u32 attempts, success, per; 534 int i; 535 536 mt7996_mac_update_stats(phy); 537 mt7996_ampdu_stat_read_phy(phy, file); 538 539 attempts = mib->tx_mpdu_attempts_cnt; 540 success = mib->tx_mpdu_success_cnt; 541 per = attempts ? 100 - success * 100 / attempts : 100; 542 seq_printf(file, "Tx attempts: %8u (MPDUs)\n", attempts); 543 seq_printf(file, "Tx success: %8u (MPDUs)\n", success); 544 seq_printf(file, "Tx PER: %u%%\n", per); 545 546 mt7996_txbf_stat_read_phy(phy, file); 547 548 /* Tx amsdu info */ 549 seq_puts(file, "Tx MSDU statistics:\n"); 550 for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) { 551 seq_printf(file, "AMSDU pack count of %d MSDU in TXD: %8d ", 552 i + 1, mib->tx_amsdu[i]); 553 if (mib->tx_amsdu_cnt) 554 seq_printf(file, "(%3d%%)\n", 555 mib->tx_amsdu[i] * 100 / mib->tx_amsdu_cnt); 556 else 557 seq_puts(file, "\n"); 558 } 559 } 560 561 static int 562 mt7996_tx_stats_show(struct seq_file *file, void *data) 563 { 564 struct mt7996_dev *dev = file->private; 565 struct mt7996_phy *phy = &dev->phy; 566 567 mutex_lock(&dev->mt76.mutex); 568 569 mt7996_tx_stats_show_phy(file, phy); 570 phy = mt7996_phy2(dev); 571 if (phy) 572 mt7996_tx_stats_show_phy(file, phy); 573 phy = mt7996_phy3(dev); 574 if (phy) 575 mt7996_tx_stats_show_phy(file, phy); 576 577 mutex_unlock(&dev->mt76.mutex); 578 579 return 0; 580 } 581 582 DEFINE_SHOW_ATTRIBUTE(mt7996_tx_stats); 583 584 static void 585 mt7996_hw_queue_read(struct seq_file *s, u32 size, 586 const struct hw_queue_map *map) 587 { 588 struct mt7996_phy *phy = s->private; 589 struct mt7996_dev *dev = phy->dev; 590 u32 i, val; 591 592 val = mt76_rr(dev, MT_FL_Q_EMPTY); 593 for (i = 0; i < size; i++) { 594 u32 ctrl, head, tail, queued; 595 596 if (val & BIT(map[i].index)) 597 continue; 598 599 ctrl = BIT(31) | (map[i].pid << 10) | ((u32)map[i].qid << 24); 600 mt76_wr(dev, MT_FL_Q0_CTRL, ctrl); 601 602 head = mt76_get_field(dev, MT_FL_Q2_CTRL, 603 GENMASK(11, 0)); 604 tail = mt76_get_field(dev, MT_FL_Q2_CTRL, 605 GENMASK(27, 16)); 606 queued = mt76_get_field(dev, MT_FL_Q3_CTRL, 607 GENMASK(11, 0)); 608 609 seq_printf(s, "\t%s: ", map[i].name); 610 seq_printf(s, "queued:0x%03x head:0x%03x tail:0x%03x\n", 611 queued, head, tail); 612 } 613 } 614 615 static void 616 mt7996_sta_hw_queue_read(void *data, struct ieee80211_sta *sta) 617 { 618 struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv; 619 struct mt7996_dev *dev = msta->vif->deflink.phy->dev; 620 struct seq_file *s = data; 621 u8 ac; 622 623 for (ac = 0; ac < 4; ac++) { 624 u32 qlen, ctrl, val; 625 u32 idx = msta->wcid.idx >> 5; 626 u8 offs = msta->wcid.idx & GENMASK(4, 0); 627 628 ctrl = BIT(31) | BIT(11) | (ac << 24); 629 val = mt76_rr(dev, MT_PLE_AC_QEMPTY(ac, idx)); 630 631 if (val & BIT(offs)) 632 continue; 633 634 mt76_wr(dev, MT_FL_Q0_CTRL, ctrl | msta->wcid.idx); 635 qlen = mt76_get_field(dev, MT_FL_Q3_CTRL, 636 GENMASK(11, 0)); 637 seq_printf(s, "\tSTA %pM wcid %d: AC%d%d queued:%d\n", 638 sta->addr, msta->wcid.idx, 639 msta->vif->deflink.mt76.wmm_idx, ac, qlen); 640 } 641 } 642 643 static int 644 mt7996_hw_queues_show(struct seq_file *file, void *data) 645 { 646 struct mt7996_dev *dev = file->private; 647 struct mt7996_phy *phy = &dev->phy; 648 static const struct hw_queue_map ple_queue_map[] = { 649 { "CPU_Q0", 0, 1, MT_CTX0 }, 650 { "CPU_Q1", 1, 1, MT_CTX0 + 1 }, 651 { "CPU_Q2", 2, 1, MT_CTX0 + 2 }, 652 { "CPU_Q3", 3, 1, MT_CTX0 + 3 }, 653 { "ALTX_Q0", 8, 2, MT_LMAC_ALTX0 }, 654 { "BMC_Q0", 9, 2, MT_LMAC_BMC0 }, 655 { "BCN_Q0", 10, 2, MT_LMAC_BCN0 }, 656 { "PSMP_Q0", 11, 2, MT_LMAC_PSMP0 }, 657 { "ALTX_Q1", 12, 2, MT_LMAC_ALTX0 + 4 }, 658 { "BMC_Q1", 13, 2, MT_LMAC_BMC0 + 4 }, 659 { "BCN_Q1", 14, 2, MT_LMAC_BCN0 + 4 }, 660 { "PSMP_Q1", 15, 2, MT_LMAC_PSMP0 + 4 }, 661 }; 662 static const struct hw_queue_map pse_queue_map[] = { 663 { "CPU Q0", 0, 1, MT_CTX0 }, 664 { "CPU Q1", 1, 1, MT_CTX0 + 1 }, 665 { "CPU Q2", 2, 1, MT_CTX0 + 2 }, 666 { "CPU Q3", 3, 1, MT_CTX0 + 3 }, 667 { "HIF_Q0", 8, 0, MT_HIF0 }, 668 { "HIF_Q1", 9, 0, MT_HIF0 + 1 }, 669 { "HIF_Q2", 10, 0, MT_HIF0 + 2 }, 670 { "HIF_Q3", 11, 0, MT_HIF0 + 3 }, 671 { "HIF_Q4", 12, 0, MT_HIF0 + 4 }, 672 { "HIF_Q5", 13, 0, MT_HIF0 + 5 }, 673 { "LMAC_Q", 16, 2, 0 }, 674 { "MDP_TXQ", 17, 2, 1 }, 675 { "MDP_RXQ", 18, 2, 2 }, 676 { "SEC_TXQ", 19, 2, 3 }, 677 { "SEC_RXQ", 20, 2, 4 }, 678 }; 679 u32 val, head, tail; 680 681 /* ple queue */ 682 val = mt76_rr(dev, MT_PLE_FREEPG_CNT); 683 head = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(11, 0)); 684 tail = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(27, 16)); 685 seq_puts(file, "PLE page info:\n"); 686 seq_printf(file, 687 "\tTotal free page: 0x%08x head: 0x%03x tail: 0x%03x\n", 688 val, head, tail); 689 690 val = mt76_rr(dev, MT_PLE_PG_HIF_GROUP); 691 head = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(11, 0)); 692 tail = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(27, 16)); 693 seq_printf(file, "\tHIF free page: 0x%03x res: 0x%03x used: 0x%03x\n", 694 val, head, tail); 695 696 seq_puts(file, "PLE non-empty queue info:\n"); 697 mt7996_hw_queue_read(file, ARRAY_SIZE(ple_queue_map), 698 &ple_queue_map[0]); 699 700 /* iterate per-sta ple queue */ 701 ieee80211_iterate_stations_atomic(phy->mt76->hw, 702 mt7996_sta_hw_queue_read, file); 703 phy = mt7996_phy2(dev); 704 if (phy) 705 ieee80211_iterate_stations_atomic(phy->mt76->hw, 706 mt7996_sta_hw_queue_read, file); 707 phy = mt7996_phy3(dev); 708 if (phy) 709 ieee80211_iterate_stations_atomic(phy->mt76->hw, 710 mt7996_sta_hw_queue_read, file); 711 712 /* pse queue */ 713 seq_puts(file, "PSE non-empty queue info:\n"); 714 mt7996_hw_queue_read(file, ARRAY_SIZE(pse_queue_map), 715 &pse_queue_map[0]); 716 717 return 0; 718 } 719 720 DEFINE_SHOW_ATTRIBUTE(mt7996_hw_queues); 721 722 static int 723 mt7996_xmit_queues_show(struct seq_file *file, void *data) 724 { 725 struct mt7996_dev *dev = file->private; 726 struct mt7996_phy *phy; 727 struct { 728 struct mt76_queue *q; 729 char *queue; 730 } queue_map[] = { 731 { dev->mphy.q_tx[MT_TXQ_BE], " MAIN0" }, 732 { NULL, " MAIN1" }, 733 { NULL, " MAIN2" }, 734 { dev->mt76.q_mcu[MT_MCUQ_WM], " MCUWM" }, 735 { dev->mt76.q_mcu[MT_MCUQ_WA], " MCUWA" }, 736 { dev->mt76.q_mcu[MT_MCUQ_FWDL], "MCUFWDL" }, 737 }; 738 int i; 739 740 phy = mt7996_phy2(dev); 741 if (phy) 742 queue_map[1].q = phy->mt76->q_tx[MT_TXQ_BE]; 743 744 phy = mt7996_phy3(dev); 745 if (phy) 746 queue_map[2].q = phy->mt76->q_tx[MT_TXQ_BE]; 747 748 seq_puts(file, " queue | hw-queued | head | tail |\n"); 749 for (i = 0; i < ARRAY_SIZE(queue_map); i++) { 750 struct mt76_queue *q = queue_map[i].q; 751 752 if (!q) 753 continue; 754 755 seq_printf(file, " %s | %9d | %9d | %9d |\n", 756 queue_map[i].queue, q->queued, q->head, 757 q->tail); 758 } 759 760 return 0; 761 } 762 763 DEFINE_SHOW_ATTRIBUTE(mt7996_xmit_queues); 764 765 static int 766 mt7996_twt_stats(struct seq_file *s, void *data) 767 { 768 struct mt7996_dev *dev = dev_get_drvdata(s->private); 769 struct mt7996_twt_flow *iter; 770 771 rcu_read_lock(); 772 773 seq_puts(s, " wcid | id | flags | exp | mantissa"); 774 seq_puts(s, " | duration | tsf |\n"); 775 list_for_each_entry_rcu(iter, &dev->twt_list, list) 776 seq_printf(s, 777 "%9d | %8d | %5c%c%c%c | %8d | %8d | %8d | %14lld |\n", 778 iter->wcid, iter->id, 779 iter->sched ? 's' : 'u', 780 iter->protection ? 'p' : '-', 781 iter->trigger ? 't' : '-', 782 iter->flowtype ? '-' : 'a', 783 iter->exp, iter->mantissa, 784 iter->duration, iter->tsf); 785 786 rcu_read_unlock(); 787 788 return 0; 789 } 790 791 /* The index of RF registers use the generic regidx, combined with two parts: 792 * WF selection [31:24] and offset [23:0]. 793 */ 794 static int 795 mt7996_rf_regval_get(void *data, u64 *val) 796 { 797 struct mt7996_dev *dev = data; 798 u32 regval; 799 int ret; 800 801 ret = mt7996_mcu_rf_regval(dev, dev->mt76.debugfs_reg, ®val, false); 802 if (ret) 803 return ret; 804 805 *val = regval; 806 807 return 0; 808 } 809 810 static int 811 mt7996_rf_regval_set(void *data, u64 val) 812 { 813 struct mt7996_dev *dev = data; 814 u32 val32 = val; 815 816 return mt7996_mcu_rf_regval(dev, dev->mt76.debugfs_reg, &val32, true); 817 } 818 819 DEFINE_DEBUGFS_ATTRIBUTE(fops_rf_regval, mt7996_rf_regval_get, 820 mt7996_rf_regval_set, "0x%08llx\n"); 821 822 int mt7996_init_debugfs(struct mt7996_dev *dev) 823 { 824 struct dentry *dir; 825 826 dir = mt76_register_debugfs_fops(&dev->mphy, NULL); 827 if (!dir) 828 return -ENOMEM; 829 830 debugfs_create_file("hw-queues", 0400, dir, dev, 831 &mt7996_hw_queues_fops); 832 debugfs_create_file("xmit-queues", 0400, dir, dev, 833 &mt7996_xmit_queues_fops); 834 debugfs_create_file("tx_stats", 0400, dir, dev, &mt7996_tx_stats_fops); 835 debugfs_create_file("sys_recovery", 0600, dir, dev, 836 &mt7996_sys_recovery_ops); 837 debugfs_create_file("fw_debug_wm", 0600, dir, dev, &fops_fw_debug_wm); 838 debugfs_create_file("fw_debug_wa", 0600, dir, dev, &fops_fw_debug_wa); 839 debugfs_create_file("fw_debug_bin", 0600, dir, dev, &fops_fw_debug_bin); 840 /* TODO: wm fw cpu utilization */ 841 debugfs_create_file("fw_util_wa", 0400, dir, dev, 842 &mt7996_fw_util_wa_fops); 843 debugfs_create_file("implicit_txbf", 0600, dir, dev, 844 &fops_implicit_txbf); 845 debugfs_create_devm_seqfile(dev->mt76.dev, "twt_stats", dir, 846 mt7996_twt_stats); 847 debugfs_create_file("rf_regval", 0600, dir, dev, &fops_rf_regval); 848 849 debugfs_create_u32("dfs_hw_pattern", 0400, dir, &dev->hw_pattern); 850 debugfs_create_file("radar_trigger", 0200, dir, dev, 851 &fops_radar_trigger); 852 debugfs_create_devm_seqfile(dev->mt76.dev, "rdd_monitor", dir, 853 mt7996_rdd_monitor); 854 855 dev->debugfs_dir = dir; 856 857 return 0; 858 } 859 860 static void 861 mt7996_debugfs_write_fwlog(struct mt7996_dev *dev, const void *hdr, int hdrlen, 862 const void *data, int len) 863 { 864 static DEFINE_SPINLOCK(lock); 865 unsigned long flags; 866 void *dest; 867 868 spin_lock_irqsave(&lock, flags); 869 dest = relay_reserve(dev->relay_fwlog, hdrlen + len + 4); 870 if (dest) { 871 *(u32 *)dest = hdrlen + len; 872 dest += 4; 873 874 if (hdrlen) { 875 memcpy(dest, hdr, hdrlen); 876 dest += hdrlen; 877 } 878 879 memcpy(dest, data, len); 880 relay_flush(dev->relay_fwlog); 881 } 882 spin_unlock_irqrestore(&lock, flags); 883 } 884 885 void mt7996_debugfs_rx_fw_monitor(struct mt7996_dev *dev, const void *data, int len) 886 { 887 struct { 888 __le32 magic; 889 u8 version; 890 u8 _rsv; 891 __le16 serial_id; 892 __le32 timestamp; 893 __le16 msg_type; 894 __le16 len; 895 } hdr = { 896 .version = 0x1, 897 .magic = cpu_to_le32(FW_BIN_LOG_MAGIC), 898 .msg_type = cpu_to_le16(PKT_TYPE_RX_FW_MONITOR), 899 }; 900 901 if (!dev->relay_fwlog) 902 return; 903 904 hdr.serial_id = cpu_to_le16(dev->fw_debug_seq++); 905 hdr.timestamp = cpu_to_le32(mt76_rr(dev, MT_LPON_FRCR(0))); 906 hdr.len = *(__le16 *)data; 907 mt7996_debugfs_write_fwlog(dev, &hdr, sizeof(hdr), data, len); 908 } 909 910 bool mt7996_debugfs_rx_log(struct mt7996_dev *dev, const void *data, int len) 911 { 912 if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC) 913 return false; 914 915 if (dev->relay_fwlog) 916 mt7996_debugfs_write_fwlog(dev, NULL, 0, data, len); 917 918 return true; 919 } 920 921 #ifdef CONFIG_MAC80211_DEBUGFS 922 /** per-station debugfs **/ 923 924 static ssize_t mt7996_sta_fixed_rate_set(struct file *file, 925 const char __user *user_buf, 926 size_t count, loff_t *ppos) 927 { 928 #define SHORT_PREAMBLE 0 929 #define LONG_PREAMBLE 1 930 struct ieee80211_sta *sta = file->private_data; 931 struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv; 932 struct mt7996_dev *dev = msta->vif->deflink.phy->dev; 933 struct ra_rate phy = {}; 934 char buf[100]; 935 int ret; 936 u16 gi, ltf; 937 938 if (count >= sizeof(buf)) 939 return -EINVAL; 940 941 if (copy_from_user(buf, user_buf, count)) 942 return -EFAULT; 943 944 if (count && buf[count - 1] == '\n') 945 buf[count - 1] = '\0'; 946 else 947 buf[count] = '\0'; 948 949 /* mode - cck: 0, ofdm: 1, ht: 2, gf: 3, vht: 4, he_su: 8, he_er: 9 EHT: 15 950 * bw - bw20: 0, bw40: 1, bw80: 2, bw160: 3, BW320: 4 951 * nss - vht: 1~4, he: 1~4, eht: 1~4, others: ignore 952 * mcs - cck: 0~4, ofdm: 0~7, ht: 0~32, vht: 0~9, he_su: 0~11, he_er: 0~2, eht: 0~13 953 * gi - (ht/vht) lgi: 0, sgi: 1; (he) 0.8us: 0, 1.6us: 1, 3.2us: 2 954 * preamble - short: 1, long: 0 955 * ldpc - off: 0, on: 1 956 * stbc - off: 0, on: 1 957 * ltf - 1xltf: 0, 2xltf: 1, 4xltf: 2 958 */ 959 if (sscanf(buf, "%hhu %hhu %hhu %hhu %hu %hhu %hhu %hhu %hhu %hu", 960 &phy.mode, &phy.bw, &phy.mcs, &phy.nss, &gi, 961 &phy.preamble, &phy.stbc, &phy.ldpc, &phy.spe, <f) != 10) { 962 dev_warn(dev->mt76.dev, 963 "format: Mode BW MCS NSS GI Preamble STBC LDPC SPE ltf\n"); 964 goto out; 965 } 966 967 phy.wlan_idx = cpu_to_le16(msta->wcid.idx); 968 phy.gi = cpu_to_le16(gi); 969 phy.ltf = cpu_to_le16(ltf); 970 phy.ldpc = phy.ldpc ? 7 : 0; 971 phy.preamble = phy.preamble ? SHORT_PREAMBLE : LONG_PREAMBLE; 972 973 ret = mt7996_mcu_set_fixed_rate_ctrl(dev, &phy, 0); 974 if (ret) 975 return -EFAULT; 976 977 out: 978 return count; 979 } 980 981 static const struct file_operations fops_fixed_rate = { 982 .write = mt7996_sta_fixed_rate_set, 983 .open = simple_open, 984 .owner = THIS_MODULE, 985 .llseek = default_llseek, 986 }; 987 988 static int 989 mt7996_queues_show(struct seq_file *s, void *data) 990 { 991 struct ieee80211_sta *sta = s->private; 992 993 mt7996_sta_hw_queue_read(s, sta); 994 995 return 0; 996 } 997 998 DEFINE_SHOW_ATTRIBUTE(mt7996_queues); 999 1000 void mt7996_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1001 struct ieee80211_sta *sta, struct dentry *dir) 1002 { 1003 debugfs_create_file("fixed_rate", 0600, dir, sta, &fops_fixed_rate); 1004 debugfs_create_file("hw-queues", 0400, dir, sta, &mt7996_queues_fops); 1005 } 1006 1007 #endif 1008