1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #include <linux/relay.h> 7 #include "mt7996.h" 8 #include "eeprom.h" 9 #include "mcu.h" 10 #include "mac.h" 11 12 #define FW_BIN_LOG_MAGIC 0x44d9c99a 13 14 /** global debugfs **/ 15 16 struct hw_queue_map { 17 const char *name; 18 u8 index; 19 u8 pid; 20 u8 qid; 21 }; 22 23 static int 24 mt7996_implicit_txbf_set(void *data, u64 val) 25 { 26 struct mt7996_dev *dev = data; 27 28 /* The existing connected stations shall reconnect to apply 29 * new implicit txbf configuration. 30 */ 31 dev->ibf = !!val; 32 33 return mt7996_mcu_set_txbf(dev, BF_HW_EN_UPDATE); 34 } 35 36 static int 37 mt7996_implicit_txbf_get(void *data, u64 *val) 38 { 39 struct mt7996_dev *dev = data; 40 41 *val = dev->ibf; 42 43 return 0; 44 } 45 46 DEFINE_DEBUGFS_ATTRIBUTE(fops_implicit_txbf, mt7996_implicit_txbf_get, 47 mt7996_implicit_txbf_set, "%lld\n"); 48 49 /* test knob of system error recovery */ 50 static ssize_t 51 mt7996_sys_recovery_set(struct file *file, const char __user *user_buf, 52 size_t count, loff_t *ppos) 53 { 54 struct mt7996_phy *phy = file->private_data; 55 struct mt7996_dev *dev = phy->dev; 56 bool band = phy->mt76->band_idx; 57 char buf[16]; 58 int ret = 0; 59 u16 val; 60 61 if (count >= sizeof(buf)) 62 return -EINVAL; 63 64 if (copy_from_user(buf, user_buf, count)) 65 return -EFAULT; 66 67 if (count && buf[count - 1] == '\n') 68 buf[count - 1] = '\0'; 69 else 70 buf[count] = '\0'; 71 72 if (kstrtou16(buf, 0, &val)) 73 return -EINVAL; 74 75 switch (val) { 76 /* 77 * 0: grab firmware current SER state. 78 * 1: trigger & enable system error L1 recovery. 79 * 2: trigger & enable system error L2 recovery. 80 * 3: trigger & enable system error L3 rx abort. 81 * 4: trigger & enable system error L3 tx abort 82 * 5: trigger & enable system error L3 tx disable. 83 * 6: trigger & enable system error L3 bf recovery. 84 * 7: trigger & enable system error L4 mdp recovery. 85 * 8: trigger & enable system error full recovery. 86 * 9: trigger firmware crash. 87 */ 88 case UNI_CMD_SER_QUERY: 89 ret = mt7996_mcu_set_ser(dev, UNI_CMD_SER_QUERY, 0, band); 90 break; 91 case UNI_CMD_SER_SET_RECOVER_L1: 92 case UNI_CMD_SER_SET_RECOVER_L2: 93 case UNI_CMD_SER_SET_RECOVER_L3_RX_ABORT: 94 case UNI_CMD_SER_SET_RECOVER_L3_TX_ABORT: 95 case UNI_CMD_SER_SET_RECOVER_L3_TX_DISABLE: 96 case UNI_CMD_SER_SET_RECOVER_L3_BF: 97 case UNI_CMD_SER_SET_RECOVER_L4_MDP: 98 ret = mt7996_mcu_set_ser(dev, UNI_CMD_SER_SET, BIT(val), band); 99 if (ret) 100 return ret; 101 102 ret = mt7996_mcu_set_ser(dev, UNI_CMD_SER_TRIGGER, val, band); 103 break; 104 105 /* enable full chip reset */ 106 case UNI_CMD_SER_SET_RECOVER_FULL: 107 mt76_set(dev, MT_WFDMA0_MCU_HOST_INT_ENA, MT_MCU_CMD_WDT_MASK); 108 dev->recovery.state |= MT_MCU_CMD_WDT_MASK; 109 mt7996_reset(dev); 110 break; 111 112 /* WARNING: trigger firmware crash */ 113 case UNI_CMD_SER_SET_SYSTEM_ASSERT: 114 ret = mt7996_mcu_trigger_assert(dev); 115 if (ret) 116 return ret; 117 break; 118 default: 119 break; 120 } 121 122 return ret ? ret : count; 123 } 124 125 static ssize_t 126 mt7996_sys_recovery_get(struct file *file, char __user *user_buf, 127 size_t count, loff_t *ppos) 128 { 129 struct mt7996_phy *phy = file->private_data; 130 struct mt7996_dev *dev = phy->dev; 131 char *buff; 132 int desc = 0; 133 ssize_t ret; 134 static const size_t bufsz = 1024; 135 136 buff = kmalloc(bufsz, GFP_KERNEL); 137 if (!buff) 138 return -ENOMEM; 139 140 /* HELP */ 141 desc += scnprintf(buff + desc, bufsz - desc, 142 "Please echo the correct value ...\n"); 143 desc += scnprintf(buff + desc, bufsz - desc, 144 "0: grab firmware transient SER state\n"); 145 desc += scnprintf(buff + desc, bufsz - desc, 146 "1: trigger system error L1 recovery\n"); 147 desc += scnprintf(buff + desc, bufsz - desc, 148 "2: trigger system error L2 recovery\n"); 149 desc += scnprintf(buff + desc, bufsz - desc, 150 "3: trigger system error L3 rx abort\n"); 151 desc += scnprintf(buff + desc, bufsz - desc, 152 "4: trigger system error L3 tx abort\n"); 153 desc += scnprintf(buff + desc, bufsz - desc, 154 "5: trigger system error L3 tx disable\n"); 155 desc += scnprintf(buff + desc, bufsz - desc, 156 "6: trigger system error L3 bf recovery\n"); 157 desc += scnprintf(buff + desc, bufsz - desc, 158 "7: trigger system error L4 mdp recovery\n"); 159 desc += scnprintf(buff + desc, bufsz - desc, 160 "8: trigger system error full recovery\n"); 161 desc += scnprintf(buff + desc, bufsz - desc, 162 "9: trigger firmware crash\n"); 163 164 /* SER statistics */ 165 desc += scnprintf(buff + desc, bufsz - desc, 166 "\nlet's dump firmware SER statistics...\n"); 167 desc += scnprintf(buff + desc, bufsz - desc, 168 "::E R , SER_STATUS = 0x%08x\n", 169 mt76_rr(dev, MT_SWDEF_SER_STATS)); 170 desc += scnprintf(buff + desc, bufsz - desc, 171 "::E R , SER_PLE_ERR = 0x%08x\n", 172 mt76_rr(dev, MT_SWDEF_PLE_STATS)); 173 desc += scnprintf(buff + desc, bufsz - desc, 174 "::E R , SER_PLE_ERR_1 = 0x%08x\n", 175 mt76_rr(dev, MT_SWDEF_PLE1_STATS)); 176 desc += scnprintf(buff + desc, bufsz - desc, 177 "::E R , SER_PLE_ERR_AMSDU = 0x%08x\n", 178 mt76_rr(dev, MT_SWDEF_PLE_AMSDU_STATS)); 179 desc += scnprintf(buff + desc, bufsz - desc, 180 "::E R , SER_PSE_ERR = 0x%08x\n", 181 mt76_rr(dev, MT_SWDEF_PSE_STATS)); 182 desc += scnprintf(buff + desc, bufsz - desc, 183 "::E R , SER_PSE_ERR_1 = 0x%08x\n", 184 mt76_rr(dev, MT_SWDEF_PSE1_STATS)); 185 desc += scnprintf(buff + desc, bufsz - desc, 186 "::E R , SER_LMAC_WISR6_B0 = 0x%08x\n", 187 mt76_rr(dev, MT_SWDEF_LAMC_WISR6_BN0_STATS)); 188 desc += scnprintf(buff + desc, bufsz - desc, 189 "::E R , SER_LMAC_WISR6_B1 = 0x%08x\n", 190 mt76_rr(dev, MT_SWDEF_LAMC_WISR6_BN1_STATS)); 191 desc += scnprintf(buff + desc, bufsz - desc, 192 "::E R , SER_LMAC_WISR6_B2 = 0x%08x\n", 193 mt76_rr(dev, MT_SWDEF_LAMC_WISR6_BN2_STATS)); 194 desc += scnprintf(buff + desc, bufsz - desc, 195 "::E R , SER_LMAC_WISR7_B0 = 0x%08x\n", 196 mt76_rr(dev, MT_SWDEF_LAMC_WISR7_BN0_STATS)); 197 desc += scnprintf(buff + desc, bufsz - desc, 198 "::E R , SER_LMAC_WISR7_B1 = 0x%08x\n", 199 mt76_rr(dev, MT_SWDEF_LAMC_WISR7_BN1_STATS)); 200 desc += scnprintf(buff + desc, bufsz - desc, 201 "::E R , SER_LMAC_WISR7_B2 = 0x%08x\n", 202 mt76_rr(dev, MT_SWDEF_LAMC_WISR7_BN2_STATS)); 203 desc += scnprintf(buff + desc, bufsz - desc, 204 "\nSYS_RESET_COUNT: WM %d, WA %d\n", 205 dev->recovery.wm_reset_count, 206 dev->recovery.wa_reset_count); 207 208 ret = simple_read_from_buffer(user_buf, count, ppos, buff, desc); 209 kfree(buff); 210 return ret; 211 } 212 213 static const struct file_operations mt7996_sys_recovery_ops = { 214 .write = mt7996_sys_recovery_set, 215 .read = mt7996_sys_recovery_get, 216 .open = simple_open, 217 .llseek = default_llseek, 218 }; 219 220 static int 221 mt7996_radar_trigger(void *data, u64 val) 222 { 223 struct mt7996_dev *dev = data; 224 225 if (val > MT_RX_SEL2) 226 return -EINVAL; 227 228 return mt7996_mcu_rdd_cmd(dev, RDD_RADAR_EMULATE, 229 val, 0, 0); 230 } 231 232 DEFINE_DEBUGFS_ATTRIBUTE(fops_radar_trigger, NULL, 233 mt7996_radar_trigger, "%lld\n"); 234 235 static int 236 mt7996_rdd_monitor(struct seq_file *s, void *data) 237 { 238 struct mt7996_dev *dev = dev_get_drvdata(s->private); 239 struct cfg80211_chan_def *chandef = &dev->rdd2_chandef; 240 const char *bw; 241 int ret = 0; 242 243 mutex_lock(&dev->mt76.mutex); 244 245 if (!cfg80211_chandef_valid(chandef)) { 246 ret = -EINVAL; 247 goto out; 248 } 249 250 if (!dev->rdd2_phy) { 251 seq_puts(s, "not running\n"); 252 goto out; 253 } 254 255 switch (chandef->width) { 256 case NL80211_CHAN_WIDTH_40: 257 bw = "40"; 258 break; 259 case NL80211_CHAN_WIDTH_80: 260 bw = "80"; 261 break; 262 case NL80211_CHAN_WIDTH_160: 263 bw = "160"; 264 break; 265 case NL80211_CHAN_WIDTH_80P80: 266 bw = "80P80"; 267 break; 268 default: 269 bw = "20"; 270 break; 271 } 272 273 seq_printf(s, "channel %d (%d MHz) width %s MHz center1: %d MHz\n", 274 chandef->chan->hw_value, chandef->chan->center_freq, 275 bw, chandef->center_freq1); 276 out: 277 mutex_unlock(&dev->mt76.mutex); 278 279 return ret; 280 } 281 282 static int 283 mt7996_fw_debug_wm_set(void *data, u64 val) 284 { 285 struct mt7996_dev *dev = data; 286 enum { 287 DEBUG_TXCMD = 62, 288 DEBUG_CMD_RPT_TX, 289 DEBUG_CMD_RPT_TRIG, 290 DEBUG_SPL, 291 DEBUG_RPT_RX, 292 DEBUG_RPT_RA = 68, 293 } debug; 294 bool tx, rx, en; 295 int ret; 296 297 dev->fw_debug_wm = val ? MCU_FW_LOG_TO_HOST : 0; 298 299 if (dev->fw_debug_bin) 300 val = MCU_FW_LOG_RELAY; 301 else 302 val = dev->fw_debug_wm; 303 304 tx = dev->fw_debug_wm || (dev->fw_debug_bin & BIT(1)); 305 rx = dev->fw_debug_wm || (dev->fw_debug_bin & BIT(2)); 306 en = dev->fw_debug_wm || (dev->fw_debug_bin & BIT(0)); 307 308 ret = mt7996_mcu_fw_log_2_host(dev, MCU_FW_LOG_WM, val); 309 if (ret) 310 return ret; 311 312 for (debug = DEBUG_TXCMD; debug <= DEBUG_RPT_RA; debug++) { 313 if (debug == 67) 314 continue; 315 316 if (debug == DEBUG_RPT_RX) 317 val = en && rx; 318 else 319 val = en && tx; 320 321 ret = mt7996_mcu_fw_dbg_ctrl(dev, debug, val); 322 if (ret) 323 return ret; 324 } 325 326 return 0; 327 } 328 329 static int 330 mt7996_fw_debug_wm_get(void *data, u64 *val) 331 { 332 struct mt7996_dev *dev = data; 333 334 *val = dev->fw_debug_wm; 335 336 return 0; 337 } 338 339 DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_wm, mt7996_fw_debug_wm_get, 340 mt7996_fw_debug_wm_set, "%lld\n"); 341 342 static int 343 mt7996_fw_debug_wa_set(void *data, u64 val) 344 { 345 struct mt7996_dev *dev = data; 346 int ret; 347 348 dev->fw_debug_wa = val ? MCU_FW_LOG_TO_HOST : 0; 349 350 ret = mt7996_mcu_fw_log_2_host(dev, MCU_FW_LOG_WA, dev->fw_debug_wa); 351 if (ret) 352 return ret; 353 354 return mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), MCU_WA_PARAM_PDMA_RX, 355 !!dev->fw_debug_wa, 0); 356 } 357 358 static int 359 mt7996_fw_debug_wa_get(void *data, u64 *val) 360 { 361 struct mt7996_dev *dev = data; 362 363 *val = dev->fw_debug_wa; 364 365 return 0; 366 } 367 368 DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_wa, mt7996_fw_debug_wa_get, 369 mt7996_fw_debug_wa_set, "%lld\n"); 370 371 static struct dentry * 372 create_buf_file_cb(const char *filename, struct dentry *parent, umode_t mode, 373 struct rchan_buf *buf, int *is_global) 374 { 375 struct dentry *f; 376 377 f = debugfs_create_file("fwlog_data", mode, parent, buf, 378 &relay_file_operations); 379 if (IS_ERR(f)) 380 return NULL; 381 382 *is_global = 1; 383 384 return f; 385 } 386 387 static int 388 remove_buf_file_cb(struct dentry *f) 389 { 390 debugfs_remove(f); 391 392 return 0; 393 } 394 395 static int 396 mt7996_fw_debug_bin_set(void *data, u64 val) 397 { 398 static struct rchan_callbacks relay_cb = { 399 .create_buf_file = create_buf_file_cb, 400 .remove_buf_file = remove_buf_file_cb, 401 }; 402 struct mt7996_dev *dev = data; 403 404 if (!dev->relay_fwlog) 405 dev->relay_fwlog = relay_open("fwlog_data", dev->debugfs_dir, 406 1500, 512, &relay_cb, NULL); 407 if (!dev->relay_fwlog) 408 return -ENOMEM; 409 410 dev->fw_debug_bin = val; 411 412 relay_reset(dev->relay_fwlog); 413 414 return mt7996_fw_debug_wm_set(dev, dev->fw_debug_wm); 415 } 416 417 static int 418 mt7996_fw_debug_bin_get(void *data, u64 *val) 419 { 420 struct mt7996_dev *dev = data; 421 422 *val = dev->fw_debug_bin; 423 424 return 0; 425 } 426 427 DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_bin, mt7996_fw_debug_bin_get, 428 mt7996_fw_debug_bin_set, "%lld\n"); 429 430 static int 431 mt7996_fw_util_wa_show(struct seq_file *file, void *data) 432 { 433 struct mt7996_dev *dev = file->private; 434 435 if (dev->fw_debug_wa) 436 return mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(QUERY), 437 MCU_WA_PARAM_CPU_UTIL, 0, 0); 438 439 return 0; 440 } 441 442 DEFINE_SHOW_ATTRIBUTE(mt7996_fw_util_wa); 443 444 static void 445 mt7996_ampdu_stat_read_phy(struct mt7996_phy *phy, struct seq_file *file) 446 { 447 struct mt7996_dev *dev = phy->dev; 448 int bound[15], range[8], i; 449 u8 band_idx = phy->mt76->band_idx; 450 451 /* Tx ampdu stat */ 452 for (i = 0; i < ARRAY_SIZE(range); i++) 453 range[i] = mt76_rr(dev, MT_MIB_ARNG(band_idx, i)); 454 455 for (i = 0; i < ARRAY_SIZE(bound); i++) 456 bound[i] = MT_MIB_ARNCR_RANGE(range[i / 2], i % 2) + 1; 457 458 seq_printf(file, "\nPhy %s, Phy band %d\n", 459 wiphy_name(phy->mt76->hw->wiphy), band_idx); 460 461 seq_printf(file, "Length: %8d | ", bound[0]); 462 for (i = 0; i < ARRAY_SIZE(bound) - 1; i++) 463 seq_printf(file, "%3d -%3d | ", 464 bound[i] + 1, bound[i + 1]); 465 466 seq_puts(file, "\nCount: "); 467 for (i = 0; i < ARRAY_SIZE(bound); i++) 468 seq_printf(file, "%8d | ", phy->mt76->aggr_stats[i]); 469 seq_puts(file, "\n"); 470 471 seq_printf(file, "BA miss count: %d\n", phy->mib.ba_miss_cnt); 472 } 473 474 static void 475 mt7996_txbf_stat_read_phy(struct mt7996_phy *phy, struct seq_file *s) 476 { 477 struct mt76_mib_stats *mib = &phy->mib; 478 static const char * const bw[] = { 479 "BW20", "BW40", "BW80", "BW160", "BW320" 480 }; 481 482 /* Tx Beamformer monitor */ 483 seq_puts(s, "\nTx Beamformer applied PPDU counts: "); 484 485 seq_printf(s, "iBF: %d, eBF: %d\n", 486 mib->tx_bf_ibf_ppdu_cnt, 487 mib->tx_bf_ebf_ppdu_cnt); 488 489 /* Tx Beamformer Rx feedback monitor */ 490 seq_puts(s, "Tx Beamformer Rx feedback statistics: "); 491 492 seq_printf(s, "All: %d, EHT: %d, HE: %d, VHT: %d, HT: %d, ", 493 mib->tx_bf_rx_fb_all_cnt, 494 mib->tx_bf_rx_fb_eht_cnt, 495 mib->tx_bf_rx_fb_he_cnt, 496 mib->tx_bf_rx_fb_vht_cnt, 497 mib->tx_bf_rx_fb_ht_cnt); 498 499 seq_printf(s, "%s, NC: %d, NR: %d\n", 500 bw[mib->tx_bf_rx_fb_bw], 501 mib->tx_bf_rx_fb_nc_cnt, 502 mib->tx_bf_rx_fb_nr_cnt); 503 504 /* Tx Beamformee Rx NDPA & Tx feedback report */ 505 seq_printf(s, "Tx Beamformee successful feedback frames: %d\n", 506 mib->tx_bf_fb_cpl_cnt); 507 seq_printf(s, "Tx Beamformee feedback triggered counts: %d\n", 508 mib->tx_bf_fb_trig_cnt); 509 510 /* Tx SU & MU counters */ 511 seq_printf(s, "Tx multi-user Beamforming counts: %d\n", 512 mib->tx_mu_bf_cnt); 513 seq_printf(s, "Tx multi-user MPDU counts: %d\n", mib->tx_mu_mpdu_cnt); 514 seq_printf(s, "Tx multi-user successful MPDU counts: %d\n", 515 mib->tx_mu_acked_mpdu_cnt); 516 seq_printf(s, "Tx single-user successful MPDU counts: %d\n", 517 mib->tx_su_acked_mpdu_cnt); 518 519 seq_puts(s, "\n"); 520 } 521 522 static int 523 mt7996_tx_stats_show(struct seq_file *file, void *data) 524 { 525 struct mt7996_phy *phy = file->private; 526 struct mt7996_dev *dev = phy->dev; 527 struct mt76_mib_stats *mib = &phy->mib; 528 int i; 529 u32 attempts, success, per; 530 531 mutex_lock(&dev->mt76.mutex); 532 533 mt7996_mac_update_stats(phy); 534 mt7996_ampdu_stat_read_phy(phy, file); 535 536 attempts = mib->tx_mpdu_attempts_cnt; 537 success = mib->tx_mpdu_success_cnt; 538 per = attempts ? 100 - success * 100 / attempts : 100; 539 seq_printf(file, "Tx attempts: %8u (MPDUs)\n", attempts); 540 seq_printf(file, "Tx success: %8u (MPDUs)\n", success); 541 seq_printf(file, "Tx PER: %u%%\n", per); 542 543 mt7996_txbf_stat_read_phy(phy, file); 544 545 /* Tx amsdu info */ 546 seq_puts(file, "Tx MSDU statistics:\n"); 547 for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) { 548 seq_printf(file, "AMSDU pack count of %d MSDU in TXD: %8d ", 549 i + 1, mib->tx_amsdu[i]); 550 if (mib->tx_amsdu_cnt) 551 seq_printf(file, "(%3d%%)\n", 552 mib->tx_amsdu[i] * 100 / mib->tx_amsdu_cnt); 553 else 554 seq_puts(file, "\n"); 555 } 556 557 mutex_unlock(&dev->mt76.mutex); 558 559 return 0; 560 } 561 562 DEFINE_SHOW_ATTRIBUTE(mt7996_tx_stats); 563 564 static void 565 mt7996_hw_queue_read(struct seq_file *s, u32 size, 566 const struct hw_queue_map *map) 567 { 568 struct mt7996_phy *phy = s->private; 569 struct mt7996_dev *dev = phy->dev; 570 u32 i, val; 571 572 val = mt76_rr(dev, MT_FL_Q_EMPTY); 573 for (i = 0; i < size; i++) { 574 u32 ctrl, head, tail, queued; 575 576 if (val & BIT(map[i].index)) 577 continue; 578 579 ctrl = BIT(31) | (map[i].pid << 10) | ((u32)map[i].qid << 24); 580 mt76_wr(dev, MT_FL_Q0_CTRL, ctrl); 581 582 head = mt76_get_field(dev, MT_FL_Q2_CTRL, 583 GENMASK(11, 0)); 584 tail = mt76_get_field(dev, MT_FL_Q2_CTRL, 585 GENMASK(27, 16)); 586 queued = mt76_get_field(dev, MT_FL_Q3_CTRL, 587 GENMASK(11, 0)); 588 589 seq_printf(s, "\t%s: ", map[i].name); 590 seq_printf(s, "queued:0x%03x head:0x%03x tail:0x%03x\n", 591 queued, head, tail); 592 } 593 } 594 595 static void 596 mt7996_sta_hw_queue_read(void *data, struct ieee80211_sta *sta) 597 { 598 struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv; 599 struct mt7996_dev *dev = msta->vif->phy->dev; 600 struct seq_file *s = data; 601 u8 ac; 602 603 for (ac = 0; ac < 4; ac++) { 604 u32 qlen, ctrl, val; 605 u32 idx = msta->wcid.idx >> 5; 606 u8 offs = msta->wcid.idx & GENMASK(4, 0); 607 608 ctrl = BIT(31) | BIT(11) | (ac << 24); 609 val = mt76_rr(dev, MT_PLE_AC_QEMPTY(ac, idx)); 610 611 if (val & BIT(offs)) 612 continue; 613 614 mt76_wr(dev, MT_FL_Q0_CTRL, ctrl | msta->wcid.idx); 615 qlen = mt76_get_field(dev, MT_FL_Q3_CTRL, 616 GENMASK(11, 0)); 617 seq_printf(s, "\tSTA %pM wcid %d: AC%d%d queued:%d\n", 618 sta->addr, msta->wcid.idx, 619 msta->vif->mt76.wmm_idx, ac, qlen); 620 } 621 } 622 623 static int 624 mt7996_hw_queues_show(struct seq_file *file, void *data) 625 { 626 struct mt7996_phy *phy = file->private; 627 struct mt7996_dev *dev = phy->dev; 628 static const struct hw_queue_map ple_queue_map[] = { 629 { "CPU_Q0", 0, 1, MT_CTX0 }, 630 { "CPU_Q1", 1, 1, MT_CTX0 + 1 }, 631 { "CPU_Q2", 2, 1, MT_CTX0 + 2 }, 632 { "CPU_Q3", 3, 1, MT_CTX0 + 3 }, 633 { "ALTX_Q0", 8, 2, MT_LMAC_ALTX0 }, 634 { "BMC_Q0", 9, 2, MT_LMAC_BMC0 }, 635 { "BCN_Q0", 10, 2, MT_LMAC_BCN0 }, 636 { "PSMP_Q0", 11, 2, MT_LMAC_PSMP0 }, 637 { "ALTX_Q1", 12, 2, MT_LMAC_ALTX0 + 4 }, 638 { "BMC_Q1", 13, 2, MT_LMAC_BMC0 + 4 }, 639 { "BCN_Q1", 14, 2, MT_LMAC_BCN0 + 4 }, 640 { "PSMP_Q1", 15, 2, MT_LMAC_PSMP0 + 4 }, 641 }; 642 static const struct hw_queue_map pse_queue_map[] = { 643 { "CPU Q0", 0, 1, MT_CTX0 }, 644 { "CPU Q1", 1, 1, MT_CTX0 + 1 }, 645 { "CPU Q2", 2, 1, MT_CTX0 + 2 }, 646 { "CPU Q3", 3, 1, MT_CTX0 + 3 }, 647 { "HIF_Q0", 8, 0, MT_HIF0 }, 648 { "HIF_Q1", 9, 0, MT_HIF0 + 1 }, 649 { "HIF_Q2", 10, 0, MT_HIF0 + 2 }, 650 { "HIF_Q3", 11, 0, MT_HIF0 + 3 }, 651 { "HIF_Q4", 12, 0, MT_HIF0 + 4 }, 652 { "HIF_Q5", 13, 0, MT_HIF0 + 5 }, 653 { "LMAC_Q", 16, 2, 0 }, 654 { "MDP_TXQ", 17, 2, 1 }, 655 { "MDP_RXQ", 18, 2, 2 }, 656 { "SEC_TXQ", 19, 2, 3 }, 657 { "SEC_RXQ", 20, 2, 4 }, 658 }; 659 u32 val, head, tail; 660 661 /* ple queue */ 662 val = mt76_rr(dev, MT_PLE_FREEPG_CNT); 663 head = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(11, 0)); 664 tail = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(27, 16)); 665 seq_puts(file, "PLE page info:\n"); 666 seq_printf(file, 667 "\tTotal free page: 0x%08x head: 0x%03x tail: 0x%03x\n", 668 val, head, tail); 669 670 val = mt76_rr(dev, MT_PLE_PG_HIF_GROUP); 671 head = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(11, 0)); 672 tail = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(27, 16)); 673 seq_printf(file, "\tHIF free page: 0x%03x res: 0x%03x used: 0x%03x\n", 674 val, head, tail); 675 676 seq_puts(file, "PLE non-empty queue info:\n"); 677 mt7996_hw_queue_read(file, ARRAY_SIZE(ple_queue_map), 678 &ple_queue_map[0]); 679 680 /* iterate per-sta ple queue */ 681 ieee80211_iterate_stations_atomic(phy->mt76->hw, 682 mt7996_sta_hw_queue_read, file); 683 /* pse queue */ 684 seq_puts(file, "PSE non-empty queue info:\n"); 685 mt7996_hw_queue_read(file, ARRAY_SIZE(pse_queue_map), 686 &pse_queue_map[0]); 687 688 return 0; 689 } 690 691 DEFINE_SHOW_ATTRIBUTE(mt7996_hw_queues); 692 693 static int 694 mt7996_xmit_queues_show(struct seq_file *file, void *data) 695 { 696 struct mt7996_phy *phy = file->private; 697 struct mt7996_dev *dev = phy->dev; 698 struct { 699 struct mt76_queue *q; 700 char *queue; 701 } queue_map[] = { 702 { phy->mt76->q_tx[MT_TXQ_BE], " MAIN" }, 703 { dev->mt76.q_mcu[MT_MCUQ_WM], " MCUWM" }, 704 { dev->mt76.q_mcu[MT_MCUQ_WA], " MCUWA" }, 705 { dev->mt76.q_mcu[MT_MCUQ_FWDL], "MCUFWDL" }, 706 }; 707 int i; 708 709 seq_puts(file, " queue | hw-queued | head | tail |\n"); 710 for (i = 0; i < ARRAY_SIZE(queue_map); i++) { 711 struct mt76_queue *q = queue_map[i].q; 712 713 if (!q) 714 continue; 715 716 seq_printf(file, " %s | %9d | %9d | %9d |\n", 717 queue_map[i].queue, q->queued, q->head, 718 q->tail); 719 } 720 721 return 0; 722 } 723 724 DEFINE_SHOW_ATTRIBUTE(mt7996_xmit_queues); 725 726 static int 727 mt7996_twt_stats(struct seq_file *s, void *data) 728 { 729 struct mt7996_dev *dev = dev_get_drvdata(s->private); 730 struct mt7996_twt_flow *iter; 731 732 rcu_read_lock(); 733 734 seq_puts(s, " wcid | id | flags | exp | mantissa"); 735 seq_puts(s, " | duration | tsf |\n"); 736 list_for_each_entry_rcu(iter, &dev->twt_list, list) 737 seq_printf(s, 738 "%9d | %8d | %5c%c%c%c | %8d | %8d | %8d | %14lld |\n", 739 iter->wcid, iter->id, 740 iter->sched ? 's' : 'u', 741 iter->protection ? 'p' : '-', 742 iter->trigger ? 't' : '-', 743 iter->flowtype ? '-' : 'a', 744 iter->exp, iter->mantissa, 745 iter->duration, iter->tsf); 746 747 rcu_read_unlock(); 748 749 return 0; 750 } 751 752 /* The index of RF registers use the generic regidx, combined with two parts: 753 * WF selection [31:24] and offset [23:0]. 754 */ 755 static int 756 mt7996_rf_regval_get(void *data, u64 *val) 757 { 758 struct mt7996_dev *dev = data; 759 u32 regval; 760 int ret; 761 762 ret = mt7996_mcu_rf_regval(dev, dev->mt76.debugfs_reg, ®val, false); 763 if (ret) 764 return ret; 765 766 *val = regval; 767 768 return 0; 769 } 770 771 static int 772 mt7996_rf_regval_set(void *data, u64 val) 773 { 774 struct mt7996_dev *dev = data; 775 u32 val32 = val; 776 777 return mt7996_mcu_rf_regval(dev, dev->mt76.debugfs_reg, &val32, true); 778 } 779 780 DEFINE_DEBUGFS_ATTRIBUTE(fops_rf_regval, mt7996_rf_regval_get, 781 mt7996_rf_regval_set, "0x%08llx\n"); 782 783 int mt7996_init_debugfs(struct mt7996_phy *phy) 784 { 785 struct mt7996_dev *dev = phy->dev; 786 struct dentry *dir; 787 788 dir = mt76_register_debugfs_fops(phy->mt76, NULL); 789 if (!dir) 790 return -ENOMEM; 791 debugfs_create_file("hw-queues", 0400, dir, phy, 792 &mt7996_hw_queues_fops); 793 debugfs_create_file("xmit-queues", 0400, dir, phy, 794 &mt7996_xmit_queues_fops); 795 debugfs_create_file("tx_stats", 0400, dir, phy, &mt7996_tx_stats_fops); 796 debugfs_create_file("sys_recovery", 0600, dir, phy, 797 &mt7996_sys_recovery_ops); 798 debugfs_create_file("fw_debug_wm", 0600, dir, dev, &fops_fw_debug_wm); 799 debugfs_create_file("fw_debug_wa", 0600, dir, dev, &fops_fw_debug_wa); 800 debugfs_create_file("fw_debug_bin", 0600, dir, dev, &fops_fw_debug_bin); 801 /* TODO: wm fw cpu utilization */ 802 debugfs_create_file("fw_util_wa", 0400, dir, dev, 803 &mt7996_fw_util_wa_fops); 804 debugfs_create_file("implicit_txbf", 0600, dir, dev, 805 &fops_implicit_txbf); 806 debugfs_create_devm_seqfile(dev->mt76.dev, "twt_stats", dir, 807 mt7996_twt_stats); 808 debugfs_create_file("rf_regval", 0600, dir, dev, &fops_rf_regval); 809 810 if (phy->mt76->cap.has_5ghz) { 811 debugfs_create_u32("dfs_hw_pattern", 0400, dir, 812 &dev->hw_pattern); 813 debugfs_create_file("radar_trigger", 0200, dir, dev, 814 &fops_radar_trigger); 815 debugfs_create_devm_seqfile(dev->mt76.dev, "rdd_monitor", dir, 816 mt7996_rdd_monitor); 817 } 818 819 if (phy == &dev->phy) 820 dev->debugfs_dir = dir; 821 822 return 0; 823 } 824 825 static void 826 mt7996_debugfs_write_fwlog(struct mt7996_dev *dev, const void *hdr, int hdrlen, 827 const void *data, int len) 828 { 829 static DEFINE_SPINLOCK(lock); 830 unsigned long flags; 831 void *dest; 832 833 spin_lock_irqsave(&lock, flags); 834 dest = relay_reserve(dev->relay_fwlog, hdrlen + len + 4); 835 if (dest) { 836 *(u32 *)dest = hdrlen + len; 837 dest += 4; 838 839 if (hdrlen) { 840 memcpy(dest, hdr, hdrlen); 841 dest += hdrlen; 842 } 843 844 memcpy(dest, data, len); 845 relay_flush(dev->relay_fwlog); 846 } 847 spin_unlock_irqrestore(&lock, flags); 848 } 849 850 void mt7996_debugfs_rx_fw_monitor(struct mt7996_dev *dev, const void *data, int len) 851 { 852 struct { 853 __le32 magic; 854 u8 version; 855 u8 _rsv; 856 __le16 serial_id; 857 __le32 timestamp; 858 __le16 msg_type; 859 __le16 len; 860 } hdr = { 861 .version = 0x1, 862 .magic = cpu_to_le32(FW_BIN_LOG_MAGIC), 863 .msg_type = cpu_to_le16(PKT_TYPE_RX_FW_MONITOR), 864 }; 865 866 if (!dev->relay_fwlog) 867 return; 868 869 hdr.serial_id = cpu_to_le16(dev->fw_debug_seq++); 870 hdr.timestamp = cpu_to_le32(mt76_rr(dev, MT_LPON_FRCR(0))); 871 hdr.len = *(__le16 *)data; 872 mt7996_debugfs_write_fwlog(dev, &hdr, sizeof(hdr), data, len); 873 } 874 875 bool mt7996_debugfs_rx_log(struct mt7996_dev *dev, const void *data, int len) 876 { 877 if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC) 878 return false; 879 880 if (dev->relay_fwlog) 881 mt7996_debugfs_write_fwlog(dev, NULL, 0, data, len); 882 883 return true; 884 } 885 886 #ifdef CONFIG_MAC80211_DEBUGFS 887 /** per-station debugfs **/ 888 889 static ssize_t mt7996_sta_fixed_rate_set(struct file *file, 890 const char __user *user_buf, 891 size_t count, loff_t *ppos) 892 { 893 #define SHORT_PREAMBLE 0 894 #define LONG_PREAMBLE 1 895 struct ieee80211_sta *sta = file->private_data; 896 struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv; 897 struct mt7996_dev *dev = msta->vif->phy->dev; 898 struct ra_rate phy = {}; 899 char buf[100]; 900 int ret; 901 u16 gi, ltf; 902 903 if (count >= sizeof(buf)) 904 return -EINVAL; 905 906 if (copy_from_user(buf, user_buf, count)) 907 return -EFAULT; 908 909 if (count && buf[count - 1] == '\n') 910 buf[count - 1] = '\0'; 911 else 912 buf[count] = '\0'; 913 914 /* mode - cck: 0, ofdm: 1, ht: 2, gf: 3, vht: 4, he_su: 8, he_er: 9 EHT: 15 915 * bw - bw20: 0, bw40: 1, bw80: 2, bw160: 3, BW320: 4 916 * nss - vht: 1~4, he: 1~4, eht: 1~4, others: ignore 917 * mcs - cck: 0~4, ofdm: 0~7, ht: 0~32, vht: 0~9, he_su: 0~11, he_er: 0~2, eht: 0~13 918 * gi - (ht/vht) lgi: 0, sgi: 1; (he) 0.8us: 0, 1.6us: 1, 3.2us: 2 919 * preamble - short: 1, long: 0 920 * ldpc - off: 0, on: 1 921 * stbc - off: 0, on: 1 922 * ltf - 1xltf: 0, 2xltf: 1, 4xltf: 2 923 */ 924 if (sscanf(buf, "%hhu %hhu %hhu %hhu %hu %hhu %hhu %hhu %hhu %hu", 925 &phy.mode, &phy.bw, &phy.mcs, &phy.nss, &gi, 926 &phy.preamble, &phy.stbc, &phy.ldpc, &phy.spe, <f) != 10) { 927 dev_warn(dev->mt76.dev, 928 "format: Mode BW MCS NSS GI Preamble STBC LDPC SPE ltf\n"); 929 goto out; 930 } 931 932 phy.wlan_idx = cpu_to_le16(msta->wcid.idx); 933 phy.gi = cpu_to_le16(gi); 934 phy.ltf = cpu_to_le16(ltf); 935 phy.ldpc = phy.ldpc ? 7 : 0; 936 phy.preamble = phy.preamble ? SHORT_PREAMBLE : LONG_PREAMBLE; 937 938 ret = mt7996_mcu_set_fixed_rate_ctrl(dev, &phy, 0); 939 if (ret) 940 return -EFAULT; 941 942 out: 943 return count; 944 } 945 946 static const struct file_operations fops_fixed_rate = { 947 .write = mt7996_sta_fixed_rate_set, 948 .open = simple_open, 949 .owner = THIS_MODULE, 950 .llseek = default_llseek, 951 }; 952 953 static int 954 mt7996_queues_show(struct seq_file *s, void *data) 955 { 956 struct ieee80211_sta *sta = s->private; 957 958 mt7996_sta_hw_queue_read(s, sta); 959 960 return 0; 961 } 962 963 DEFINE_SHOW_ATTRIBUTE(mt7996_queues); 964 965 void mt7996_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 966 struct ieee80211_sta *sta, struct dentry *dir) 967 { 968 debugfs_create_file("fixed_rate", 0600, dir, sta, &fops_fixed_rate); 969 debugfs_create_file("hw-queues", 0400, dir, sta, &mt7996_queues_fops); 970 } 971 972 #endif 973