1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* Copyright (C) 2023 MediaTek Inc. */ 3 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 8 #include "mt7925.h" 9 #include "mac.h" 10 #include "mcu.h" 11 #include "regd.h" 12 #include "../dma.h" 13 14 static const struct pci_device_id mt7925_pci_device_table[] = { 15 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7925), 16 .driver_data = (kernel_ulong_t)MT7925_FIRMWARE_WM }, 17 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0717), 18 .driver_data = (kernel_ulong_t)MT7925_FIRMWARE_WM }, 19 { }, 20 }; 21 22 static bool mt7925_disable_aspm; 23 module_param_named(disable_aspm, mt7925_disable_aspm, bool, 0644); 24 MODULE_PARM_DESC(disable_aspm, "disable PCI ASPM support"); 25 26 static int mt7925e_init_reset(struct mt792x_dev *dev) 27 { 28 return mt792x_wpdma_reset(dev, true); 29 } 30 31 static void mt7925e_unregister_device(struct mt792x_dev *dev) 32 { 33 int i; 34 struct mt76_connac_pm *pm = &dev->pm; 35 struct ieee80211_hw *hw = mt76_hw(dev); 36 37 if (dev->phy.chip_cap & MT792x_CHIP_CAP_WF_RF_PIN_CTRL_EVT_EN) 38 wiphy_rfkill_stop_polling(hw->wiphy); 39 40 cancel_work_sync(&dev->init_work); 41 mt76_unregister_device(&dev->mt76); 42 mt76_for_each_q_rx(&dev->mt76, i) 43 napi_disable(&dev->mt76.napi[i]); 44 cancel_delayed_work_sync(&pm->ps_work); 45 cancel_work_sync(&pm->wake_work); 46 cancel_work_sync(&dev->reset_work); 47 48 mt7925_tx_token_put(dev); 49 __mt792x_mcu_drv_pmctrl(dev); 50 mt792x_dma_cleanup(dev); 51 mt792x_wfsys_reset(dev); 52 skb_queue_purge(&dev->mt76.mcu.res_q); 53 54 tasklet_disable(&dev->mt76.irq_tasklet); 55 } 56 57 static void mt7925_reg_remap_restore(struct mt792x_dev *dev) 58 { 59 /* remap to ori status */ 60 if (unlikely(dev->backup_l1)) { 61 dev->bus_ops->wr(&dev->mt76, MT_HIF_REMAP_L1, dev->backup_l1); 62 dev->backup_l1 = 0; 63 } 64 65 if (dev->backup_l2) { 66 dev->bus_ops->wr(&dev->mt76, MT_HIF_REMAP_L2, dev->backup_l2); 67 dev->backup_l2 = 0; 68 } 69 } 70 71 static u32 mt7925_reg_map_l1(struct mt792x_dev *dev, u32 addr) 72 { 73 u32 offset = FIELD_GET(MT_HIF_REMAP_L1_OFFSET, addr); 74 u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, addr); 75 76 dev->backup_l1 = dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1); 77 78 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L1, 79 MT_HIF_REMAP_L1_MASK, 80 FIELD_PREP(MT_HIF_REMAP_L1_MASK, base)); 81 82 /* use read to push write */ 83 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1); 84 85 return MT_HIF_REMAP_BASE_L1 + offset; 86 } 87 88 static u32 mt7925_reg_map_l2(struct mt792x_dev *dev, u32 addr) 89 { 90 u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, MT_HIF_REMAP_BASE_L2); 91 92 dev->backup_l2 = dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1); 93 94 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L1, 95 MT_HIF_REMAP_L1_MASK, 96 FIELD_PREP(MT_HIF_REMAP_L1_MASK, base)); 97 98 dev->bus_ops->wr(&dev->mt76, MT_HIF_REMAP_L2, addr); 99 /* use read to push write */ 100 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1); 101 102 return MT_HIF_REMAP_BASE_L1; 103 } 104 105 static u32 __mt7925_reg_addr(struct mt792x_dev *dev, u32 addr) 106 { 107 static const struct mt76_connac_reg_map fixed_map[] = { 108 { 0x830c0000, 0x000000, 0x0001000 }, /* WF_MCU_BUS_CR_REMAP */ 109 { 0x54000000, 0x002000, 0x0001000 }, /* WFDMA PCIE0 MCU DMA0 */ 110 { 0x55000000, 0x003000, 0x0001000 }, /* WFDMA PCIE0 MCU DMA1 */ 111 { 0x56000000, 0x004000, 0x0001000 }, /* WFDMA reserved */ 112 { 0x57000000, 0x005000, 0x0001000 }, /* WFDMA MCU wrap CR */ 113 { 0x58000000, 0x006000, 0x0001000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */ 114 { 0x59000000, 0x007000, 0x0001000 }, /* WFDMA PCIE1 MCU DMA1 */ 115 { 0x820c0000, 0x008000, 0x0004000 }, /* WF_UMAC_TOP (PLE) */ 116 { 0x820c8000, 0x00c000, 0x0002000 }, /* WF_UMAC_TOP (PSE) */ 117 { 0x820cc000, 0x00e000, 0x0002000 }, /* WF_UMAC_TOP (PP) */ 118 { 0x74030000, 0x010000, 0x0001000 }, /* PCIe MAC */ 119 { 0x820e0000, 0x020000, 0x0000400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */ 120 { 0x820e1000, 0x020400, 0x0000200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */ 121 { 0x820e2000, 0x020800, 0x0000400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ 122 { 0x820e3000, 0x020c00, 0x0000400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */ 123 { 0x820e4000, 0x021000, 0x0000400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ 124 { 0x820e5000, 0x021400, 0x0000800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */ 125 { 0x820ce000, 0x021c00, 0x0000200 }, /* WF_LMAC_TOP (WF_SEC) */ 126 { 0x820e7000, 0x021e00, 0x0000200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ 127 { 0x820cf000, 0x022000, 0x0001000 }, /* WF_LMAC_TOP (WF_PF) */ 128 { 0x820e9000, 0x023400, 0x0000200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ 129 { 0x820ea000, 0x024000, 0x0000200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */ 130 { 0x820eb000, 0x024200, 0x0000400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ 131 { 0x820ec000, 0x024600, 0x0000200 }, /* WF_LMAC_TOP BN0 (WF_INT) */ 132 { 0x820ed000, 0x024800, 0x0000800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ 133 { 0x820ca000, 0x026000, 0x0002000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */ 134 { 0x820d0000, 0x030000, 0x0010000 }, /* WF_LMAC_TOP (WF_WTBLON) */ 135 { 0x40000000, 0x070000, 0x0010000 }, /* WF_UMAC_SYSRAM */ 136 { 0x00400000, 0x080000, 0x0010000 }, /* WF_MCU_SYSRAM */ 137 { 0x00410000, 0x090000, 0x0010000 }, /* WF_MCU_SYSRAM (configure register) */ 138 { 0x820f0000, 0x0a0000, 0x0000400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */ 139 { 0x820f1000, 0x0a0600, 0x0000200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */ 140 { 0x820f2000, 0x0a0800, 0x0000400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */ 141 { 0x820f3000, 0x0a0c00, 0x0000400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */ 142 { 0x820f4000, 0x0a1000, 0x0000400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */ 143 { 0x820f5000, 0x0a1400, 0x0000800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */ 144 { 0x820f7000, 0x0a1e00, 0x0000200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */ 145 { 0x820f9000, 0x0a3400, 0x0000200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ 146 { 0x820fa000, 0x0a4000, 0x0000200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */ 147 { 0x820fb000, 0x0a4200, 0x0000400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */ 148 { 0x820fc000, 0x0a4600, 0x0000200 }, /* WF_LMAC_TOP BN1 (WF_INT) */ 149 { 0x820fd000, 0x0a4800, 0x0000800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */ 150 { 0x820c4000, 0x0a8000, 0x0004000 }, /* WF_LMAC_TOP BN1 (WF_MUCOP) */ 151 { 0x820b0000, 0x0ae000, 0x0001000 }, /* [APB2] WFSYS_ON */ 152 { 0x80020000, 0x0b0000, 0x0010000 }, /* WF_TOP_MISC_OFF */ 153 { 0x81020000, 0x0c0000, 0x0010000 }, /* WF_TOP_MISC_ON */ 154 { 0x7c020000, 0x0d0000, 0x0010000 }, /* CONN_INFRA, wfdma */ 155 { 0x7c060000, 0x0e0000, 0x0010000 }, /* CONN_INFRA, conn_host_csr_top */ 156 { 0x7c000000, 0x0f0000, 0x0010000 }, /* CONN_INFRA */ 157 { 0x70020000, 0x1f0000, 0x0010000 }, /* Reserved for CBTOP, can't switch */ 158 { 0x7c500000, 0x060000, 0x2000000 }, /* remap */ 159 { 0x0, 0x0, 0x0 } /* End */ 160 }; 161 int i; 162 163 if (addr < 0x200000) 164 return addr; 165 166 mt7925_reg_remap_restore(dev); 167 168 for (i = 0; i < ARRAY_SIZE(fixed_map); i++) { 169 u32 ofs; 170 171 if (addr < fixed_map[i].phys) 172 continue; 173 174 ofs = addr - fixed_map[i].phys; 175 if (ofs > fixed_map[i].size) 176 continue; 177 178 return fixed_map[i].maps + ofs; 179 } 180 181 if ((addr >= 0x18000000 && addr < 0x18c00000) || 182 (addr >= 0x70000000 && addr < 0x78000000) || 183 (addr >= 0x7c000000 && addr < 0x7c400000)) 184 return mt7925_reg_map_l1(dev, addr); 185 186 return mt7925_reg_map_l2(dev, addr); 187 } 188 189 static u32 mt7925_rr(struct mt76_dev *mdev, u32 offset) 190 { 191 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76); 192 u32 addr = __mt7925_reg_addr(dev, offset); 193 194 return dev->bus_ops->rr(mdev, addr); 195 } 196 197 static void mt7925_wr(struct mt76_dev *mdev, u32 offset, u32 val) 198 { 199 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76); 200 u32 addr = __mt7925_reg_addr(dev, offset); 201 202 dev->bus_ops->wr(mdev, addr, val); 203 } 204 205 static u32 mt7925_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val) 206 { 207 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76); 208 u32 addr = __mt7925_reg_addr(dev, offset); 209 210 return dev->bus_ops->rmw(mdev, addr, mask, val); 211 } 212 213 static int mt7925_dma_init(struct mt792x_dev *dev) 214 { 215 int ret; 216 217 mt76_dma_attach(&dev->mt76); 218 219 ret = mt792x_dma_disable(dev, true); 220 if (ret) 221 return ret; 222 223 /* init tx queue */ 224 ret = mt76_connac_init_tx_queues(dev->phy.mt76, MT7925_TXQ_BAND0, 225 MT7925_TX_RING_SIZE, 226 MT_TX_RING_BASE, NULL, 0); 227 if (ret) 228 return ret; 229 230 mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, 0x4); 231 232 /* command to WM */ 233 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7925_TXQ_MCU_WM, 234 MT7925_TX_MCU_RING_SIZE, MT_TX_RING_BASE); 235 if (ret) 236 return ret; 237 238 /* firmware download */ 239 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL, MT7925_TXQ_FWDL, 240 MT7925_TX_FWDL_RING_SIZE, MT_TX_RING_BASE); 241 if (ret) 242 return ret; 243 244 /* rx event */ 245 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 246 MT7925_RXQ_MCU_WM, MT7925_RX_MCU_RING_SIZE, 247 MT_RX_BUF_SIZE, MT_RX_EVENT_RING_BASE); 248 if (ret) 249 return ret; 250 251 /* rx data */ 252 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN], 253 MT7925_RXQ_BAND0, MT7925_RX_RING_SIZE, 254 MT_RX_BUF_SIZE, MT_RX_DATA_RING_BASE); 255 if (ret) 256 return ret; 257 258 ret = mt76_init_queues(dev, mt792x_poll_rx); 259 if (ret < 0) 260 return ret; 261 262 netif_napi_add_tx(dev->mt76.tx_napi_dev, &dev->mt76.tx_napi, 263 mt792x_poll_tx); 264 napi_enable(&dev->mt76.tx_napi); 265 266 return mt792x_dma_enable(dev); 267 } 268 269 static int mt7925_pci_probe(struct pci_dev *pdev, 270 const struct pci_device_id *id) 271 { 272 static const struct mt76_driver_ops drv_ops = { 273 /* txwi_size = txd size + txp size */ 274 .txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_hw_txp), 275 .drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ | 276 MT_DRV_AMSDU_OFFLOAD, 277 .survey_flags = SURVEY_INFO_TIME_TX | 278 SURVEY_INFO_TIME_RX | 279 SURVEY_INFO_TIME_BSS_RX, 280 .token_size = MT7925_TOKEN_SIZE, 281 .tx_prepare_skb = mt7925e_tx_prepare_skb, 282 .tx_complete_skb = mt76_connac_tx_complete_skb, 283 .rx_check = mt7925_rx_check, 284 .rx_skb = mt7925_queue_rx_skb, 285 .rx_poll_complete = mt792x_rx_poll_complete, 286 .sta_add = mt7925_mac_sta_add, 287 .sta_event = mt7925_mac_sta_event, 288 .sta_remove = mt7925_mac_sta_remove, 289 .update_survey = mt792x_update_channel, 290 }; 291 static const struct mt792x_hif_ops mt7925_pcie_ops = { 292 .init_reset = mt7925e_init_reset, 293 .reset = mt7925e_mac_reset, 294 .mcu_init = mt7925e_mcu_init, 295 .drv_own = mt792xe_mcu_drv_pmctrl, 296 .fw_own = mt792xe_mcu_fw_pmctrl, 297 }; 298 static const struct mt792x_irq_map irq_map = { 299 .host_irq_enable = MT_WFDMA0_HOST_INT_ENA, 300 .tx = { 301 .all_complete_mask = MT_INT_TX_DONE_ALL, 302 .mcu_complete_mask = MT_INT_TX_DONE_MCU, 303 }, 304 .rx = { 305 .data_complete_mask = HOST_RX_DONE_INT_ENA2, 306 .wm_complete_mask = HOST_RX_DONE_INT_ENA0, 307 }, 308 }; 309 struct ieee80211_ops *ops; 310 struct mt76_bus_ops *bus_ops; 311 struct mt792x_dev *dev; 312 struct mt76_dev *mdev; 313 u8 features; 314 int ret; 315 u16 cmd; 316 317 ret = pcim_enable_device(pdev); 318 if (ret) 319 return ret; 320 321 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev)); 322 if (ret) 323 return ret; 324 325 pci_read_config_word(pdev, PCI_COMMAND, &cmd); 326 if (!(cmd & PCI_COMMAND_MEMORY)) { 327 cmd |= PCI_COMMAND_MEMORY; 328 pci_write_config_word(pdev, PCI_COMMAND, cmd); 329 } 330 pci_set_master(pdev); 331 332 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 333 if (ret < 0) 334 return ret; 335 336 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 337 if (ret) 338 goto err_free_pci_vec; 339 340 if (mt7925_disable_aspm) 341 mt76_pci_disable_aspm(pdev); 342 343 ops = mt792x_get_mac80211_ops(&pdev->dev, &mt7925_ops, 344 (void *)id->driver_data, &features); 345 if (!ops) { 346 ret = -ENOMEM; 347 goto err_free_pci_vec; 348 } 349 350 mdev = mt76_alloc_device(&pdev->dev, sizeof(*dev), ops, &drv_ops); 351 if (!mdev) { 352 ret = -ENOMEM; 353 goto err_free_pci_vec; 354 } 355 356 pci_set_drvdata(pdev, mdev); 357 358 dev = container_of(mdev, struct mt792x_dev, mt76); 359 dev->fw_features = features; 360 dev->hif_ops = &mt7925_pcie_ops; 361 dev->irq_map = &irq_map; 362 mt76_mmio_init(&dev->mt76, pcim_iomap_table(pdev)[0]); 363 tasklet_init(&mdev->irq_tasklet, mt792x_irq_tasklet, (unsigned long)dev); 364 365 dev->phy.dev = dev; 366 dev->phy.mt76 = &dev->mt76.phy; 367 dev->mt76.phy.priv = &dev->phy; 368 dev->bus_ops = dev->mt76.bus; 369 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops), 370 GFP_KERNEL); 371 if (!bus_ops) { 372 ret = -ENOMEM; 373 goto err_free_dev; 374 } 375 376 bus_ops->rr = mt7925_rr; 377 bus_ops->wr = mt7925_wr; 378 bus_ops->rmw = mt7925_rmw; 379 dev->mt76.bus = bus_ops; 380 381 if (!mt7925_disable_aspm && mt76_pci_aspm_supported(pdev)) 382 dev->aspm_supported = true; 383 384 ret = __mt792x_mcu_fw_pmctrl(dev); 385 if (ret) 386 goto err_free_dev; 387 388 ret = __mt792xe_mcu_drv_pmctrl(dev); 389 if (ret) 390 goto err_free_dev; 391 392 mdev->rev = (mt76_rr(dev, MT_HW_CHIPID) << 16) | 393 (mt76_rr(dev, MT_HW_REV) & 0xff); 394 395 dev_info(mdev->dev, "ASIC revision: %04x\n", mdev->rev); 396 397 mt76_rmw_field(dev, MT_HW_EMI_CTL, MT_HW_EMI_CTL_SLPPROT_EN, 1); 398 399 ret = mt792x_wfsys_reset(dev); 400 if (ret) 401 goto err_free_dev; 402 403 mt76_wr(dev, irq_map.host_irq_enable, 0); 404 405 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff); 406 407 ret = devm_request_irq(mdev->dev, pdev->irq, mt792x_irq_handler, 408 IRQF_SHARED, KBUILD_MODNAME, dev); 409 if (ret) 410 goto err_free_dev; 411 412 ret = mt7925_dma_init(dev); 413 if (ret) 414 goto err_free_irq; 415 416 ret = mt7925_register_device(dev); 417 if (ret) 418 goto err_free_irq; 419 420 return 0; 421 422 err_free_irq: 423 devm_free_irq(&pdev->dev, pdev->irq, dev); 424 err_free_dev: 425 mt76_free_device(&dev->mt76); 426 err_free_pci_vec: 427 pci_free_irq_vectors(pdev); 428 429 return ret; 430 } 431 432 static void mt7925_pci_remove(struct pci_dev *pdev) 433 { 434 struct mt76_dev *mdev = pci_get_drvdata(pdev); 435 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76); 436 437 mt7925e_unregister_device(dev); 438 set_bit(MT76_REMOVED, &mdev->phy.state); 439 devm_free_irq(&pdev->dev, pdev->irq, dev); 440 mt76_free_device(&dev->mt76); 441 pci_free_irq_vectors(pdev); 442 } 443 444 static int mt7925_pci_suspend(struct device *device) 445 { 446 struct pci_dev *pdev = to_pci_dev(device); 447 struct mt76_dev *mdev = pci_get_drvdata(pdev); 448 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76); 449 struct mt76_connac_pm *pm = &dev->pm; 450 int i, err, ret; 451 452 pm->suspended = true; 453 dev->hif_resumed = false; 454 flush_work(&dev->reset_work); 455 cancel_delayed_work_sync(&pm->ps_work); 456 cancel_work_sync(&pm->wake_work); 457 458 mt7925_roc_abort_sync(dev); 459 460 err = mt792x_mcu_drv_pmctrl(dev); 461 if (err < 0) 462 goto restore_suspend; 463 464 wait_event_timeout(dev->wait, 465 !dev->regd_in_progress, 5 * HZ); 466 467 /* always enable deep sleep during suspend to reduce 468 * power consumption 469 */ 470 mt7925_mcu_set_deep_sleep(dev, true); 471 472 mt76_connac_mcu_set_hif_suspend(mdev, true, false); 473 ret = wait_event_timeout(dev->wait, 474 dev->hif_idle, 3 * HZ); 475 if (!ret) { 476 err = -ETIMEDOUT; 477 goto restore_suspend; 478 } 479 480 napi_disable(&mdev->tx_napi); 481 mt76_worker_disable(&mdev->tx_worker); 482 483 mt76_for_each_q_rx(mdev, i) { 484 napi_disable(&mdev->napi[i]); 485 } 486 487 /* wait until dma is idle */ 488 mt76_poll(dev, MT_WFDMA0_GLO_CFG, 489 MT_WFDMA0_GLO_CFG_TX_DMA_BUSY | 490 MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 1000); 491 492 /* put dma disabled */ 493 mt76_clear(dev, MT_WFDMA0_GLO_CFG, 494 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN); 495 496 /* disable interrupt */ 497 mt76_wr(dev, dev->irq_map->host_irq_enable, 0); 498 499 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0); 500 501 synchronize_irq(pdev->irq); 502 tasklet_kill(&mdev->irq_tasklet); 503 504 err = mt792x_mcu_fw_pmctrl(dev); 505 if (err) 506 goto restore_napi; 507 508 return 0; 509 510 restore_napi: 511 mt76_for_each_q_rx(mdev, i) { 512 napi_enable(&mdev->napi[i]); 513 } 514 napi_enable(&mdev->tx_napi); 515 516 if (!pm->ds_enable) 517 mt7925_mcu_set_deep_sleep(dev, false); 518 519 mt76_connac_mcu_set_hif_suspend(mdev, false, false); 520 ret = wait_event_timeout(dev->wait, 521 dev->hif_resumed, 3 * HZ); 522 if (!ret) 523 err = -ETIMEDOUT; 524 restore_suspend: 525 pm->suspended = false; 526 527 if (err < 0) 528 mt792x_reset(&dev->mt76); 529 530 return err; 531 } 532 533 static int _mt7925_pci_resume(struct device *device, bool restore) 534 { 535 struct pci_dev *pdev = to_pci_dev(device); 536 struct mt76_dev *mdev = pci_get_drvdata(pdev); 537 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76); 538 struct mt76_connac_pm *pm = &dev->pm; 539 int i, err, ret; 540 541 dev->hif_idle = false; 542 err = mt792x_mcu_drv_pmctrl(dev); 543 if (err < 0) 544 goto failed; 545 546 mt792x_wpdma_reinit_cond(dev); 547 548 /* enable interrupt */ 549 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff); 550 mt76_connac_irq_enable(&dev->mt76, 551 dev->irq_map->tx.all_complete_mask | 552 MT_INT_RX_DONE_ALL | MT_INT_MCU_CMD); 553 mt76_set(dev, MT_MCU2HOST_SW_INT_ENA, MT_MCU_CMD_WAKE_RX_PCIE); 554 555 /* put dma enabled */ 556 mt76_set(dev, MT_WFDMA0_GLO_CFG, 557 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN); 558 559 mt76_worker_enable(&mdev->tx_worker); 560 561 mt76_for_each_q_rx(mdev, i) { 562 napi_enable(&mdev->napi[i]); 563 } 564 napi_enable(&mdev->tx_napi); 565 566 local_bh_disable(); 567 mt76_for_each_q_rx(mdev, i) { 568 napi_schedule(&mdev->napi[i]); 569 } 570 napi_schedule(&mdev->tx_napi); 571 local_bh_enable(); 572 573 if (restore) 574 goto failed; 575 576 mt76_connac_mcu_set_hif_suspend(mdev, false, false); 577 ret = wait_event_timeout(dev->wait, 578 dev->hif_resumed, 3 * HZ); 579 if (!ret) { 580 err = -ETIMEDOUT; 581 goto failed; 582 } 583 584 /* restore previous ds setting */ 585 if (!pm->ds_enable) 586 mt7925_mcu_set_deep_sleep(dev, false); 587 588 mt7925_mcu_regd_update(dev, mdev->alpha2, dev->country_ie_env); 589 failed: 590 pm->suspended = false; 591 592 if (err < 0 || restore) 593 mt792x_reset(&dev->mt76); 594 595 return err; 596 } 597 598 static void mt7925_pci_shutdown(struct pci_dev *pdev) 599 { 600 mt7925_pci_remove(pdev); 601 } 602 603 static int mt7925_pci_resume(struct device *device) 604 { 605 return _mt7925_pci_resume(device, false); 606 } 607 608 static int mt7925_pci_restore(struct device *device) 609 { 610 return _mt7925_pci_resume(device, true); 611 } 612 613 static const struct dev_pm_ops mt7925_pm_ops = { 614 .suspend = pm_sleep_ptr(mt7925_pci_suspend), 615 .resume = pm_sleep_ptr(mt7925_pci_resume), 616 .freeze = pm_sleep_ptr(mt7925_pci_suspend), 617 .thaw = pm_sleep_ptr(mt7925_pci_resume), 618 .poweroff = pm_sleep_ptr(mt7925_pci_suspend), 619 .restore = pm_sleep_ptr(mt7925_pci_restore), 620 }; 621 622 static struct pci_driver mt7925_pci_driver = { 623 .name = KBUILD_MODNAME, 624 .id_table = mt7925_pci_device_table, 625 .probe = mt7925_pci_probe, 626 .remove = mt7925_pci_remove, 627 .shutdown = mt7925_pci_shutdown, 628 .driver.pm = pm_sleep_ptr(&mt7925_pm_ops), 629 }; 630 631 module_pci_driver(mt7925_pci_driver); 632 633 MODULE_DEVICE_TABLE(pci, mt7925_pci_device_table); 634 MODULE_FIRMWARE(MT7925_FIRMWARE_WM); 635 MODULE_FIRMWARE(MT7925_ROM_PATCH); 636 MODULE_AUTHOR("Deren Wu <deren.wu@mediatek.com>"); 637 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>"); 638 MODULE_DESCRIPTION("MediaTek MT7925E (PCIe) wireless driver"); 639 MODULE_LICENSE("Dual BSD/GPL"); 640