1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #ifndef __MT7921_REGS_H 5 #define __MT7921_REGS_H 6 7 #include "../mt792x_regs.h" 8 9 #define MT_MDP_BASE 0x820cd000 10 #define MT_MDP(ofs) (MT_MDP_BASE + (ofs)) 11 12 #define MT_MDP_DCR0 MT_MDP(0x000) 13 #define MT_MDP_DCR0_DAMSDU_EN BIT(15) 14 #define MT_MDP_DCR0_RX_HDR_TRANS_EN BIT(19) 15 16 #define MT_MDP_DCR1 MT_MDP(0x004) 17 #define MT_MDP_DCR1_MAX_RX_LEN GENMASK(15, 3) 18 19 #define MT_MDP_BNRCFR0(_band) MT_MDP(0x070 + ((_band) << 8)) 20 #define MT_MDP_RCFR0_MCU_RX_MGMT GENMASK(5, 4) 21 #define MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR GENMASK(7, 6) 22 #define MT_MDP_RCFR0_MCU_RX_CTL_BAR GENMASK(9, 8) 23 24 #define MT_MDP_BNRCFR1(_band) MT_MDP(0x074 + ((_band) << 8)) 25 #define MT_MDP_RCFR1_MCU_RX_BYPASS GENMASK(23, 22) 26 #define MT_MDP_RCFR1_RX_DROPPED_UCAST GENMASK(28, 27) 27 #define MT_MDP_RCFR1_RX_DROPPED_MCAST GENMASK(30, 29) 28 #define MT_MDP_TO_HIF 0 29 #define MT_MDP_TO_WM 1 30 31 #define MT_WFDMA0_HOST_INT_ENA MT_WFDMA0(0x204) 32 #define HOST_RX_DONE_INT_ENA0 BIT(0) 33 #define HOST_RX_DONE_INT_ENA1 BIT(1) 34 #define HOST_RX_DONE_INT_ENA2 BIT(2) 35 #define HOST_RX_DONE_INT_ENA3 BIT(3) 36 #define HOST_TX_DONE_INT_ENA0 BIT(4) 37 #define HOST_TX_DONE_INT_ENA1 BIT(5) 38 #define HOST_TX_DONE_INT_ENA2 BIT(6) 39 #define HOST_TX_DONE_INT_ENA3 BIT(7) 40 #define HOST_TX_DONE_INT_ENA4 BIT(8) 41 #define HOST_TX_DONE_INT_ENA5 BIT(9) 42 #define HOST_TX_DONE_INT_ENA6 BIT(10) 43 #define HOST_TX_DONE_INT_ENA7 BIT(11) 44 #define HOST_TX_DONE_INT_ENA8 BIT(12) 45 #define HOST_TX_DONE_INT_ENA9 BIT(13) 46 #define HOST_TX_DONE_INT_ENA10 BIT(14) 47 #define HOST_TX_DONE_INT_ENA11 BIT(15) 48 #define HOST_TX_DONE_INT_ENA12 BIT(16) 49 #define HOST_TX_DONE_INT_ENA13 BIT(17) 50 #define HOST_TX_DONE_INT_ENA14 BIT(18) 51 #define HOST_RX_COHERENT_EN BIT(20) 52 #define HOST_TX_COHERENT_EN BIT(21) 53 #define HOST_RX_DONE_INT_ENA4 BIT(22) 54 #define HOST_RX_DONE_INT_ENA5 BIT(23) 55 #define HOST_TX_DONE_INT_ENA16 BIT(26) 56 #define HOST_TX_DONE_INT_ENA17 BIT(27) 57 #define MCU2HOST_SW_INT_ENA BIT(29) 58 #define HOST_TX_DONE_INT_ENA18 BIT(30) 59 60 /* WFDMA interrupt */ 61 #define MT_INT_RX_DONE_DATA HOST_RX_DONE_INT_ENA2 62 #define MT_INT_RX_DONE_WM HOST_RX_DONE_INT_ENA0 63 #define MT_INT_RX_DONE_WM2 HOST_RX_DONE_INT_ENA4 64 #define MT_INT_RX_DONE_ALL (MT_INT_RX_DONE_DATA | \ 65 MT_INT_RX_DONE_WM | \ 66 MT_INT_RX_DONE_WM2) 67 #define MT_INT_TX_DONE_MCU_WM HOST_TX_DONE_INT_ENA17 68 #define MT_INT_TX_DONE_FWDL HOST_TX_DONE_INT_ENA16 69 #define MT_INT_TX_DONE_BAND0 HOST_TX_DONE_INT_ENA0 70 #define MT_INT_MCU_CMD MCU2HOST_SW_INT_ENA 71 72 #define MT_INT_TX_DONE_MCU (MT_INT_TX_DONE_MCU_WM | \ 73 MT_INT_TX_DONE_FWDL) 74 #define MT_INT_TX_DONE_ALL (MT_INT_TX_DONE_MCU_WM | \ 75 MT_INT_TX_DONE_BAND0 | \ 76 GENMASK(18, 4)) 77 78 #define MT_RX_DATA_RING_BASE MT_WFDMA0(0x520) 79 80 #define MT_INFRA_CFG_BASE 0xfe000 81 #define MT_INFRA(ofs) (MT_INFRA_CFG_BASE + (ofs)) 82 83 #define MT_HIF_REMAP_L1 MT_INFRA(0x24c) 84 #define MT_HIF_REMAP_L1_MASK GENMASK(15, 0) 85 #define MT_HIF_REMAP_L1_OFFSET GENMASK(15, 0) 86 #define MT_HIF_REMAP_L1_BASE GENMASK(31, 16) 87 #define MT_HIF_REMAP_BASE_L1 0x40000 88 89 #define MT_WFSYS_SW_RST_B 0x18000140 90 #define WFSYS_SW_RST_B BIT(0) 91 #define WFSYS_SW_INIT_DONE BIT(4) 92 93 #define MT_WTBLON_TOP_WDUCR MT_WTBLON_TOP(0x200) 94 #define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(2, 0) 95 96 #endif 97