1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. 3 * 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/module.h> 8 #include <linux/pci.h> 9 10 #include "mt7921.h" 11 #include "../mt76_connac2_mac.h" 12 #include "mcu.h" 13 14 static const struct pci_device_id mt7921_pci_device_table[] = { 15 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7961), 16 .driver_data = (kernel_ulong_t)MT7921_FIRMWARE_WM }, 17 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7922), 18 .driver_data = (kernel_ulong_t)MT7922_FIRMWARE_WM }, 19 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0608), 20 .driver_data = (kernel_ulong_t)MT7921_FIRMWARE_WM }, 21 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0616), 22 .driver_data = (kernel_ulong_t)MT7922_FIRMWARE_WM }, 23 { }, 24 }; 25 26 static bool mt7921_disable_aspm; 27 module_param_named(disable_aspm, mt7921_disable_aspm, bool, 0644); 28 MODULE_PARM_DESC(disable_aspm, "disable PCI ASPM support"); 29 30 static int mt7921e_init_reset(struct mt792x_dev *dev) 31 { 32 return mt792x_wpdma_reset(dev, true); 33 } 34 35 static void mt7921e_unregister_device(struct mt792x_dev *dev) 36 { 37 int i; 38 struct mt76_connac_pm *pm = &dev->pm; 39 40 cancel_work_sync(&dev->init_work); 41 mt76_unregister_device(&dev->mt76); 42 mt76_for_each_q_rx(&dev->mt76, i) 43 napi_disable(&dev->mt76.napi[i]); 44 cancel_delayed_work_sync(&pm->ps_work); 45 cancel_work_sync(&pm->wake_work); 46 cancel_work_sync(&dev->reset_work); 47 48 mt76_connac2_tx_token_put(&dev->mt76); 49 __mt7921_mcu_drv_pmctrl(dev); 50 mt792x_dma_cleanup(dev); 51 mt792x_wfsys_reset(dev); 52 skb_queue_purge(&dev->mt76.mcu.res_q); 53 54 tasklet_disable(&dev->mt76.irq_tasklet); 55 } 56 57 static u32 __mt7921_reg_addr(struct mt792x_dev *dev, u32 addr) 58 { 59 static const struct mt76_connac_reg_map fixed_map[] = { 60 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ 61 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ 62 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ 63 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ 64 { 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ 65 { 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ 66 { 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */ 67 { 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */ 68 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */ 69 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure register) */ 70 { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */ 71 { 0x54000000, 0x02000, 0x01000 }, /* WFDMA PCIE0 MCU DMA0 */ 72 { 0x55000000, 0x03000, 0x01000 }, /* WFDMA PCIE0 MCU DMA1 */ 73 { 0x58000000, 0x06000, 0x01000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */ 74 { 0x59000000, 0x07000, 0x01000 }, /* WFDMA PCIE1 MCU DMA1 */ 75 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */ 76 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */ 77 { 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */ 78 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */ 79 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */ 80 { 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */ 81 { 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */ 82 { 0x820cc000, 0x0e000, 0x01000 }, /* WF_UMAC_TOP (PP) */ 83 { 0x820cd000, 0x0f000, 0x01000 }, /* WF_MDP_TOP */ 84 { 0x74030000, 0x10000, 0x10000 }, /* PCIE_MAC_IREG */ 85 { 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */ 86 { 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */ 87 { 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */ 88 { 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */ 89 { 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ 90 { 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */ 91 { 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */ 92 { 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */ 93 { 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */ 94 { 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */ 95 { 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */ 96 { 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */ 97 { 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */ 98 { 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */ 99 { 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ 100 { 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */ 101 { 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */ 102 { 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */ 103 { 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */ 104 }; 105 int i; 106 107 if (addr < 0x100000) 108 return addr; 109 110 for (i = 0; i < ARRAY_SIZE(fixed_map); i++) { 111 u32 ofs; 112 113 if (addr < fixed_map[i].phys) 114 continue; 115 116 ofs = addr - fixed_map[i].phys; 117 if (ofs > fixed_map[i].size) 118 continue; 119 120 return fixed_map[i].maps + ofs; 121 } 122 123 if ((addr >= 0x18000000 && addr < 0x18c00000) || 124 (addr >= 0x70000000 && addr < 0x78000000) || 125 (addr >= 0x7c000000 && addr < 0x7c400000)) 126 return mt7921_reg_map_l1(dev, addr); 127 128 dev_err(dev->mt76.dev, "Access currently unsupported address %08x\n", 129 addr); 130 131 return 0; 132 } 133 134 static u32 mt7921_rr(struct mt76_dev *mdev, u32 offset) 135 { 136 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76); 137 u32 addr = __mt7921_reg_addr(dev, offset); 138 139 return dev->bus_ops->rr(mdev, addr); 140 } 141 142 static void mt7921_wr(struct mt76_dev *mdev, u32 offset, u32 val) 143 { 144 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76); 145 u32 addr = __mt7921_reg_addr(dev, offset); 146 147 dev->bus_ops->wr(mdev, addr, val); 148 } 149 150 static u32 mt7921_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val) 151 { 152 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76); 153 u32 addr = __mt7921_reg_addr(dev, offset); 154 155 return dev->bus_ops->rmw(mdev, addr, mask, val); 156 } 157 158 static int mt7921_pci_probe(struct pci_dev *pdev, 159 const struct pci_device_id *id) 160 { 161 static const struct mt76_driver_ops drv_ops = { 162 /* txwi_size = txd size + txp size */ 163 .txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_hw_txp), 164 .drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ | 165 MT_DRV_AMSDU_OFFLOAD, 166 .survey_flags = SURVEY_INFO_TIME_TX | 167 SURVEY_INFO_TIME_RX | 168 SURVEY_INFO_TIME_BSS_RX, 169 .token_size = MT7921_TOKEN_SIZE, 170 .tx_prepare_skb = mt7921e_tx_prepare_skb, 171 .tx_complete_skb = mt76_connac_tx_complete_skb, 172 .rx_check = mt7921_rx_check, 173 .rx_skb = mt7921_queue_rx_skb, 174 .rx_poll_complete = mt792x_rx_poll_complete, 175 .sta_add = mt7921_mac_sta_add, 176 .sta_assoc = mt7921_mac_sta_assoc, 177 .sta_remove = mt7921_mac_sta_remove, 178 .update_survey = mt792x_update_channel, 179 }; 180 static const struct mt792x_hif_ops mt7921_pcie_ops = { 181 .init_reset = mt7921e_init_reset, 182 .reset = mt7921e_mac_reset, 183 .mcu_init = mt7921e_mcu_init, 184 .drv_own = mt7921e_mcu_drv_pmctrl, 185 .fw_own = mt7921e_mcu_fw_pmctrl, 186 }; 187 static const struct mt792x_irq_map irq_map = { 188 .host_irq_enable = MT_WFDMA0_HOST_INT_ENA, 189 .tx = { 190 .all_complete_mask = MT_INT_TX_DONE_ALL, 191 .mcu_complete_mask = MT_INT_TX_DONE_MCU, 192 }, 193 .rx = { 194 .data_complete_mask = MT_INT_RX_DONE_DATA, 195 .wm_complete_mask = MT_INT_RX_DONE_WM, 196 .wm2_complete_mask = MT_INT_RX_DONE_WM2, 197 }, 198 }; 199 struct ieee80211_ops *ops; 200 struct mt76_bus_ops *bus_ops; 201 struct mt792x_dev *dev; 202 struct mt76_dev *mdev; 203 u8 features; 204 int ret; 205 u16 cmd; 206 207 ret = pcim_enable_device(pdev); 208 if (ret) 209 return ret; 210 211 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev)); 212 if (ret) 213 return ret; 214 215 pci_read_config_word(pdev, PCI_COMMAND, &cmd); 216 if (!(cmd & PCI_COMMAND_MEMORY)) { 217 cmd |= PCI_COMMAND_MEMORY; 218 pci_write_config_word(pdev, PCI_COMMAND, cmd); 219 } 220 pci_set_master(pdev); 221 222 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 223 if (ret < 0) 224 return ret; 225 226 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 227 if (ret) 228 goto err_free_pci_vec; 229 230 if (mt7921_disable_aspm) 231 mt76_pci_disable_aspm(pdev); 232 233 ops = mt792x_get_mac80211_ops(&pdev->dev, &mt7921_ops, 234 (void *)id->driver_data, &features); 235 if (!ops) { 236 ret = -ENOMEM; 237 goto err_free_pci_vec; 238 } 239 240 mdev = mt76_alloc_device(&pdev->dev, sizeof(*dev), ops, &drv_ops); 241 if (!mdev) { 242 ret = -ENOMEM; 243 goto err_free_pci_vec; 244 } 245 246 pci_set_drvdata(pdev, mdev); 247 248 dev = container_of(mdev, struct mt792x_dev, mt76); 249 dev->fw_features = features; 250 dev->hif_ops = &mt7921_pcie_ops; 251 dev->irq_map = &irq_map; 252 mt76_mmio_init(&dev->mt76, pcim_iomap_table(pdev)[0]); 253 tasklet_init(&mdev->irq_tasklet, mt792x_irq_tasklet, (unsigned long)dev); 254 255 dev->phy.dev = dev; 256 dev->phy.mt76 = &dev->mt76.phy; 257 dev->mt76.phy.priv = &dev->phy; 258 dev->bus_ops = dev->mt76.bus; 259 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops), 260 GFP_KERNEL); 261 if (!bus_ops) { 262 ret = -ENOMEM; 263 goto err_free_dev; 264 } 265 266 bus_ops->rr = mt7921_rr; 267 bus_ops->wr = mt7921_wr; 268 bus_ops->rmw = mt7921_rmw; 269 dev->mt76.bus = bus_ops; 270 271 ret = mt7921e_mcu_fw_pmctrl(dev); 272 if (ret) 273 goto err_free_dev; 274 275 ret = __mt7921e_mcu_drv_pmctrl(dev); 276 if (ret) 277 goto err_free_dev; 278 279 mdev->rev = (mt7921_l1_rr(dev, MT_HW_CHIPID) << 16) | 280 (mt7921_l1_rr(dev, MT_HW_REV) & 0xff); 281 dev_info(mdev->dev, "ASIC revision: %04x\n", mdev->rev); 282 283 ret = mt792x_wfsys_reset(dev); 284 if (ret) 285 goto err_free_dev; 286 287 mt76_wr(dev, irq_map.host_irq_enable, 0); 288 289 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff); 290 291 ret = devm_request_irq(mdev->dev, pdev->irq, mt792x_irq_handler, 292 IRQF_SHARED, KBUILD_MODNAME, dev); 293 if (ret) 294 goto err_free_dev; 295 296 ret = mt7921_dma_init(dev); 297 if (ret) 298 goto err_free_irq; 299 300 ret = mt7921_register_device(dev); 301 if (ret) 302 goto err_free_irq; 303 304 return 0; 305 306 err_free_irq: 307 devm_free_irq(&pdev->dev, pdev->irq, dev); 308 err_free_dev: 309 mt76_free_device(&dev->mt76); 310 err_free_pci_vec: 311 pci_free_irq_vectors(pdev); 312 313 return ret; 314 } 315 316 static void mt7921_pci_remove(struct pci_dev *pdev) 317 { 318 struct mt76_dev *mdev = pci_get_drvdata(pdev); 319 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76); 320 321 mt7921e_unregister_device(dev); 322 devm_free_irq(&pdev->dev, pdev->irq, dev); 323 mt76_free_device(&dev->mt76); 324 pci_free_irq_vectors(pdev); 325 } 326 327 static int mt7921_pci_suspend(struct device *device) 328 { 329 struct pci_dev *pdev = to_pci_dev(device); 330 struct mt76_dev *mdev = pci_get_drvdata(pdev); 331 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76); 332 struct mt76_connac_pm *pm = &dev->pm; 333 int i, err; 334 335 pm->suspended = true; 336 flush_work(&dev->reset_work); 337 cancel_delayed_work_sync(&pm->ps_work); 338 cancel_work_sync(&pm->wake_work); 339 340 err = mt7921_mcu_drv_pmctrl(dev); 341 if (err < 0) 342 goto restore_suspend; 343 344 err = mt76_connac_mcu_set_hif_suspend(mdev, true); 345 if (err) 346 goto restore_suspend; 347 348 /* always enable deep sleep during suspend to reduce 349 * power consumption 350 */ 351 mt76_connac_mcu_set_deep_sleep(&dev->mt76, true); 352 353 napi_disable(&mdev->tx_napi); 354 mt76_worker_disable(&mdev->tx_worker); 355 356 mt76_for_each_q_rx(mdev, i) { 357 napi_disable(&mdev->napi[i]); 358 } 359 360 /* wait until dma is idle */ 361 mt76_poll(dev, MT_WFDMA0_GLO_CFG, 362 MT_WFDMA0_GLO_CFG_TX_DMA_BUSY | 363 MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 1000); 364 365 /* put dma disabled */ 366 mt76_clear(dev, MT_WFDMA0_GLO_CFG, 367 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN); 368 369 /* disable interrupt */ 370 mt76_wr(dev, dev->irq_map->host_irq_enable, 0); 371 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0); 372 synchronize_irq(pdev->irq); 373 tasklet_kill(&mdev->irq_tasklet); 374 375 err = mt7921_mcu_fw_pmctrl(dev); 376 if (err) 377 goto restore_napi; 378 379 return 0; 380 381 restore_napi: 382 mt76_for_each_q_rx(mdev, i) { 383 napi_enable(&mdev->napi[i]); 384 } 385 napi_enable(&mdev->tx_napi); 386 387 if (!pm->ds_enable) 388 mt76_connac_mcu_set_deep_sleep(&dev->mt76, false); 389 390 mt76_connac_mcu_set_hif_suspend(mdev, false); 391 392 restore_suspend: 393 pm->suspended = false; 394 395 if (err < 0) 396 mt792x_reset(&dev->mt76); 397 398 return err; 399 } 400 401 static int mt7921_pci_resume(struct device *device) 402 { 403 struct pci_dev *pdev = to_pci_dev(device); 404 struct mt76_dev *mdev = pci_get_drvdata(pdev); 405 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76); 406 struct mt76_connac_pm *pm = &dev->pm; 407 int i, err; 408 409 err = mt7921_mcu_drv_pmctrl(dev); 410 if (err < 0) 411 goto failed; 412 413 mt792x_wpdma_reinit_cond(dev); 414 415 /* enable interrupt */ 416 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff); 417 mt76_connac_irq_enable(&dev->mt76, 418 dev->irq_map->tx.all_complete_mask | 419 MT_INT_RX_DONE_ALL | MT_INT_MCU_CMD); 420 mt76_set(dev, MT_MCU2HOST_SW_INT_ENA, MT_MCU_CMD_WAKE_RX_PCIE); 421 422 /* put dma enabled */ 423 mt76_set(dev, MT_WFDMA0_GLO_CFG, 424 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN); 425 426 mt76_worker_enable(&mdev->tx_worker); 427 428 local_bh_disable(); 429 mt76_for_each_q_rx(mdev, i) { 430 napi_enable(&mdev->napi[i]); 431 napi_schedule(&mdev->napi[i]); 432 } 433 napi_enable(&mdev->tx_napi); 434 napi_schedule(&mdev->tx_napi); 435 local_bh_enable(); 436 437 /* restore previous ds setting */ 438 if (!pm->ds_enable) 439 mt76_connac_mcu_set_deep_sleep(&dev->mt76, false); 440 441 err = mt76_connac_mcu_set_hif_suspend(mdev, false); 442 failed: 443 pm->suspended = false; 444 445 if (err < 0) 446 mt792x_reset(&dev->mt76); 447 448 return err; 449 } 450 451 static void mt7921_pci_shutdown(struct pci_dev *pdev) 452 { 453 mt7921_pci_remove(pdev); 454 } 455 456 static DEFINE_SIMPLE_DEV_PM_OPS(mt7921_pm_ops, mt7921_pci_suspend, mt7921_pci_resume); 457 458 static struct pci_driver mt7921_pci_driver = { 459 .name = KBUILD_MODNAME, 460 .id_table = mt7921_pci_device_table, 461 .probe = mt7921_pci_probe, 462 .remove = mt7921_pci_remove, 463 .shutdown = mt7921_pci_shutdown, 464 .driver.pm = pm_sleep_ptr(&mt7921_pm_ops), 465 }; 466 467 module_pci_driver(mt7921_pci_driver); 468 469 MODULE_DEVICE_TABLE(pci, mt7921_pci_device_table); 470 MODULE_FIRMWARE(MT7921_FIRMWARE_WM); 471 MODULE_FIRMWARE(MT7921_ROM_PATCH); 472 MODULE_FIRMWARE(MT7922_FIRMWARE_WM); 473 MODULE_FIRMWARE(MT7922_ROM_PATCH); 474 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 475 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>"); 476 MODULE_LICENSE("Dual BSD/GPL"); 477