1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. 3 * 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/module.h> 8 #include <linux/pci.h> 9 #include <linux/of.h> 10 11 #include "mt7921.h" 12 #include "../mt76_connac2_mac.h" 13 #include "../dma.h" 14 #include "mcu.h" 15 16 static const struct pci_device_id mt7921_pci_device_table[] = { 17 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7961), 18 .driver_data = (kernel_ulong_t)MT7921_FIRMWARE_WM }, 19 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7922), 20 .driver_data = (kernel_ulong_t)MT7922_FIRMWARE_WM }, 21 { PCI_DEVICE(PCI_VENDOR_ID_ITTIM, 0x7922), 22 .driver_data = (kernel_ulong_t)MT7922_FIRMWARE_WM }, 23 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0608), 24 .driver_data = (kernel_ulong_t)MT7921_FIRMWARE_WM }, 25 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0616), 26 .driver_data = (kernel_ulong_t)MT7922_FIRMWARE_WM }, 27 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7920), 28 .driver_data = (kernel_ulong_t)MT7920_FIRMWARE_WM }, 29 { }, 30 }; 31 32 static bool mt7921_disable_aspm; 33 module_param_named(disable_aspm, mt7921_disable_aspm, bool, 0644); 34 MODULE_PARM_DESC(disable_aspm, "disable PCI ASPM support"); 35 36 static int mt7921e_init_reset(struct mt792x_dev *dev) 37 { 38 return mt792x_wpdma_reset(dev, true); 39 } 40 41 static void mt7921e_unregister_device(struct mt792x_dev *dev) 42 { 43 int i; 44 struct mt76_connac_pm *pm = &dev->pm; 45 46 cancel_work_sync(&dev->init_work); 47 mt76_unregister_device(&dev->mt76); 48 mt76_for_each_q_rx(&dev->mt76, i) 49 napi_disable(&dev->mt76.napi[i]); 50 cancel_delayed_work_sync(&pm->ps_work); 51 cancel_work_sync(&pm->wake_work); 52 cancel_work_sync(&dev->reset_work); 53 54 mt76_connac2_tx_token_put(&dev->mt76); 55 __mt792x_mcu_drv_pmctrl(dev); 56 mt792x_dma_cleanup(dev); 57 mt792x_wfsys_reset(dev); 58 skb_queue_purge(&dev->mt76.mcu.res_q); 59 60 tasklet_disable(&dev->mt76.irq_tasklet); 61 } 62 63 static u32 __mt7921_reg_addr(struct mt792x_dev *dev, u32 addr) 64 { 65 static const struct mt76_connac_reg_map fixed_map[] = { 66 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ 67 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ 68 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ 69 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ 70 { 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ 71 { 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ 72 { 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */ 73 { 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */ 74 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */ 75 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure register) */ 76 { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */ 77 { 0x54000000, 0x02000, 0x01000 }, /* WFDMA PCIE0 MCU DMA0 */ 78 { 0x55000000, 0x03000, 0x01000 }, /* WFDMA PCIE0 MCU DMA1 */ 79 { 0x58000000, 0x06000, 0x01000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */ 80 { 0x59000000, 0x07000, 0x01000 }, /* WFDMA PCIE1 MCU DMA1 */ 81 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */ 82 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */ 83 { 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */ 84 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */ 85 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */ 86 { 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */ 87 { 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */ 88 { 0x820cc000, 0x0e000, 0x01000 }, /* WF_UMAC_TOP (PP) */ 89 { 0x820cd000, 0x0f000, 0x01000 }, /* WF_MDP_TOP */ 90 { 0x74030000, 0x10000, 0x10000 }, /* PCIE_MAC_IREG */ 91 { 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */ 92 { 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */ 93 { 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */ 94 { 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */ 95 { 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ 96 { 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */ 97 { 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */ 98 { 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */ 99 { 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */ 100 { 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */ 101 { 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */ 102 { 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */ 103 { 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */ 104 { 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */ 105 { 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ 106 { 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */ 107 { 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */ 108 { 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */ 109 { 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */ 110 }; 111 int i; 112 113 if (addr < 0x100000) 114 return addr; 115 116 for (i = 0; i < ARRAY_SIZE(fixed_map); i++) { 117 u32 ofs; 118 119 if (addr < fixed_map[i].phys) 120 continue; 121 122 ofs = addr - fixed_map[i].phys; 123 if (ofs > fixed_map[i].size) 124 continue; 125 126 return fixed_map[i].maps + ofs; 127 } 128 129 if ((addr >= 0x18000000 && addr < 0x18c00000) || 130 (addr >= 0x70000000 && addr < 0x78000000) || 131 (addr >= 0x7c000000 && addr < 0x7c400000)) 132 return mt7921_reg_map_l1(dev, addr); 133 134 dev_err(dev->mt76.dev, "Access currently unsupported address %08x\n", 135 addr); 136 137 return 0; 138 } 139 140 static u32 mt7921_rr(struct mt76_dev *mdev, u32 offset) 141 { 142 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76); 143 u32 addr = __mt7921_reg_addr(dev, offset); 144 145 return dev->bus_ops->rr(mdev, addr); 146 } 147 148 static void mt7921_wr(struct mt76_dev *mdev, u32 offset, u32 val) 149 { 150 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76); 151 u32 addr = __mt7921_reg_addr(dev, offset); 152 153 dev->bus_ops->wr(mdev, addr, val); 154 } 155 156 static u32 mt7921_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val) 157 { 158 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76); 159 u32 addr = __mt7921_reg_addr(dev, offset); 160 161 return dev->bus_ops->rmw(mdev, addr, mask, val); 162 } 163 164 static int mt7921_dma_init(struct mt792x_dev *dev) 165 { 166 int ret; 167 168 mt76_dma_attach(&dev->mt76); 169 170 ret = mt792x_dma_disable(dev, true); 171 if (ret) 172 return ret; 173 174 /* init tx queue */ 175 ret = mt76_connac_init_tx_queues(dev->phy.mt76, MT7921_TXQ_BAND0, 176 MT7921_TX_RING_SIZE, 177 MT_TX_RING_BASE, NULL, 0); 178 if (ret) 179 return ret; 180 181 mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, 0x4); 182 183 /* command to WM */ 184 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7921_TXQ_MCU_WM, 185 MT7921_TX_MCU_RING_SIZE, MT_TX_RING_BASE); 186 if (ret) 187 return ret; 188 189 /* firmware download */ 190 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL, MT7921_TXQ_FWDL, 191 MT7921_TX_FWDL_RING_SIZE, MT_TX_RING_BASE); 192 if (ret) 193 return ret; 194 195 /* event from WM before firmware download */ 196 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 197 MT7921_RXQ_MCU_WM, 198 MT7921_RX_MCU_RING_SIZE, 199 MT_RX_BUF_SIZE, MT_RX_EVENT_RING_BASE); 200 if (ret) 201 return ret; 202 203 /* Change mcu queue after firmware download */ 204 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA], 205 MT7921_RXQ_MCU_WM, 206 MT7921_RX_MCU_WA_RING_SIZE, 207 MT_RX_BUF_SIZE, MT_WFDMA0(0x540)); 208 if (ret) 209 return ret; 210 211 /* rx data */ 212 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN], 213 MT7921_RXQ_BAND0, MT7921_RX_RING_SIZE, 214 MT_RX_BUF_SIZE, MT_RX_DATA_RING_BASE); 215 if (ret) 216 return ret; 217 218 ret = mt76_init_queues(dev, mt792x_poll_rx); 219 if (ret < 0) 220 return ret; 221 222 netif_napi_add_tx(&dev->mt76.tx_napi_dev, &dev->mt76.tx_napi, 223 mt792x_poll_tx); 224 napi_enable(&dev->mt76.tx_napi); 225 226 return mt792x_dma_enable(dev); 227 } 228 229 static int mt7921_pci_probe(struct pci_dev *pdev, 230 const struct pci_device_id *id) 231 { 232 static const struct mt76_driver_ops drv_ops = { 233 /* txwi_size = txd size + txp size */ 234 .txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_hw_txp), 235 .drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ | 236 MT_DRV_AMSDU_OFFLOAD, 237 .survey_flags = SURVEY_INFO_TIME_TX | 238 SURVEY_INFO_TIME_RX | 239 SURVEY_INFO_TIME_BSS_RX, 240 .token_size = MT7921_TOKEN_SIZE, 241 .tx_prepare_skb = mt7921e_tx_prepare_skb, 242 .tx_complete_skb = mt76_connac_tx_complete_skb, 243 .rx_check = mt7921_rx_check, 244 .rx_skb = mt7921_queue_rx_skb, 245 .rx_poll_complete = mt792x_rx_poll_complete, 246 .sta_add = mt7921_mac_sta_add, 247 .sta_assoc = mt7921_mac_sta_assoc, 248 .sta_remove = mt7921_mac_sta_remove, 249 .update_survey = mt792x_update_channel, 250 }; 251 static const struct mt792x_hif_ops mt7921_pcie_ops = { 252 .init_reset = mt7921e_init_reset, 253 .reset = mt7921e_mac_reset, 254 .mcu_init = mt7921e_mcu_init, 255 .drv_own = mt792xe_mcu_drv_pmctrl, 256 .fw_own = mt792xe_mcu_fw_pmctrl, 257 }; 258 static const struct mt792x_irq_map irq_map = { 259 .host_irq_enable = MT_WFDMA0_HOST_INT_ENA, 260 .tx = { 261 .all_complete_mask = MT_INT_TX_DONE_ALL, 262 .mcu_complete_mask = MT_INT_TX_DONE_MCU, 263 }, 264 .rx = { 265 .data_complete_mask = MT_INT_RX_DONE_DATA, 266 .wm_complete_mask = MT_INT_RX_DONE_WM, 267 .wm2_complete_mask = MT_INT_RX_DONE_WM2, 268 }, 269 }; 270 struct ieee80211_ops *ops; 271 struct mt76_bus_ops *bus_ops; 272 struct mt792x_dev *dev; 273 struct mt76_dev *mdev; 274 u16 cmd, chipid; 275 u8 features; 276 int ret; 277 278 ret = pcim_enable_device(pdev); 279 if (ret) 280 return ret; 281 282 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev)); 283 if (ret) 284 return ret; 285 286 pci_read_config_word(pdev, PCI_COMMAND, &cmd); 287 if (!(cmd & PCI_COMMAND_MEMORY)) { 288 cmd |= PCI_COMMAND_MEMORY; 289 pci_write_config_word(pdev, PCI_COMMAND, cmd); 290 } 291 pci_set_master(pdev); 292 293 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 294 if (ret < 0) 295 return ret; 296 297 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 298 if (ret) 299 goto err_free_pci_vec; 300 301 if (mt7921_disable_aspm) 302 mt76_pci_disable_aspm(pdev); 303 304 ops = mt792x_get_mac80211_ops(&pdev->dev, &mt7921_ops, 305 (void *)id->driver_data, &features); 306 if (!ops) { 307 ret = -ENOMEM; 308 goto err_free_pci_vec; 309 } 310 311 mdev = mt76_alloc_device(&pdev->dev, sizeof(*dev), ops, &drv_ops); 312 if (!mdev) { 313 ret = -ENOMEM; 314 goto err_free_pci_vec; 315 } 316 317 pci_set_drvdata(pdev, mdev); 318 319 dev = container_of(mdev, struct mt792x_dev, mt76); 320 dev->fw_features = features; 321 dev->hif_ops = &mt7921_pcie_ops; 322 dev->irq_map = &irq_map; 323 mt76_mmio_init(&dev->mt76, pcim_iomap_table(pdev)[0]); 324 tasklet_init(&mdev->irq_tasklet, mt792x_irq_tasklet, (unsigned long)dev); 325 326 dev->phy.dev = dev; 327 dev->phy.mt76 = &dev->mt76.phy; 328 dev->mt76.phy.priv = &dev->phy; 329 dev->bus_ops = dev->mt76.bus; 330 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops), 331 GFP_KERNEL); 332 if (!bus_ops) { 333 ret = -ENOMEM; 334 goto err_free_dev; 335 } 336 337 bus_ops->rr = mt7921_rr; 338 bus_ops->wr = mt7921_wr; 339 bus_ops->rmw = mt7921_rmw; 340 dev->mt76.bus = bus_ops; 341 342 ret = mt792xe_mcu_fw_pmctrl(dev); 343 if (ret) 344 goto err_free_dev; 345 346 ret = __mt792xe_mcu_drv_pmctrl(dev); 347 if (ret) 348 goto err_free_dev; 349 350 chipid = mt7921_l1_rr(dev, MT_HW_CHIPID); 351 if (chipid == 0x7961 && (mt7921_l1_rr(dev, MT_HW_BOUND) & BIT(7))) 352 chipid = 0x7920; 353 mdev->rev = (chipid << 16) | 354 (mt7921_l1_rr(dev, MT_HW_REV) & 0xff); 355 dev_info(mdev->dev, "ASIC revision: %04x\n", mdev->rev); 356 357 ret = mt792x_wfsys_reset(dev); 358 if (ret) 359 goto err_free_dev; 360 361 mt76_wr(dev, irq_map.host_irq_enable, 0); 362 363 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff); 364 365 ret = devm_request_irq(mdev->dev, pdev->irq, mt792x_irq_handler, 366 IRQF_SHARED, KBUILD_MODNAME, dev); 367 if (ret) 368 goto err_free_dev; 369 370 ret = mt7921_dma_init(dev); 371 if (ret) 372 goto err_free_irq; 373 374 ret = mt7921_register_device(dev); 375 if (ret) 376 goto err_free_irq; 377 378 if (of_property_read_bool(dev->mt76.dev->of_node, "wakeup-source")) 379 device_init_wakeup(dev->mt76.dev, true); 380 381 return 0; 382 383 err_free_irq: 384 devm_free_irq(&pdev->dev, pdev->irq, dev); 385 err_free_dev: 386 mt76_free_device(&dev->mt76); 387 err_free_pci_vec: 388 pci_free_irq_vectors(pdev); 389 390 return ret; 391 } 392 393 static void mt7921_pci_remove(struct pci_dev *pdev) 394 { 395 struct mt76_dev *mdev = pci_get_drvdata(pdev); 396 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76); 397 398 if (of_property_read_bool(dev->mt76.dev->of_node, "wakeup-source")) 399 device_init_wakeup(dev->mt76.dev, false); 400 401 mt7921e_unregister_device(dev); 402 set_bit(MT76_REMOVED, &mdev->phy.state); 403 devm_free_irq(&pdev->dev, pdev->irq, dev); 404 mt76_free_device(&dev->mt76); 405 pci_free_irq_vectors(pdev); 406 } 407 408 static int mt7921_pci_suspend(struct device *device) 409 { 410 struct pci_dev *pdev = to_pci_dev(device); 411 struct mt76_dev *mdev = pci_get_drvdata(pdev); 412 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76); 413 struct mt76_connac_pm *pm = &dev->pm; 414 int i, err; 415 416 pm->suspended = true; 417 flush_work(&dev->reset_work); 418 cancel_delayed_work_sync(&pm->ps_work); 419 cancel_work_sync(&pm->wake_work); 420 421 mt7921_roc_abort_sync(dev); 422 423 err = mt792x_mcu_drv_pmctrl(dev); 424 if (err < 0) 425 goto restore_suspend; 426 427 wait_event_timeout(dev->wait, 428 !dev->regd_in_progress, 5 * HZ); 429 430 err = mt7921_mcu_radio_led_ctrl(dev, EXT_CMD_RADIO_OFF_LED); 431 if (err < 0) 432 goto restore_suspend; 433 434 err = mt76_connac_mcu_set_hif_suspend(mdev, true); 435 if (err) 436 goto restore_suspend; 437 438 /* always enable deep sleep during suspend to reduce 439 * power consumption 440 */ 441 mt76_connac_mcu_set_deep_sleep(&dev->mt76, true); 442 443 napi_disable(&mdev->tx_napi); 444 mt76_worker_disable(&mdev->tx_worker); 445 446 mt76_for_each_q_rx(mdev, i) { 447 napi_disable(&mdev->napi[i]); 448 } 449 450 /* wait until dma is idle */ 451 mt76_poll(dev, MT_WFDMA0_GLO_CFG, 452 MT_WFDMA0_GLO_CFG_TX_DMA_BUSY | 453 MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 1000); 454 455 /* put dma disabled */ 456 mt76_clear(dev, MT_WFDMA0_GLO_CFG, 457 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN); 458 459 /* disable interrupt */ 460 mt76_wr(dev, dev->irq_map->host_irq_enable, 0); 461 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0); 462 synchronize_irq(pdev->irq); 463 tasklet_kill(&mdev->irq_tasklet); 464 465 err = mt792x_mcu_fw_pmctrl(dev); 466 if (err) 467 goto restore_napi; 468 469 return 0; 470 471 restore_napi: 472 mt76_for_each_q_rx(mdev, i) { 473 napi_enable(&mdev->napi[i]); 474 } 475 napi_enable(&mdev->tx_napi); 476 477 if (!pm->ds_enable) 478 mt76_connac_mcu_set_deep_sleep(&dev->mt76, false); 479 480 mt76_connac_mcu_set_hif_suspend(mdev, false); 481 482 restore_suspend: 483 pm->suspended = false; 484 485 if (err < 0) 486 mt792x_reset(&dev->mt76); 487 488 return err; 489 } 490 491 static int mt7921_pci_resume(struct device *device) 492 { 493 struct pci_dev *pdev = to_pci_dev(device); 494 struct mt76_dev *mdev = pci_get_drvdata(pdev); 495 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76); 496 struct mt76_connac_pm *pm = &dev->pm; 497 int i, err; 498 499 err = mt792x_mcu_drv_pmctrl(dev); 500 if (err < 0) 501 goto failed; 502 503 mt792x_wpdma_reinit_cond(dev); 504 505 /* enable interrupt */ 506 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff); 507 mt76_connac_irq_enable(&dev->mt76, 508 dev->irq_map->tx.all_complete_mask | 509 MT_INT_RX_DONE_ALL | MT_INT_MCU_CMD); 510 mt76_set(dev, MT_MCU2HOST_SW_INT_ENA, MT_MCU_CMD_WAKE_RX_PCIE); 511 512 /* put dma enabled */ 513 mt76_set(dev, MT_WFDMA0_GLO_CFG, 514 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN); 515 516 mt76_worker_enable(&mdev->tx_worker); 517 518 local_bh_disable(); 519 mt76_for_each_q_rx(mdev, i) { 520 napi_enable(&mdev->napi[i]); 521 napi_schedule(&mdev->napi[i]); 522 } 523 napi_enable(&mdev->tx_napi); 524 napi_schedule(&mdev->tx_napi); 525 local_bh_enable(); 526 527 /* restore previous ds setting */ 528 if (!pm->ds_enable) 529 mt76_connac_mcu_set_deep_sleep(&dev->mt76, false); 530 531 err = mt76_connac_mcu_set_hif_suspend(mdev, false); 532 if (err < 0) 533 goto failed; 534 535 mt7921_regd_update(dev); 536 err = mt7921_mcu_radio_led_ctrl(dev, EXT_CMD_RADIO_ON_LED); 537 failed: 538 pm->suspended = false; 539 540 if (err < 0) 541 mt792x_reset(&dev->mt76); 542 543 return err; 544 } 545 546 static void mt7921_pci_shutdown(struct pci_dev *pdev) 547 { 548 mt7921_pci_remove(pdev); 549 } 550 551 static DEFINE_SIMPLE_DEV_PM_OPS(mt7921_pm_ops, mt7921_pci_suspend, mt7921_pci_resume); 552 553 static struct pci_driver mt7921_pci_driver = { 554 .name = KBUILD_MODNAME, 555 .id_table = mt7921_pci_device_table, 556 .probe = mt7921_pci_probe, 557 .remove = mt7921_pci_remove, 558 .shutdown = mt7921_pci_shutdown, 559 .driver.pm = pm_sleep_ptr(&mt7921_pm_ops), 560 }; 561 562 module_pci_driver(mt7921_pci_driver); 563 564 MODULE_DEVICE_TABLE(pci, mt7921_pci_device_table); 565 MODULE_FIRMWARE(MT7920_FIRMWARE_WM); 566 MODULE_FIRMWARE(MT7920_ROM_PATCH); 567 MODULE_FIRMWARE(MT7921_FIRMWARE_WM); 568 MODULE_FIRMWARE(MT7921_ROM_PATCH); 569 MODULE_FIRMWARE(MT7922_FIRMWARE_WM); 570 MODULE_FIRMWARE(MT7922_ROM_PATCH); 571 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 572 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>"); 573 MODULE_DESCRIPTION("MediaTek MT7921E (PCIe) wireless driver"); 574 MODULE_LICENSE("Dual BSD/GPL"); 575