1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include <linux/devcoredump.h> 5 #include <linux/etherdevice.h> 6 #include <linux/timekeeping.h> 7 #include "mt7921.h" 8 #include "../dma.h" 9 #include "mac.h" 10 #include "mcu.h" 11 12 #define HE_BITS(f) cpu_to_le16(IEEE80211_RADIOTAP_HE_##f) 13 #define HE_PREP(f, m, v) le16_encode_bits(le32_get_bits(v, MT_CRXV_HE_##m),\ 14 IEEE80211_RADIOTAP_HE_##f) 15 16 static struct mt76_wcid *mt7921_rx_get_wcid(struct mt7921_dev *dev, 17 u16 idx, bool unicast) 18 { 19 struct mt7921_sta *sta; 20 struct mt76_wcid *wcid; 21 22 if (idx >= ARRAY_SIZE(dev->mt76.wcid)) 23 return NULL; 24 25 wcid = rcu_dereference(dev->mt76.wcid[idx]); 26 if (unicast || !wcid) 27 return wcid; 28 29 if (!wcid->sta) 30 return NULL; 31 32 sta = container_of(wcid, struct mt7921_sta, wcid); 33 if (!sta->vif) 34 return NULL; 35 36 return &sta->vif->sta.wcid; 37 } 38 39 void mt7921_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps) 40 { 41 } 42 EXPORT_SYMBOL_GPL(mt7921_sta_ps); 43 44 bool mt7921_mac_wtbl_update(struct mt7921_dev *dev, int idx, u32 mask) 45 { 46 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX, 47 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask); 48 49 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 50 0, 5000); 51 } 52 53 void mt7921_mac_sta_poll(struct mt7921_dev *dev) 54 { 55 static const u8 ac_to_tid[] = { 56 [IEEE80211_AC_BE] = 0, 57 [IEEE80211_AC_BK] = 1, 58 [IEEE80211_AC_VI] = 4, 59 [IEEE80211_AC_VO] = 6 60 }; 61 struct ieee80211_sta *sta; 62 struct mt7921_sta *msta; 63 u32 tx_time[IEEE80211_NUM_ACS], rx_time[IEEE80211_NUM_ACS]; 64 LIST_HEAD(sta_poll_list); 65 struct rate_info *rate; 66 int i; 67 68 spin_lock_bh(&dev->sta_poll_lock); 69 list_splice_init(&dev->sta_poll_list, &sta_poll_list); 70 spin_unlock_bh(&dev->sta_poll_lock); 71 72 while (true) { 73 bool clear = false; 74 u32 addr, val; 75 u16 idx; 76 u8 bw; 77 78 spin_lock_bh(&dev->sta_poll_lock); 79 if (list_empty(&sta_poll_list)) { 80 spin_unlock_bh(&dev->sta_poll_lock); 81 break; 82 } 83 msta = list_first_entry(&sta_poll_list, 84 struct mt7921_sta, poll_list); 85 list_del_init(&msta->poll_list); 86 spin_unlock_bh(&dev->sta_poll_lock); 87 88 idx = msta->wcid.idx; 89 addr = mt7921_mac_wtbl_lmac_addr(idx, MT_WTBL_AC0_CTT_OFFSET); 90 91 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 92 u32 tx_last = msta->airtime_ac[i]; 93 u32 rx_last = msta->airtime_ac[i + 4]; 94 95 msta->airtime_ac[i] = mt76_rr(dev, addr); 96 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4); 97 98 tx_time[i] = msta->airtime_ac[i] - tx_last; 99 rx_time[i] = msta->airtime_ac[i + 4] - rx_last; 100 101 if ((tx_last | rx_last) & BIT(30)) 102 clear = true; 103 104 addr += 8; 105 } 106 107 if (clear) { 108 mt7921_mac_wtbl_update(dev, idx, 109 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 110 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac)); 111 } 112 113 if (!msta->wcid.sta) 114 continue; 115 116 sta = container_of((void *)msta, struct ieee80211_sta, 117 drv_priv); 118 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 119 u8 q = mt7921_lmac_mapping(dev, i); 120 u32 tx_cur = tx_time[q]; 121 u32 rx_cur = rx_time[q]; 122 u8 tid = ac_to_tid[i]; 123 124 if (!tx_cur && !rx_cur) 125 continue; 126 127 ieee80211_sta_register_airtime(sta, tid, tx_cur, 128 rx_cur); 129 } 130 131 /* We don't support reading GI info from txs packets. 132 * For accurate tx status reporting and AQL improvement, 133 * we need to make sure that flags match so polling GI 134 * from per-sta counters directly. 135 */ 136 rate = &msta->wcid.rate; 137 addr = mt7921_mac_wtbl_lmac_addr(idx, 138 MT_WTBL_TXRX_CAP_RATE_OFFSET); 139 val = mt76_rr(dev, addr); 140 141 switch (rate->bw) { 142 case RATE_INFO_BW_160: 143 bw = IEEE80211_STA_RX_BW_160; 144 break; 145 case RATE_INFO_BW_80: 146 bw = IEEE80211_STA_RX_BW_80; 147 break; 148 case RATE_INFO_BW_40: 149 bw = IEEE80211_STA_RX_BW_40; 150 break; 151 default: 152 bw = IEEE80211_STA_RX_BW_20; 153 break; 154 } 155 156 if (rate->flags & RATE_INFO_FLAGS_HE_MCS) { 157 u8 offs = MT_WTBL_TXRX_RATE_G2_HE + 2 * bw; 158 159 rate->he_gi = (val & (0x3 << offs)) >> offs; 160 } else if (rate->flags & 161 (RATE_INFO_FLAGS_VHT_MCS | RATE_INFO_FLAGS_MCS)) { 162 if (val & BIT(MT_WTBL_TXRX_RATE_G2 + bw)) 163 rate->flags |= RATE_INFO_FLAGS_SHORT_GI; 164 else 165 rate->flags &= ~RATE_INFO_FLAGS_SHORT_GI; 166 } 167 } 168 } 169 EXPORT_SYMBOL_GPL(mt7921_mac_sta_poll); 170 171 static void 172 mt7921_mac_decode_he_radiotap_ru(struct mt76_rx_status *status, 173 struct ieee80211_radiotap_he *he, 174 __le32 *rxv) 175 { 176 u32 ru_h, ru_l; 177 u8 ru, offs = 0; 178 179 ru_l = FIELD_GET(MT_PRXV_HE_RU_ALLOC_L, le32_to_cpu(rxv[0])); 180 ru_h = FIELD_GET(MT_PRXV_HE_RU_ALLOC_H, le32_to_cpu(rxv[1])); 181 ru = (u8)(ru_l | ru_h << 4); 182 183 status->bw = RATE_INFO_BW_HE_RU; 184 185 switch (ru) { 186 case 0 ... 36: 187 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_26; 188 offs = ru; 189 break; 190 case 37 ... 52: 191 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_52; 192 offs = ru - 37; 193 break; 194 case 53 ... 60: 195 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_106; 196 offs = ru - 53; 197 break; 198 case 61 ... 64: 199 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_242; 200 offs = ru - 61; 201 break; 202 case 65 ... 66: 203 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_484; 204 offs = ru - 65; 205 break; 206 case 67: 207 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_996; 208 break; 209 case 68: 210 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 211 break; 212 } 213 214 he->data1 |= HE_BITS(DATA1_BW_RU_ALLOC_KNOWN); 215 he->data2 |= HE_BITS(DATA2_RU_OFFSET_KNOWN) | 216 le16_encode_bits(offs, 217 IEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET); 218 } 219 220 static void 221 mt7921_mac_decode_he_mu_radiotap(struct sk_buff *skb, 222 struct mt76_rx_status *status, 223 __le32 *rxv) 224 { 225 static const struct ieee80211_radiotap_he_mu mu_known = { 226 .flags1 = HE_BITS(MU_FLAGS1_SIG_B_MCS_KNOWN) | 227 HE_BITS(MU_FLAGS1_SIG_B_DCM_KNOWN) | 228 HE_BITS(MU_FLAGS1_CH1_RU_KNOWN) | 229 HE_BITS(MU_FLAGS1_SIG_B_SYMS_USERS_KNOWN) | 230 HE_BITS(MU_FLAGS1_SIG_B_COMP_KNOWN), 231 .flags2 = HE_BITS(MU_FLAGS2_BW_FROM_SIG_A_BW_KNOWN) | 232 HE_BITS(MU_FLAGS2_PUNC_FROM_SIG_A_BW_KNOWN), 233 }; 234 struct ieee80211_radiotap_he_mu *he_mu; 235 236 he_mu = skb_push(skb, sizeof(mu_known)); 237 memcpy(he_mu, &mu_known, sizeof(mu_known)); 238 239 #define MU_PREP(f, v) le16_encode_bits(v, IEEE80211_RADIOTAP_HE_MU_##f) 240 241 he_mu->flags1 |= MU_PREP(FLAGS1_SIG_B_MCS, status->rate_idx); 242 if (status->he_dcm) 243 he_mu->flags1 |= MU_PREP(FLAGS1_SIG_B_DCM, status->he_dcm); 244 245 he_mu->flags2 |= MU_PREP(FLAGS2_BW_FROM_SIG_A_BW, status->bw) | 246 MU_PREP(FLAGS2_SIG_B_SYMS_USERS, 247 le32_get_bits(rxv[2], MT_CRXV_HE_NUM_USER)); 248 249 he_mu->ru_ch1[0] = FIELD_GET(MT_CRXV_HE_RU0, le32_to_cpu(rxv[3])); 250 251 if (status->bw >= RATE_INFO_BW_40) { 252 he_mu->flags1 |= HE_BITS(MU_FLAGS1_CH2_RU_KNOWN); 253 he_mu->ru_ch2[0] = 254 FIELD_GET(MT_CRXV_HE_RU1, le32_to_cpu(rxv[3])); 255 } 256 257 if (status->bw >= RATE_INFO_BW_80) { 258 he_mu->ru_ch1[1] = 259 FIELD_GET(MT_CRXV_HE_RU2, le32_to_cpu(rxv[3])); 260 he_mu->ru_ch2[1] = 261 FIELD_GET(MT_CRXV_HE_RU3, le32_to_cpu(rxv[3])); 262 } 263 } 264 265 static void 266 mt7921_mac_decode_he_radiotap(struct sk_buff *skb, 267 struct mt76_rx_status *status, 268 __le32 *rxv, u32 phy) 269 { 270 static const struct ieee80211_radiotap_he known = { 271 .data1 = HE_BITS(DATA1_DATA_MCS_KNOWN) | 272 HE_BITS(DATA1_DATA_DCM_KNOWN) | 273 HE_BITS(DATA1_STBC_KNOWN) | 274 HE_BITS(DATA1_CODING_KNOWN) | 275 HE_BITS(DATA1_LDPC_XSYMSEG_KNOWN) | 276 HE_BITS(DATA1_DOPPLER_KNOWN) | 277 HE_BITS(DATA1_SPTL_REUSE_KNOWN) | 278 HE_BITS(DATA1_BSS_COLOR_KNOWN), 279 .data2 = HE_BITS(DATA2_GI_KNOWN) | 280 HE_BITS(DATA2_TXBF_KNOWN) | 281 HE_BITS(DATA2_PE_DISAMBIG_KNOWN) | 282 HE_BITS(DATA2_TXOP_KNOWN), 283 }; 284 struct ieee80211_radiotap_he *he = NULL; 285 u32 ltf_size = le32_get_bits(rxv[2], MT_CRXV_HE_LTF_SIZE) + 1; 286 287 he = skb_push(skb, sizeof(known)); 288 memcpy(he, &known, sizeof(known)); 289 290 he->data3 = HE_PREP(DATA3_BSS_COLOR, BSS_COLOR, rxv[14]) | 291 HE_PREP(DATA3_LDPC_XSYMSEG, LDPC_EXT_SYM, rxv[2]); 292 he->data4 = HE_PREP(DATA4_SU_MU_SPTL_REUSE, SR_MASK, rxv[11]); 293 he->data5 = HE_PREP(DATA5_PE_DISAMBIG, PE_DISAMBIG, rxv[2]) | 294 le16_encode_bits(ltf_size, 295 IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE); 296 if (le32_to_cpu(rxv[0]) & MT_PRXV_TXBF) 297 he->data5 |= HE_BITS(DATA5_TXBF); 298 he->data6 = HE_PREP(DATA6_TXOP, TXOP_DUR, rxv[14]) | 299 HE_PREP(DATA6_DOPPLER, DOPPLER, rxv[14]); 300 301 switch (phy) { 302 case MT_PHY_TYPE_HE_SU: 303 he->data1 |= HE_BITS(DATA1_FORMAT_SU) | 304 HE_BITS(DATA1_UL_DL_KNOWN) | 305 HE_BITS(DATA1_BEAM_CHANGE_KNOWN); 306 307 he->data3 |= HE_PREP(DATA3_BEAM_CHANGE, BEAM_CHNG, rxv[14]) | 308 HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]); 309 he->data4 |= HE_PREP(DATA4_SU_MU_SPTL_REUSE, SR_MASK, rxv[11]); 310 break; 311 case MT_PHY_TYPE_HE_EXT_SU: 312 he->data1 |= HE_BITS(DATA1_FORMAT_EXT_SU) | 313 HE_BITS(DATA1_UL_DL_KNOWN); 314 315 he->data3 |= HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]); 316 break; 317 case MT_PHY_TYPE_HE_MU: 318 he->data1 |= HE_BITS(DATA1_FORMAT_MU) | 319 HE_BITS(DATA1_UL_DL_KNOWN); 320 321 he->data3 |= HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]); 322 he->data4 |= HE_PREP(DATA4_MU_STA_ID, MU_AID, rxv[7]); 323 324 mt7921_mac_decode_he_radiotap_ru(status, he, rxv); 325 break; 326 case MT_PHY_TYPE_HE_TB: 327 he->data1 |= HE_BITS(DATA1_FORMAT_TRIG) | 328 HE_BITS(DATA1_SPTL_REUSE2_KNOWN) | 329 HE_BITS(DATA1_SPTL_REUSE3_KNOWN) | 330 HE_BITS(DATA1_SPTL_REUSE4_KNOWN); 331 332 he->data4 |= HE_PREP(DATA4_TB_SPTL_REUSE1, SR_MASK, rxv[11]) | 333 HE_PREP(DATA4_TB_SPTL_REUSE2, SR1_MASK, rxv[11]) | 334 HE_PREP(DATA4_TB_SPTL_REUSE3, SR2_MASK, rxv[11]) | 335 HE_PREP(DATA4_TB_SPTL_REUSE4, SR3_MASK, rxv[11]); 336 337 mt7921_mac_decode_he_radiotap_ru(status, he, rxv); 338 break; 339 default: 340 break; 341 } 342 } 343 344 static void 345 mt7921_get_status_freq_info(struct mt7921_dev *dev, struct mt76_phy *mphy, 346 struct mt76_rx_status *status, u8 chfreq) 347 { 348 if (!test_bit(MT76_HW_SCANNING, &mphy->state) && 349 !test_bit(MT76_HW_SCHED_SCANNING, &mphy->state) && 350 !test_bit(MT76_STATE_ROC, &mphy->state)) { 351 status->freq = mphy->chandef.chan->center_freq; 352 status->band = mphy->chandef.chan->band; 353 return; 354 } 355 356 if (chfreq > 180) { 357 status->band = NL80211_BAND_6GHZ; 358 chfreq = (chfreq - 181) * 4 + 1; 359 } else if (chfreq > 14) { 360 status->band = NL80211_BAND_5GHZ; 361 } else { 362 status->band = NL80211_BAND_2GHZ; 363 } 364 status->freq = ieee80211_channel_to_frequency(chfreq, status->band); 365 } 366 367 static void 368 mt7921_mac_rssi_iter(void *priv, u8 *mac, struct ieee80211_vif *vif) 369 { 370 struct sk_buff *skb = priv; 371 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 372 struct mt7921_vif *mvif = (struct mt7921_vif *)vif->drv_priv; 373 struct ieee80211_hdr *hdr = mt76_skb_get_hdr(skb); 374 375 if (status->signal > 0) 376 return; 377 378 if (!ether_addr_equal(vif->addr, hdr->addr1)) 379 return; 380 381 ewma_rssi_add(&mvif->rssi, -status->signal); 382 } 383 384 static void 385 mt7921_mac_assoc_rssi(struct mt7921_dev *dev, struct sk_buff *skb) 386 { 387 struct ieee80211_hdr *hdr = mt76_skb_get_hdr(skb); 388 389 if (!ieee80211_is_assoc_resp(hdr->frame_control) && 390 !ieee80211_is_auth(hdr->frame_control)) 391 return; 392 393 ieee80211_iterate_active_interfaces_atomic(mt76_hw(dev), 394 IEEE80211_IFACE_ITER_RESUME_ALL, 395 mt7921_mac_rssi_iter, skb); 396 } 397 398 static int 399 mt7921_mac_fill_rx(struct mt7921_dev *dev, struct sk_buff *skb) 400 { 401 u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM; 402 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 403 bool hdr_trans, unicast, insert_ccmp_hdr = false; 404 u8 chfreq, qos_ctl = 0, remove_pad, amsdu_info; 405 __le32 *rxv = NULL, *rxd = (__le32 *)skb->data; 406 struct mt76_phy *mphy = &dev->mt76.phy; 407 struct mt7921_phy *phy = &dev->phy; 408 struct ieee80211_supported_band *sband; 409 struct ieee80211_hdr *hdr; 410 u32 rxd0 = le32_to_cpu(rxd[0]); 411 u32 rxd1 = le32_to_cpu(rxd[1]); 412 u32 rxd2 = le32_to_cpu(rxd[2]); 413 u32 rxd3 = le32_to_cpu(rxd[3]); 414 u32 rxd4 = le32_to_cpu(rxd[4]); 415 u16 seq_ctrl = 0; 416 __le16 fc = 0; 417 u32 mode = 0; 418 int i, idx; 419 420 memset(status, 0, sizeof(*status)); 421 422 if (rxd1 & MT_RXD1_NORMAL_BAND_IDX) 423 return -EINVAL; 424 425 if (!test_bit(MT76_STATE_RUNNING, &mphy->state)) 426 return -EINVAL; 427 428 if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR) 429 return -EINVAL; 430 431 chfreq = FIELD_GET(MT_RXD3_NORMAL_CH_FREQ, rxd3); 432 unicast = FIELD_GET(MT_RXD3_NORMAL_ADDR_TYPE, rxd3) == MT_RXD3_NORMAL_U2M; 433 idx = FIELD_GET(MT_RXD1_NORMAL_WLAN_IDX, rxd1); 434 hdr_trans = rxd2 & MT_RXD2_NORMAL_HDR_TRANS; 435 status->wcid = mt7921_rx_get_wcid(dev, idx, unicast); 436 437 if (status->wcid) { 438 struct mt7921_sta *msta; 439 440 msta = container_of(status->wcid, struct mt7921_sta, wcid); 441 spin_lock_bh(&dev->sta_poll_lock); 442 if (list_empty(&msta->poll_list)) 443 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 444 spin_unlock_bh(&dev->sta_poll_lock); 445 } 446 447 mt7921_get_status_freq_info(dev, mphy, status, chfreq); 448 449 switch (status->band) { 450 case NL80211_BAND_5GHZ: 451 sband = &mphy->sband_5g.sband; 452 break; 453 case NL80211_BAND_6GHZ: 454 sband = &mphy->sband_6g.sband; 455 break; 456 default: 457 sband = &mphy->sband_2g.sband; 458 break; 459 } 460 461 if (!sband->channels) 462 return -EINVAL; 463 464 if ((rxd0 & csum_mask) == csum_mask) 465 skb->ip_summed = CHECKSUM_UNNECESSARY; 466 467 if (rxd1 & MT_RXD1_NORMAL_FCS_ERR) 468 status->flag |= RX_FLAG_FAILED_FCS_CRC; 469 470 if (rxd1 & MT_RXD1_NORMAL_TKIP_MIC_ERR) 471 status->flag |= RX_FLAG_MMIC_ERROR; 472 473 if (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1) != 0 && 474 !(rxd1 & (MT_RXD1_NORMAL_CLM | MT_RXD1_NORMAL_CM))) { 475 status->flag |= RX_FLAG_DECRYPTED; 476 status->flag |= RX_FLAG_IV_STRIPPED; 477 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED; 478 } 479 480 remove_pad = FIELD_GET(MT_RXD2_NORMAL_HDR_OFFSET, rxd2); 481 482 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR) 483 return -EINVAL; 484 485 rxd += 6; 486 if (rxd1 & MT_RXD1_NORMAL_GROUP_4) { 487 u32 v0 = le32_to_cpu(rxd[0]); 488 u32 v2 = le32_to_cpu(rxd[2]); 489 490 fc = cpu_to_le16(FIELD_GET(MT_RXD6_FRAME_CONTROL, v0)); 491 seq_ctrl = FIELD_GET(MT_RXD8_SEQ_CTRL, v2); 492 qos_ctl = FIELD_GET(MT_RXD8_QOS_CTL, v2); 493 494 rxd += 4; 495 if ((u8 *)rxd - skb->data >= skb->len) 496 return -EINVAL; 497 } 498 499 if (rxd1 & MT_RXD1_NORMAL_GROUP_1) { 500 u8 *data = (u8 *)rxd; 501 502 if (status->flag & RX_FLAG_DECRYPTED) { 503 switch (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1)) { 504 case MT_CIPHER_AES_CCMP: 505 case MT_CIPHER_CCMP_CCX: 506 case MT_CIPHER_CCMP_256: 507 insert_ccmp_hdr = 508 FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2); 509 fallthrough; 510 case MT_CIPHER_TKIP: 511 case MT_CIPHER_TKIP_NO_MIC: 512 case MT_CIPHER_GCMP: 513 case MT_CIPHER_GCMP_256: 514 status->iv[0] = data[5]; 515 status->iv[1] = data[4]; 516 status->iv[2] = data[3]; 517 status->iv[3] = data[2]; 518 status->iv[4] = data[1]; 519 status->iv[5] = data[0]; 520 break; 521 default: 522 break; 523 } 524 } 525 rxd += 4; 526 if ((u8 *)rxd - skb->data >= skb->len) 527 return -EINVAL; 528 } 529 530 if (rxd1 & MT_RXD1_NORMAL_GROUP_2) { 531 status->timestamp = le32_to_cpu(rxd[0]); 532 status->flag |= RX_FLAG_MACTIME_START; 533 534 if (!(rxd2 & MT_RXD2_NORMAL_NON_AMPDU)) { 535 status->flag |= RX_FLAG_AMPDU_DETAILS; 536 537 /* all subframes of an A-MPDU have the same timestamp */ 538 if (phy->rx_ampdu_ts != status->timestamp) { 539 if (!++phy->ampdu_ref) 540 phy->ampdu_ref++; 541 } 542 phy->rx_ampdu_ts = status->timestamp; 543 544 status->ampdu_ref = phy->ampdu_ref; 545 } 546 547 rxd += 2; 548 if ((u8 *)rxd - skb->data >= skb->len) 549 return -EINVAL; 550 } 551 552 /* RXD Group 3 - P-RXV */ 553 if (rxd1 & MT_RXD1_NORMAL_GROUP_3) { 554 u8 stbc, gi; 555 u32 v0, v1; 556 bool cck; 557 558 rxv = rxd; 559 rxd += 2; 560 if ((u8 *)rxd - skb->data >= skb->len) 561 return -EINVAL; 562 563 v0 = le32_to_cpu(rxv[0]); 564 v1 = le32_to_cpu(rxv[1]); 565 566 if (v0 & MT_PRXV_HT_AD_CODE) 567 status->enc_flags |= RX_ENC_FLAG_LDPC; 568 569 status->chains = mphy->antenna_mask; 570 status->chain_signal[0] = to_rssi(MT_PRXV_RCPI0, v1); 571 status->chain_signal[1] = to_rssi(MT_PRXV_RCPI1, v1); 572 status->chain_signal[2] = to_rssi(MT_PRXV_RCPI2, v1); 573 status->chain_signal[3] = to_rssi(MT_PRXV_RCPI3, v1); 574 status->signal = -128; 575 for (i = 0; i < hweight8(mphy->antenna_mask); i++) { 576 if (!(status->chains & BIT(i)) || 577 status->chain_signal[i] >= 0) 578 continue; 579 580 status->signal = max(status->signal, 581 status->chain_signal[i]); 582 } 583 584 if (status->signal == -128) 585 status->flag |= RX_FLAG_NO_SIGNAL_VAL; 586 587 stbc = FIELD_GET(MT_PRXV_STBC, v0); 588 gi = FIELD_GET(MT_PRXV_SGI, v0); 589 cck = false; 590 591 idx = i = FIELD_GET(MT_PRXV_TX_RATE, v0); 592 mode = FIELD_GET(MT_PRXV_TX_MODE, v0); 593 594 switch (mode) { 595 case MT_PHY_TYPE_CCK: 596 cck = true; 597 fallthrough; 598 case MT_PHY_TYPE_OFDM: 599 i = mt76_get_rate(&dev->mt76, sband, i, cck); 600 break; 601 case MT_PHY_TYPE_HT_GF: 602 case MT_PHY_TYPE_HT: 603 status->encoding = RX_ENC_HT; 604 if (i > 31) 605 return -EINVAL; 606 break; 607 case MT_PHY_TYPE_VHT: 608 status->nss = 609 FIELD_GET(MT_PRXV_NSTS, v0) + 1; 610 status->encoding = RX_ENC_VHT; 611 if (i > 9) 612 return -EINVAL; 613 break; 614 case MT_PHY_TYPE_HE_MU: 615 status->flag |= RX_FLAG_RADIOTAP_HE_MU; 616 fallthrough; 617 case MT_PHY_TYPE_HE_SU: 618 case MT_PHY_TYPE_HE_EXT_SU: 619 case MT_PHY_TYPE_HE_TB: 620 status->nss = 621 FIELD_GET(MT_PRXV_NSTS, v0) + 1; 622 status->encoding = RX_ENC_HE; 623 status->flag |= RX_FLAG_RADIOTAP_HE; 624 i &= GENMASK(3, 0); 625 626 if (gi <= NL80211_RATE_INFO_HE_GI_3_2) 627 status->he_gi = gi; 628 629 status->he_dcm = !!(idx & MT_PRXV_TX_DCM); 630 break; 631 default: 632 return -EINVAL; 633 } 634 635 status->rate_idx = i; 636 637 switch (FIELD_GET(MT_PRXV_FRAME_MODE, v0)) { 638 case IEEE80211_STA_RX_BW_20: 639 break; 640 case IEEE80211_STA_RX_BW_40: 641 if (mode & MT_PHY_TYPE_HE_EXT_SU && 642 (idx & MT_PRXV_TX_ER_SU_106T)) { 643 status->bw = RATE_INFO_BW_HE_RU; 644 status->he_ru = 645 NL80211_RATE_INFO_HE_RU_ALLOC_106; 646 } else { 647 status->bw = RATE_INFO_BW_40; 648 } 649 break; 650 case IEEE80211_STA_RX_BW_80: 651 status->bw = RATE_INFO_BW_80; 652 break; 653 case IEEE80211_STA_RX_BW_160: 654 status->bw = RATE_INFO_BW_160; 655 break; 656 default: 657 return -EINVAL; 658 } 659 660 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc; 661 if (mode < MT_PHY_TYPE_HE_SU && gi) 662 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 663 664 if (rxd1 & MT_RXD1_NORMAL_GROUP_5) { 665 rxd += 18; 666 if ((u8 *)rxd - skb->data >= skb->len) 667 return -EINVAL; 668 } 669 } 670 671 skb_pull(skb, (u8 *)rxd - skb->data + 2 * remove_pad); 672 673 amsdu_info = FIELD_GET(MT_RXD4_NORMAL_PAYLOAD_FORMAT, rxd4); 674 status->amsdu = !!amsdu_info; 675 if (status->amsdu) { 676 status->first_amsdu = amsdu_info == MT_RXD4_FIRST_AMSDU_FRAME; 677 status->last_amsdu = amsdu_info == MT_RXD4_LAST_AMSDU_FRAME; 678 if (!hdr_trans) { 679 memmove(skb->data + 2, skb->data, 680 ieee80211_get_hdrlen_from_skb(skb)); 681 skb_pull(skb, 2); 682 } 683 } 684 685 if (!hdr_trans) { 686 if (insert_ccmp_hdr) { 687 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1); 688 689 mt76_insert_ccmp_hdr(skb, key_id); 690 } 691 692 hdr = mt76_skb_get_hdr(skb); 693 fc = hdr->frame_control; 694 if (ieee80211_is_data_qos(fc)) { 695 seq_ctrl = le16_to_cpu(hdr->seq_ctrl); 696 qos_ctl = *ieee80211_get_qos_ctl(hdr); 697 } 698 } else { 699 status->flag &= ~(RX_FLAG_RADIOTAP_HE | 700 RX_FLAG_RADIOTAP_HE_MU); 701 status->flag |= RX_FLAG_8023; 702 } 703 704 mt7921_mac_assoc_rssi(dev, skb); 705 706 if (rxv && status->flag & RX_FLAG_RADIOTAP_HE) { 707 mt7921_mac_decode_he_radiotap(skb, status, rxv, mode); 708 709 if (status->flag & RX_FLAG_RADIOTAP_HE_MU) 710 mt7921_mac_decode_he_mu_radiotap(skb, status, rxv); 711 } 712 713 if (!status->wcid || !ieee80211_is_data_qos(fc)) 714 return 0; 715 716 status->aggr = unicast && !ieee80211_is_qos_nullfunc(fc); 717 status->seqno = IEEE80211_SEQ_TO_SN(seq_ctrl); 718 status->qos_ctl = qos_ctl; 719 720 return 0; 721 } 722 723 static void 724 mt7921_mac_write_txwi_8023(struct mt7921_dev *dev, __le32 *txwi, 725 struct sk_buff *skb, struct mt76_wcid *wcid) 726 { 727 u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 728 u8 fc_type, fc_stype; 729 bool wmm = false; 730 u32 val; 731 732 if (wcid->sta) { 733 struct ieee80211_sta *sta; 734 735 sta = container_of((void *)wcid, struct ieee80211_sta, drv_priv); 736 wmm = sta->wme; 737 } 738 739 val = FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_3) | 740 FIELD_PREP(MT_TXD1_TID, tid); 741 742 if (be16_to_cpu(skb->protocol) >= ETH_P_802_3_MIN) 743 val |= MT_TXD1_ETH_802_3; 744 745 txwi[1] |= cpu_to_le32(val); 746 747 fc_type = IEEE80211_FTYPE_DATA >> 2; 748 fc_stype = wmm ? IEEE80211_STYPE_QOS_DATA >> 4 : 0; 749 750 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) | 751 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype); 752 753 txwi[2] |= cpu_to_le32(val); 754 755 val = FIELD_PREP(MT_TXD7_TYPE, fc_type) | 756 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype); 757 txwi[7] |= cpu_to_le32(val); 758 } 759 760 static void 761 mt7921_mac_write_txwi_80211(struct mt7921_dev *dev, __le32 *txwi, 762 struct sk_buff *skb, struct ieee80211_key_conf *key) 763 { 764 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 765 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 766 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 767 bool multicast = is_multicast_ether_addr(hdr->addr1); 768 u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 769 __le16 fc = hdr->frame_control; 770 u8 fc_type, fc_stype; 771 u32 val; 772 773 if (ieee80211_is_action(fc) && 774 mgmt->u.action.category == WLAN_CATEGORY_BACK && 775 mgmt->u.action.u.addba_req.action_code == WLAN_ACTION_ADDBA_REQ) { 776 u16 capab = le16_to_cpu(mgmt->u.action.u.addba_req.capab); 777 778 txwi[5] |= cpu_to_le32(MT_TXD5_ADD_BA); 779 tid = (capab >> 2) & IEEE80211_QOS_CTL_TID_MASK; 780 } else if (ieee80211_is_back_req(hdr->frame_control)) { 781 struct ieee80211_bar *bar = (struct ieee80211_bar *)hdr; 782 u16 control = le16_to_cpu(bar->control); 783 784 tid = FIELD_GET(IEEE80211_BAR_CTRL_TID_INFO_MASK, control); 785 } 786 787 val = FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) | 788 FIELD_PREP(MT_TXD1_HDR_INFO, 789 ieee80211_get_hdrlen_from_skb(skb) / 2) | 790 FIELD_PREP(MT_TXD1_TID, tid); 791 txwi[1] |= cpu_to_le32(val); 792 793 fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2; 794 fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4; 795 796 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) | 797 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype) | 798 FIELD_PREP(MT_TXD2_MULTICAST, multicast); 799 800 if (key && multicast && ieee80211_is_robust_mgmt_frame(skb) && 801 key->cipher == WLAN_CIPHER_SUITE_AES_CMAC) { 802 val |= MT_TXD2_BIP; 803 txwi[3] &= ~cpu_to_le32(MT_TXD3_PROTECT_FRAME); 804 } 805 806 if (!ieee80211_is_data(fc) || multicast || 807 info->flags & IEEE80211_TX_CTL_USE_MINRATE) 808 val |= MT_TXD2_FIX_RATE; 809 810 txwi[2] |= cpu_to_le32(val); 811 812 if (ieee80211_is_beacon(fc)) { 813 txwi[3] &= ~cpu_to_le32(MT_TXD3_SW_POWER_MGMT); 814 txwi[3] |= cpu_to_le32(MT_TXD3_REM_TX_COUNT); 815 } 816 817 if (info->flags & IEEE80211_TX_CTL_INJECTED) { 818 u16 seqno = le16_to_cpu(hdr->seq_ctrl); 819 820 if (ieee80211_is_back_req(hdr->frame_control)) { 821 struct ieee80211_bar *bar; 822 823 bar = (struct ieee80211_bar *)skb->data; 824 seqno = le16_to_cpu(bar->start_seq_num); 825 } 826 827 val = MT_TXD3_SN_VALID | 828 FIELD_PREP(MT_TXD3_SEQ, IEEE80211_SEQ_TO_SN(seqno)); 829 txwi[3] |= cpu_to_le32(val); 830 } 831 832 val = FIELD_PREP(MT_TXD7_TYPE, fc_type) | 833 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype); 834 txwi[7] |= cpu_to_le32(val); 835 } 836 837 void mt7921_mac_write_txwi(struct mt7921_dev *dev, __le32 *txwi, 838 struct sk_buff *skb, struct mt76_wcid *wcid, 839 struct ieee80211_key_conf *key, int pid, 840 bool beacon) 841 { 842 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 843 struct ieee80211_vif *vif = info->control.vif; 844 struct mt76_phy *mphy = &dev->mphy; 845 u8 p_fmt, q_idx, omac_idx = 0, wmm_idx = 0; 846 bool is_8023 = info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP; 847 u16 tx_count = 15; 848 u32 val; 849 850 if (vif) { 851 struct mt76_vif *mvif = (struct mt76_vif *)vif->drv_priv; 852 853 omac_idx = mvif->omac_idx; 854 wmm_idx = mvif->wmm_idx; 855 } 856 857 if (beacon) { 858 p_fmt = MT_TX_TYPE_FW; 859 q_idx = MT_LMAC_BCN0; 860 } else if (skb_get_queue_mapping(skb) >= MT_TXQ_PSD) { 861 p_fmt = MT_TX_TYPE_CT; 862 q_idx = MT_LMAC_ALTX0; 863 } else { 864 p_fmt = MT_TX_TYPE_CT; 865 q_idx = wmm_idx * MT7921_MAX_WMM_SETS + 866 mt7921_lmac_mapping(dev, skb_get_queue_mapping(skb)); 867 } 868 869 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) | 870 FIELD_PREP(MT_TXD0_PKT_FMT, p_fmt) | 871 FIELD_PREP(MT_TXD0_Q_IDX, q_idx); 872 txwi[0] = cpu_to_le32(val); 873 874 val = MT_TXD1_LONG_FORMAT | 875 FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) | 876 FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx); 877 878 txwi[1] = cpu_to_le32(val); 879 txwi[2] = 0; 880 881 val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count); 882 if (key) 883 val |= MT_TXD3_PROTECT_FRAME; 884 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 885 val |= MT_TXD3_NO_ACK; 886 887 txwi[3] = cpu_to_le32(val); 888 txwi[4] = 0; 889 890 val = FIELD_PREP(MT_TXD5_PID, pid); 891 if (pid >= MT_PACKET_ID_FIRST) 892 val |= MT_TXD5_TX_STATUS_HOST; 893 txwi[5] = cpu_to_le32(val); 894 895 txwi[6] = 0; 896 txwi[7] = wcid->amsdu ? cpu_to_le32(MT_TXD7_HW_AMSDU) : 0; 897 898 if (is_8023) 899 mt7921_mac_write_txwi_8023(dev, txwi, skb, wcid); 900 else 901 mt7921_mac_write_txwi_80211(dev, txwi, skb, key); 902 903 if (txwi[2] & cpu_to_le32(MT_TXD2_FIX_RATE)) { 904 int rateidx = ffs(vif->bss_conf.basic_rates) - 1; 905 u16 rate, mode; 906 907 /* hardware won't add HTC for mgmt/ctrl frame */ 908 txwi[2] |= cpu_to_le32(MT_TXD2_HTC_VLD); 909 910 rate = mt76_calculate_default_rate(mphy, rateidx); 911 mode = rate >> 8; 912 rate &= GENMASK(7, 0); 913 rate |= FIELD_PREP(MT_TX_RATE_MODE, mode); 914 915 val = MT_TXD6_FIXED_BW | 916 FIELD_PREP(MT_TXD6_TX_RATE, rate); 917 txwi[6] |= cpu_to_le32(val); 918 txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE); 919 } 920 } 921 EXPORT_SYMBOL_GPL(mt7921_mac_write_txwi); 922 923 void mt7921_tx_check_aggr(struct ieee80211_sta *sta, __le32 *txwi) 924 { 925 struct mt7921_sta *msta; 926 u16 fc, tid; 927 u32 val; 928 929 if (!sta || !(sta->ht_cap.ht_supported || sta->he_cap.has_he)) 930 return; 931 932 tid = FIELD_GET(MT_TXD1_TID, le32_to_cpu(txwi[1])); 933 if (tid >= 6) /* skip VO queue */ 934 return; 935 936 val = le32_to_cpu(txwi[2]); 937 fc = FIELD_GET(MT_TXD2_FRAME_TYPE, val) << 2 | 938 FIELD_GET(MT_TXD2_SUB_TYPE, val) << 4; 939 if (unlikely(fc != (IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_DATA))) 940 return; 941 942 msta = (struct mt7921_sta *)sta->drv_priv; 943 if (!test_and_set_bit(tid, &msta->ampdu_state)) 944 ieee80211_start_tx_ba_session(sta, tid, 0); 945 } 946 EXPORT_SYMBOL_GPL(mt7921_tx_check_aggr); 947 948 static bool 949 mt7921_mac_add_txs_skb(struct mt7921_dev *dev, struct mt76_wcid *wcid, int pid, 950 __le32 *txs_data) 951 { 952 struct ieee80211_supported_band *sband; 953 struct mt76_dev *mdev = &dev->mt76; 954 struct ieee80211_tx_info *info; 955 struct rate_info rate = {}; 956 struct sk_buff_head list; 957 struct sk_buff *skb; 958 bool cck = false; 959 u32 txrate, txs; 960 961 mt76_tx_status_lock(mdev, &list); 962 skb = mt76_tx_status_skb_get(mdev, wcid, pid, &list); 963 if (!skb) 964 goto out; 965 966 info = IEEE80211_SKB_CB(skb); 967 txs = le32_to_cpu(txs_data[0]); 968 if (!(txs & MT_TXS0_ACK_ERROR_MASK)) 969 info->flags |= IEEE80211_TX_STAT_ACK; 970 971 info->status.ampdu_len = 1; 972 info->status.ampdu_ack_len = !!(info->flags & 973 IEEE80211_TX_STAT_ACK); 974 975 info->status.rates[0].idx = -1; 976 977 if (!wcid->sta) 978 goto out; 979 980 txrate = FIELD_GET(MT_TXS0_TX_RATE, txs); 981 982 rate.mcs = FIELD_GET(MT_TX_RATE_IDX, txrate); 983 rate.nss = FIELD_GET(MT_TX_RATE_NSS, txrate) + 1; 984 985 switch (FIELD_GET(MT_TX_RATE_MODE, txrate)) { 986 case MT_PHY_TYPE_CCK: 987 cck = true; 988 fallthrough; 989 case MT_PHY_TYPE_OFDM: 990 if (dev->mphy.chandef.chan->band == NL80211_BAND_5GHZ) 991 sband = &dev->mphy.sband_5g.sband; 992 else 993 sband = &dev->mphy.sband_2g.sband; 994 995 rate.mcs = mt76_get_rate(dev->mphy.dev, sband, rate.mcs, cck); 996 rate.legacy = sband->bitrates[rate.mcs].bitrate; 997 break; 998 case MT_PHY_TYPE_HT: 999 case MT_PHY_TYPE_HT_GF: 1000 rate.mcs += (rate.nss - 1) * 8; 1001 if (rate.mcs > 31) 1002 goto out; 1003 1004 rate.flags = RATE_INFO_FLAGS_MCS; 1005 if (wcid->rate.flags & RATE_INFO_FLAGS_SHORT_GI) 1006 rate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1007 break; 1008 case MT_PHY_TYPE_VHT: 1009 if (rate.mcs > 9) 1010 goto out; 1011 1012 rate.flags = RATE_INFO_FLAGS_VHT_MCS; 1013 break; 1014 case MT_PHY_TYPE_HE_SU: 1015 case MT_PHY_TYPE_HE_EXT_SU: 1016 case MT_PHY_TYPE_HE_TB: 1017 case MT_PHY_TYPE_HE_MU: 1018 if (rate.mcs > 11) 1019 goto out; 1020 1021 rate.he_gi = wcid->rate.he_gi; 1022 rate.he_dcm = FIELD_GET(MT_TX_RATE_DCM, txrate); 1023 rate.flags = RATE_INFO_FLAGS_HE_MCS; 1024 break; 1025 default: 1026 goto out; 1027 } 1028 1029 switch (FIELD_GET(MT_TXS0_BW, txs)) { 1030 case IEEE80211_STA_RX_BW_160: 1031 rate.bw = RATE_INFO_BW_160; 1032 break; 1033 case IEEE80211_STA_RX_BW_80: 1034 rate.bw = RATE_INFO_BW_80; 1035 break; 1036 case IEEE80211_STA_RX_BW_40: 1037 rate.bw = RATE_INFO_BW_40; 1038 break; 1039 default: 1040 rate.bw = RATE_INFO_BW_20; 1041 break; 1042 } 1043 wcid->rate = rate; 1044 1045 out: 1046 if (skb) 1047 mt76_tx_status_skb_done(mdev, skb, &list); 1048 mt76_tx_status_unlock(mdev, &list); 1049 1050 return !!skb; 1051 } 1052 1053 static void mt7921_mac_add_txs(struct mt7921_dev *dev, void *data) 1054 { 1055 struct mt7921_sta *msta = NULL; 1056 struct mt76_wcid *wcid; 1057 __le32 *txs_data = data; 1058 u16 wcidx; 1059 u32 txs; 1060 u8 pid; 1061 1062 txs = le32_to_cpu(txs_data[0]); 1063 if (FIELD_GET(MT_TXS0_TXS_FORMAT, txs) > 1) 1064 return; 1065 1066 txs = le32_to_cpu(txs_data[2]); 1067 wcidx = FIELD_GET(MT_TXS2_WCID, txs); 1068 1069 txs = le32_to_cpu(txs_data[3]); 1070 pid = FIELD_GET(MT_TXS3_PID, txs); 1071 1072 if (pid < MT_PACKET_ID_FIRST) 1073 return; 1074 1075 if (wcidx >= MT7921_WTBL_SIZE) 1076 return; 1077 1078 rcu_read_lock(); 1079 1080 wcid = rcu_dereference(dev->mt76.wcid[wcidx]); 1081 if (!wcid) 1082 goto out; 1083 1084 mt7921_mac_add_txs_skb(dev, wcid, pid, txs_data); 1085 1086 if (!wcid->sta) 1087 goto out; 1088 1089 msta = container_of(wcid, struct mt7921_sta, wcid); 1090 spin_lock_bh(&dev->sta_poll_lock); 1091 if (list_empty(&msta->poll_list)) 1092 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 1093 spin_unlock_bh(&dev->sta_poll_lock); 1094 1095 out: 1096 rcu_read_unlock(); 1097 } 1098 1099 void mt7921_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 1100 struct sk_buff *skb) 1101 { 1102 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 1103 __le32 *rxd = (__le32 *)skb->data; 1104 __le32 *end = (__le32 *)&skb->data[skb->len]; 1105 enum rx_pkt_type type; 1106 u16 flag; 1107 1108 type = FIELD_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0])); 1109 flag = FIELD_GET(MT_RXD0_PKT_FLAG, le32_to_cpu(rxd[0])); 1110 1111 if (type == PKT_TYPE_RX_EVENT && flag == 0x1) 1112 type = PKT_TYPE_NORMAL_MCU; 1113 1114 switch (type) { 1115 case PKT_TYPE_RX_EVENT: 1116 mt7921_mcu_rx_event(dev, skb); 1117 break; 1118 case PKT_TYPE_TXS: 1119 for (rxd += 2; rxd + 8 <= end; rxd += 8) 1120 mt7921_mac_add_txs(dev, rxd); 1121 dev_kfree_skb(skb); 1122 break; 1123 case PKT_TYPE_NORMAL_MCU: 1124 case PKT_TYPE_NORMAL: 1125 if (!mt7921_mac_fill_rx(dev, skb)) { 1126 mt76_rx(&dev->mt76, q, skb); 1127 return; 1128 } 1129 fallthrough; 1130 default: 1131 dev_kfree_skb(skb); 1132 break; 1133 } 1134 } 1135 EXPORT_SYMBOL_GPL(mt7921_queue_rx_skb); 1136 1137 void mt7921_mac_reset_counters(struct mt7921_phy *phy) 1138 { 1139 struct mt7921_dev *dev = phy->dev; 1140 int i; 1141 1142 for (i = 0; i < 4; i++) { 1143 mt76_rr(dev, MT_TX_AGG_CNT(0, i)); 1144 mt76_rr(dev, MT_TX_AGG_CNT2(0, i)); 1145 } 1146 1147 dev->mt76.phy.survey_time = ktime_get_boottime(); 1148 memset(&dev->mt76.aggr_stats[0], 0, sizeof(dev->mt76.aggr_stats) / 2); 1149 1150 /* reset airtime counters */ 1151 mt76_rr(dev, MT_MIB_SDR9(0)); 1152 mt76_rr(dev, MT_MIB_SDR36(0)); 1153 mt76_rr(dev, MT_MIB_SDR37(0)); 1154 1155 mt76_set(dev, MT_WF_RMAC_MIB_TIME0(0), MT_WF_RMAC_MIB_RXTIME_CLR); 1156 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(0), MT_WF_RMAC_MIB_RXTIME_CLR); 1157 } 1158 1159 void mt7921_mac_set_timing(struct mt7921_phy *phy) 1160 { 1161 s16 coverage_class = phy->coverage_class; 1162 struct mt7921_dev *dev = phy->dev; 1163 u32 val, reg_offset; 1164 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | 1165 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); 1166 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | 1167 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28); 1168 bool is_2ghz = phy->mt76->chandef.chan->band == NL80211_BAND_2GHZ; 1169 int sifs = is_2ghz ? 10 : 16, offset; 1170 1171 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state)) 1172 return; 1173 1174 mt76_set(dev, MT_ARB_SCR(0), 1175 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1176 udelay(1); 1177 1178 offset = 3 * coverage_class; 1179 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | 1180 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); 1181 1182 mt76_wr(dev, MT_TMAC_CDTR(0), cck + reg_offset); 1183 mt76_wr(dev, MT_TMAC_ODTR(0), ofdm + reg_offset); 1184 mt76_wr(dev, MT_TMAC_ICR0(0), 1185 FIELD_PREP(MT_IFS_EIFS, 360) | 1186 FIELD_PREP(MT_IFS_RIFS, 2) | 1187 FIELD_PREP(MT_IFS_SIFS, sifs) | 1188 FIELD_PREP(MT_IFS_SLOT, phy->slottime)); 1189 1190 if (phy->slottime < 20 || !is_2ghz) 1191 val = MT7921_CFEND_RATE_DEFAULT; 1192 else 1193 val = MT7921_CFEND_RATE_11B; 1194 1195 mt76_rmw_field(dev, MT_AGG_ACR0(0), MT_AGG_ACR_CFEND_RATE, val); 1196 mt76_clear(dev, MT_ARB_SCR(0), 1197 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1198 } 1199 1200 static u8 1201 mt7921_phy_get_nf(struct mt7921_phy *phy, int idx) 1202 { 1203 return 0; 1204 } 1205 1206 static void 1207 mt7921_phy_update_channel(struct mt76_phy *mphy, int idx) 1208 { 1209 struct mt7921_dev *dev = container_of(mphy->dev, struct mt7921_dev, mt76); 1210 struct mt7921_phy *phy = (struct mt7921_phy *)mphy->priv; 1211 struct mt76_channel_state *state; 1212 u64 busy_time, tx_time, rx_time, obss_time; 1213 int nf; 1214 1215 busy_time = mt76_get_field(dev, MT_MIB_SDR9(idx), 1216 MT_MIB_SDR9_BUSY_MASK); 1217 tx_time = mt76_get_field(dev, MT_MIB_SDR36(idx), 1218 MT_MIB_SDR36_TXTIME_MASK); 1219 rx_time = mt76_get_field(dev, MT_MIB_SDR37(idx), 1220 MT_MIB_SDR37_RXTIME_MASK); 1221 obss_time = mt76_get_field(dev, MT_WF_RMAC_MIB_AIRTIME14(idx), 1222 MT_MIB_OBSSTIME_MASK); 1223 1224 nf = mt7921_phy_get_nf(phy, idx); 1225 if (!phy->noise) 1226 phy->noise = nf << 4; 1227 else if (nf) 1228 phy->noise += nf - (phy->noise >> 4); 1229 1230 state = mphy->chan_state; 1231 state->cc_busy += busy_time; 1232 state->cc_tx += tx_time; 1233 state->cc_rx += rx_time + obss_time; 1234 state->cc_bss_rx += rx_time; 1235 state->noise = -(phy->noise >> 4); 1236 } 1237 1238 void mt7921_update_channel(struct mt76_phy *mphy) 1239 { 1240 struct mt7921_dev *dev = container_of(mphy->dev, struct mt7921_dev, mt76); 1241 1242 if (mt76_connac_pm_wake(mphy, &dev->pm)) 1243 return; 1244 1245 mt7921_phy_update_channel(mphy, 0); 1246 /* reset obss airtime */ 1247 mt76_set(dev, MT_WF_RMAC_MIB_TIME0(0), MT_WF_RMAC_MIB_RXTIME_CLR); 1248 1249 mt76_connac_power_save_sched(mphy, &dev->pm); 1250 } 1251 EXPORT_SYMBOL_GPL(mt7921_update_channel); 1252 1253 static void 1254 mt7921_vif_connect_iter(void *priv, u8 *mac, 1255 struct ieee80211_vif *vif) 1256 { 1257 struct mt7921_vif *mvif = (struct mt7921_vif *)vif->drv_priv; 1258 struct mt7921_dev *dev = mvif->phy->dev; 1259 1260 if (vif->type == NL80211_IFTYPE_STATION) 1261 ieee80211_disconnect(vif, true); 1262 1263 mt76_connac_mcu_uni_add_dev(&dev->mphy, vif, &mvif->sta.wcid, true); 1264 mt7921_mcu_set_tx(dev, vif); 1265 } 1266 1267 /* system error recovery */ 1268 void mt7921_mac_reset_work(struct work_struct *work) 1269 { 1270 struct mt7921_dev *dev = container_of(work, struct mt7921_dev, 1271 reset_work); 1272 struct ieee80211_hw *hw = mt76_hw(dev); 1273 struct mt76_connac_pm *pm = &dev->pm; 1274 int i; 1275 1276 dev_err(dev->mt76.dev, "chip reset\n"); 1277 dev->hw_full_reset = true; 1278 ieee80211_stop_queues(hw); 1279 1280 cancel_delayed_work_sync(&dev->mphy.mac_work); 1281 cancel_delayed_work_sync(&pm->ps_work); 1282 cancel_work_sync(&pm->wake_work); 1283 1284 mutex_lock(&dev->mt76.mutex); 1285 for (i = 0; i < 10; i++) 1286 if (!mt7921_dev_reset(dev)) 1287 break; 1288 mutex_unlock(&dev->mt76.mutex); 1289 1290 if (i == 10) 1291 dev_err(dev->mt76.dev, "chip reset failed\n"); 1292 1293 if (test_and_clear_bit(MT76_HW_SCANNING, &dev->mphy.state)) { 1294 struct cfg80211_scan_info info = { 1295 .aborted = true, 1296 }; 1297 1298 ieee80211_scan_completed(dev->mphy.hw, &info); 1299 } 1300 1301 dev->hw_full_reset = false; 1302 ieee80211_wake_queues(hw); 1303 ieee80211_iterate_active_interfaces(hw, 1304 IEEE80211_IFACE_ITER_RESUME_ALL, 1305 mt7921_vif_connect_iter, NULL); 1306 mt76_connac_power_save_sched(&dev->mt76.phy, pm); 1307 } 1308 1309 void mt7921_reset(struct mt76_dev *mdev) 1310 { 1311 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 1312 1313 if (!dev->hw_init_done) 1314 return; 1315 1316 if (dev->hw_full_reset) 1317 return; 1318 1319 queue_work(dev->mt76.wq, &dev->reset_work); 1320 } 1321 1322 void mt7921_mac_update_mib_stats(struct mt7921_phy *phy) 1323 { 1324 struct mt7921_dev *dev = phy->dev; 1325 struct mib_stats *mib = &phy->mib; 1326 int i, aggr0 = 0, aggr1; 1327 1328 mib->fcs_err_cnt += mt76_get_field(dev, MT_MIB_SDR3(0), 1329 MT_MIB_SDR3_FCS_ERR_MASK); 1330 mib->ack_fail_cnt += mt76_get_field(dev, MT_MIB_MB_BSDR3(0), 1331 MT_MIB_ACK_FAIL_COUNT_MASK); 1332 mib->ba_miss_cnt += mt76_get_field(dev, MT_MIB_MB_BSDR2(0), 1333 MT_MIB_BA_FAIL_COUNT_MASK); 1334 mib->rts_cnt += mt76_get_field(dev, MT_MIB_MB_BSDR0(0), 1335 MT_MIB_RTS_COUNT_MASK); 1336 mib->rts_retries_cnt += mt76_get_field(dev, MT_MIB_MB_BSDR1(0), 1337 MT_MIB_RTS_FAIL_COUNT_MASK); 1338 1339 for (i = 0, aggr1 = aggr0 + 4; i < 4; i++) { 1340 u32 val, val2; 1341 1342 val = mt76_rr(dev, MT_TX_AGG_CNT(0, i)); 1343 val2 = mt76_rr(dev, MT_TX_AGG_CNT2(0, i)); 1344 1345 dev->mt76.aggr_stats[aggr0++] += val & 0xffff; 1346 dev->mt76.aggr_stats[aggr0++] += val >> 16; 1347 dev->mt76.aggr_stats[aggr1++] += val2 & 0xffff; 1348 dev->mt76.aggr_stats[aggr1++] += val2 >> 16; 1349 } 1350 } 1351 1352 void mt7921_mac_work(struct work_struct *work) 1353 { 1354 struct mt7921_phy *phy; 1355 struct mt76_phy *mphy; 1356 1357 mphy = (struct mt76_phy *)container_of(work, struct mt76_phy, 1358 mac_work.work); 1359 phy = mphy->priv; 1360 1361 mt7921_mutex_acquire(phy->dev); 1362 1363 mt76_update_survey(mphy); 1364 if (++mphy->mac_work_count == 2) { 1365 mphy->mac_work_count = 0; 1366 1367 mt7921_mac_update_mib_stats(phy); 1368 } 1369 1370 mt7921_mutex_release(phy->dev); 1371 1372 mt76_tx_status_check(mphy->dev, false); 1373 ieee80211_queue_delayed_work(phy->mt76->hw, &mphy->mac_work, 1374 MT7921_WATCHDOG_TIME); 1375 } 1376 1377 void mt7921_pm_wake_work(struct work_struct *work) 1378 { 1379 struct mt7921_dev *dev; 1380 struct mt76_phy *mphy; 1381 1382 dev = (struct mt7921_dev *)container_of(work, struct mt7921_dev, 1383 pm.wake_work); 1384 mphy = dev->phy.mt76; 1385 1386 if (!mt7921_mcu_drv_pmctrl(dev)) { 1387 int i; 1388 1389 mt76_for_each_q_rx(&dev->mt76, i) 1390 napi_schedule(&dev->mt76.napi[i]); 1391 mt76_connac_pm_dequeue_skbs(mphy, &dev->pm); 1392 mt7921_mcu_tx_cleanup(dev); 1393 if (test_bit(MT76_STATE_RUNNING, &mphy->state)) 1394 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, 1395 MT7921_WATCHDOG_TIME); 1396 } 1397 1398 ieee80211_wake_queues(mphy->hw); 1399 wake_up(&dev->pm.wait); 1400 } 1401 1402 void mt7921_pm_power_save_work(struct work_struct *work) 1403 { 1404 struct mt7921_dev *dev; 1405 unsigned long delta; 1406 struct mt76_phy *mphy; 1407 1408 dev = (struct mt7921_dev *)container_of(work, struct mt7921_dev, 1409 pm.ps_work.work); 1410 mphy = dev->phy.mt76; 1411 1412 delta = dev->pm.idle_timeout; 1413 if (test_bit(MT76_HW_SCANNING, &mphy->state) || 1414 test_bit(MT76_HW_SCHED_SCANNING, &mphy->state)) 1415 goto out; 1416 1417 if (time_is_after_jiffies(dev->pm.last_activity + delta)) { 1418 delta = dev->pm.last_activity + delta - jiffies; 1419 goto out; 1420 } 1421 1422 if (!mt7921_mcu_fw_pmctrl(dev)) { 1423 cancel_delayed_work_sync(&mphy->mac_work); 1424 return; 1425 } 1426 out: 1427 queue_delayed_work(dev->mt76.wq, &dev->pm.ps_work, delta); 1428 } 1429 1430 void mt7921_coredump_work(struct work_struct *work) 1431 { 1432 struct mt7921_dev *dev; 1433 char *dump, *data; 1434 1435 dev = (struct mt7921_dev *)container_of(work, struct mt7921_dev, 1436 coredump.work.work); 1437 1438 if (time_is_after_jiffies(dev->coredump.last_activity + 1439 4 * MT76_CONNAC_COREDUMP_TIMEOUT)) { 1440 queue_delayed_work(dev->mt76.wq, &dev->coredump.work, 1441 MT76_CONNAC_COREDUMP_TIMEOUT); 1442 return; 1443 } 1444 1445 dump = vzalloc(MT76_CONNAC_COREDUMP_SZ); 1446 data = dump; 1447 1448 while (true) { 1449 struct sk_buff *skb; 1450 1451 spin_lock_bh(&dev->mt76.lock); 1452 skb = __skb_dequeue(&dev->coredump.msg_list); 1453 spin_unlock_bh(&dev->mt76.lock); 1454 1455 if (!skb) 1456 break; 1457 1458 skb_pull(skb, sizeof(struct mt7921_mcu_rxd)); 1459 if (!dump || data + skb->len - dump > MT76_CONNAC_COREDUMP_SZ) { 1460 dev_kfree_skb(skb); 1461 continue; 1462 } 1463 1464 memcpy(data, skb->data, skb->len); 1465 data += skb->len; 1466 1467 dev_kfree_skb(skb); 1468 } 1469 1470 if (dump) 1471 dev_coredumpv(dev->mt76.dev, dump, MT76_CONNAC_COREDUMP_SZ, 1472 GFP_KERNEL); 1473 1474 mt7921_reset(&dev->mt76); 1475 } 1476