1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include <linux/devcoredump.h> 5 #include <linux/etherdevice.h> 6 #include <linux/timekeeping.h> 7 #include "mt7921.h" 8 #include "../dma.h" 9 #include "../mt76_connac2_mac.h" 10 #include "mcu.h" 11 12 #define MT_WTBL_TXRX_CAP_RATE_OFFSET 7 13 #define MT_WTBL_TXRX_RATE_G2_HE 24 14 #define MT_WTBL_TXRX_RATE_G2 12 15 16 #define MT_WTBL_AC0_CTT_OFFSET 20 17 18 static u32 mt7921_mac_wtbl_lmac_addr(int idx, u8 offset) 19 { 20 return MT_WTBL_LMAC_OFFS(idx, 0) + offset * 4; 21 } 22 23 static struct mt76_wcid *mt7921_rx_get_wcid(struct mt7921_dev *dev, 24 u16 idx, bool unicast) 25 { 26 struct mt7921_sta *sta; 27 struct mt76_wcid *wcid; 28 29 if (idx >= ARRAY_SIZE(dev->mt76.wcid)) 30 return NULL; 31 32 wcid = rcu_dereference(dev->mt76.wcid[idx]); 33 if (unicast || !wcid) 34 return wcid; 35 36 if (!wcid->sta) 37 return NULL; 38 39 sta = container_of(wcid, struct mt7921_sta, wcid); 40 if (!sta->vif) 41 return NULL; 42 43 return &sta->vif->sta.wcid; 44 } 45 46 bool mt7921_mac_wtbl_update(struct mt7921_dev *dev, int idx, u32 mask) 47 { 48 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX, 49 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask); 50 51 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 52 0, 5000); 53 } 54 55 void mt7921_mac_sta_poll(struct mt7921_dev *dev) 56 { 57 static const u8 ac_to_tid[] = { 58 [IEEE80211_AC_BE] = 0, 59 [IEEE80211_AC_BK] = 1, 60 [IEEE80211_AC_VI] = 4, 61 [IEEE80211_AC_VO] = 6 62 }; 63 struct ieee80211_sta *sta; 64 struct mt7921_sta *msta; 65 u32 tx_time[IEEE80211_NUM_ACS], rx_time[IEEE80211_NUM_ACS]; 66 LIST_HEAD(sta_poll_list); 67 struct rate_info *rate; 68 s8 rssi[4]; 69 int i; 70 71 spin_lock_bh(&dev->sta_poll_lock); 72 list_splice_init(&dev->sta_poll_list, &sta_poll_list); 73 spin_unlock_bh(&dev->sta_poll_lock); 74 75 while (true) { 76 bool clear = false; 77 u32 addr, val; 78 u16 idx; 79 u8 bw; 80 81 spin_lock_bh(&dev->sta_poll_lock); 82 if (list_empty(&sta_poll_list)) { 83 spin_unlock_bh(&dev->sta_poll_lock); 84 break; 85 } 86 msta = list_first_entry(&sta_poll_list, 87 struct mt7921_sta, poll_list); 88 list_del_init(&msta->poll_list); 89 spin_unlock_bh(&dev->sta_poll_lock); 90 91 idx = msta->wcid.idx; 92 addr = mt7921_mac_wtbl_lmac_addr(idx, MT_WTBL_AC0_CTT_OFFSET); 93 94 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 95 u32 tx_last = msta->airtime_ac[i]; 96 u32 rx_last = msta->airtime_ac[i + 4]; 97 98 msta->airtime_ac[i] = mt76_rr(dev, addr); 99 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4); 100 101 tx_time[i] = msta->airtime_ac[i] - tx_last; 102 rx_time[i] = msta->airtime_ac[i + 4] - rx_last; 103 104 if ((tx_last | rx_last) & BIT(30)) 105 clear = true; 106 107 addr += 8; 108 } 109 110 if (clear) { 111 mt7921_mac_wtbl_update(dev, idx, 112 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 113 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac)); 114 } 115 116 if (!msta->wcid.sta) 117 continue; 118 119 sta = container_of((void *)msta, struct ieee80211_sta, 120 drv_priv); 121 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 122 u8 q = mt76_connac_lmac_mapping(i); 123 u32 tx_cur = tx_time[q]; 124 u32 rx_cur = rx_time[q]; 125 u8 tid = ac_to_tid[i]; 126 127 if (!tx_cur && !rx_cur) 128 continue; 129 130 ieee80211_sta_register_airtime(sta, tid, tx_cur, 131 rx_cur); 132 } 133 134 /* We don't support reading GI info from txs packets. 135 * For accurate tx status reporting and AQL improvement, 136 * we need to make sure that flags match so polling GI 137 * from per-sta counters directly. 138 */ 139 rate = &msta->wcid.rate; 140 addr = mt7921_mac_wtbl_lmac_addr(idx, 141 MT_WTBL_TXRX_CAP_RATE_OFFSET); 142 val = mt76_rr(dev, addr); 143 144 switch (rate->bw) { 145 case RATE_INFO_BW_160: 146 bw = IEEE80211_STA_RX_BW_160; 147 break; 148 case RATE_INFO_BW_80: 149 bw = IEEE80211_STA_RX_BW_80; 150 break; 151 case RATE_INFO_BW_40: 152 bw = IEEE80211_STA_RX_BW_40; 153 break; 154 default: 155 bw = IEEE80211_STA_RX_BW_20; 156 break; 157 } 158 159 if (rate->flags & RATE_INFO_FLAGS_HE_MCS) { 160 u8 offs = MT_WTBL_TXRX_RATE_G2_HE + 2 * bw; 161 162 rate->he_gi = (val & (0x3 << offs)) >> offs; 163 } else if (rate->flags & 164 (RATE_INFO_FLAGS_VHT_MCS | RATE_INFO_FLAGS_MCS)) { 165 if (val & BIT(MT_WTBL_TXRX_RATE_G2 + bw)) 166 rate->flags |= RATE_INFO_FLAGS_SHORT_GI; 167 else 168 rate->flags &= ~RATE_INFO_FLAGS_SHORT_GI; 169 } 170 171 /* get signal strength of resp frames (CTS/BA/ACK) */ 172 addr = mt7921_mac_wtbl_lmac_addr(idx, 30); 173 val = mt76_rr(dev, addr); 174 175 rssi[0] = to_rssi(GENMASK(7, 0), val); 176 rssi[1] = to_rssi(GENMASK(15, 8), val); 177 rssi[2] = to_rssi(GENMASK(23, 16), val); 178 rssi[3] = to_rssi(GENMASK(31, 14), val); 179 180 msta->ack_signal = 181 mt76_rx_signal(msta->vif->phy->mt76->antenna_mask, rssi); 182 183 ewma_avg_signal_add(&msta->avg_ack_signal, -msta->ack_signal); 184 } 185 } 186 EXPORT_SYMBOL_GPL(mt7921_mac_sta_poll); 187 188 static void 189 mt7921_get_status_freq_info(struct mt7921_dev *dev, struct mt76_phy *mphy, 190 struct mt76_rx_status *status, u8 chfreq) 191 { 192 if (chfreq > 180) { 193 status->band = NL80211_BAND_6GHZ; 194 chfreq = (chfreq - 181) * 4 + 1; 195 } else if (chfreq > 14) { 196 status->band = NL80211_BAND_5GHZ; 197 } else { 198 status->band = NL80211_BAND_2GHZ; 199 } 200 status->freq = ieee80211_channel_to_frequency(chfreq, status->band); 201 } 202 203 static void 204 mt7921_mac_rssi_iter(void *priv, u8 *mac, struct ieee80211_vif *vif) 205 { 206 struct sk_buff *skb = priv; 207 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 208 struct mt7921_vif *mvif = (struct mt7921_vif *)vif->drv_priv; 209 struct ieee80211_hdr *hdr = mt76_skb_get_hdr(skb); 210 211 if (status->signal > 0) 212 return; 213 214 if (!ether_addr_equal(vif->addr, hdr->addr1)) 215 return; 216 217 ewma_rssi_add(&mvif->rssi, -status->signal); 218 } 219 220 static void 221 mt7921_mac_assoc_rssi(struct mt7921_dev *dev, struct sk_buff *skb) 222 { 223 struct ieee80211_hdr *hdr = mt76_skb_get_hdr(skb); 224 225 if (!ieee80211_is_assoc_resp(hdr->frame_control) && 226 !ieee80211_is_auth(hdr->frame_control)) 227 return; 228 229 ieee80211_iterate_active_interfaces_atomic(mt76_hw(dev), 230 IEEE80211_IFACE_ITER_RESUME_ALL, 231 mt7921_mac_rssi_iter, skb); 232 } 233 234 static int 235 mt7921_mac_fill_rx(struct mt7921_dev *dev, struct sk_buff *skb) 236 { 237 u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM; 238 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 239 bool hdr_trans, unicast, insert_ccmp_hdr = false; 240 u8 chfreq, qos_ctl = 0, remove_pad, amsdu_info; 241 u16 hdr_gap; 242 __le32 *rxv = NULL, *rxd = (__le32 *)skb->data; 243 struct mt76_phy *mphy = &dev->mt76.phy; 244 struct mt7921_phy *phy = &dev->phy; 245 struct ieee80211_supported_band *sband; 246 u32 csum_status = *(u32 *)skb->cb; 247 u32 rxd0 = le32_to_cpu(rxd[0]); 248 u32 rxd1 = le32_to_cpu(rxd[1]); 249 u32 rxd2 = le32_to_cpu(rxd[2]); 250 u32 rxd3 = le32_to_cpu(rxd[3]); 251 u32 rxd4 = le32_to_cpu(rxd[4]); 252 struct mt7921_sta *msta = NULL; 253 u16 seq_ctrl = 0; 254 __le16 fc = 0; 255 u8 mode = 0; 256 int i, idx; 257 258 memset(status, 0, sizeof(*status)); 259 260 if (rxd1 & MT_RXD1_NORMAL_BAND_IDX) 261 return -EINVAL; 262 263 if (!test_bit(MT76_STATE_RUNNING, &mphy->state)) 264 return -EINVAL; 265 266 if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR) 267 return -EINVAL; 268 269 hdr_trans = rxd2 & MT_RXD2_NORMAL_HDR_TRANS; 270 if (hdr_trans && (rxd1 & MT_RXD1_NORMAL_CM)) 271 return -EINVAL; 272 273 /* ICV error or CCMP/BIP/WPI MIC error */ 274 if (rxd1 & MT_RXD1_NORMAL_ICV_ERR) 275 status->flag |= RX_FLAG_ONLY_MONITOR; 276 277 chfreq = FIELD_GET(MT_RXD3_NORMAL_CH_FREQ, rxd3); 278 unicast = FIELD_GET(MT_RXD3_NORMAL_ADDR_TYPE, rxd3) == MT_RXD3_NORMAL_U2M; 279 idx = FIELD_GET(MT_RXD1_NORMAL_WLAN_IDX, rxd1); 280 status->wcid = mt7921_rx_get_wcid(dev, idx, unicast); 281 282 if (status->wcid) { 283 msta = container_of(status->wcid, struct mt7921_sta, wcid); 284 spin_lock_bh(&dev->sta_poll_lock); 285 if (list_empty(&msta->poll_list)) 286 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 287 spin_unlock_bh(&dev->sta_poll_lock); 288 } 289 290 mt7921_get_status_freq_info(dev, mphy, status, chfreq); 291 292 switch (status->band) { 293 case NL80211_BAND_5GHZ: 294 sband = &mphy->sband_5g.sband; 295 break; 296 case NL80211_BAND_6GHZ: 297 sband = &mphy->sband_6g.sband; 298 break; 299 default: 300 sband = &mphy->sband_2g.sband; 301 break; 302 } 303 304 if (!sband->channels) 305 return -EINVAL; 306 307 if (mt76_is_mmio(&dev->mt76) && (rxd0 & csum_mask) == csum_mask && 308 !(csum_status & (BIT(0) | BIT(2) | BIT(3)))) 309 skb->ip_summed = CHECKSUM_UNNECESSARY; 310 311 if (rxd1 & MT_RXD1_NORMAL_FCS_ERR) 312 status->flag |= RX_FLAG_FAILED_FCS_CRC; 313 314 if (rxd1 & MT_RXD1_NORMAL_TKIP_MIC_ERR) 315 status->flag |= RX_FLAG_MMIC_ERROR; 316 317 if (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1) != 0 && 318 !(rxd1 & (MT_RXD1_NORMAL_CLM | MT_RXD1_NORMAL_CM))) { 319 status->flag |= RX_FLAG_DECRYPTED; 320 status->flag |= RX_FLAG_IV_STRIPPED; 321 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED; 322 } 323 324 remove_pad = FIELD_GET(MT_RXD2_NORMAL_HDR_OFFSET, rxd2); 325 326 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR) 327 return -EINVAL; 328 329 rxd += 6; 330 if (rxd1 & MT_RXD1_NORMAL_GROUP_4) { 331 u32 v0 = le32_to_cpu(rxd[0]); 332 u32 v2 = le32_to_cpu(rxd[2]); 333 334 fc = cpu_to_le16(FIELD_GET(MT_RXD6_FRAME_CONTROL, v0)); 335 seq_ctrl = FIELD_GET(MT_RXD8_SEQ_CTRL, v2); 336 qos_ctl = FIELD_GET(MT_RXD8_QOS_CTL, v2); 337 338 rxd += 4; 339 if ((u8 *)rxd - skb->data >= skb->len) 340 return -EINVAL; 341 } 342 343 if (rxd1 & MT_RXD1_NORMAL_GROUP_1) { 344 u8 *data = (u8 *)rxd; 345 346 if (status->flag & RX_FLAG_DECRYPTED) { 347 switch (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1)) { 348 case MT_CIPHER_AES_CCMP: 349 case MT_CIPHER_CCMP_CCX: 350 case MT_CIPHER_CCMP_256: 351 insert_ccmp_hdr = 352 FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2); 353 fallthrough; 354 case MT_CIPHER_TKIP: 355 case MT_CIPHER_TKIP_NO_MIC: 356 case MT_CIPHER_GCMP: 357 case MT_CIPHER_GCMP_256: 358 status->iv[0] = data[5]; 359 status->iv[1] = data[4]; 360 status->iv[2] = data[3]; 361 status->iv[3] = data[2]; 362 status->iv[4] = data[1]; 363 status->iv[5] = data[0]; 364 break; 365 default: 366 break; 367 } 368 } 369 rxd += 4; 370 if ((u8 *)rxd - skb->data >= skb->len) 371 return -EINVAL; 372 } 373 374 if (rxd1 & MT_RXD1_NORMAL_GROUP_2) { 375 status->timestamp = le32_to_cpu(rxd[0]); 376 status->flag |= RX_FLAG_MACTIME_START; 377 378 if (!(rxd2 & MT_RXD2_NORMAL_NON_AMPDU)) { 379 status->flag |= RX_FLAG_AMPDU_DETAILS; 380 381 /* all subframes of an A-MPDU have the same timestamp */ 382 if (phy->rx_ampdu_ts != status->timestamp) { 383 if (!++phy->ampdu_ref) 384 phy->ampdu_ref++; 385 } 386 phy->rx_ampdu_ts = status->timestamp; 387 388 status->ampdu_ref = phy->ampdu_ref; 389 } 390 391 rxd += 2; 392 if ((u8 *)rxd - skb->data >= skb->len) 393 return -EINVAL; 394 } 395 396 /* RXD Group 3 - P-RXV */ 397 if (rxd1 & MT_RXD1_NORMAL_GROUP_3) { 398 u32 v0, v1; 399 int ret; 400 401 rxv = rxd; 402 rxd += 2; 403 if ((u8 *)rxd - skb->data >= skb->len) 404 return -EINVAL; 405 406 v0 = le32_to_cpu(rxv[0]); 407 v1 = le32_to_cpu(rxv[1]); 408 409 if (v0 & MT_PRXV_HT_AD_CODE) 410 status->enc_flags |= RX_ENC_FLAG_LDPC; 411 412 ret = mt76_connac2_mac_fill_rx_rate(&dev->mt76, status, sband, 413 rxv, &mode); 414 if (ret < 0) 415 return ret; 416 417 if (rxd1 & MT_RXD1_NORMAL_GROUP_5) { 418 rxd += 6; 419 if ((u8 *)rxd - skb->data >= skb->len) 420 return -EINVAL; 421 422 rxv = rxd; 423 /* Monitor mode would use RCPI described in GROUP 5 424 * instead. 425 */ 426 v1 = le32_to_cpu(rxv[0]); 427 428 rxd += 12; 429 if ((u8 *)rxd - skb->data >= skb->len) 430 return -EINVAL; 431 } 432 433 status->chains = mphy->antenna_mask; 434 status->chain_signal[0] = to_rssi(MT_PRXV_RCPI0, v1); 435 status->chain_signal[1] = to_rssi(MT_PRXV_RCPI1, v1); 436 status->chain_signal[2] = to_rssi(MT_PRXV_RCPI2, v1); 437 status->chain_signal[3] = to_rssi(MT_PRXV_RCPI3, v1); 438 status->signal = -128; 439 for (i = 0; i < hweight8(mphy->antenna_mask); i++) { 440 if (!(status->chains & BIT(i)) || 441 status->chain_signal[i] >= 0) 442 continue; 443 444 status->signal = max(status->signal, 445 status->chain_signal[i]); 446 } 447 } 448 449 amsdu_info = FIELD_GET(MT_RXD4_NORMAL_PAYLOAD_FORMAT, rxd4); 450 status->amsdu = !!amsdu_info; 451 if (status->amsdu) { 452 status->first_amsdu = amsdu_info == MT_RXD4_FIRST_AMSDU_FRAME; 453 status->last_amsdu = amsdu_info == MT_RXD4_LAST_AMSDU_FRAME; 454 } 455 456 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad; 457 if (hdr_trans && ieee80211_has_morefrags(fc)) { 458 struct ieee80211_vif *vif; 459 int err; 460 461 if (!msta || !msta->vif) 462 return -EINVAL; 463 464 vif = container_of((void *)msta->vif, struct ieee80211_vif, 465 drv_priv); 466 err = mt76_connac2_reverse_frag0_hdr_trans(vif, skb, hdr_gap); 467 if (err) 468 return err; 469 470 hdr_trans = false; 471 } else { 472 skb_pull(skb, hdr_gap); 473 if (!hdr_trans && status->amsdu) { 474 memmove(skb->data + 2, skb->data, 475 ieee80211_get_hdrlen_from_skb(skb)); 476 skb_pull(skb, 2); 477 } 478 } 479 480 if (!hdr_trans) { 481 struct ieee80211_hdr *hdr; 482 483 if (insert_ccmp_hdr) { 484 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1); 485 486 mt76_insert_ccmp_hdr(skb, key_id); 487 } 488 489 hdr = mt76_skb_get_hdr(skb); 490 fc = hdr->frame_control; 491 if (ieee80211_is_data_qos(fc)) { 492 seq_ctrl = le16_to_cpu(hdr->seq_ctrl); 493 qos_ctl = *ieee80211_get_qos_ctl(hdr); 494 } 495 } else { 496 status->flag |= RX_FLAG_8023; 497 } 498 499 mt7921_mac_assoc_rssi(dev, skb); 500 501 if (rxv && mode >= MT_PHY_TYPE_HE_SU && !(status->flag & RX_FLAG_8023)) 502 mt76_connac2_mac_decode_he_radiotap(&dev->mt76, skb, rxv, mode); 503 504 if (!status->wcid || !ieee80211_is_data_qos(fc)) 505 return 0; 506 507 status->aggr = unicast && !ieee80211_is_qos_nullfunc(fc); 508 status->seqno = IEEE80211_SEQ_TO_SN(seq_ctrl); 509 status->qos_ctl = qos_ctl; 510 511 return 0; 512 } 513 514 static void mt7921_tx_check_aggr(struct ieee80211_sta *sta, __le32 *txwi) 515 { 516 struct mt7921_sta *msta; 517 u16 fc, tid; 518 u32 val; 519 520 if (!sta || !(sta->deflink.ht_cap.ht_supported || sta->deflink.he_cap.has_he)) 521 return; 522 523 tid = le32_get_bits(txwi[1], MT_TXD1_TID); 524 if (tid >= 6) /* skip VO queue */ 525 return; 526 527 val = le32_to_cpu(txwi[2]); 528 fc = FIELD_GET(MT_TXD2_FRAME_TYPE, val) << 2 | 529 FIELD_GET(MT_TXD2_SUB_TYPE, val) << 4; 530 if (unlikely(fc != (IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_DATA))) 531 return; 532 533 msta = (struct mt7921_sta *)sta->drv_priv; 534 if (!test_and_set_bit(tid, &msta->ampdu_state)) 535 ieee80211_start_tx_ba_session(sta, tid, 0); 536 } 537 538 void mt7921_mac_add_txs(struct mt7921_dev *dev, void *data) 539 { 540 struct mt7921_sta *msta = NULL; 541 struct mt76_wcid *wcid; 542 __le32 *txs_data = data; 543 u16 wcidx; 544 u8 pid; 545 546 if (le32_get_bits(txs_data[0], MT_TXS0_TXS_FORMAT) > 1) 547 return; 548 549 wcidx = le32_get_bits(txs_data[2], MT_TXS2_WCID); 550 pid = le32_get_bits(txs_data[3], MT_TXS3_PID); 551 552 if (pid < MT_PACKET_ID_FIRST) 553 return; 554 555 if (wcidx >= MT7921_WTBL_SIZE) 556 return; 557 558 rcu_read_lock(); 559 560 wcid = rcu_dereference(dev->mt76.wcid[wcidx]); 561 if (!wcid) 562 goto out; 563 564 msta = container_of(wcid, struct mt7921_sta, wcid); 565 566 mt76_connac2_mac_add_txs_skb(&dev->mt76, wcid, pid, txs_data); 567 if (!wcid->sta) 568 goto out; 569 570 spin_lock_bh(&dev->sta_poll_lock); 571 if (list_empty(&msta->poll_list)) 572 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 573 spin_unlock_bh(&dev->sta_poll_lock); 574 575 out: 576 rcu_read_unlock(); 577 } 578 579 void mt7921_txwi_free(struct mt7921_dev *dev, struct mt76_txwi_cache *t, 580 struct ieee80211_sta *sta, bool clear_status, 581 struct list_head *free_list) 582 { 583 struct mt76_dev *mdev = &dev->mt76; 584 __le32 *txwi; 585 u16 wcid_idx; 586 587 mt76_connac_txp_skb_unmap(mdev, t); 588 if (!t->skb) 589 goto out; 590 591 txwi = (__le32 *)mt76_get_txwi_ptr(mdev, t); 592 if (sta) { 593 struct mt76_wcid *wcid = (struct mt76_wcid *)sta->drv_priv; 594 595 if (likely(t->skb->protocol != cpu_to_be16(ETH_P_PAE))) 596 mt7921_tx_check_aggr(sta, txwi); 597 598 wcid_idx = wcid->idx; 599 } else { 600 wcid_idx = le32_get_bits(txwi[1], MT_TXD1_WLAN_IDX); 601 } 602 603 __mt76_tx_complete_skb(mdev, wcid_idx, t->skb, free_list); 604 out: 605 t->skb = NULL; 606 mt76_put_txwi(mdev, t); 607 } 608 EXPORT_SYMBOL_GPL(mt7921_txwi_free); 609 610 static void mt7921_mac_tx_free(struct mt7921_dev *dev, void *data, int len) 611 { 612 struct mt76_connac_tx_free *free = data; 613 __le32 *tx_info = (__le32 *)(data + sizeof(*free)); 614 struct mt76_dev *mdev = &dev->mt76; 615 struct mt76_txwi_cache *txwi; 616 struct ieee80211_sta *sta = NULL; 617 struct sk_buff *skb, *tmp; 618 void *end = data + len; 619 LIST_HEAD(free_list); 620 bool wake = false; 621 u8 i, count; 622 623 /* clean DMA queues and unmap buffers first */ 624 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false); 625 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false); 626 627 count = le16_get_bits(free->ctrl, MT_TX_FREE_MSDU_CNT); 628 if (WARN_ON_ONCE((void *)&tx_info[count] > end)) 629 return; 630 631 for (i = 0; i < count; i++) { 632 u32 msdu, info = le32_to_cpu(tx_info[i]); 633 u8 stat; 634 635 /* 1'b1: new wcid pair. 636 * 1'b0: msdu_id with the same 'wcid pair' as above. 637 */ 638 if (info & MT_TX_FREE_PAIR) { 639 struct mt7921_sta *msta; 640 struct mt76_wcid *wcid; 641 u16 idx; 642 643 count++; 644 idx = FIELD_GET(MT_TX_FREE_WLAN_ID, info); 645 wcid = rcu_dereference(dev->mt76.wcid[idx]); 646 sta = wcid_to_sta(wcid); 647 if (!sta) 648 continue; 649 650 msta = container_of(wcid, struct mt7921_sta, wcid); 651 spin_lock_bh(&dev->sta_poll_lock); 652 if (list_empty(&msta->poll_list)) 653 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 654 spin_unlock_bh(&dev->sta_poll_lock); 655 continue; 656 } 657 658 msdu = FIELD_GET(MT_TX_FREE_MSDU_ID, info); 659 stat = FIELD_GET(MT_TX_FREE_STATUS, info); 660 661 txwi = mt76_token_release(mdev, msdu, &wake); 662 if (!txwi) 663 continue; 664 665 mt7921_txwi_free(dev, txwi, sta, stat, &free_list); 666 } 667 668 if (wake) 669 mt76_set_tx_blocked(&dev->mt76, false); 670 671 list_for_each_entry_safe(skb, tmp, &free_list, list) { 672 skb_list_del_init(skb); 673 napi_consume_skb(skb, 1); 674 } 675 676 rcu_read_lock(); 677 mt7921_mac_sta_poll(dev); 678 rcu_read_unlock(); 679 680 mt76_worker_schedule(&dev->mt76.tx_worker); 681 } 682 683 bool mt7921_rx_check(struct mt76_dev *mdev, void *data, int len) 684 { 685 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 686 __le32 *rxd = (__le32 *)data; 687 __le32 *end = (__le32 *)&rxd[len / 4]; 688 enum rx_pkt_type type; 689 690 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); 691 692 switch (type) { 693 case PKT_TYPE_TXRX_NOTIFY: 694 /* PKT_TYPE_TXRX_NOTIFY can be received only by mmio devices */ 695 mt7921_mac_tx_free(dev, data, len); /* mmio */ 696 return false; 697 case PKT_TYPE_TXS: 698 for (rxd += 2; rxd + 8 <= end; rxd += 8) 699 mt7921_mac_add_txs(dev, rxd); 700 return false; 701 default: 702 return true; 703 } 704 } 705 EXPORT_SYMBOL_GPL(mt7921_rx_check); 706 707 void mt7921_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 708 struct sk_buff *skb, u32 *info) 709 { 710 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 711 __le32 *rxd = (__le32 *)skb->data; 712 __le32 *end = (__le32 *)&skb->data[skb->len]; 713 enum rx_pkt_type type; 714 u16 flag; 715 716 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); 717 flag = le32_get_bits(rxd[0], MT_RXD0_PKT_FLAG); 718 719 if (type == PKT_TYPE_RX_EVENT && flag == 0x1) 720 type = PKT_TYPE_NORMAL_MCU; 721 722 switch (type) { 723 case PKT_TYPE_TXRX_NOTIFY: 724 /* PKT_TYPE_TXRX_NOTIFY can be received only by mmio devices */ 725 mt7921_mac_tx_free(dev, skb->data, skb->len); 726 napi_consume_skb(skb, 1); 727 break; 728 case PKT_TYPE_RX_EVENT: 729 mt7921_mcu_rx_event(dev, skb); 730 break; 731 case PKT_TYPE_TXS: 732 for (rxd += 2; rxd + 8 <= end; rxd += 8) 733 mt7921_mac_add_txs(dev, rxd); 734 dev_kfree_skb(skb); 735 break; 736 case PKT_TYPE_NORMAL_MCU: 737 case PKT_TYPE_NORMAL: 738 if (!mt7921_mac_fill_rx(dev, skb)) { 739 mt76_rx(&dev->mt76, q, skb); 740 return; 741 } 742 fallthrough; 743 default: 744 dev_kfree_skb(skb); 745 break; 746 } 747 } 748 EXPORT_SYMBOL_GPL(mt7921_queue_rx_skb); 749 750 void mt7921_mac_reset_counters(struct mt7921_phy *phy) 751 { 752 struct mt7921_dev *dev = phy->dev; 753 int i; 754 755 for (i = 0; i < 4; i++) { 756 mt76_rr(dev, MT_TX_AGG_CNT(0, i)); 757 mt76_rr(dev, MT_TX_AGG_CNT2(0, i)); 758 } 759 760 dev->mt76.phy.survey_time = ktime_get_boottime(); 761 memset(phy->mt76->aggr_stats, 0, sizeof(phy->mt76->aggr_stats)); 762 763 /* reset airtime counters */ 764 mt76_rr(dev, MT_MIB_SDR9(0)); 765 mt76_rr(dev, MT_MIB_SDR36(0)); 766 mt76_rr(dev, MT_MIB_SDR37(0)); 767 768 mt76_set(dev, MT_WF_RMAC_MIB_TIME0(0), MT_WF_RMAC_MIB_RXTIME_CLR); 769 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(0), MT_WF_RMAC_MIB_RXTIME_CLR); 770 } 771 772 void mt7921_mac_set_timing(struct mt7921_phy *phy) 773 { 774 s16 coverage_class = phy->coverage_class; 775 struct mt7921_dev *dev = phy->dev; 776 u32 val, reg_offset; 777 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | 778 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); 779 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | 780 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28); 781 bool is_2ghz = phy->mt76->chandef.chan->band == NL80211_BAND_2GHZ; 782 int sifs = is_2ghz ? 10 : 16, offset; 783 784 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state)) 785 return; 786 787 mt76_set(dev, MT_ARB_SCR(0), 788 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 789 udelay(1); 790 791 offset = 3 * coverage_class; 792 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | 793 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); 794 795 mt76_wr(dev, MT_TMAC_CDTR(0), cck + reg_offset); 796 mt76_wr(dev, MT_TMAC_ODTR(0), ofdm + reg_offset); 797 mt76_wr(dev, MT_TMAC_ICR0(0), 798 FIELD_PREP(MT_IFS_EIFS, 360) | 799 FIELD_PREP(MT_IFS_RIFS, 2) | 800 FIELD_PREP(MT_IFS_SIFS, sifs) | 801 FIELD_PREP(MT_IFS_SLOT, phy->slottime)); 802 803 if (phy->slottime < 20 || !is_2ghz) 804 val = MT7921_CFEND_RATE_DEFAULT; 805 else 806 val = MT7921_CFEND_RATE_11B; 807 808 mt76_rmw_field(dev, MT_AGG_ACR0(0), MT_AGG_ACR_CFEND_RATE, val); 809 mt76_clear(dev, MT_ARB_SCR(0), 810 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 811 } 812 813 static u8 814 mt7921_phy_get_nf(struct mt7921_phy *phy, int idx) 815 { 816 return 0; 817 } 818 819 static void 820 mt7921_phy_update_channel(struct mt76_phy *mphy, int idx) 821 { 822 struct mt7921_dev *dev = container_of(mphy->dev, struct mt7921_dev, mt76); 823 struct mt7921_phy *phy = (struct mt7921_phy *)mphy->priv; 824 struct mt76_channel_state *state; 825 u64 busy_time, tx_time, rx_time, obss_time; 826 int nf; 827 828 busy_time = mt76_get_field(dev, MT_MIB_SDR9(idx), 829 MT_MIB_SDR9_BUSY_MASK); 830 tx_time = mt76_get_field(dev, MT_MIB_SDR36(idx), 831 MT_MIB_SDR36_TXTIME_MASK); 832 rx_time = mt76_get_field(dev, MT_MIB_SDR37(idx), 833 MT_MIB_SDR37_RXTIME_MASK); 834 obss_time = mt76_get_field(dev, MT_WF_RMAC_MIB_AIRTIME14(idx), 835 MT_MIB_OBSSTIME_MASK); 836 837 nf = mt7921_phy_get_nf(phy, idx); 838 if (!phy->noise) 839 phy->noise = nf << 4; 840 else if (nf) 841 phy->noise += nf - (phy->noise >> 4); 842 843 state = mphy->chan_state; 844 state->cc_busy += busy_time; 845 state->cc_tx += tx_time; 846 state->cc_rx += rx_time + obss_time; 847 state->cc_bss_rx += rx_time; 848 state->noise = -(phy->noise >> 4); 849 } 850 851 void mt7921_update_channel(struct mt76_phy *mphy) 852 { 853 struct mt7921_dev *dev = container_of(mphy->dev, struct mt7921_dev, mt76); 854 855 if (mt76_connac_pm_wake(mphy, &dev->pm)) 856 return; 857 858 mt7921_phy_update_channel(mphy, 0); 859 /* reset obss airtime */ 860 mt76_set(dev, MT_WF_RMAC_MIB_TIME0(0), MT_WF_RMAC_MIB_RXTIME_CLR); 861 862 mt76_connac_power_save_sched(mphy, &dev->pm); 863 } 864 EXPORT_SYMBOL_GPL(mt7921_update_channel); 865 866 static void 867 mt7921_vif_connect_iter(void *priv, u8 *mac, 868 struct ieee80211_vif *vif) 869 { 870 struct mt7921_vif *mvif = (struct mt7921_vif *)vif->drv_priv; 871 struct mt7921_dev *dev = mvif->phy->dev; 872 struct ieee80211_hw *hw = mt76_hw(dev); 873 874 if (vif->type == NL80211_IFTYPE_STATION) 875 ieee80211_disconnect(vif, true); 876 877 mt76_connac_mcu_uni_add_dev(&dev->mphy, vif, &mvif->sta.wcid, true); 878 mt7921_mcu_set_tx(dev, vif); 879 880 if (vif->type == NL80211_IFTYPE_AP) { 881 mt76_connac_mcu_uni_add_bss(dev->phy.mt76, vif, &mvif->sta.wcid, 882 true, NULL); 883 mt7921_mcu_sta_update(dev, NULL, vif, true, 884 MT76_STA_INFO_STATE_NONE); 885 mt7921_mcu_uni_add_beacon_offload(dev, hw, vif, true); 886 } 887 } 888 889 /* system error recovery */ 890 void mt7921_mac_reset_work(struct work_struct *work) 891 { 892 struct mt7921_dev *dev = container_of(work, struct mt7921_dev, 893 reset_work); 894 struct ieee80211_hw *hw = mt76_hw(dev); 895 struct mt76_connac_pm *pm = &dev->pm; 896 int i, ret; 897 898 dev_dbg(dev->mt76.dev, "chip reset\n"); 899 dev->hw_full_reset = true; 900 ieee80211_stop_queues(hw); 901 902 cancel_delayed_work_sync(&dev->mphy.mac_work); 903 cancel_delayed_work_sync(&pm->ps_work); 904 cancel_work_sync(&pm->wake_work); 905 906 for (i = 0; i < 10; i++) { 907 mutex_lock(&dev->mt76.mutex); 908 ret = mt7921_dev_reset(dev); 909 mutex_unlock(&dev->mt76.mutex); 910 911 if (!ret) 912 break; 913 } 914 915 if (i == 10) 916 dev_err(dev->mt76.dev, "chip reset failed\n"); 917 918 if (test_and_clear_bit(MT76_HW_SCANNING, &dev->mphy.state)) { 919 struct cfg80211_scan_info info = { 920 .aborted = true, 921 }; 922 923 ieee80211_scan_completed(dev->mphy.hw, &info); 924 } 925 926 dev->hw_full_reset = false; 927 pm->suspended = false; 928 ieee80211_wake_queues(hw); 929 ieee80211_iterate_active_interfaces(hw, 930 IEEE80211_IFACE_ITER_RESUME_ALL, 931 mt7921_vif_connect_iter, NULL); 932 mt76_connac_power_save_sched(&dev->mt76.phy, pm); 933 } 934 935 void mt7921_reset(struct mt76_dev *mdev) 936 { 937 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 938 struct mt76_connac_pm *pm = &dev->pm; 939 940 if (!dev->hw_init_done) 941 return; 942 943 if (dev->hw_full_reset) 944 return; 945 946 if (pm->suspended) 947 return; 948 949 queue_work(dev->mt76.wq, &dev->reset_work); 950 } 951 EXPORT_SYMBOL_GPL(mt7921_reset); 952 953 void mt7921_mac_update_mib_stats(struct mt7921_phy *phy) 954 { 955 struct mt7921_dev *dev = phy->dev; 956 struct mib_stats *mib = &phy->mib; 957 int i, aggr0 = 0, aggr1; 958 u32 val; 959 960 mib->fcs_err_cnt += mt76_get_field(dev, MT_MIB_SDR3(0), 961 MT_MIB_SDR3_FCS_ERR_MASK); 962 mib->ack_fail_cnt += mt76_get_field(dev, MT_MIB_MB_BSDR3(0), 963 MT_MIB_ACK_FAIL_COUNT_MASK); 964 mib->ba_miss_cnt += mt76_get_field(dev, MT_MIB_MB_BSDR2(0), 965 MT_MIB_BA_FAIL_COUNT_MASK); 966 mib->rts_cnt += mt76_get_field(dev, MT_MIB_MB_BSDR0(0), 967 MT_MIB_RTS_COUNT_MASK); 968 mib->rts_retries_cnt += mt76_get_field(dev, MT_MIB_MB_BSDR1(0), 969 MT_MIB_RTS_FAIL_COUNT_MASK); 970 971 mib->tx_ampdu_cnt += mt76_rr(dev, MT_MIB_SDR12(0)); 972 mib->tx_mpdu_attempts_cnt += mt76_rr(dev, MT_MIB_SDR14(0)); 973 mib->tx_mpdu_success_cnt += mt76_rr(dev, MT_MIB_SDR15(0)); 974 975 val = mt76_rr(dev, MT_MIB_SDR32(0)); 976 mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR9_EBF_CNT_MASK, val); 977 mib->tx_pkt_ibf_cnt += FIELD_GET(MT_MIB_SDR9_IBF_CNT_MASK, val); 978 979 val = mt76_rr(dev, MT_ETBF_TX_APP_CNT(0)); 980 mib->tx_bf_ibf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_IBF_CNT, val); 981 mib->tx_bf_ebf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_EBF_CNT, val); 982 983 val = mt76_rr(dev, MT_ETBF_RX_FB_CNT(0)); 984 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_ETBF_RX_FB_ALL, val); 985 mib->tx_bf_rx_fb_he_cnt += FIELD_GET(MT_ETBF_RX_FB_HE, val); 986 mib->tx_bf_rx_fb_vht_cnt += FIELD_GET(MT_ETBF_RX_FB_VHT, val); 987 mib->tx_bf_rx_fb_ht_cnt += FIELD_GET(MT_ETBF_RX_FB_HT, val); 988 989 mib->rx_mpdu_cnt += mt76_rr(dev, MT_MIB_SDR5(0)); 990 mib->rx_ampdu_cnt += mt76_rr(dev, MT_MIB_SDR22(0)); 991 mib->rx_ampdu_bytes_cnt += mt76_rr(dev, MT_MIB_SDR23(0)); 992 mib->rx_ba_cnt += mt76_rr(dev, MT_MIB_SDR31(0)); 993 994 for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) { 995 val = mt76_rr(dev, MT_PLE_AMSDU_PACK_MSDU_CNT(i)); 996 mib->tx_amsdu[i] += val; 997 mib->tx_amsdu_cnt += val; 998 } 999 1000 for (i = 0, aggr1 = aggr0 + 8; i < 4; i++) { 1001 u32 val2; 1002 1003 val = mt76_rr(dev, MT_TX_AGG_CNT(0, i)); 1004 val2 = mt76_rr(dev, MT_TX_AGG_CNT2(0, i)); 1005 1006 phy->mt76->aggr_stats[aggr0++] += val & 0xffff; 1007 phy->mt76->aggr_stats[aggr0++] += val >> 16; 1008 phy->mt76->aggr_stats[aggr1++] += val2 & 0xffff; 1009 phy->mt76->aggr_stats[aggr1++] += val2 >> 16; 1010 } 1011 } 1012 1013 void mt7921_mac_work(struct work_struct *work) 1014 { 1015 struct mt7921_phy *phy; 1016 struct mt76_phy *mphy; 1017 1018 mphy = (struct mt76_phy *)container_of(work, struct mt76_phy, 1019 mac_work.work); 1020 phy = mphy->priv; 1021 1022 mt7921_mutex_acquire(phy->dev); 1023 1024 mt76_update_survey(mphy); 1025 if (++mphy->mac_work_count == 2) { 1026 mphy->mac_work_count = 0; 1027 1028 mt7921_mac_update_mib_stats(phy); 1029 } 1030 1031 mt7921_mutex_release(phy->dev); 1032 1033 mt76_tx_status_check(mphy->dev, false); 1034 ieee80211_queue_delayed_work(phy->mt76->hw, &mphy->mac_work, 1035 MT7921_WATCHDOG_TIME); 1036 } 1037 1038 void mt7921_pm_wake_work(struct work_struct *work) 1039 { 1040 struct mt7921_dev *dev; 1041 struct mt76_phy *mphy; 1042 1043 dev = (struct mt7921_dev *)container_of(work, struct mt7921_dev, 1044 pm.wake_work); 1045 mphy = dev->phy.mt76; 1046 1047 if (!mt7921_mcu_drv_pmctrl(dev)) { 1048 struct mt76_dev *mdev = &dev->mt76; 1049 int i; 1050 1051 if (mt76_is_sdio(mdev)) { 1052 mt76_connac_pm_dequeue_skbs(mphy, &dev->pm); 1053 mt76_worker_schedule(&mdev->sdio.txrx_worker); 1054 } else { 1055 local_bh_disable(); 1056 mt76_for_each_q_rx(mdev, i) 1057 napi_schedule(&mdev->napi[i]); 1058 local_bh_enable(); 1059 mt76_connac_pm_dequeue_skbs(mphy, &dev->pm); 1060 mt76_connac_tx_cleanup(mdev); 1061 } 1062 if (test_bit(MT76_STATE_RUNNING, &mphy->state)) 1063 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, 1064 MT7921_WATCHDOG_TIME); 1065 } 1066 1067 ieee80211_wake_queues(mphy->hw); 1068 wake_up(&dev->pm.wait); 1069 } 1070 1071 void mt7921_pm_power_save_work(struct work_struct *work) 1072 { 1073 struct mt7921_dev *dev; 1074 unsigned long delta; 1075 struct mt76_phy *mphy; 1076 1077 dev = (struct mt7921_dev *)container_of(work, struct mt7921_dev, 1078 pm.ps_work.work); 1079 mphy = dev->phy.mt76; 1080 1081 delta = dev->pm.idle_timeout; 1082 if (test_bit(MT76_HW_SCANNING, &mphy->state) || 1083 test_bit(MT76_HW_SCHED_SCANNING, &mphy->state) || 1084 dev->fw_assert) 1085 goto out; 1086 1087 if (mutex_is_locked(&dev->mt76.mutex)) 1088 /* if mt76 mutex is held we should not put the device 1089 * to sleep since we are currently accessing device 1090 * register map. We need to wait for the next power_save 1091 * trigger. 1092 */ 1093 goto out; 1094 1095 if (time_is_after_jiffies(dev->pm.last_activity + delta)) { 1096 delta = dev->pm.last_activity + delta - jiffies; 1097 goto out; 1098 } 1099 1100 if (!mt7921_mcu_fw_pmctrl(dev)) { 1101 cancel_delayed_work_sync(&mphy->mac_work); 1102 return; 1103 } 1104 out: 1105 queue_delayed_work(dev->mt76.wq, &dev->pm.ps_work, delta); 1106 } 1107 1108 void mt7921_coredump_work(struct work_struct *work) 1109 { 1110 struct mt7921_dev *dev; 1111 char *dump, *data; 1112 1113 dev = (struct mt7921_dev *)container_of(work, struct mt7921_dev, 1114 coredump.work.work); 1115 1116 if (time_is_after_jiffies(dev->coredump.last_activity + 1117 4 * MT76_CONNAC_COREDUMP_TIMEOUT)) { 1118 queue_delayed_work(dev->mt76.wq, &dev->coredump.work, 1119 MT76_CONNAC_COREDUMP_TIMEOUT); 1120 return; 1121 } 1122 1123 dump = vzalloc(MT76_CONNAC_COREDUMP_SZ); 1124 data = dump; 1125 1126 while (true) { 1127 struct sk_buff *skb; 1128 1129 spin_lock_bh(&dev->mt76.lock); 1130 skb = __skb_dequeue(&dev->coredump.msg_list); 1131 spin_unlock_bh(&dev->mt76.lock); 1132 1133 if (!skb) 1134 break; 1135 1136 skb_pull(skb, sizeof(struct mt76_connac2_mcu_rxd)); 1137 if (!dump || data + skb->len - dump > MT76_CONNAC_COREDUMP_SZ) { 1138 dev_kfree_skb(skb); 1139 continue; 1140 } 1141 1142 memcpy(data, skb->data, skb->len); 1143 data += skb->len; 1144 1145 dev_kfree_skb(skb); 1146 } 1147 1148 if (dump) 1149 dev_coredumpv(dev->mt76.dev, dump, MT76_CONNAC_COREDUMP_SZ, 1150 GFP_KERNEL); 1151 1152 mt7921_reset(&dev->mt76); 1153 } 1154 1155 /* usb_sdio */ 1156 static void 1157 mt7921_usb_sdio_write_txwi(struct mt7921_dev *dev, struct mt76_wcid *wcid, 1158 enum mt76_txq_id qid, struct ieee80211_sta *sta, 1159 struct ieee80211_key_conf *key, int pid, 1160 struct sk_buff *skb) 1161 { 1162 __le32 *txwi = (__le32 *)(skb->data - MT_SDIO_TXD_SIZE); 1163 1164 memset(txwi, 0, MT_SDIO_TXD_SIZE); 1165 mt76_connac2_mac_write_txwi(&dev->mt76, txwi, skb, wcid, key, pid, qid, 0); 1166 skb_push(skb, MT_SDIO_TXD_SIZE); 1167 } 1168 1169 int mt7921_usb_sdio_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, 1170 enum mt76_txq_id qid, struct mt76_wcid *wcid, 1171 struct ieee80211_sta *sta, 1172 struct mt76_tx_info *tx_info) 1173 { 1174 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 1175 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb); 1176 struct ieee80211_key_conf *key = info->control.hw_key; 1177 struct sk_buff *skb = tx_info->skb; 1178 int err, pad, pktid, type; 1179 1180 if (unlikely(tx_info->skb->len <= ETH_HLEN)) 1181 return -EINVAL; 1182 1183 if (!wcid) 1184 wcid = &dev->mt76.global_wcid; 1185 1186 if (sta) { 1187 struct mt7921_sta *msta = (struct mt7921_sta *)sta->drv_priv; 1188 1189 if (time_after(jiffies, msta->last_txs + HZ / 4)) { 1190 info->flags |= IEEE80211_TX_CTL_REQ_TX_STATUS; 1191 msta->last_txs = jiffies; 1192 } 1193 } 1194 1195 pktid = mt76_tx_status_skb_add(&dev->mt76, wcid, skb); 1196 mt7921_usb_sdio_write_txwi(dev, wcid, qid, sta, key, pktid, skb); 1197 1198 type = mt76_is_sdio(mdev) ? MT7921_SDIO_DATA : 0; 1199 mt7921_skb_add_usb_sdio_hdr(dev, skb, type); 1200 pad = round_up(skb->len, 4) - skb->len; 1201 if (mt76_is_usb(mdev)) 1202 pad += 4; 1203 1204 err = mt76_skb_adjust_pad(skb, pad); 1205 if (err) 1206 /* Release pktid in case of error. */ 1207 idr_remove(&wcid->pktid, pktid); 1208 1209 return err; 1210 } 1211 EXPORT_SYMBOL_GPL(mt7921_usb_sdio_tx_prepare_skb); 1212 1213 void mt7921_usb_sdio_tx_complete_skb(struct mt76_dev *mdev, 1214 struct mt76_queue_entry *e) 1215 { 1216 __le32 *txwi = (__le32 *)(e->skb->data + MT_SDIO_HDR_SIZE); 1217 unsigned int headroom = MT_SDIO_TXD_SIZE + MT_SDIO_HDR_SIZE; 1218 struct ieee80211_sta *sta; 1219 struct mt76_wcid *wcid; 1220 u16 idx; 1221 1222 idx = le32_get_bits(txwi[1], MT_TXD1_WLAN_IDX); 1223 wcid = rcu_dereference(mdev->wcid[idx]); 1224 sta = wcid_to_sta(wcid); 1225 1226 if (sta && likely(e->skb->protocol != cpu_to_be16(ETH_P_PAE))) 1227 mt7921_tx_check_aggr(sta, txwi); 1228 1229 skb_pull(e->skb, headroom); 1230 mt76_tx_complete_skb(mdev, e->wcid, e->skb); 1231 } 1232 EXPORT_SYMBOL_GPL(mt7921_usb_sdio_tx_complete_skb); 1233 1234 bool mt7921_usb_sdio_tx_status_data(struct mt76_dev *mdev, u8 *update) 1235 { 1236 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 1237 1238 mt7921_mutex_acquire(dev); 1239 mt7921_mac_sta_poll(dev); 1240 mt7921_mutex_release(dev); 1241 1242 return false; 1243 } 1244 EXPORT_SYMBOL_GPL(mt7921_usb_sdio_tx_status_data); 1245 1246 #if IS_ENABLED(CONFIG_IPV6) 1247 void mt7921_set_ipv6_ns_work(struct work_struct *work) 1248 { 1249 struct mt7921_dev *dev = container_of(work, struct mt7921_dev, 1250 ipv6_ns_work); 1251 struct sk_buff *skb; 1252 int ret = 0; 1253 1254 do { 1255 skb = skb_dequeue(&dev->ipv6_ns_list); 1256 1257 if (!skb) 1258 break; 1259 1260 mt7921_mutex_acquire(dev); 1261 ret = mt76_mcu_skb_send_msg(&dev->mt76, skb, 1262 MCU_UNI_CMD(OFFLOAD), true); 1263 mt7921_mutex_release(dev); 1264 1265 } while (!ret); 1266 1267 if (ret) 1268 skb_queue_purge(&dev->ipv6_ns_list); 1269 } 1270 #endif 1271