1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include "mt7915.h" 5 #include "mac.h" 6 #include "mcu.h" 7 #include "testmode.h" 8 9 enum { 10 TM_CHANGED_TXPOWER, 11 TM_CHANGED_FREQ_OFFSET, 12 13 /* must be last */ 14 NUM_TM_CHANGED 15 }; 16 17 static const u8 tm_change_map[] = { 18 [TM_CHANGED_TXPOWER] = MT76_TM_ATTR_TX_POWER, 19 [TM_CHANGED_FREQ_OFFSET] = MT76_TM_ATTR_FREQ_OFFSET, 20 }; 21 22 struct reg_band { 23 u32 band[2]; 24 }; 25 26 #define REG_BAND(_reg) \ 27 { .band[0] = MT_##_reg(0), .band[1] = MT_##_reg(1) } 28 #define REG_BAND_IDX(_reg, _idx) \ 29 { .band[0] = MT_##_reg(0, _idx), .band[1] = MT_##_reg(1, _idx) } 30 31 static const struct reg_band reg_backup_list[] = { 32 REG_BAND_IDX(AGG_PCR0, 0), 33 REG_BAND_IDX(AGG_PCR0, 1), 34 REG_BAND_IDX(AGG_AWSCR0, 0), 35 REG_BAND_IDX(AGG_AWSCR0, 1), 36 REG_BAND_IDX(AGG_AWSCR0, 2), 37 REG_BAND_IDX(AGG_AWSCR0, 3), 38 REG_BAND(AGG_MRCR), 39 REG_BAND(TMAC_TFCR0), 40 REG_BAND(TMAC_TCR0), 41 REG_BAND(AGG_ATCR1), 42 REG_BAND(AGG_ATCR3), 43 REG_BAND(TMAC_TRCR0), 44 REG_BAND(TMAC_ICR0), 45 REG_BAND_IDX(ARB_DRNGR0, 0), 46 REG_BAND_IDX(ARB_DRNGR0, 1), 47 REG_BAND(WF_RFCR), 48 REG_BAND(WF_RFCR1), 49 }; 50 51 static int 52 mt7915_tm_set_tx_power(struct mt7915_phy *phy) 53 { 54 struct mt7915_dev *dev = phy->dev; 55 struct mt76_phy *mphy = phy->mt76; 56 struct cfg80211_chan_def *chandef = &mphy->chandef; 57 int freq = chandef->center_freq1; 58 int ret; 59 struct { 60 u8 format_id; 61 u8 dbdc_idx; 62 s8 tx_power; 63 u8 ant_idx; /* Only 0 is valid */ 64 u8 center_chan; 65 u8 rsv[3]; 66 } __packed req = { 67 .format_id = 0xf, 68 .dbdc_idx = phy != &dev->phy, 69 .center_chan = ieee80211_frequency_to_channel(freq), 70 }; 71 u8 *tx_power = NULL; 72 73 if (phy->mt76->test.state != MT76_TM_STATE_OFF) 74 tx_power = phy->mt76->test.tx_power; 75 76 /* Tx power of the other antennas are the same as antenna 0 */ 77 if (tx_power && tx_power[0]) 78 req.tx_power = tx_power[0]; 79 80 ret = mt76_mcu_send_msg(&dev->mt76, 81 MCU_EXT_CMD(TX_POWER_FEATURE_CTRL), 82 &req, sizeof(req), false); 83 84 return ret; 85 } 86 87 static int 88 mt7915_tm_set_freq_offset(struct mt7915_phy *phy, bool en, u32 val) 89 { 90 struct mt7915_dev *dev = phy->dev; 91 struct mt7915_tm_cmd req = { 92 .testmode_en = en, 93 .param_idx = MCU_ATE_SET_FREQ_OFFSET, 94 .param.freq.band = phy != &dev->phy, 95 .param.freq.freq_offset = cpu_to_le32(val), 96 }; 97 98 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), &req, 99 sizeof(req), false); 100 } 101 102 static int 103 mt7915_tm_mode_ctrl(struct mt7915_dev *dev, bool enable) 104 { 105 struct { 106 u8 format_id; 107 bool enable; 108 u8 rsv[2]; 109 } __packed req = { 110 .format_id = 0x6, 111 .enable = enable, 112 }; 113 114 return mt76_mcu_send_msg(&dev->mt76, 115 MCU_EXT_CMD(TX_POWER_FEATURE_CTRL), 116 &req, sizeof(req), false); 117 } 118 119 static int 120 mt7915_tm_set_trx(struct mt7915_phy *phy, int type, bool en) 121 { 122 struct mt7915_dev *dev = phy->dev; 123 struct mt7915_tm_cmd req = { 124 .testmode_en = 1, 125 .param_idx = MCU_ATE_SET_TRX, 126 .param.trx.type = type, 127 .param.trx.enable = en, 128 .param.trx.band = phy != &dev->phy, 129 }; 130 131 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), &req, 132 sizeof(req), false); 133 } 134 135 static int 136 mt7915_tm_clean_hwq(struct mt7915_phy *phy, u8 wcid) 137 { 138 struct mt7915_dev *dev = phy->dev; 139 struct mt7915_tm_cmd req = { 140 .testmode_en = 1, 141 .param_idx = MCU_ATE_CLEAN_TXQUEUE, 142 .param.clean.wcid = wcid, 143 .param.clean.band = phy != &dev->phy, 144 }; 145 146 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), &req, 147 sizeof(req), false); 148 } 149 150 static int 151 mt7915_tm_set_slot_time(struct mt7915_phy *phy, u8 slot_time, u8 sifs) 152 { 153 struct mt7915_dev *dev = phy->dev; 154 struct mt7915_tm_cmd req = { 155 .testmode_en = !(phy->mt76->test.state == MT76_TM_STATE_OFF), 156 .param_idx = MCU_ATE_SET_SLOT_TIME, 157 .param.slot.slot_time = slot_time, 158 .param.slot.sifs = sifs, 159 .param.slot.rifs = 2, 160 .param.slot.eifs = cpu_to_le16(60), 161 .param.slot.band = phy != &dev->phy, 162 }; 163 164 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), &req, 165 sizeof(req), false); 166 } 167 168 static int 169 mt7915_tm_set_tam_arb(struct mt7915_phy *phy, bool enable, bool mu) 170 { 171 struct mt7915_dev *dev = phy->dev; 172 u32 op_mode; 173 174 if (!enable) 175 op_mode = TAM_ARB_OP_MODE_NORMAL; 176 else if (mu) 177 op_mode = TAM_ARB_OP_MODE_TEST; 178 else 179 op_mode = TAM_ARB_OP_MODE_FORCE_SU; 180 181 return mt7915_mcu_set_muru_ctrl(dev, MURU_SET_ARB_OP_MODE, op_mode); 182 } 183 184 static int 185 mt7915_tm_set_wmm_qid(struct mt7915_dev *dev, u8 qid, u8 aifs, u8 cw_min, 186 u16 cw_max, u16 txop) 187 { 188 struct mt7915_mcu_tx req = { .total = 1 }; 189 struct edca *e = &req.edca[0]; 190 191 e->queue = qid; 192 e->set = WMM_PARAM_SET; 193 194 e->aifs = aifs; 195 e->cw_min = cw_min; 196 e->cw_max = cpu_to_le16(cw_max); 197 e->txop = cpu_to_le16(txop); 198 199 return mt7915_mcu_update_edca(dev, &req); 200 } 201 202 static int 203 mt7915_tm_set_ipg_params(struct mt7915_phy *phy, u32 ipg, u8 mode) 204 { 205 #define TM_DEFAULT_SIFS 10 206 #define TM_MAX_SIFS 127 207 #define TM_MAX_AIFSN 0xf 208 #define TM_MIN_AIFSN 0x1 209 #define BBP_PROC_TIME 1500 210 struct mt7915_dev *dev = phy->dev; 211 u8 sig_ext = (mode == MT76_TM_TX_MODE_CCK) ? 0 : 6; 212 u8 slot_time = 9, sifs = TM_DEFAULT_SIFS; 213 u8 aifsn = TM_MIN_AIFSN; 214 u32 i2t_time, tr2t_time, txv_time; 215 bool ext_phy = phy != &dev->phy; 216 u16 cw = 0; 217 218 if (ipg < sig_ext + slot_time + sifs) 219 ipg = 0; 220 221 if (!ipg) 222 goto done; 223 224 ipg -= sig_ext; 225 226 if (ipg <= (TM_MAX_SIFS + slot_time)) { 227 sifs = ipg - slot_time; 228 } else { 229 u32 val = (ipg + slot_time) / slot_time; 230 231 while (val >>= 1) 232 cw++; 233 234 if (cw > 16) 235 cw = 16; 236 237 ipg -= ((1 << cw) - 1) * slot_time; 238 239 aifsn = ipg / slot_time; 240 if (aifsn > TM_MAX_AIFSN) 241 aifsn = TM_MAX_AIFSN; 242 243 ipg -= aifsn * slot_time; 244 245 if (ipg > TM_DEFAULT_SIFS) { 246 if (ipg < TM_MAX_SIFS) 247 sifs = ipg; 248 else 249 sifs = TM_MAX_SIFS; 250 } 251 } 252 done: 253 txv_time = mt76_get_field(dev, MT_TMAC_ATCR(ext_phy), 254 MT_TMAC_ATCR_TXV_TOUT); 255 txv_time *= 50; /* normal clock time */ 256 257 i2t_time = (slot_time * 1000 - txv_time - BBP_PROC_TIME) / 50; 258 tr2t_time = (sifs * 1000 - txv_time - BBP_PROC_TIME) / 50; 259 260 mt76_set(dev, MT_TMAC_TRCR0(ext_phy), 261 FIELD_PREP(MT_TMAC_TRCR0_TR2T_CHK, tr2t_time) | 262 FIELD_PREP(MT_TMAC_TRCR0_I2T_CHK, i2t_time)); 263 264 mt7915_tm_set_slot_time(phy, slot_time, sifs); 265 266 return mt7915_tm_set_wmm_qid(dev, 267 mt7915_lmac_mapping(dev, IEEE80211_AC_BE), 268 aifsn, cw, cw, 0); 269 } 270 271 static int 272 mt7915_tm_set_tx_len(struct mt7915_phy *phy, u32 tx_time) 273 { 274 struct mt76_phy *mphy = phy->mt76; 275 struct mt76_testmode_data *td = &mphy->test; 276 struct ieee80211_supported_band *sband; 277 struct rate_info rate = {}; 278 u16 flags = 0, tx_len; 279 u32 bitrate; 280 int ret; 281 282 if (!tx_time) 283 return 0; 284 285 rate.mcs = td->tx_rate_idx; 286 rate.nss = td->tx_rate_nss; 287 288 switch (td->tx_rate_mode) { 289 case MT76_TM_TX_MODE_CCK: 290 case MT76_TM_TX_MODE_OFDM: 291 if (mphy->chandef.chan->band == NL80211_BAND_5GHZ) 292 sband = &mphy->sband_5g.sband; 293 else 294 sband = &mphy->sband_2g.sband; 295 296 rate.legacy = sband->bitrates[rate.mcs].bitrate; 297 break; 298 case MT76_TM_TX_MODE_HT: 299 rate.mcs += rate.nss * 8; 300 flags |= RATE_INFO_FLAGS_MCS; 301 302 if (td->tx_rate_sgi) 303 flags |= RATE_INFO_FLAGS_SHORT_GI; 304 break; 305 case MT76_TM_TX_MODE_VHT: 306 flags |= RATE_INFO_FLAGS_VHT_MCS; 307 308 if (td->tx_rate_sgi) 309 flags |= RATE_INFO_FLAGS_SHORT_GI; 310 break; 311 case MT76_TM_TX_MODE_HE_SU: 312 case MT76_TM_TX_MODE_HE_EXT_SU: 313 case MT76_TM_TX_MODE_HE_TB: 314 case MT76_TM_TX_MODE_HE_MU: 315 rate.he_gi = td->tx_rate_sgi; 316 flags |= RATE_INFO_FLAGS_HE_MCS; 317 break; 318 default: 319 break; 320 } 321 rate.flags = flags; 322 323 switch (mphy->chandef.width) { 324 case NL80211_CHAN_WIDTH_160: 325 case NL80211_CHAN_WIDTH_80P80: 326 rate.bw = RATE_INFO_BW_160; 327 break; 328 case NL80211_CHAN_WIDTH_80: 329 rate.bw = RATE_INFO_BW_80; 330 break; 331 case NL80211_CHAN_WIDTH_40: 332 rate.bw = RATE_INFO_BW_40; 333 break; 334 default: 335 rate.bw = RATE_INFO_BW_20; 336 break; 337 } 338 339 bitrate = cfg80211_calculate_bitrate(&rate); 340 tx_len = bitrate * tx_time / 10 / 8; 341 342 ret = mt76_testmode_alloc_skb(phy->mt76, tx_len); 343 if (ret) 344 return ret; 345 346 return 0; 347 } 348 349 static void 350 mt7915_tm_reg_backup_restore(struct mt7915_phy *phy) 351 { 352 int n_regs = ARRAY_SIZE(reg_backup_list); 353 struct mt7915_dev *dev = phy->dev; 354 bool ext_phy = phy != &dev->phy; 355 u32 *b = phy->test.reg_backup; 356 int i; 357 358 if (phy->mt76->test.state == MT76_TM_STATE_OFF) { 359 for (i = 0; i < n_regs; i++) 360 mt76_wr(dev, reg_backup_list[i].band[ext_phy], b[i]); 361 return; 362 } 363 364 if (b) 365 return; 366 367 b = devm_kzalloc(dev->mt76.dev, 4 * n_regs, GFP_KERNEL); 368 if (!b) 369 return; 370 371 phy->test.reg_backup = b; 372 for (i = 0; i < n_regs; i++) 373 b[i] = mt76_rr(dev, reg_backup_list[i].band[ext_phy]); 374 375 mt76_clear(dev, MT_AGG_PCR0(ext_phy, 0), MT_AGG_PCR0_MM_PROT | 376 MT_AGG_PCR0_GF_PROT | MT_AGG_PCR0_ERP_PROT | 377 MT_AGG_PCR0_VHT_PROT | MT_AGG_PCR0_BW20_PROT | 378 MT_AGG_PCR0_BW40_PROT | MT_AGG_PCR0_BW80_PROT); 379 mt76_set(dev, MT_AGG_PCR0(ext_phy, 0), MT_AGG_PCR0_PTA_WIN_DIS); 380 381 mt76_wr(dev, MT_AGG_PCR0(ext_phy, 1), MT_AGG_PCR1_RTS0_NUM_THRES | 382 MT_AGG_PCR1_RTS0_LEN_THRES); 383 384 mt76_clear(dev, MT_AGG_MRCR(ext_phy), MT_AGG_MRCR_BAR_CNT_LIMIT | 385 MT_AGG_MRCR_LAST_RTS_CTS_RN | MT_AGG_MRCR_RTS_FAIL_LIMIT | 386 MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT); 387 388 mt76_rmw(dev, MT_AGG_MRCR(ext_phy), MT_AGG_MRCR_RTS_FAIL_LIMIT | 389 MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT, 390 FIELD_PREP(MT_AGG_MRCR_RTS_FAIL_LIMIT, 1) | 391 FIELD_PREP(MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT, 1)); 392 393 mt76_wr(dev, MT_TMAC_TFCR0(ext_phy), 0); 394 mt76_clear(dev, MT_TMAC_TCR0(ext_phy), MT_TMAC_TCR0_TBTT_STOP_CTRL); 395 396 /* config rx filter for testmode rx */ 397 mt76_wr(dev, MT_WF_RFCR(ext_phy), 0xcf70a); 398 mt76_wr(dev, MT_WF_RFCR1(ext_phy), 0); 399 } 400 401 static void 402 mt7915_tm_init(struct mt7915_phy *phy, bool en) 403 { 404 struct mt7915_dev *dev = phy->dev; 405 406 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state)) 407 return; 408 409 mt7915_mcu_set_sku_en(phy, !en); 410 411 mt7915_tm_mode_ctrl(dev, en); 412 mt7915_tm_reg_backup_restore(phy); 413 mt7915_tm_set_trx(phy, TM_MAC_TXRX, !en); 414 415 mt7915_mcu_add_bss_info(phy, phy->monitor_vif, en); 416 mt7915_mcu_add_sta(dev, phy->monitor_vif, NULL, en); 417 418 if (!en) 419 mt7915_tm_set_tam_arb(phy, en, 0); 420 } 421 422 static void 423 mt7915_tm_update_channel(struct mt7915_phy *phy) 424 { 425 mutex_unlock(&phy->dev->mt76.mutex); 426 mt7915_set_channel(phy); 427 mutex_lock(&phy->dev->mt76.mutex); 428 429 mt7915_mcu_set_chan_info(phy, MCU_EXT_CMD(SET_RX_PATH)); 430 } 431 432 static void 433 mt7915_tm_set_tx_frames(struct mt7915_phy *phy, bool en) 434 { 435 static const u8 spe_idx_map[] = {0, 0, 1, 0, 3, 2, 4, 0, 436 9, 8, 6, 10, 16, 12, 18, 0}; 437 struct mt76_testmode_data *td = &phy->mt76->test; 438 struct mt7915_dev *dev = phy->dev; 439 struct ieee80211_tx_info *info; 440 u8 duty_cycle = td->tx_duty_cycle; 441 u32 tx_time = td->tx_time; 442 u32 ipg = td->tx_ipg; 443 444 mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, false); 445 mt7915_tm_clean_hwq(phy, dev->mt76.global_wcid.idx); 446 447 if (en) { 448 mt7915_tm_update_channel(phy); 449 450 if (td->tx_spe_idx) { 451 phy->test.spe_idx = td->tx_spe_idx; 452 } else { 453 u8 tx_ant = td->tx_antenna_mask; 454 455 if (phy != &dev->phy) 456 tx_ant >>= 2; 457 phy->test.spe_idx = spe_idx_map[tx_ant]; 458 } 459 } 460 461 mt7915_tm_set_tam_arb(phy, en, 462 td->tx_rate_mode == MT76_TM_TX_MODE_HE_MU); 463 464 /* if all three params are set, duty_cycle will be ignored */ 465 if (duty_cycle && tx_time && !ipg) { 466 ipg = tx_time * 100 / duty_cycle - tx_time; 467 } else if (duty_cycle && !tx_time && ipg) { 468 if (duty_cycle < 100) 469 tx_time = duty_cycle * ipg / (100 - duty_cycle); 470 } 471 472 mt7915_tm_set_ipg_params(phy, ipg, td->tx_rate_mode); 473 mt7915_tm_set_tx_len(phy, tx_time); 474 475 if (ipg) 476 td->tx_queued_limit = MT76_TM_TIMEOUT * 1000000 / ipg / 2; 477 478 if (!en || !td->tx_skb) 479 return; 480 481 info = IEEE80211_SKB_CB(td->tx_skb); 482 info->control.vif = phy->monitor_vif; 483 484 mt7915_tm_set_trx(phy, TM_MAC_TX, en); 485 } 486 487 static void 488 mt7915_tm_set_rx_frames(struct mt7915_phy *phy, bool en) 489 { 490 mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, false); 491 492 if (en) { 493 struct mt7915_dev *dev = phy->dev; 494 495 mt7915_tm_update_channel(phy); 496 497 /* read-clear */ 498 mt76_rr(dev, MT_MIB_SDR3(phy != &dev->phy)); 499 mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, en); 500 } 501 } 502 503 static int 504 mt7915_tm_rf_switch_mode(struct mt7915_dev *dev, u32 oper) 505 { 506 struct mt7915_tm_rf_test req = { 507 .op.op_mode = cpu_to_le32(oper), 508 }; 509 510 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RF_TEST), &req, 511 sizeof(req), true); 512 } 513 514 static int 515 mt7915_tm_set_tx_cont(struct mt7915_phy *phy, bool en) 516 { 517 #define TX_CONT_START 0x05 518 #define TX_CONT_STOP 0x06 519 struct mt7915_dev *dev = phy->dev; 520 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 521 int freq1 = ieee80211_frequency_to_channel(chandef->center_freq1); 522 struct mt76_testmode_data *td = &phy->mt76->test; 523 u32 func_idx = en ? TX_CONT_START : TX_CONT_STOP; 524 u8 rate_idx = td->tx_rate_idx, mode; 525 u16 rateval; 526 struct mt7915_tm_rf_test req = { 527 .action = 1, 528 .icap_len = 120, 529 .op.rf.func_idx = cpu_to_le32(func_idx), 530 }; 531 struct tm_tx_cont *tx_cont = &req.op.rf.param.tx_cont; 532 533 tx_cont->control_ch = chandef->chan->hw_value; 534 tx_cont->center_ch = freq1; 535 tx_cont->tx_ant = td->tx_antenna_mask; 536 tx_cont->band = phy != &dev->phy; 537 538 switch (chandef->width) { 539 case NL80211_CHAN_WIDTH_40: 540 tx_cont->bw = CMD_CBW_40MHZ; 541 break; 542 case NL80211_CHAN_WIDTH_80: 543 tx_cont->bw = CMD_CBW_80MHZ; 544 break; 545 case NL80211_CHAN_WIDTH_80P80: 546 tx_cont->bw = CMD_CBW_8080MHZ; 547 break; 548 case NL80211_CHAN_WIDTH_160: 549 tx_cont->bw = CMD_CBW_160MHZ; 550 break; 551 case NL80211_CHAN_WIDTH_5: 552 tx_cont->bw = CMD_CBW_5MHZ; 553 break; 554 case NL80211_CHAN_WIDTH_10: 555 tx_cont->bw = CMD_CBW_10MHZ; 556 break; 557 case NL80211_CHAN_WIDTH_20: 558 tx_cont->bw = CMD_CBW_20MHZ; 559 break; 560 case NL80211_CHAN_WIDTH_20_NOHT: 561 tx_cont->bw = CMD_CBW_20MHZ; 562 break; 563 default: 564 return -EINVAL; 565 } 566 567 if (!en) { 568 req.op.rf.param.func_data = cpu_to_le32(phy != &dev->phy); 569 goto out; 570 } 571 572 if (td->tx_rate_mode <= MT76_TM_TX_MODE_OFDM) { 573 struct ieee80211_supported_band *sband; 574 u8 idx = rate_idx; 575 576 if (chandef->chan->band == NL80211_BAND_5GHZ) 577 sband = &phy->mt76->sband_5g.sband; 578 else 579 sband = &phy->mt76->sband_2g.sband; 580 581 if (td->tx_rate_mode == MT76_TM_TX_MODE_OFDM) 582 idx += 4; 583 rate_idx = sband->bitrates[idx].hw_value & 0xff; 584 } 585 586 switch (td->tx_rate_mode) { 587 case MT76_TM_TX_MODE_CCK: 588 mode = MT_PHY_TYPE_CCK; 589 break; 590 case MT76_TM_TX_MODE_OFDM: 591 mode = MT_PHY_TYPE_OFDM; 592 break; 593 case MT76_TM_TX_MODE_HT: 594 mode = MT_PHY_TYPE_HT; 595 break; 596 case MT76_TM_TX_MODE_VHT: 597 mode = MT_PHY_TYPE_VHT; 598 break; 599 case MT76_TM_TX_MODE_HE_SU: 600 mode = MT_PHY_TYPE_HE_SU; 601 break; 602 case MT76_TM_TX_MODE_HE_EXT_SU: 603 mode = MT_PHY_TYPE_HE_EXT_SU; 604 break; 605 case MT76_TM_TX_MODE_HE_TB: 606 mode = MT_PHY_TYPE_HE_TB; 607 break; 608 case MT76_TM_TX_MODE_HE_MU: 609 mode = MT_PHY_TYPE_HE_MU; 610 break; 611 default: 612 return -EINVAL; 613 } 614 615 rateval = mode << 6 | rate_idx; 616 tx_cont->rateval = cpu_to_le16(rateval); 617 618 out: 619 if (!en) { 620 int ret; 621 622 ret = mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RF_TEST), &req, 623 sizeof(req), true); 624 if (ret) 625 return ret; 626 627 return mt7915_tm_rf_switch_mode(dev, RF_OPER_NORMAL); 628 } 629 630 mt7915_tm_rf_switch_mode(dev, RF_OPER_RF_TEST); 631 mt7915_tm_update_channel(phy); 632 633 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RF_TEST), &req, 634 sizeof(req), true); 635 } 636 637 static void 638 mt7915_tm_update_params(struct mt7915_phy *phy, u32 changed) 639 { 640 struct mt76_testmode_data *td = &phy->mt76->test; 641 bool en = phy->mt76->test.state != MT76_TM_STATE_OFF; 642 643 if (changed & BIT(TM_CHANGED_FREQ_OFFSET)) 644 mt7915_tm_set_freq_offset(phy, en, en ? td->freq_offset : 0); 645 if (changed & BIT(TM_CHANGED_TXPOWER)) 646 mt7915_tm_set_tx_power(phy); 647 } 648 649 static int 650 mt7915_tm_set_state(struct mt76_phy *mphy, enum mt76_testmode_state state) 651 { 652 struct mt76_testmode_data *td = &mphy->test; 653 struct mt7915_phy *phy = mphy->priv; 654 enum mt76_testmode_state prev_state = td->state; 655 656 mphy->test.state = state; 657 658 if (prev_state == MT76_TM_STATE_TX_FRAMES || 659 state == MT76_TM_STATE_TX_FRAMES) 660 mt7915_tm_set_tx_frames(phy, state == MT76_TM_STATE_TX_FRAMES); 661 else if (prev_state == MT76_TM_STATE_RX_FRAMES || 662 state == MT76_TM_STATE_RX_FRAMES) 663 mt7915_tm_set_rx_frames(phy, state == MT76_TM_STATE_RX_FRAMES); 664 else if (prev_state == MT76_TM_STATE_TX_CONT || 665 state == MT76_TM_STATE_TX_CONT) 666 mt7915_tm_set_tx_cont(phy, state == MT76_TM_STATE_TX_CONT); 667 else if (prev_state == MT76_TM_STATE_OFF || 668 state == MT76_TM_STATE_OFF) 669 mt7915_tm_init(phy, !(state == MT76_TM_STATE_OFF)); 670 671 if ((state == MT76_TM_STATE_IDLE && 672 prev_state == MT76_TM_STATE_OFF) || 673 (state == MT76_TM_STATE_OFF && 674 prev_state == MT76_TM_STATE_IDLE)) { 675 u32 changed = 0; 676 int i; 677 678 for (i = 0; i < ARRAY_SIZE(tm_change_map); i++) { 679 u16 cur = tm_change_map[i]; 680 681 if (td->param_set[cur / 32] & BIT(cur % 32)) 682 changed |= BIT(i); 683 } 684 685 mt7915_tm_update_params(phy, changed); 686 } 687 688 return 0; 689 } 690 691 static int 692 mt7915_tm_set_params(struct mt76_phy *mphy, struct nlattr **tb, 693 enum mt76_testmode_state new_state) 694 { 695 struct mt76_testmode_data *td = &mphy->test; 696 struct mt7915_phy *phy = mphy->priv; 697 u32 changed = 0; 698 int i; 699 700 BUILD_BUG_ON(NUM_TM_CHANGED >= 32); 701 702 if (new_state == MT76_TM_STATE_OFF || 703 td->state == MT76_TM_STATE_OFF) 704 return 0; 705 706 if (td->tx_antenna_mask & ~mphy->chainmask) 707 return -EINVAL; 708 709 for (i = 0; i < ARRAY_SIZE(tm_change_map); i++) { 710 if (tb[tm_change_map[i]]) 711 changed |= BIT(i); 712 } 713 714 mt7915_tm_update_params(phy, changed); 715 716 return 0; 717 } 718 719 static int 720 mt7915_tm_dump_stats(struct mt76_phy *mphy, struct sk_buff *msg) 721 { 722 struct mt7915_phy *phy = mphy->priv; 723 struct mt7915_dev *dev = phy->dev; 724 bool ext_phy = phy != &dev->phy; 725 enum mt76_rxq_id q; 726 void *rx, *rssi; 727 u16 fcs_err; 728 int i; 729 730 rx = nla_nest_start(msg, MT76_TM_STATS_ATTR_LAST_RX); 731 if (!rx) 732 return -ENOMEM; 733 734 if (nla_put_s32(msg, MT76_TM_RX_ATTR_FREQ_OFFSET, phy->test.last_freq_offset)) 735 return -ENOMEM; 736 737 rssi = nla_nest_start(msg, MT76_TM_RX_ATTR_RCPI); 738 if (!rssi) 739 return -ENOMEM; 740 741 for (i = 0; i < ARRAY_SIZE(phy->test.last_rcpi); i++) 742 if (nla_put_u8(msg, i, phy->test.last_rcpi[i])) 743 return -ENOMEM; 744 745 nla_nest_end(msg, rssi); 746 747 rssi = nla_nest_start(msg, MT76_TM_RX_ATTR_IB_RSSI); 748 if (!rssi) 749 return -ENOMEM; 750 751 for (i = 0; i < ARRAY_SIZE(phy->test.last_ib_rssi); i++) 752 if (nla_put_s8(msg, i, phy->test.last_ib_rssi[i])) 753 return -ENOMEM; 754 755 nla_nest_end(msg, rssi); 756 757 rssi = nla_nest_start(msg, MT76_TM_RX_ATTR_WB_RSSI); 758 if (!rssi) 759 return -ENOMEM; 760 761 for (i = 0; i < ARRAY_SIZE(phy->test.last_wb_rssi); i++) 762 if (nla_put_s8(msg, i, phy->test.last_wb_rssi[i])) 763 return -ENOMEM; 764 765 nla_nest_end(msg, rssi); 766 767 if (nla_put_u8(msg, MT76_TM_RX_ATTR_SNR, phy->test.last_snr)) 768 return -ENOMEM; 769 770 nla_nest_end(msg, rx); 771 772 fcs_err = mt76_get_field(dev, MT_MIB_SDR3(ext_phy), 773 MT_MIB_SDR3_FCS_ERR_MASK); 774 q = ext_phy ? MT_RXQ_EXT : MT_RXQ_MAIN; 775 mphy->test.rx_stats.packets[q] += fcs_err; 776 mphy->test.rx_stats.fcs_error[q] += fcs_err; 777 778 return 0; 779 } 780 781 const struct mt76_testmode_ops mt7915_testmode_ops = { 782 .set_state = mt7915_tm_set_state, 783 .set_params = mt7915_tm_set_params, 784 .dump_stats = mt7915_tm_dump_stats, 785 }; 786