1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2022 MediaTek Inc. */ 3 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/platform_device.h> 7 #include <linux/pinctrl/consumer.h> 8 #include <linux/of.h> 9 #include <linux/of_reserved_mem.h> 10 #include <linux/of_gpio.h> 11 #include <linux/iopoll.h> 12 #include <linux/reset.h> 13 #include <linux/of_net.h> 14 #include <linux/clk.h> 15 16 #include "mt7915.h" 17 18 #define MT7981_CON_INFRA_VERSION 0x02090000 19 #define MT7986_CON_INFRA_VERSION 0x02070000 20 21 /* INFRACFG */ 22 #define MT_INFRACFG_CONN2AP_SLPPROT 0x0d0 23 #define MT_INFRACFG_AP2CONN_SLPPROT 0x0d4 24 25 #define MT_INFRACFG_RX_EN_MASK BIT(16) 26 #define MT_INFRACFG_TX_RDY_MASK BIT(4) 27 #define MT_INFRACFG_TX_EN_MASK BIT(0) 28 29 /* TOP POS */ 30 #define MT_TOP_POS_FAST_CTRL 0x114 31 #define MT_TOP_POS_FAST_EN_MASK BIT(3) 32 33 #define MT_TOP_POS_SKU 0x21c 34 #define MT_TOP_POS_SKU_MASK GENMASK(31, 28) 35 #define MT_TOP_POS_SKU_ADIE_DBDC_MASK BIT(2) 36 37 enum { 38 ADIE_SB, 39 ADIE_DBDC 40 }; 41 42 static int 43 mt76_wmac_spi_read(struct mt7915_dev *dev, u8 adie, u32 addr, u32 *val) 44 { 45 int ret; 46 u32 cur; 47 48 ret = read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT), 49 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 50 dev, MT_TOP_SPI_BUSY_CR(adie)); 51 if (ret) 52 return ret; 53 54 mt76_wr(dev, MT_TOP_SPI_ADDR_CR(adie), 55 MT_TOP_SPI_READ_ADDR_FORMAT | addr); 56 mt76_wr(dev, MT_TOP_SPI_WRITE_DATA_CR(adie), 0); 57 58 ret = read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT), 59 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 60 dev, MT_TOP_SPI_BUSY_CR(adie)); 61 if (ret) 62 return ret; 63 64 *val = mt76_rr(dev, MT_TOP_SPI_READ_DATA_CR(adie)); 65 66 return 0; 67 } 68 69 static int 70 mt76_wmac_spi_write(struct mt7915_dev *dev, u8 adie, u32 addr, u32 val) 71 { 72 int ret; 73 u32 cur; 74 75 ret = read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT), 76 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 77 dev, MT_TOP_SPI_BUSY_CR(adie)); 78 if (ret) 79 return ret; 80 81 mt76_wr(dev, MT_TOP_SPI_ADDR_CR(adie), 82 MT_TOP_SPI_WRITE_ADDR_FORMAT | addr); 83 mt76_wr(dev, MT_TOP_SPI_WRITE_DATA_CR(adie), val); 84 85 return read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT), 86 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 87 dev, MT_TOP_SPI_BUSY_CR(adie)); 88 } 89 90 static int 91 mt76_wmac_spi_rmw(struct mt7915_dev *dev, u8 adie, 92 u32 addr, u32 mask, u32 val) 93 { 94 u32 cur, ret; 95 96 ret = mt76_wmac_spi_read(dev, adie, addr, &cur); 97 if (ret) 98 return ret; 99 100 cur &= ~mask; 101 cur |= val; 102 103 return mt76_wmac_spi_write(dev, adie, addr, cur); 104 } 105 106 static int 107 mt7986_wmac_adie_efuse_read(struct mt7915_dev *dev, u8 adie, 108 u32 addr, u32 *data) 109 { 110 int ret, temp; 111 u32 val, mask; 112 113 ret = mt76_wmac_spi_write(dev, adie, MT_ADIE_EFUSE_CFG, 114 MT_ADIE_EFUSE_CTRL_MASK); 115 if (ret) 116 return ret; 117 118 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_EFUSE2_CTRL, BIT(30), 0x0); 119 if (ret) 120 return ret; 121 122 mask = (MT_ADIE_EFUSE_MODE_MASK | MT_ADIE_EFUSE_ADDR_MASK | 123 MT_ADIE_EFUSE_KICK_MASK); 124 val = FIELD_PREP(MT_ADIE_EFUSE_MODE_MASK, 0) | 125 FIELD_PREP(MT_ADIE_EFUSE_ADDR_MASK, addr) | 126 FIELD_PREP(MT_ADIE_EFUSE_KICK_MASK, 1); 127 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_EFUSE2_CTRL, mask, val); 128 if (ret) 129 return ret; 130 131 ret = read_poll_timeout(mt76_wmac_spi_read, temp, 132 !temp && !FIELD_GET(MT_ADIE_EFUSE_KICK_MASK, val), 133 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 134 dev, adie, MT_ADIE_EFUSE2_CTRL, &val); 135 if (ret) 136 return ret; 137 138 ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_EFUSE2_CTRL, &val); 139 if (ret) 140 return ret; 141 142 if (FIELD_GET(MT_ADIE_EFUSE_VALID_MASK, val) == 1) 143 ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_EFUSE_RDATA0, 144 data); 145 146 return ret; 147 } 148 149 static inline void mt76_wmac_spi_lock(struct mt7915_dev *dev) 150 { 151 u32 cur; 152 153 read_poll_timeout(mt76_rr, cur, 154 FIELD_GET(MT_SEMA_RFSPI_STATUS_MASK, cur), 155 1000, 1000 * MSEC_PER_SEC, false, dev, 156 MT_SEMA_RFSPI_STATUS); 157 } 158 159 static inline void mt76_wmac_spi_unlock(struct mt7915_dev *dev) 160 { 161 mt76_wr(dev, MT_SEMA_RFSPI_RELEASE, 1); 162 } 163 164 static u32 mt76_wmac_rmw(void __iomem *base, u32 offset, u32 mask, u32 val) 165 { 166 val |= readl(base + offset) & ~mask; 167 writel(val, base + offset); 168 169 return val; 170 } 171 172 static u8 mt798x_wmac_check_adie_type(struct mt7915_dev *dev) 173 { 174 u32 val; 175 176 /* Only DBDC A-die is used with MT7981 */ 177 if (is_mt7981(&dev->mt76)) 178 return ADIE_DBDC; 179 180 val = readl(dev->sku + MT_TOP_POS_SKU); 181 182 return FIELD_GET(MT_TOP_POS_SKU_ADIE_DBDC_MASK, val); 183 } 184 185 static int mt7986_wmac_consys_reset(struct mt7915_dev *dev, bool enable) 186 { 187 if (!enable) 188 return reset_control_assert(dev->rstc); 189 190 mt76_wmac_rmw(dev->sku, MT_TOP_POS_FAST_CTRL, 191 MT_TOP_POS_FAST_EN_MASK, 192 FIELD_PREP(MT_TOP_POS_FAST_EN_MASK, 0x1)); 193 194 return reset_control_deassert(dev->rstc); 195 } 196 197 static int mt7986_wmac_gpio_setup(struct mt7915_dev *dev) 198 { 199 struct pinctrl_state *state; 200 struct pinctrl *pinctrl; 201 int ret; 202 u8 type; 203 204 type = mt798x_wmac_check_adie_type(dev); 205 pinctrl = devm_pinctrl_get(dev->mt76.dev); 206 if (IS_ERR(pinctrl)) 207 return PTR_ERR(pinctrl); 208 209 switch (type) { 210 case ADIE_SB: 211 state = pinctrl_lookup_state(pinctrl, "default"); 212 if (IS_ERR_OR_NULL(state)) 213 return -EINVAL; 214 break; 215 case ADIE_DBDC: 216 state = pinctrl_lookup_state(pinctrl, "dbdc"); 217 if (IS_ERR_OR_NULL(state)) 218 return -EINVAL; 219 break; 220 default: 221 return -EINVAL; 222 } 223 224 ret = pinctrl_select_state(pinctrl, state); 225 if (ret) 226 return ret; 227 228 usleep_range(500, 1000); 229 230 return 0; 231 } 232 233 static int mt7986_wmac_consys_lockup(struct mt7915_dev *dev, bool enable) 234 { 235 int ret; 236 u32 cur; 237 238 mt76_wmac_rmw(dev->dcm, MT_INFRACFG_AP2CONN_SLPPROT, 239 MT_INFRACFG_RX_EN_MASK, 240 FIELD_PREP(MT_INFRACFG_RX_EN_MASK, enable)); 241 ret = read_poll_timeout(readl, cur, !(cur & MT_INFRACFG_RX_EN_MASK), 242 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 243 dev->dcm + MT_INFRACFG_AP2CONN_SLPPROT); 244 if (ret) 245 return ret; 246 247 mt76_wmac_rmw(dev->dcm, MT_INFRACFG_AP2CONN_SLPPROT, 248 MT_INFRACFG_TX_EN_MASK, 249 FIELD_PREP(MT_INFRACFG_TX_EN_MASK, enable)); 250 ret = read_poll_timeout(readl, cur, !(cur & MT_INFRACFG_TX_RDY_MASK), 251 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 252 dev->dcm + MT_INFRACFG_AP2CONN_SLPPROT); 253 if (ret) 254 return ret; 255 256 mt76_wmac_rmw(dev->dcm, MT_INFRACFG_CONN2AP_SLPPROT, 257 MT_INFRACFG_RX_EN_MASK, 258 FIELD_PREP(MT_INFRACFG_RX_EN_MASK, enable)); 259 mt76_wmac_rmw(dev->dcm, MT_INFRACFG_CONN2AP_SLPPROT, 260 MT_INFRACFG_TX_EN_MASK, 261 FIELD_PREP(MT_INFRACFG_TX_EN_MASK, enable)); 262 263 return 0; 264 } 265 266 static int mt798x_wmac_coninfra_check(struct mt7915_dev *dev) 267 { 268 u32 cur; 269 u32 con_infra_version; 270 271 if (is_mt7981(&dev->mt76)) { 272 con_infra_version = MT7981_CON_INFRA_VERSION; 273 } else if (is_mt7986(&dev->mt76)) { 274 con_infra_version = MT7986_CON_INFRA_VERSION; 275 } else { 276 WARN_ON(1); 277 return -EINVAL; 278 } 279 280 return read_poll_timeout(mt76_rr, cur, (cur == con_infra_version), 281 USEC_PER_MSEC, 50 * USEC_PER_MSEC, 282 false, dev, MT_CONN_INFRA_BASE); 283 } 284 285 static int mt798x_wmac_coninfra_setup(struct mt7915_dev *dev) 286 { 287 struct device *pdev = dev->mt76.dev; 288 struct reserved_mem *rmem; 289 struct device_node *np; 290 u32 val; 291 292 np = of_parse_phandle(pdev->of_node, "memory-region", 0); 293 if (!np) 294 return -EINVAL; 295 296 rmem = of_reserved_mem_lookup(np); 297 of_node_put(np); 298 if (!rmem) 299 return -EINVAL; 300 301 val = (rmem->base >> 16) & MT_TOP_MCU_EMI_BASE_MASK; 302 303 if (is_mt7986(&dev->mt76)) { 304 /* Set conninfra subsys PLL check */ 305 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS, 306 MT_INFRA_CKGEN_BUS_RDY_SEL_MASK, 0x1); 307 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS, 308 MT_INFRA_CKGEN_BUS_RDY_SEL_MASK, 0x1); 309 } 310 311 mt76_rmw_field(dev, MT_TOP_MCU_EMI_BASE, 312 MT_TOP_MCU_EMI_BASE_MASK, val); 313 314 if (is_mt7981(&dev->mt76)) { 315 mt76_rmw_field(dev, MT_TOP_WF_AP_PERI_BASE, 316 MT_TOP_WF_AP_PERI_BASE_MASK, 0x300d0000 >> 16); 317 318 mt76_rmw_field(dev, MT_TOP_EFUSE_BASE, 319 MT_TOP_EFUSE_BASE_MASK, 0x11f20000 >> 16); 320 } 321 322 mt76_wr(dev, MT_INFRA_BUS_EMI_START, rmem->base); 323 mt76_wr(dev, MT_INFRA_BUS_EMI_END, rmem->size); 324 325 mt76_rr(dev, MT_CONN_INFRA_EFUSE); 326 327 /* Set conninfra sysram */ 328 mt76_wr(dev, MT_TOP_RGU_SYSRAM_PDN, 0); 329 mt76_wr(dev, MT_TOP_RGU_SYSRAM_SLP, 1); 330 331 return 0; 332 } 333 334 static int mt798x_wmac_sku_setup(struct mt7915_dev *dev, u32 *adie_type) 335 { 336 int ret; 337 u32 adie_main = 0, adie_ext = 0; 338 339 mt76_rmw_field(dev, MT_CONN_INFRA_ADIE_RESET, 340 MT_CONN_INFRA_ADIE1_RESET_MASK, 0x1); 341 342 if (is_mt7986(&dev->mt76)) { 343 mt76_rmw_field(dev, MT_CONN_INFRA_ADIE_RESET, 344 MT_CONN_INFRA_ADIE2_RESET_MASK, 0x1); 345 } 346 347 mt76_wmac_spi_lock(dev); 348 349 ret = mt76_wmac_spi_read(dev, 0, MT_ADIE_CHIP_ID, &adie_main); 350 if (ret) 351 goto out; 352 353 if (is_mt7986(&dev->mt76)) { 354 ret = mt76_wmac_spi_read(dev, 1, MT_ADIE_CHIP_ID, &adie_ext); 355 if (ret) 356 goto out; 357 } 358 359 *adie_type = FIELD_GET(MT_ADIE_CHIP_ID_MASK, adie_main) | 360 (MT_ADIE_CHIP_ID_MASK & adie_ext); 361 362 out: 363 mt76_wmac_spi_unlock(dev); 364 365 return 0; 366 } 367 368 static inline u16 mt7986_adie_idx(u8 adie, u32 adie_type) 369 { 370 if (adie == 0) 371 return u32_get_bits(adie_type, MT_ADIE_IDX0); 372 else 373 return u32_get_bits(adie_type, MT_ADIE_IDX1); 374 } 375 376 static inline bool is_7975(struct mt7915_dev *dev, u8 adie, u32 adie_type) 377 { 378 return mt7986_adie_idx(adie, adie_type) == 0x7975; 379 } 380 381 static inline bool is_7976(struct mt7915_dev *dev, u8 adie, u32 adie_type) 382 { 383 return mt7986_adie_idx(adie, adie_type) == 0x7976; 384 } 385 386 static int mt7986_wmac_adie_thermal_cal(struct mt7915_dev *dev, u8 adie) 387 { 388 int ret; 389 u32 data, val; 390 391 ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_THADC_ANALOG, 392 &data); 393 if (ret || FIELD_GET(MT_ADIE_ANA_EN_MASK, data)) { 394 val = FIELD_GET(MT_ADIE_VRPI_SEL_EFUSE_MASK, data); 395 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_RG_TOP_THADC_BG, 396 MT_ADIE_VRPI_SEL_CR_MASK, 397 FIELD_PREP(MT_ADIE_VRPI_SEL_CR_MASK, val)); 398 if (ret) 399 return ret; 400 401 val = FIELD_GET(MT_ADIE_PGA_GAIN_EFUSE_MASK, data); 402 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_RG_TOP_THADC, 403 MT_ADIE_PGA_GAIN_MASK, 404 FIELD_PREP(MT_ADIE_PGA_GAIN_MASK, val)); 405 if (ret) 406 return ret; 407 } 408 409 ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_THADC_SLOP, 410 &data); 411 if (ret || FIELD_GET(MT_ADIE_ANA_EN_MASK, data)) { 412 val = FIELD_GET(MT_ADIE_LDO_CTRL_EFUSE_MASK, data); 413 414 return mt76_wmac_spi_rmw(dev, adie, MT_ADIE_RG_TOP_THADC, 415 MT_ADIE_LDO_CTRL_MASK, 416 FIELD_PREP(MT_ADIE_LDO_CTRL_MASK, val)); 417 } 418 419 return 0; 420 } 421 422 static int 423 mt7986_read_efuse_xo_trim_7976(struct mt7915_dev *dev, u8 adie, 424 bool is_40m, int *result) 425 { 426 int ret; 427 u32 data, addr; 428 429 addr = is_40m ? MT_ADIE_XTAL_AXM_40M_OSC : MT_ADIE_XTAL_AXM_80M_OSC; 430 ret = mt7986_wmac_adie_efuse_read(dev, adie, addr, &data); 431 if (ret) 432 return ret; 433 434 if (!FIELD_GET(MT_ADIE_XO_TRIM_EN_MASK, data)) { 435 *result = 64; 436 } else { 437 *result = FIELD_GET(MT_ADIE_TRIM_MASK, data); 438 addr = is_40m ? MT_ADIE_XTAL_TRIM1_40M_OSC : 439 MT_ADIE_XTAL_TRIM1_80M_OSC; 440 ret = mt7986_wmac_adie_efuse_read(dev, adie, addr, &data); 441 if (ret) 442 return ret; 443 444 if (FIELD_GET(MT_ADIE_XO_TRIM_EN_MASK, data) && 445 FIELD_GET(MT_ADIE_XTAL_DECREASE_MASK, data)) 446 *result -= FIELD_GET(MT_ADIE_EFUSE_TRIM_MASK, data); 447 else if (FIELD_GET(MT_ADIE_XO_TRIM_EN_MASK, data)) 448 *result += FIELD_GET(MT_ADIE_EFUSE_TRIM_MASK, data); 449 450 *result = max(0, min(127, *result)); 451 } 452 453 return 0; 454 } 455 456 static int mt7986_wmac_adie_xtal_trim_7976(struct mt7915_dev *dev, u8 adie) 457 { 458 int ret, trim_80m, trim_40m; 459 u32 data, val, mode; 460 461 ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_XO_TRIM_FLOW, 462 &data); 463 if (ret || !FIELD_GET(BIT(1), data)) 464 return 0; 465 466 ret = mt7986_read_efuse_xo_trim_7976(dev, adie, false, &trim_80m); 467 if (ret) 468 return ret; 469 470 ret = mt7986_read_efuse_xo_trim_7976(dev, adie, true, &trim_40m); 471 if (ret) 472 return ret; 473 474 ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_RG_STRAP_PIN_IN, &val); 475 if (ret) 476 return ret; 477 478 mode = FIELD_PREP(GENMASK(6, 4), val); 479 if (!mode || mode == 0x2) { 480 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_XTAL_C1, 481 GENMASK(31, 24), 482 FIELD_PREP(GENMASK(31, 24), trim_80m)); 483 if (ret) 484 return ret; 485 486 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_XTAL_C2, 487 GENMASK(31, 24), 488 FIELD_PREP(GENMASK(31, 24), trim_80m)); 489 } else if (mode == 0x3 || mode == 0x4 || mode == 0x6) { 490 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_XTAL_C1, 491 GENMASK(23, 16), 492 FIELD_PREP(GENMASK(23, 16), trim_40m)); 493 if (ret) 494 return ret; 495 496 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_XTAL_C2, 497 GENMASK(23, 16), 498 FIELD_PREP(GENMASK(23, 16), trim_40m)); 499 } 500 501 return ret; 502 } 503 504 static int mt798x_wmac_adie_patch_7976(struct mt7915_dev *dev, u8 adie) 505 { 506 u32 id, version, rg_xo_01, rg_xo_03; 507 int ret; 508 509 ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_CHIP_ID, &id); 510 if (ret) 511 return ret; 512 513 version = FIELD_GET(MT_ADIE_VERSION_MASK, id); 514 515 ret = mt76_wmac_spi_write(dev, adie, MT_ADIE_RG_TOP_THADC, 0x4a563b00); 516 if (ret) 517 return ret; 518 519 if (version == 0x8a00 || version == 0x8a10 || 520 version == 0x8b00 || version == 0x8c10) { 521 rg_xo_01 = 0x1d59080f; 522 rg_xo_03 = 0x34c00fe0; 523 } else { 524 if (is_mt7981(&dev->mt76)) { 525 rg_xo_01 = 0x1959c80f; 526 } else if (is_mt7986(&dev->mt76)) { 527 rg_xo_01 = 0x1959f80f; 528 } else { 529 WARN_ON(1); 530 return -EINVAL; 531 } 532 rg_xo_03 = 0x34d00fe0; 533 } 534 535 ret = mt76_wmac_spi_write(dev, adie, MT_ADIE_RG_XO_01, rg_xo_01); 536 if (ret) 537 return ret; 538 539 return mt76_wmac_spi_write(dev, adie, MT_ADIE_RG_XO_03, rg_xo_03); 540 } 541 542 static int 543 mt7986_read_efuse_xo_trim_7975(struct mt7915_dev *dev, u8 adie, 544 u32 addr, u32 *result) 545 { 546 int ret; 547 u32 data; 548 549 ret = mt7986_wmac_adie_efuse_read(dev, adie, addr, &data); 550 if (ret) 551 return ret; 552 553 if ((data & MT_ADIE_XO_TRIM_EN_MASK)) { 554 if ((data & MT_ADIE_XTAL_DECREASE_MASK)) 555 *result -= (data & MT_ADIE_EFUSE_TRIM_MASK); 556 else 557 *result += (data & MT_ADIE_EFUSE_TRIM_MASK); 558 559 *result = (*result & MT_ADIE_TRIM_MASK); 560 } 561 562 return 0; 563 } 564 565 static int mt7986_wmac_adie_xtal_trim_7975(struct mt7915_dev *dev, u8 adie) 566 { 567 int ret; 568 u32 data, result = 0, value; 569 570 ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_7975_XTAL_EN, 571 &data); 572 if (ret || !(data & BIT(1))) 573 return 0; 574 575 ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_7975_XTAL_CAL, 576 &data); 577 if (ret) 578 return ret; 579 580 if (data & MT_ADIE_XO_TRIM_EN_MASK) 581 result = (data & MT_ADIE_TRIM_MASK); 582 583 ret = mt7986_read_efuse_xo_trim_7975(dev, adie, MT_ADIE_7975_XO_TRIM2, 584 &result); 585 if (ret) 586 return ret; 587 588 ret = mt7986_read_efuse_xo_trim_7975(dev, adie, MT_ADIE_7975_XO_TRIM3, 589 &result); 590 if (ret) 591 return ret; 592 593 ret = mt7986_read_efuse_xo_trim_7975(dev, adie, MT_ADIE_7975_XO_TRIM4, 594 &result); 595 if (ret) 596 return ret; 597 598 /* Update trim value to C1 and C2*/ 599 value = FIELD_GET(MT_ADIE_7975_XO_CTRL2_C1_MASK, result) | 600 FIELD_GET(MT_ADIE_7975_XO_CTRL2_C2_MASK, result); 601 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_7975_XO_CTRL2, 602 MT_ADIE_7975_XO_CTRL2_MASK, value); 603 if (ret) 604 return ret; 605 606 ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_7975_XTAL, &value); 607 if (ret) 608 return ret; 609 610 if (value & MT_ADIE_7975_XTAL_EN_MASK) { 611 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_7975_XO_2, 612 MT_ADIE_7975_XO_2_FIX_EN, 0x0); 613 if (ret) 614 return ret; 615 } 616 617 return mt76_wmac_spi_rmw(dev, adie, MT_ADIE_7975_XO_CTRL6, 618 MT_ADIE_7975_XO_CTRL6_MASK, 0x1); 619 } 620 621 static int mt7986_wmac_adie_patch_7975(struct mt7915_dev *dev, u8 adie) 622 { 623 int ret; 624 625 /* disable CAL LDO and fine tune RFDIG LDO */ 626 ret = mt76_wmac_spi_write(dev, adie, 0x348, 0x00000002); 627 if (ret) 628 return ret; 629 630 ret = mt76_wmac_spi_write(dev, adie, 0x378, 0x00000002); 631 if (ret) 632 return ret; 633 634 ret = mt76_wmac_spi_write(dev, adie, 0x3a8, 0x00000002); 635 if (ret) 636 return ret; 637 638 ret = mt76_wmac_spi_write(dev, adie, 0x3d8, 0x00000002); 639 if (ret) 640 return ret; 641 642 /* set CKA driving and filter */ 643 ret = mt76_wmac_spi_write(dev, adie, 0xa1c, 0x30000aaa); 644 if (ret) 645 return ret; 646 647 /* set CKB LDO to 1.4V */ 648 ret = mt76_wmac_spi_write(dev, adie, 0xa84, 0x8470008a); 649 if (ret) 650 return ret; 651 652 /* turn on SX0 LTBUF */ 653 if (is_mt7981(&dev->mt76)) { 654 ret = mt76_wmac_spi_write(dev, adie, 0x074, 0x00000007); 655 } else if (is_mt7986(&dev->mt76)) { 656 ret = mt76_wmac_spi_write(dev, adie, 0x074, 0x00000002); 657 } else { 658 WARN_ON(1); 659 return -EINVAL; 660 } 661 662 if (ret) 663 return ret; 664 665 /* CK_BUF_SW_EN = 1 (all buf in manual mode.) */ 666 ret = mt76_wmac_spi_write(dev, adie, 0xaa4, 0x01001fc0); 667 if (ret) 668 return ret; 669 670 /* BT mode/WF normal mode 00000005 */ 671 ret = mt76_wmac_spi_write(dev, adie, 0x070, 0x00000005); 672 if (ret) 673 return ret; 674 675 /* BG thermal sensor offset update */ 676 ret = mt76_wmac_spi_write(dev, adie, 0x344, 0x00000088); 677 if (ret) 678 return ret; 679 680 ret = mt76_wmac_spi_write(dev, adie, 0x374, 0x00000088); 681 if (ret) 682 return ret; 683 684 ret = mt76_wmac_spi_write(dev, adie, 0x3a4, 0x00000088); 685 if (ret) 686 return ret; 687 688 ret = mt76_wmac_spi_write(dev, adie, 0x3d4, 0x00000088); 689 if (ret) 690 return ret; 691 692 /* set WCON VDD IPTAT to "0000" */ 693 ret = mt76_wmac_spi_write(dev, adie, 0xa80, 0x44d07000); 694 if (ret) 695 return ret; 696 697 /* change back LTBUF SX3 drving to default value */ 698 ret = mt76_wmac_spi_write(dev, adie, 0xa88, 0x3900aaaa); 699 if (ret) 700 return ret; 701 702 /* SM input cap off */ 703 ret = mt76_wmac_spi_write(dev, adie, 0x2c4, 0x00000000); 704 if (ret) 705 return ret; 706 707 /* set CKB driving and filter */ 708 if (is_mt7986(&dev->mt76)) 709 return mt76_wmac_spi_write(dev, adie, 0x2c8, 0x00000072); 710 711 return ret; 712 } 713 714 static int mt7986_wmac_adie_cfg(struct mt7915_dev *dev, u8 adie, u32 adie_type) 715 { 716 int ret; 717 718 mt76_wmac_spi_lock(dev); 719 ret = mt76_wmac_spi_write(dev, adie, MT_ADIE_CLK_EN, ~0); 720 if (ret) 721 goto out; 722 723 if (is_7975(dev, adie, adie_type)) { 724 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_7975_COCLK, 725 BIT(1), 0x1); 726 if (ret) 727 goto out; 728 729 ret = mt7986_wmac_adie_thermal_cal(dev, adie); 730 if (ret) 731 goto out; 732 733 ret = mt7986_wmac_adie_xtal_trim_7975(dev, adie); 734 if (ret) 735 goto out; 736 737 ret = mt7986_wmac_adie_patch_7975(dev, adie); 738 } else if (is_7976(dev, adie, adie_type)) { 739 if (mt798x_wmac_check_adie_type(dev) == ADIE_DBDC) { 740 ret = mt76_wmac_spi_write(dev, adie, 741 MT_ADIE_WRI_CK_SEL, 0x1c); 742 if (ret) 743 goto out; 744 } 745 746 ret = mt7986_wmac_adie_thermal_cal(dev, adie); 747 if (ret) 748 goto out; 749 750 ret = mt7986_wmac_adie_xtal_trim_7976(dev, adie); 751 if (ret) 752 goto out; 753 754 ret = mt798x_wmac_adie_patch_7976(dev, adie); 755 } 756 out: 757 mt76_wmac_spi_unlock(dev); 758 759 return ret; 760 } 761 762 static int 763 mt7986_wmac_afe_cal(struct mt7915_dev *dev, u8 adie, bool dbdc, u32 adie_type) 764 { 765 int ret; 766 u8 idx; 767 u32 txcal; 768 769 mt76_wmac_spi_lock(dev); 770 if (is_7975(dev, adie, adie_type)) 771 ret = mt76_wmac_spi_write(dev, adie, 772 MT_AFE_RG_ENCAL_WBTAC_IF_SW, 773 0x80000000); 774 else 775 ret = mt76_wmac_spi_write(dev, adie, 776 MT_AFE_RG_ENCAL_WBTAC_IF_SW, 777 0x88888005); 778 if (ret) 779 goto out; 780 781 idx = dbdc ? ADIE_DBDC : adie; 782 783 mt76_rmw_field(dev, MT_AFE_DIG_EN_01(idx), 784 MT_AFE_RG_WBG_EN_RCK_MASK, 0x1); 785 usleep_range(60, 100); 786 787 mt76_rmw(dev, MT_AFE_DIG_EN_01(idx), 788 MT_AFE_RG_WBG_EN_RCK_MASK, 0x0); 789 790 mt76_rmw_field(dev, MT_AFE_DIG_EN_03(idx), 791 MT_AFE_RG_WBG_EN_BPLL_UP_MASK, 0x1); 792 usleep_range(30, 100); 793 794 mt76_rmw_field(dev, MT_AFE_DIG_EN_03(idx), 795 MT_AFE_RG_WBG_EN_WPLL_UP_MASK, 0x1); 796 usleep_range(60, 100); 797 798 txcal = (MT_AFE_RG_WBG_EN_TXCAL_BT | 799 MT_AFE_RG_WBG_EN_TXCAL_WF0 | 800 MT_AFE_RG_WBG_EN_TXCAL_WF1 | 801 MT_AFE_RG_WBG_EN_TXCAL_WF2 | 802 MT_AFE_RG_WBG_EN_TXCAL_WF3); 803 if (is_mt7981(&dev->mt76)) 804 txcal |= MT_AFE_RG_WBG_EN_TXCAL_WF4; 805 806 mt76_set(dev, MT_AFE_DIG_EN_01(idx), txcal); 807 usleep_range(800, 1000); 808 809 mt76_clear(dev, MT_AFE_DIG_EN_01(idx), txcal); 810 mt76_rmw(dev, MT_AFE_DIG_EN_03(idx), 811 MT_AFE_RG_WBG_EN_PLL_UP_MASK, 0x0); 812 813 ret = mt76_wmac_spi_write(dev, adie, MT_AFE_RG_ENCAL_WBTAC_IF_SW, 814 0x5); 815 816 out: 817 mt76_wmac_spi_unlock(dev); 818 819 return ret; 820 } 821 822 static void mt7986_wmac_subsys_pll_initial(struct mt7915_dev *dev, u8 band) 823 { 824 mt76_rmw(dev, MT_AFE_PLL_STB_TIME(band), 825 MT_AFE_PLL_STB_TIME_MASK, MT_AFE_PLL_STB_TIME_VAL); 826 827 mt76_rmw(dev, MT_AFE_DIG_EN_02(band), 828 MT_AFE_PLL_CFG_MASK, MT_AFE_PLL_CFG_VAL); 829 830 mt76_rmw(dev, MT_AFE_DIG_TOP_01(band), 831 MT_AFE_DIG_TOP_01_MASK, MT_AFE_DIG_TOP_01_VAL); 832 } 833 834 static void mt7986_wmac_subsys_setting(struct mt7915_dev *dev) 835 { 836 /* Subsys pll init */ 837 mt7986_wmac_subsys_pll_initial(dev, 0); 838 mt7986_wmac_subsys_pll_initial(dev, 1); 839 840 /* Set legacy OSC control stable time*/ 841 mt76_rmw(dev, MT_CONN_INFRA_OSC_RC_EN, 842 MT_CONN_INFRA_OSC_RC_EN_MASK, 0x0); 843 mt76_rmw(dev, MT_CONN_INFRA_OSC_CTRL, 844 MT_CONN_INFRA_OSC_STB_TIME_MASK, 0x80706); 845 846 /* prevent subsys from power on/of in a short time interval */ 847 mt76_rmw(dev, MT_TOP_WFSYS_PWR, 848 MT_TOP_PWR_ACK_MASK | MT_TOP_PWR_KEY_MASK, 849 MT_TOP_PWR_KEY); 850 } 851 852 static int mt7986_wmac_bus_timeout(struct mt7915_dev *dev) 853 { 854 mt76_rmw_field(dev, MT_INFRA_BUS_OFF_TIMEOUT, 855 MT_INFRA_BUS_TIMEOUT_LIMIT_MASK, 0x2); 856 857 mt76_rmw_field(dev, MT_INFRA_BUS_OFF_TIMEOUT, 858 MT_INFRA_BUS_TIMEOUT_EN_MASK, 0xf); 859 860 mt76_rmw_field(dev, MT_INFRA_BUS_ON_TIMEOUT, 861 MT_INFRA_BUS_TIMEOUT_LIMIT_MASK, 0xc); 862 863 mt76_rmw_field(dev, MT_INFRA_BUS_ON_TIMEOUT, 864 MT_INFRA_BUS_TIMEOUT_EN_MASK, 0xf); 865 866 return mt798x_wmac_coninfra_check(dev); 867 } 868 869 static void mt7986_wmac_clock_enable(struct mt7915_dev *dev, u32 adie_type) 870 { 871 u32 cur; 872 873 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS_WPLL_DIV_1, 874 MT_INFRA_CKGEN_DIV_SEL_MASK, 0x1); 875 876 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS_WPLL_DIV_2, 877 MT_INFRA_CKGEN_DIV_SEL_MASK, 0x1); 878 879 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS_WPLL_DIV_1, 880 MT_INFRA_CKGEN_DIV_EN_MASK, 0x1); 881 882 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS_WPLL_DIV_2, 883 MT_INFRA_CKGEN_DIV_EN_MASK, 0x1); 884 885 mt76_rmw_field(dev, MT_INFRA_CKGEN_RFSPI_WPLL_DIV, 886 MT_INFRA_CKGEN_DIV_SEL_MASK, 0x8); 887 888 mt76_rmw_field(dev, MT_INFRA_CKGEN_RFSPI_WPLL_DIV, 889 MT_INFRA_CKGEN_DIV_EN_MASK, 0x1); 890 891 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS, 892 MT_INFRA_CKGEN_BUS_CLK_SEL_MASK, 0x0); 893 894 mt76_rmw_field(dev, MT_CONN_INFRA_HW_CTRL, 895 MT_CONN_INFRA_HW_CTRL_MASK, 0x1); 896 897 mt76_rmw(dev, MT_TOP_CONN_INFRA_WAKEUP, 898 MT_TOP_CONN_INFRA_WAKEUP_MASK, 0x1); 899 900 usleep_range(900, 1000); 901 902 mt76_wmac_spi_lock(dev); 903 if (is_7975(dev, 0, adie_type) || is_7976(dev, 0, adie_type)) { 904 mt76_rmw_field(dev, MT_ADIE_SLP_CTRL_CK0(0), 905 MT_SLP_CTRL_EN_MASK, 0x1); 906 907 read_poll_timeout(mt76_rr, cur, !(cur & MT_SLP_CTRL_BSY_MASK), 908 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 909 dev, MT_ADIE_SLP_CTRL_CK0(0)); 910 } 911 if (is_7975(dev, 1, adie_type) || is_7976(dev, 1, adie_type)) { 912 mt76_rmw_field(dev, MT_ADIE_SLP_CTRL_CK0(1), 913 MT_SLP_CTRL_EN_MASK, 0x1); 914 915 read_poll_timeout(mt76_rr, cur, !(cur & MT_SLP_CTRL_BSY_MASK), 916 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 917 dev, MT_ADIE_SLP_CTRL_CK0(0)); 918 } 919 mt76_wmac_spi_unlock(dev); 920 921 mt76_rmw(dev, MT_TOP_CONN_INFRA_WAKEUP, 922 MT_TOP_CONN_INFRA_WAKEUP_MASK, 0x0); 923 usleep_range(900, 1000); 924 } 925 926 static int mt7986_wmac_top_wfsys_wakeup(struct mt7915_dev *dev, bool enable) 927 { 928 mt76_rmw_field(dev, MT_TOP_WFSYS_WAKEUP, 929 MT_TOP_WFSYS_WAKEUP_MASK, enable); 930 931 usleep_range(900, 1000); 932 933 if (!enable) 934 return 0; 935 936 return mt798x_wmac_coninfra_check(dev); 937 } 938 939 static int mt7986_wmac_wm_enable(struct mt7915_dev *dev, bool enable) 940 { 941 u32 cur; 942 943 if (is_mt7986(&dev->mt76)) 944 mt76_wr(dev, MT_CONNINFRA_SKU_DEC_ADDR, 0); 945 946 mt76_rmw_field(dev, MT7986_TOP_WM_RESET, 947 MT7986_TOP_WM_RESET_MASK, enable); 948 if (!enable) 949 return 0; 950 951 return read_poll_timeout(mt76_rr, cur, (cur == 0x1d1e), 952 USEC_PER_MSEC, 5000 * USEC_PER_MSEC, false, 953 dev, MT_TOP_CFG_ON_ROM_IDX); 954 } 955 956 static int mt7986_wmac_wfsys_poweron(struct mt7915_dev *dev, bool enable) 957 { 958 u32 mask = MT_TOP_PWR_EN_MASK | MT_TOP_PWR_KEY_MASK; 959 u32 cur; 960 961 mt76_rmw(dev, MT_TOP_WFSYS_PWR, mask, 962 MT_TOP_PWR_KEY | FIELD_PREP(MT_TOP_PWR_EN_MASK, enable)); 963 964 return read_poll_timeout(mt76_rr, cur, 965 (FIELD_GET(MT_TOP_WFSYS_RESET_STATUS_MASK, cur) == enable), 966 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 967 dev, MT_TOP_WFSYS_RESET_STATUS); 968 } 969 970 static int mt7986_wmac_wfsys_setting(struct mt7915_dev *dev) 971 { 972 int ret; 973 u32 cur; 974 975 /* Turn off wfsys2conn bus sleep protect */ 976 mt76_rmw(dev, MT_CONN_INFRA_WF_SLP_PROT, 977 MT_CONN_INFRA_WF_SLP_PROT_MASK, 0x0); 978 979 ret = mt7986_wmac_wfsys_poweron(dev, true); 980 if (ret) 981 return ret; 982 983 /* Check bus sleep protect */ 984 985 ret = read_poll_timeout(mt76_rr, cur, 986 !(cur & MT_CONN_INFRA_CONN_WF_MASK), 987 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 988 dev, MT_CONN_INFRA_WF_SLP_PROT_RDY); 989 if (ret) 990 return ret; 991 992 ret = read_poll_timeout(mt76_rr, cur, !(cur & MT_SLP_WFDMA2CONN_MASK), 993 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 994 dev, MT_SLP_STATUS); 995 if (ret) 996 return ret; 997 998 return read_poll_timeout(mt76_rr, cur, (cur == 0x02060000), 999 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 1000 dev, MT_TOP_CFG_IP_VERSION_ADDR); 1001 } 1002 1003 static void mt7986_wmac_wfsys_set_timeout(struct mt7915_dev *dev) 1004 { 1005 u32 mask = MT_MCU_BUS_TIMEOUT_SET_MASK | 1006 MT_MCU_BUS_TIMEOUT_CG_EN_MASK | 1007 MT_MCU_BUS_TIMEOUT_EN_MASK; 1008 u32 val = FIELD_PREP(MT_MCU_BUS_TIMEOUT_SET_MASK, 1) | 1009 FIELD_PREP(MT_MCU_BUS_TIMEOUT_CG_EN_MASK, 1) | 1010 FIELD_PREP(MT_MCU_BUS_TIMEOUT_EN_MASK, 1); 1011 1012 mt76_rmw(dev, MT_MCU_BUS_TIMEOUT, mask, val); 1013 1014 mt76_wr(dev, MT_MCU_BUS_REMAP, 0x810f0000); 1015 1016 mask = MT_MCU_BUS_DBG_TIMEOUT_SET_MASK | 1017 MT_MCU_BUS_DBG_TIMEOUT_CK_EN_MASK | 1018 MT_MCU_BUS_DBG_TIMEOUT_EN_MASK; 1019 val = FIELD_PREP(MT_MCU_BUS_DBG_TIMEOUT_SET_MASK, 0x3aa) | 1020 FIELD_PREP(MT_MCU_BUS_DBG_TIMEOUT_CK_EN_MASK, 1) | 1021 FIELD_PREP(MT_MCU_BUS_DBG_TIMEOUT_EN_MASK, 1); 1022 1023 mt76_rmw(dev, MT_MCU_BUS_DBG_TIMEOUT, mask, val); 1024 } 1025 1026 static int mt7986_wmac_sku_update(struct mt7915_dev *dev, u32 adie_type) 1027 { 1028 u32 val; 1029 1030 if (is_7976(dev, 0, adie_type) && is_7976(dev, 1, adie_type)) 1031 val = 0xf; 1032 else if (is_7975(dev, 0, adie_type) && is_7975(dev, 1, adie_type)) 1033 val = 0xd; 1034 else if (is_7976(dev, 0, adie_type)) 1035 val = 0x7; 1036 else if (is_7975(dev, 1, adie_type)) 1037 val = 0x8; 1038 else if (is_7976(dev, 1, adie_type)) 1039 val = 0xa; 1040 else 1041 return -EINVAL; 1042 1043 mt76_wmac_rmw(dev->sku, MT_TOP_POS_SKU, MT_TOP_POS_SKU_MASK, 1044 FIELD_PREP(MT_TOP_POS_SKU_MASK, val)); 1045 1046 mt76_wr(dev, MT_CONNINFRA_SKU_DEC_ADDR, val); 1047 1048 return 0; 1049 } 1050 1051 static int 1052 mt7986_wmac_adie_setup(struct mt7915_dev *dev, u8 adie, u32 adie_type) 1053 { 1054 int ret; 1055 1056 if (!(is_7975(dev, adie, adie_type) || is_7976(dev, adie, adie_type))) 1057 return 0; 1058 1059 ret = mt7986_wmac_adie_cfg(dev, adie, adie_type); 1060 if (ret) 1061 return ret; 1062 1063 ret = mt7986_wmac_afe_cal(dev, adie, false, adie_type); 1064 if (ret) 1065 return ret; 1066 1067 if (!adie && (mt798x_wmac_check_adie_type(dev) == ADIE_DBDC)) 1068 ret = mt7986_wmac_afe_cal(dev, adie, true, adie_type); 1069 1070 return ret; 1071 } 1072 1073 static int mt7986_wmac_subsys_powerup(struct mt7915_dev *dev, u32 adie_type) 1074 { 1075 int ret; 1076 1077 mt7986_wmac_subsys_setting(dev); 1078 1079 ret = mt7986_wmac_bus_timeout(dev); 1080 if (ret) 1081 return ret; 1082 1083 mt7986_wmac_clock_enable(dev, adie_type); 1084 1085 return 0; 1086 } 1087 1088 static int mt7986_wmac_wfsys_powerup(struct mt7915_dev *dev) 1089 { 1090 int ret; 1091 1092 ret = mt7986_wmac_wm_enable(dev, false); 1093 if (ret) 1094 return ret; 1095 1096 ret = mt7986_wmac_wfsys_setting(dev); 1097 if (ret) 1098 return ret; 1099 1100 mt7986_wmac_wfsys_set_timeout(dev); 1101 1102 return mt7986_wmac_wm_enable(dev, true); 1103 } 1104 1105 int mt7986_wmac_enable(struct mt7915_dev *dev) 1106 { 1107 int ret; 1108 u32 adie_type; 1109 1110 ret = mt7986_wmac_consys_reset(dev, true); 1111 if (ret) 1112 return ret; 1113 1114 ret = mt7986_wmac_gpio_setup(dev); 1115 if (ret) 1116 return ret; 1117 1118 ret = mt7986_wmac_consys_lockup(dev, false); 1119 if (ret) 1120 return ret; 1121 1122 ret = mt798x_wmac_coninfra_check(dev); 1123 if (ret) 1124 return ret; 1125 1126 ret = mt798x_wmac_coninfra_setup(dev); 1127 if (ret) 1128 return ret; 1129 1130 ret = mt798x_wmac_sku_setup(dev, &adie_type); 1131 if (ret) 1132 return ret; 1133 1134 ret = mt7986_wmac_adie_setup(dev, 0, adie_type); 1135 if (ret) 1136 return ret; 1137 1138 /* mt7981 doesn't support a second a-die */ 1139 if (is_mt7986(&dev->mt76)) { 1140 ret = mt7986_wmac_adie_setup(dev, 1, adie_type); 1141 if (ret) 1142 return ret; 1143 } 1144 1145 ret = mt7986_wmac_subsys_powerup(dev, adie_type); 1146 if (ret) 1147 return ret; 1148 1149 ret = mt7986_wmac_top_wfsys_wakeup(dev, true); 1150 if (ret) 1151 return ret; 1152 1153 ret = mt7986_wmac_wfsys_powerup(dev); 1154 if (ret) 1155 return ret; 1156 1157 return mt7986_wmac_sku_update(dev, adie_type); 1158 } 1159 1160 void mt7986_wmac_disable(struct mt7915_dev *dev) 1161 { 1162 u32 cur; 1163 1164 mt7986_wmac_top_wfsys_wakeup(dev, true); 1165 1166 /* Turn on wfsys2conn bus sleep protect */ 1167 mt76_rmw_field(dev, MT_CONN_INFRA_WF_SLP_PROT, 1168 MT_CONN_INFRA_WF_SLP_PROT_MASK, 0x1); 1169 1170 /* Check wfsys2conn bus sleep protect */ 1171 read_poll_timeout(mt76_rr, cur, !(cur ^ MT_CONN_INFRA_CONN), 1172 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, 1173 dev, MT_CONN_INFRA_WF_SLP_PROT_RDY); 1174 1175 mt7986_wmac_wfsys_poweron(dev, false); 1176 1177 /* Turn back wpll setting */ 1178 mt76_rmw_field(dev, MT_AFE_DIG_EN_02(0), MT_AFE_MCU_BPLL_CFG_MASK, 0x2); 1179 mt76_rmw_field(dev, MT_AFE_DIG_EN_02(0), MT_AFE_WPLL_CFG_MASK, 0x2); 1180 1181 /* Reset EMI */ 1182 mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ, 1183 MT_CONN_INFRA_EMI_REQ_MASK, 0x1); 1184 mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ, 1185 MT_CONN_INFRA_EMI_REQ_MASK, 0x0); 1186 mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ, 1187 MT_CONN_INFRA_INFRA_REQ_MASK, 0x1); 1188 mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ, 1189 MT_CONN_INFRA_INFRA_REQ_MASK, 0x0); 1190 1191 mt7986_wmac_top_wfsys_wakeup(dev, false); 1192 mt7986_wmac_consys_lockup(dev, true); 1193 mt7986_wmac_consys_reset(dev, false); 1194 } 1195 1196 static int mt798x_wmac_init(struct mt7915_dev *dev) 1197 { 1198 struct device *pdev = dev->mt76.dev; 1199 struct platform_device *pfdev = to_platform_device(pdev); 1200 struct clk *mcu_clk, *ap_conn_clk; 1201 1202 mcu_clk = devm_clk_get(pdev, "mcu"); 1203 if (IS_ERR(mcu_clk)) 1204 dev_err(pdev, "mcu clock not found\n"); 1205 else if (clk_prepare_enable(mcu_clk)) 1206 dev_err(pdev, "mcu clock configuration failed\n"); 1207 1208 ap_conn_clk = devm_clk_get(pdev, "ap2conn"); 1209 if (IS_ERR(ap_conn_clk)) 1210 dev_err(pdev, "ap2conn clock not found\n"); 1211 else if (clk_prepare_enable(ap_conn_clk)) 1212 dev_err(pdev, "ap2conn clock configuration failed\n"); 1213 1214 dev->dcm = devm_platform_ioremap_resource(pfdev, 1); 1215 if (IS_ERR(dev->dcm)) 1216 return PTR_ERR(dev->dcm); 1217 1218 dev->sku = devm_platform_ioremap_resource(pfdev, 2); 1219 if (IS_ERR(dev->sku)) 1220 return PTR_ERR(dev->sku); 1221 1222 dev->rstc = devm_reset_control_get(pdev, "consys"); 1223 return PTR_ERR_OR_ZERO(dev->rstc); 1224 } 1225 1226 static int mt798x_wmac_probe(struct platform_device *pdev) 1227 { 1228 void __iomem *mem_base; 1229 struct mt7915_dev *dev; 1230 struct mt76_dev *mdev; 1231 int irq, ret; 1232 u32 chip_id; 1233 1234 chip_id = (uintptr_t)of_device_get_match_data(&pdev->dev); 1235 1236 mem_base = devm_platform_ioremap_resource(pdev, 0); 1237 if (IS_ERR(mem_base)) { 1238 dev_err(&pdev->dev, "Failed to get memory resource\n"); 1239 return PTR_ERR(mem_base); 1240 } 1241 1242 dev = mt7915_mmio_probe(&pdev->dev, mem_base, chip_id); 1243 if (IS_ERR(dev)) 1244 return PTR_ERR(dev); 1245 1246 mdev = &dev->mt76; 1247 ret = mt7915_mmio_wed_init(dev, pdev, false, &irq); 1248 if (ret < 0) 1249 goto free_device; 1250 1251 if (!ret) { 1252 irq = platform_get_irq(pdev, 0); 1253 if (irq < 0) { 1254 ret = irq; 1255 goto free_device; 1256 } 1257 } 1258 1259 ret = devm_request_irq(mdev->dev, irq, mt7915_irq_handler, 1260 IRQF_SHARED, KBUILD_MODNAME, dev); 1261 if (ret) 1262 goto free_device; 1263 1264 ret = mt798x_wmac_init(dev); 1265 if (ret) 1266 goto free_irq; 1267 1268 mt7915_wfsys_reset(dev); 1269 1270 ret = mt7915_register_device(dev); 1271 if (ret) 1272 goto free_irq; 1273 1274 return 0; 1275 1276 free_irq: 1277 devm_free_irq(mdev->dev, irq, dev); 1278 free_device: 1279 if (mtk_wed_device_active(&mdev->mmio.wed)) 1280 mtk_wed_device_detach(&mdev->mmio.wed); 1281 mt76_free_device(mdev); 1282 1283 return ret; 1284 } 1285 1286 static void mt798x_wmac_remove(struct platform_device *pdev) 1287 { 1288 struct mt7915_dev *dev = platform_get_drvdata(pdev); 1289 1290 mt7915_unregister_device(dev); 1291 } 1292 1293 static const struct of_device_id mt798x_wmac_of_match[] = { 1294 { .compatible = "mediatek,mt7981-wmac", .data = (u32 *)0x7981 }, 1295 { .compatible = "mediatek,mt7986-wmac", .data = (u32 *)0x7986 }, 1296 {}, 1297 }; 1298 1299 MODULE_DEVICE_TABLE(of, mt798x_wmac_of_match); 1300 1301 struct platform_driver mt798x_wmac_driver = { 1302 .driver = { 1303 .name = "mt798x-wmac", 1304 .of_match_table = mt798x_wmac_of_match, 1305 }, 1306 .probe = mt798x_wmac_probe, 1307 .remove_new = mt798x_wmac_remove, 1308 }; 1309 1310 MODULE_FIRMWARE(MT7986_FIRMWARE_WA); 1311 MODULE_FIRMWARE(MT7986_FIRMWARE_WM); 1312 MODULE_FIRMWARE(MT7986_FIRMWARE_WM_MT7975); 1313 MODULE_FIRMWARE(MT7986_ROM_PATCH); 1314 MODULE_FIRMWARE(MT7986_ROM_PATCH_MT7975); 1315 1316 MODULE_FIRMWARE(MT7981_FIRMWARE_WA); 1317 MODULE_FIRMWARE(MT7981_FIRMWARE_WM); 1318 MODULE_FIRMWARE(MT7981_ROM_PATCH); 1319