1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #ifndef __MT7915_H 5 #define __MT7915_H 6 7 #include <linux/interrupt.h> 8 #include <linux/ktime.h> 9 #include "../mt76.h" 10 #include "regs.h" 11 12 #define MT7915_MAX_INTERFACES 19 13 #define MT7915_MAX_WMM_SETS 4 14 #define MT7915_WTBL_SIZE 288 15 #define MT7916_WTBL_SIZE 544 16 #define MT7915_WTBL_RESERVED (mt7915_wtbl_size(dev) - 1) 17 #define MT7915_WTBL_STA (MT7915_WTBL_RESERVED - \ 18 MT7915_MAX_INTERFACES) 19 20 #define MT7915_WATCHDOG_TIME (HZ / 10) 21 #define MT7915_RESET_TIMEOUT (30 * HZ) 22 23 #define MT7915_TX_RING_SIZE 2048 24 #define MT7915_TX_MCU_RING_SIZE 256 25 #define MT7915_TX_FWDL_RING_SIZE 128 26 27 #define MT7915_RX_RING_SIZE 1536 28 #define MT7915_RX_MCU_RING_SIZE 512 29 30 #define MT7915_FIRMWARE_WA "mediatek/mt7915_wa.bin" 31 #define MT7915_FIRMWARE_WM "mediatek/mt7915_wm.bin" 32 #define MT7915_ROM_PATCH "mediatek/mt7915_rom_patch.bin" 33 34 #define MT7916_FIRMWARE_WA "mediatek/mt7916_wa.bin" 35 #define MT7916_FIRMWARE_WM "mediatek/mt7916_wm.bin" 36 #define MT7916_ROM_PATCH "mediatek/mt7916_rom_patch.bin" 37 38 #define MT7915_EEPROM_DEFAULT "mediatek/mt7915_eeprom.bin" 39 #define MT7915_EEPROM_DEFAULT_DBDC "mediatek/mt7915_eeprom_dbdc.bin" 40 #define MT7916_EEPROM_DEFAULT "mediatek/mt7916_eeprom.bin" 41 42 #define MT7915_EEPROM_SIZE 3584 43 #define MT7916_EEPROM_SIZE 4096 44 45 #define MT7915_EEPROM_BLOCK_SIZE 16 46 #define MT7915_TOKEN_SIZE 8192 47 48 #define MT7915_CFEND_RATE_DEFAULT 0x49 /* OFDM 24M */ 49 #define MT7915_CFEND_RATE_11B 0x03 /* 11B LP, 11M */ 50 51 #define MT7915_THERMAL_THROTTLE_MAX 100 52 53 #define MT7915_SKU_RATE_NUM 161 54 55 #define MT7915_MAX_TWT_AGRT 16 56 #define MT7915_MAX_STA_TWT_AGRT 8 57 #define MT7915_MAX_QUEUE (__MT_RXQ_MAX + __MT_MCUQ_MAX + 2) 58 59 struct mt7915_vif; 60 struct mt7915_sta; 61 struct mt7915_dfs_pulse; 62 struct mt7915_dfs_pattern; 63 64 enum mt7915_txq_id { 65 MT7915_TXQ_FWDL = 16, 66 MT7915_TXQ_MCU_WM, 67 MT7915_TXQ_BAND0, 68 MT7915_TXQ_BAND1, 69 MT7915_TXQ_MCU_WA, 70 }; 71 72 enum mt7915_rxq_id { 73 MT7915_RXQ_BAND0 = 0, 74 MT7915_RXQ_BAND1, 75 MT7915_RXQ_MCU_WM = 0, 76 MT7915_RXQ_MCU_WA, 77 MT7915_RXQ_MCU_WA_EXT, 78 }; 79 80 enum mt7916_rxq_id { 81 MT7916_RXQ_MCU_WM = 0, 82 MT7916_RXQ_MCU_WA, 83 MT7916_RXQ_MCU_WA_MAIN, 84 MT7916_RXQ_MCU_WA_EXT, 85 MT7916_RXQ_BAND0, 86 MT7916_RXQ_BAND1, 87 }; 88 89 struct mt7915_sta_key_conf { 90 s8 keyidx; 91 u8 key[16]; 92 }; 93 94 struct mt7915_twt_flow { 95 struct list_head list; 96 u64 start_tsf; 97 u64 tsf; 98 u32 duration; 99 u16 wcid; 100 __le16 mantissa; 101 u8 exp; 102 u8 table_id; 103 u8 id; 104 u8 protection:1; 105 u8 flowtype:1; 106 u8 trigger:1; 107 u8 sched:1; 108 }; 109 110 struct mt7915_sta { 111 struct mt76_wcid wcid; /* must be first */ 112 113 struct mt7915_vif *vif; 114 115 struct list_head poll_list; 116 struct list_head rc_list; 117 u32 airtime_ac[8]; 118 119 unsigned long changed; 120 unsigned long jiffies; 121 unsigned long ampdu_state; 122 123 struct mt76_sta_stats stats; 124 125 struct mt7915_sta_key_conf bip; 126 127 struct { 128 u8 flowid_mask; 129 struct mt7915_twt_flow flow[MT7915_MAX_STA_TWT_AGRT]; 130 } twt; 131 }; 132 133 struct mt7915_vif_cap { 134 bool ldpc:1; 135 bool vht_su_ebfer:1; 136 bool vht_su_ebfee:1; 137 bool vht_mu_ebfer:1; 138 bool vht_mu_ebfee:1; 139 bool he_su_ebfer:1; 140 bool he_su_ebfee:1; 141 bool he_mu_ebfer:1; 142 }; 143 144 struct mt7915_vif { 145 struct mt76_vif mt76; /* must be first */ 146 147 struct mt7915_vif_cap cap; 148 struct mt7915_sta sta; 149 struct mt7915_phy *phy; 150 151 struct ieee80211_tx_queue_params queue_params[IEEE80211_NUM_ACS]; 152 struct cfg80211_bitrate_mask bitrate_mask; 153 }; 154 155 /* per-phy stats. */ 156 struct mib_stats { 157 u32 ack_fail_cnt; 158 u32 fcs_err_cnt; 159 u32 rts_cnt; 160 u32 rts_retries_cnt; 161 u32 ba_miss_cnt; 162 u32 tx_bf_cnt; 163 u32 tx_mu_mpdu_cnt; 164 u32 tx_mu_acked_mpdu_cnt; 165 u32 tx_su_acked_mpdu_cnt; 166 u32 tx_bf_ibf_ppdu_cnt; 167 u32 tx_bf_ebf_ppdu_cnt; 168 169 u32 tx_bf_rx_fb_all_cnt; 170 u32 tx_bf_rx_fb_he_cnt; 171 u32 tx_bf_rx_fb_vht_cnt; 172 u32 tx_bf_rx_fb_ht_cnt; 173 174 u32 tx_bf_rx_fb_bw; /* value of last sample, not cumulative */ 175 u32 tx_bf_rx_fb_nc_cnt; 176 u32 tx_bf_rx_fb_nr_cnt; 177 u32 tx_bf_fb_cpl_cnt; 178 u32 tx_bf_fb_trig_cnt; 179 180 u32 tx_ampdu_cnt; 181 u32 tx_stop_q_empty_cnt; 182 u32 tx_mpdu_attempts_cnt; 183 u32 tx_mpdu_success_cnt; 184 u32 tx_pkt_ebf_cnt; 185 u32 tx_pkt_ibf_cnt; 186 187 u32 tx_rwp_fail_cnt; 188 u32 tx_rwp_need_cnt; 189 190 /* rx stats */ 191 u32 rx_fifo_full_cnt; 192 u32 channel_idle_cnt; 193 u32 rx_vector_mismatch_cnt; 194 u32 rx_delimiter_fail_cnt; 195 u32 rx_len_mismatch_cnt; 196 u32 rx_mpdu_cnt; 197 u32 rx_ampdu_cnt; 198 u32 rx_ampdu_bytes_cnt; 199 u32 rx_ampdu_valid_subframe_cnt; 200 u32 rx_ampdu_valid_subframe_bytes_cnt; 201 u32 rx_pfdrop_cnt; 202 u32 rx_vec_queue_overflow_drop_cnt; 203 u32 rx_ba_cnt; 204 205 u32 tx_amsdu[8]; 206 u32 tx_amsdu_cnt; 207 }; 208 209 struct mt7915_hif { 210 struct list_head list; 211 212 struct device *dev; 213 void __iomem *regs; 214 int irq; 215 }; 216 217 struct mt7915_phy { 218 struct mt76_phy *mt76; 219 struct mt7915_dev *dev; 220 221 struct ieee80211_sband_iftype_data iftype[2][NUM_NL80211_IFTYPES]; 222 223 struct ieee80211_vif *monitor_vif; 224 225 struct thermal_cooling_device *cdev; 226 u8 throttle_state; 227 u32 throttle_temp[2]; /* 0: critical high, 1: maximum */ 228 229 u32 rxfilter; 230 u64 omac_mask; 231 232 u16 noise; 233 234 s16 coverage_class; 235 u8 slottime; 236 237 u8 rdd_state; 238 int dfs_state; 239 240 u32 rx_ampdu_ts; 241 u32 ampdu_ref; 242 243 struct mib_stats mib; 244 struct mt76_channel_state state_ts; 245 246 #ifdef CONFIG_NL80211_TESTMODE 247 struct { 248 u32 *reg_backup; 249 250 s32 last_freq_offset; 251 u8 last_rcpi[4]; 252 s8 last_ib_rssi[4]; 253 s8 last_wb_rssi[4]; 254 u8 last_snr; 255 256 u8 spe_idx; 257 } test; 258 #endif 259 }; 260 261 struct mt7915_dev { 262 union { /* must be first */ 263 struct mt76_dev mt76; 264 struct mt76_phy mphy; 265 }; 266 267 struct mt7915_hif *hif2; 268 struct mt7915_reg_desc reg; 269 u8 q_id[MT7915_MAX_QUEUE]; 270 u32 q_int_mask[MT7915_MAX_QUEUE]; 271 u32 wfdma_mask; 272 273 const struct mt76_bus_ops *bus_ops; 274 struct tasklet_struct irq_tasklet; 275 struct mt7915_phy phy; 276 277 u16 chainmask; 278 u32 hif_idx; 279 280 struct work_struct init_work; 281 struct work_struct rc_work; 282 struct work_struct reset_work; 283 wait_queue_head_t reset_wait; 284 u32 reset_state; 285 286 struct list_head sta_rc_list; 287 struct list_head sta_poll_list; 288 struct list_head twt_list; 289 spinlock_t sta_poll_lock; 290 291 u32 hw_pattern; 292 293 bool dbdc_support; 294 bool flash_mode; 295 bool muru_debug; 296 bool ibf; 297 u8 fw_debug_wm; 298 u8 fw_debug_wa; 299 300 void *cal; 301 302 struct { 303 u8 table_mask; 304 u8 n_agrt; 305 } twt; 306 }; 307 308 enum { 309 WFDMA0 = 0x0, 310 WFDMA1, 311 WFDMA_EXT, 312 __MT_WFDMA_MAX, 313 }; 314 315 enum { 316 MT_CTX0, 317 MT_HIF0 = 0x0, 318 319 MT_LMAC_AC00 = 0x0, 320 MT_LMAC_AC01, 321 MT_LMAC_AC02, 322 MT_LMAC_AC03, 323 MT_LMAC_ALTX0 = 0x10, 324 MT_LMAC_BMC0, 325 MT_LMAC_BCN0, 326 MT_LMAC_PSMP0, 327 }; 328 329 enum { 330 MT_RX_SEL0, 331 MT_RX_SEL1, 332 }; 333 334 enum mt7915_rdd_cmd { 335 RDD_STOP, 336 RDD_START, 337 RDD_DET_MODE, 338 RDD_RADAR_EMULATE, 339 RDD_START_TXQ = 20, 340 RDD_CAC_START = 50, 341 RDD_CAC_END, 342 RDD_NORMAL_START, 343 RDD_DISABLE_DFS_CAL, 344 RDD_PULSE_DBG, 345 RDD_READ_PULSE, 346 RDD_RESUME_BF, 347 RDD_IRQ_OFF, 348 }; 349 350 static inline struct mt7915_phy * 351 mt7915_hw_phy(struct ieee80211_hw *hw) 352 { 353 struct mt76_phy *phy = hw->priv; 354 355 return phy->priv; 356 } 357 358 static inline struct mt7915_dev * 359 mt7915_hw_dev(struct ieee80211_hw *hw) 360 { 361 struct mt76_phy *phy = hw->priv; 362 363 return container_of(phy->dev, struct mt7915_dev, mt76); 364 } 365 366 static inline struct mt7915_phy * 367 mt7915_ext_phy(struct mt7915_dev *dev) 368 { 369 struct mt76_phy *phy = dev->mt76.phy2; 370 371 if (!phy) 372 return NULL; 373 374 return phy->priv; 375 } 376 377 static inline u8 mt7915_lmac_mapping(struct mt7915_dev *dev, u8 ac) 378 { 379 /* LMAC uses the reverse order of mac80211 AC indexes */ 380 return 3 - ac; 381 } 382 383 extern const struct ieee80211_ops mt7915_ops; 384 extern const struct mt76_testmode_ops mt7915_testmode_ops; 385 extern struct pci_driver mt7915_pci_driver; 386 extern struct pci_driver mt7915_hif_driver; 387 388 int mt7915_mmio_probe(struct device *pdev, 389 void __iomem *mem_base, 390 u32 device_id, 391 int irq, struct mt7915_hif *hif2); 392 u64 __mt7915_get_tsf(struct ieee80211_hw *hw, struct mt7915_vif *mvif); 393 int mt7915_register_device(struct mt7915_dev *dev); 394 void mt7915_unregister_device(struct mt7915_dev *dev); 395 int mt7915_eeprom_init(struct mt7915_dev *dev); 396 void mt7915_eeprom_parse_hw_cap(struct mt7915_dev *dev, 397 struct mt7915_phy *phy); 398 int mt7915_eeprom_get_target_power(struct mt7915_dev *dev, 399 struct ieee80211_channel *chan, 400 u8 chain_idx); 401 s8 mt7915_eeprom_get_power_delta(struct mt7915_dev *dev, int band); 402 int mt7915_dma_init(struct mt7915_dev *dev); 403 void mt7915_dma_prefetch(struct mt7915_dev *dev); 404 void mt7915_dma_cleanup(struct mt7915_dev *dev); 405 int mt7915_mcu_init(struct mt7915_dev *dev); 406 int mt7915_mcu_twt_agrt_update(struct mt7915_dev *dev, 407 struct mt7915_vif *mvif, 408 struct mt7915_twt_flow *flow, 409 int cmd); 410 int mt7915_mcu_add_dev_info(struct mt7915_phy *phy, 411 struct ieee80211_vif *vif, bool enable); 412 int mt7915_mcu_add_bss_info(struct mt7915_phy *phy, 413 struct ieee80211_vif *vif, int enable); 414 int mt7915_mcu_add_sta(struct mt7915_dev *dev, struct ieee80211_vif *vif, 415 struct ieee80211_sta *sta, bool enable); 416 int mt7915_mcu_sta_update_hdr_trans(struct mt7915_dev *dev, 417 struct ieee80211_vif *vif, 418 struct ieee80211_sta *sta); 419 int mt7915_mcu_add_tx_ba(struct mt7915_dev *dev, 420 struct ieee80211_ampdu_params *params, 421 bool add); 422 int mt7915_mcu_add_rx_ba(struct mt7915_dev *dev, 423 struct ieee80211_ampdu_params *params, 424 bool add); 425 int mt7915_mcu_add_key(struct mt7915_dev *dev, struct ieee80211_vif *vif, 426 struct mt7915_sta *msta, struct ieee80211_key_conf *key, 427 enum set_key_cmd cmd); 428 int mt7915_mcu_update_bss_color(struct mt7915_dev *dev, struct ieee80211_vif *vif, 429 struct cfg80211_he_bss_color *he_bss_color); 430 int mt7915_mcu_add_beacon(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 431 int enable); 432 int mt7915_mcu_add_obss_spr(struct mt7915_dev *dev, struct ieee80211_vif *vif, 433 bool enable); 434 int mt7915_mcu_add_rate_ctrl(struct mt7915_dev *dev, struct ieee80211_vif *vif, 435 struct ieee80211_sta *sta, bool changed); 436 int mt7915_mcu_add_smps(struct mt7915_dev *dev, struct ieee80211_vif *vif, 437 struct ieee80211_sta *sta); 438 int mt7915_set_channel(struct mt7915_phy *phy); 439 int mt7915_mcu_set_chan_info(struct mt7915_phy *phy, int cmd); 440 int mt7915_mcu_set_tx(struct mt7915_dev *dev, struct ieee80211_vif *vif); 441 int mt7915_mcu_update_edca(struct mt7915_dev *dev, void *req); 442 int mt7915_mcu_set_fixed_rate_ctrl(struct mt7915_dev *dev, 443 struct ieee80211_vif *vif, 444 struct ieee80211_sta *sta, 445 void *data, u32 field); 446 int mt7915_mcu_set_eeprom(struct mt7915_dev *dev); 447 int mt7915_mcu_get_eeprom(struct mt7915_dev *dev, u32 offset); 448 int mt7915_mcu_get_eeprom_free_block(struct mt7915_dev *dev, u8 *block_num); 449 int mt7915_mcu_set_mac(struct mt7915_dev *dev, int band, bool enable, 450 bool hdr_trans); 451 int mt7915_mcu_set_test_param(struct mt7915_dev *dev, u8 param, bool test_mode, 452 u8 en); 453 int mt7915_mcu_set_scs(struct mt7915_dev *dev, u8 band, bool enable); 454 int mt7915_mcu_set_ser(struct mt7915_dev *dev, u8 action, u8 set, u8 band); 455 int mt7915_mcu_set_rts_thresh(struct mt7915_phy *phy, u32 val); 456 int mt7915_mcu_set_pm(struct mt7915_dev *dev, int band, int enter); 457 int mt7915_mcu_set_sku_en(struct mt7915_phy *phy, bool enable); 458 int mt7915_mcu_set_txpower_sku(struct mt7915_phy *phy); 459 int mt7915_mcu_get_txpower_sku(struct mt7915_phy *phy, s8 *txpower, int len); 460 int mt7915_mcu_set_txbf(struct mt7915_dev *dev, u8 action); 461 int mt7915_mcu_set_fcc5_lpn(struct mt7915_dev *dev, int val); 462 int mt7915_mcu_set_pulse_th(struct mt7915_dev *dev, 463 const struct mt7915_dfs_pulse *pulse); 464 int mt7915_mcu_set_radar_th(struct mt7915_dev *dev, int index, 465 const struct mt7915_dfs_pattern *pattern); 466 int mt7915_mcu_set_muru_ctrl(struct mt7915_dev *dev, u32 cmd, u32 val); 467 int mt7915_mcu_apply_group_cal(struct mt7915_dev *dev); 468 int mt7915_mcu_apply_tx_dpd(struct mt7915_phy *phy); 469 int mt7915_mcu_get_chan_mib_info(struct mt7915_phy *phy, bool chan_switch); 470 int mt7915_mcu_get_temperature(struct mt7915_phy *phy); 471 int mt7915_mcu_set_thermal_throttling(struct mt7915_phy *phy, u8 state); 472 int mt7915_mcu_get_rx_rate(struct mt7915_phy *phy, struct ieee80211_vif *vif, 473 struct ieee80211_sta *sta, struct rate_info *rate); 474 int mt7915_mcu_rdd_cmd(struct mt7915_dev *dev, enum mt7915_rdd_cmd cmd, 475 u8 index, u8 rx_sel, u8 val); 476 int mt7915_mcu_wa_cmd(struct mt7915_dev *dev, int cmd, u32 a1, u32 a2, u32 a3); 477 int mt7915_mcu_fw_log_2_host(struct mt7915_dev *dev, u8 type, u8 ctrl); 478 int mt7915_mcu_fw_dbg_ctrl(struct mt7915_dev *dev, u32 module, u8 level); 479 void mt7915_mcu_rx_event(struct mt7915_dev *dev, struct sk_buff *skb); 480 void mt7915_mcu_exit(struct mt7915_dev *dev); 481 482 static inline bool is_mt7915(struct mt76_dev *dev) 483 { 484 return mt76_chip(dev) == 0x7915; 485 } 486 487 static inline u16 mt7915_wtbl_size(struct mt7915_dev *dev) 488 { 489 return is_mt7915(&dev->mt76) ? MT7915_WTBL_SIZE : MT7916_WTBL_SIZE; 490 } 491 492 static inline u16 mt7915_eeprom_size(struct mt7915_dev *dev) 493 { 494 return is_mt7915(&dev->mt76) ? MT7915_EEPROM_SIZE : MT7916_EEPROM_SIZE; 495 } 496 497 void mt7915_dual_hif_set_irq_mask(struct mt7915_dev *dev, bool write_reg, 498 u32 clear, u32 set); 499 500 static inline void mt7915_irq_enable(struct mt7915_dev *dev, u32 mask) 501 { 502 if (dev->hif2) 503 mt7915_dual_hif_set_irq_mask(dev, false, 0, mask); 504 else 505 mt76_set_irq_mask(&dev->mt76, 0, 0, mask); 506 507 tasklet_schedule(&dev->irq_tasklet); 508 } 509 510 static inline void mt7915_irq_disable(struct mt7915_dev *dev, u32 mask) 511 { 512 if (dev->hif2) 513 mt7915_dual_hif_set_irq_mask(dev, true, mask, 0); 514 else 515 mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0); 516 } 517 518 u32 mt7915_mac_wtbl_lmac_addr(struct mt7915_dev *dev, u16 wcid, u8 dw); 519 bool mt7915_mac_wtbl_update(struct mt7915_dev *dev, int idx, u32 mask); 520 void mt7915_mac_reset_counters(struct mt7915_phy *phy); 521 void mt7915_mac_cca_stats_reset(struct mt7915_phy *phy); 522 void mt7915_mac_enable_nf(struct mt7915_dev *dev, bool ext_phy); 523 void mt7915_mac_write_txwi(struct mt7915_dev *dev, __le32 *txwi, 524 struct sk_buff *skb, struct mt76_wcid *wcid, int pid, 525 struct ieee80211_key_conf *key, bool beacon); 526 void mt7915_mac_set_timing(struct mt7915_phy *phy); 527 int mt7915_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif, 528 struct ieee80211_sta *sta); 529 void mt7915_mac_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif, 530 struct ieee80211_sta *sta); 531 void mt7915_mac_work(struct work_struct *work); 532 void mt7915_mac_reset_work(struct work_struct *work); 533 void mt7915_mac_sta_rc_work(struct work_struct *work); 534 void mt7915_mac_update_stats(struct mt7915_phy *phy); 535 void mt7915_mac_twt_teardown_flow(struct mt7915_dev *dev, 536 struct mt7915_sta *msta, 537 u8 flowid); 538 void mt7915_mac_add_twt_setup(struct ieee80211_hw *hw, 539 struct ieee80211_sta *sta, 540 struct ieee80211_twt_setup *twt); 541 int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, 542 enum mt76_txq_id qid, struct mt76_wcid *wcid, 543 struct ieee80211_sta *sta, 544 struct mt76_tx_info *tx_info); 545 void mt7915_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e); 546 void mt7915_tx_token_put(struct mt7915_dev *dev); 547 int mt7915_init_tx_queues(struct mt7915_phy *phy, int idx, int n_desc, int ring_base); 548 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 549 struct sk_buff *skb); 550 bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len); 551 void mt7915_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps); 552 void mt7915_stats_work(struct work_struct *work); 553 int mt76_dfs_start_rdd(struct mt7915_dev *dev, bool force); 554 int mt7915_dfs_init_radar_detector(struct mt7915_phy *phy); 555 void mt7915_set_stream_he_caps(struct mt7915_phy *phy); 556 void mt7915_set_stream_vht_txbf_caps(struct mt7915_phy *phy); 557 void mt7915_update_channel(struct mt76_phy *mphy); 558 int mt7915_mcu_muru_debug_set(struct mt7915_dev *dev, bool enable); 559 int mt7915_mcu_muru_debug_get(struct mt7915_phy *phy, void *ms); 560 int mt7915_init_debugfs(struct mt7915_phy *phy); 561 #ifdef CONFIG_MAC80211_DEBUGFS 562 void mt7915_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 563 struct ieee80211_sta *sta, struct dentry *dir); 564 #endif 565 566 #endif 567