1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #ifndef __MT7915_H 5 #define __MT7915_H 6 7 #include <linux/interrupt.h> 8 #include <linux/ktime.h> 9 #include "../mt76_connac.h" 10 #include "regs.h" 11 12 #define MT7915_MAX_INTERFACES 19 13 #define MT7915_WTBL_SIZE 288 14 #define MT7916_WTBL_SIZE 544 15 #define MT7915_WTBL_RESERVED (mt7915_wtbl_size(dev) - 1) 16 #define MT7915_WTBL_STA (MT7915_WTBL_RESERVED - \ 17 MT7915_MAX_INTERFACES) 18 19 #define MT7915_WATCHDOG_TIME (HZ / 10) 20 #define MT7915_RESET_TIMEOUT (30 * HZ) 21 22 #define MT7915_TX_RING_SIZE 2048 23 #define MT7915_TX_MCU_RING_SIZE 256 24 #define MT7915_TX_FWDL_RING_SIZE 128 25 26 #define MT7915_RX_RING_SIZE 1536 27 #define MT7915_RX_MCU_RING_SIZE 512 28 29 #define MT7915_FIRMWARE_WA "mediatek/mt7915_wa.bin" 30 #define MT7915_FIRMWARE_WM "mediatek/mt7915_wm.bin" 31 #define MT7915_ROM_PATCH "mediatek/mt7915_rom_patch.bin" 32 33 #define MT7916_FIRMWARE_WA "mediatek/mt7916_wa.bin" 34 #define MT7916_FIRMWARE_WM "mediatek/mt7916_wm.bin" 35 #define MT7916_ROM_PATCH "mediatek/mt7916_rom_patch.bin" 36 37 #define MT7986_FIRMWARE_WA "mediatek/mt7986_wa.bin" 38 #define MT7986_FIRMWARE_WM "mediatek/mt7986_wm.bin" 39 #define MT7986_FIRMWARE_WM_MT7975 "mediatek/mt7986_wm_mt7975.bin" 40 #define MT7986_ROM_PATCH "mediatek/mt7986_rom_patch.bin" 41 #define MT7986_ROM_PATCH_MT7975 "mediatek/mt7986_rom_patch_mt7975.bin" 42 43 #define MT7915_EEPROM_DEFAULT "mediatek/mt7915_eeprom.bin" 44 #define MT7915_EEPROM_DEFAULT_DBDC "mediatek/mt7915_eeprom_dbdc.bin" 45 #define MT7916_EEPROM_DEFAULT "mediatek/mt7916_eeprom.bin" 46 #define MT7986_EEPROM_MT7975_DEFAULT "mediatek/mt7986_eeprom_mt7975.bin" 47 #define MT7986_EEPROM_MT7975_DUAL_DEFAULT "mediatek/mt7986_eeprom_mt7975_dual.bin" 48 #define MT7986_EEPROM_MT7976_DEFAULT "mediatek/mt7986_eeprom_mt7976.bin" 49 #define MT7986_EEPROM_MT7976_DEFAULT_DBDC "mediatek/mt7986_eeprom_mt7976_dbdc.bin" 50 #define MT7986_EEPROM_MT7976_DUAL_DEFAULT "mediatek/mt7986_eeprom_mt7976_dual.bin" 51 52 #define MT7915_EEPROM_SIZE 3584 53 #define MT7916_EEPROM_SIZE 4096 54 55 #define MT7915_EEPROM_BLOCK_SIZE 16 56 #define MT7915_TOKEN_SIZE 8192 57 58 #define MT7915_CFEND_RATE_DEFAULT 0x49 /* OFDM 24M */ 59 #define MT7915_CFEND_RATE_11B 0x03 /* 11B LP, 11M */ 60 61 #define MT7915_THERMAL_THROTTLE_MAX 100 62 #define MT7915_CDEV_THROTTLE_MAX 99 63 64 #define MT7915_SKU_RATE_NUM 161 65 66 #define MT7915_MAX_TWT_AGRT 16 67 #define MT7915_MAX_STA_TWT_AGRT 8 68 #define MT7915_MIN_TWT_DUR 64 69 #define MT7915_MAX_QUEUE (MT_RXQ_BAND2 + __MT_MCUQ_MAX + 2) 70 71 struct mt7915_vif; 72 struct mt7915_sta; 73 struct mt7915_dfs_pulse; 74 struct mt7915_dfs_pattern; 75 76 enum mt7915_txq_id { 77 MT7915_TXQ_FWDL = 16, 78 MT7915_TXQ_MCU_WM, 79 MT7915_TXQ_BAND0, 80 MT7915_TXQ_BAND1, 81 MT7915_TXQ_MCU_WA, 82 }; 83 84 enum mt7915_rxq_id { 85 MT7915_RXQ_BAND0 = 0, 86 MT7915_RXQ_BAND1, 87 MT7915_RXQ_MCU_WM = 0, 88 MT7915_RXQ_MCU_WA, 89 MT7915_RXQ_MCU_WA_EXT, 90 }; 91 92 enum mt7916_rxq_id { 93 MT7916_RXQ_MCU_WM = 0, 94 MT7916_RXQ_MCU_WA, 95 MT7916_RXQ_MCU_WA_MAIN, 96 MT7916_RXQ_MCU_WA_EXT, 97 MT7916_RXQ_BAND0, 98 MT7916_RXQ_BAND1, 99 }; 100 101 struct mt7915_twt_flow { 102 struct list_head list; 103 u64 start_tsf; 104 u64 tsf; 105 u32 duration; 106 u16 wcid; 107 __le16 mantissa; 108 u8 exp; 109 u8 table_id; 110 u8 id; 111 u8 protection:1; 112 u8 flowtype:1; 113 u8 trigger:1; 114 u8 sched:1; 115 }; 116 117 DECLARE_EWMA(avg_signal, 10, 8) 118 119 struct mt7915_sta { 120 struct mt76_wcid wcid; /* must be first */ 121 122 struct mt7915_vif *vif; 123 124 struct list_head poll_list; 125 struct list_head rc_list; 126 u32 airtime_ac[8]; 127 128 int ack_signal; 129 struct ewma_avg_signal avg_ack_signal; 130 131 unsigned long changed; 132 unsigned long jiffies; 133 unsigned long ampdu_state; 134 struct mt76_connac_sta_key_conf bip; 135 136 struct { 137 u8 flowid_mask; 138 struct mt7915_twt_flow flow[MT7915_MAX_STA_TWT_AGRT]; 139 } twt; 140 }; 141 142 struct mt7915_vif_cap { 143 bool ht_ldpc:1; 144 bool vht_ldpc:1; 145 bool he_ldpc:1; 146 bool vht_su_ebfer:1; 147 bool vht_su_ebfee:1; 148 bool vht_mu_ebfer:1; 149 bool vht_mu_ebfee:1; 150 bool he_su_ebfer:1; 151 bool he_su_ebfee:1; 152 bool he_mu_ebfer:1; 153 }; 154 155 struct mt7915_vif { 156 struct mt76_vif mt76; /* must be first */ 157 158 struct mt7915_vif_cap cap; 159 struct mt7915_sta sta; 160 struct mt7915_phy *phy; 161 162 struct ieee80211_tx_queue_params queue_params[IEEE80211_NUM_ACS]; 163 struct cfg80211_bitrate_mask bitrate_mask; 164 }; 165 166 /* per-phy stats. */ 167 struct mib_stats { 168 u32 ack_fail_cnt; 169 u32 fcs_err_cnt; 170 u32 rts_cnt; 171 u32 rts_retries_cnt; 172 u32 ba_miss_cnt; 173 u32 tx_bf_cnt; 174 u32 tx_mu_mpdu_cnt; 175 u32 tx_mu_acked_mpdu_cnt; 176 u32 tx_su_acked_mpdu_cnt; 177 u32 tx_bf_ibf_ppdu_cnt; 178 u32 tx_bf_ebf_ppdu_cnt; 179 180 u32 tx_bf_rx_fb_all_cnt; 181 u32 tx_bf_rx_fb_he_cnt; 182 u32 tx_bf_rx_fb_vht_cnt; 183 u32 tx_bf_rx_fb_ht_cnt; 184 185 u32 tx_bf_rx_fb_bw; /* value of last sample, not cumulative */ 186 u32 tx_bf_rx_fb_nc_cnt; 187 u32 tx_bf_rx_fb_nr_cnt; 188 u32 tx_bf_fb_cpl_cnt; 189 u32 tx_bf_fb_trig_cnt; 190 191 u32 tx_ampdu_cnt; 192 u32 tx_stop_q_empty_cnt; 193 u32 tx_mpdu_attempts_cnt; 194 u32 tx_mpdu_success_cnt; 195 u32 tx_pkt_ebf_cnt; 196 u32 tx_pkt_ibf_cnt; 197 198 u32 tx_rwp_fail_cnt; 199 u32 tx_rwp_need_cnt; 200 201 /* rx stats */ 202 u32 rx_fifo_full_cnt; 203 u32 channel_idle_cnt; 204 u32 primary_cca_busy_time; 205 u32 secondary_cca_busy_time; 206 u32 primary_energy_detect_time; 207 u32 cck_mdrdy_time; 208 u32 ofdm_mdrdy_time; 209 u32 green_mdrdy_time; 210 u32 rx_vector_mismatch_cnt; 211 u32 rx_delimiter_fail_cnt; 212 u32 rx_mrdy_cnt; 213 u32 rx_len_mismatch_cnt; 214 u32 rx_mpdu_cnt; 215 u32 rx_ampdu_cnt; 216 u32 rx_ampdu_bytes_cnt; 217 u32 rx_ampdu_valid_subframe_cnt; 218 u32 rx_ampdu_valid_subframe_bytes_cnt; 219 u32 rx_pfdrop_cnt; 220 u32 rx_vec_queue_overflow_drop_cnt; 221 u32 rx_ba_cnt; 222 223 u32 tx_amsdu[8]; 224 u32 tx_amsdu_cnt; 225 }; 226 227 struct mt7915_hif { 228 struct list_head list; 229 230 struct device *dev; 231 void __iomem *regs; 232 int irq; 233 }; 234 235 struct mt7915_phy { 236 struct mt76_phy *mt76; 237 struct mt7915_dev *dev; 238 239 struct ieee80211_sband_iftype_data iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES]; 240 241 struct ieee80211_vif *monitor_vif; 242 243 struct thermal_cooling_device *cdev; 244 u8 cdev_state; 245 u8 throttle_state; 246 u32 throttle_temp[2]; /* 0: critical high, 1: maximum */ 247 248 u32 rxfilter; 249 u64 omac_mask; 250 u8 band_idx; 251 252 u16 noise; 253 254 s16 coverage_class; 255 u8 slottime; 256 257 u8 rdd_state; 258 259 u32 trb_ts; 260 261 u32 rx_ampdu_ts; 262 u32 ampdu_ref; 263 264 struct mib_stats mib; 265 struct mt76_channel_state state_ts; 266 267 #ifdef CONFIG_NL80211_TESTMODE 268 struct { 269 u32 *reg_backup; 270 271 s32 last_freq_offset; 272 u8 last_rcpi[4]; 273 s8 last_ib_rssi[4]; 274 s8 last_wb_rssi[4]; 275 u8 last_snr; 276 277 u8 spe_idx; 278 } test; 279 #endif 280 }; 281 282 struct mt7915_dev { 283 union { /* must be first */ 284 struct mt76_dev mt76; 285 struct mt76_phy mphy; 286 }; 287 288 struct mt7915_hif *hif2; 289 struct mt7915_reg_desc reg; 290 u8 q_id[MT7915_MAX_QUEUE]; 291 u32 q_int_mask[MT7915_MAX_QUEUE]; 292 u32 wfdma_mask; 293 294 const struct mt76_bus_ops *bus_ops; 295 struct tasklet_struct irq_tasklet; 296 struct mt7915_phy phy; 297 298 /* monitor rx chain configured channel */ 299 struct cfg80211_chan_def rdd2_chandef; 300 struct mt7915_phy *rdd2_phy; 301 302 u16 chainmask; 303 u16 chainshift; 304 u32 hif_idx; 305 306 struct work_struct init_work; 307 struct work_struct rc_work; 308 struct work_struct reset_work; 309 wait_queue_head_t reset_wait; 310 311 struct { 312 u32 state; 313 u32 wa_reset_count; 314 u32 wm_reset_count; 315 bool hw_full_reset:1; 316 bool hw_init_done:1; 317 bool restart:1; 318 } recovery; 319 320 struct list_head sta_rc_list; 321 struct list_head sta_poll_list; 322 struct list_head twt_list; 323 spinlock_t sta_poll_lock; 324 325 u32 hw_pattern; 326 327 bool dbdc_support; 328 bool flash_mode; 329 bool muru_debug; 330 bool ibf; 331 332 struct dentry *debugfs_dir; 333 struct rchan *relay_fwlog; 334 335 void *cal; 336 337 struct { 338 u8 debug_wm; 339 u8 debug_wa; 340 u8 debug_bin; 341 } fw; 342 343 struct { 344 u16 table_mask; 345 u8 n_agrt; 346 } twt; 347 348 struct reset_control *rstc; 349 void __iomem *dcm; 350 void __iomem *sku; 351 }; 352 353 enum { 354 WFDMA0 = 0x0, 355 WFDMA1, 356 WFDMA_EXT, 357 __MT_WFDMA_MAX, 358 }; 359 360 enum { 361 MT_RX_SEL0, 362 MT_RX_SEL1, 363 MT_RX_SEL2, /* monitor chain */ 364 }; 365 366 enum mt7915_rdd_cmd { 367 RDD_STOP, 368 RDD_START, 369 RDD_DET_MODE, 370 RDD_RADAR_EMULATE, 371 RDD_START_TXQ = 20, 372 RDD_SET_WF_ANT = 30, 373 RDD_CAC_START = 50, 374 RDD_CAC_END, 375 RDD_NORMAL_START, 376 RDD_DISABLE_DFS_CAL, 377 RDD_PULSE_DBG, 378 RDD_READ_PULSE, 379 RDD_RESUME_BF, 380 RDD_IRQ_OFF, 381 }; 382 383 static inline struct mt7915_phy * 384 mt7915_hw_phy(struct ieee80211_hw *hw) 385 { 386 struct mt76_phy *phy = hw->priv; 387 388 return phy->priv; 389 } 390 391 static inline struct mt7915_dev * 392 mt7915_hw_dev(struct ieee80211_hw *hw) 393 { 394 struct mt76_phy *phy = hw->priv; 395 396 return container_of(phy->dev, struct mt7915_dev, mt76); 397 } 398 399 static inline struct mt7915_phy * 400 mt7915_ext_phy(struct mt7915_dev *dev) 401 { 402 struct mt76_phy *phy = dev->mt76.phys[MT_BAND1]; 403 404 if (!phy) 405 return NULL; 406 407 return phy->priv; 408 } 409 410 static inline u32 mt7915_check_adie(struct mt7915_dev *dev, bool sku) 411 { 412 u32 mask = sku ? MT_CONNINFRA_SKU_MASK : MT_ADIE_TYPE_MASK; 413 414 if (!is_mt7986(&dev->mt76)) 415 return 0; 416 417 return mt76_rr(dev, MT_CONNINFRA_SKU_DEC_ADDR) & mask; 418 } 419 420 extern const struct ieee80211_ops mt7915_ops; 421 extern const struct mt76_testmode_ops mt7915_testmode_ops; 422 extern struct pci_driver mt7915_pci_driver; 423 extern struct pci_driver mt7915_hif_driver; 424 extern struct platform_driver mt7986_wmac_driver; 425 426 #ifdef CONFIG_MT7986_WMAC 427 int mt7986_wmac_enable(struct mt7915_dev *dev); 428 void mt7986_wmac_disable(struct mt7915_dev *dev); 429 #else 430 static inline int mt7986_wmac_enable(struct mt7915_dev *dev) 431 { 432 return 0; 433 } 434 435 static inline void mt7986_wmac_disable(struct mt7915_dev *dev) 436 { 437 } 438 #endif 439 struct mt7915_dev *mt7915_mmio_probe(struct device *pdev, 440 void __iomem *mem_base, u32 device_id); 441 void mt7915_wfsys_reset(struct mt7915_dev *dev); 442 irqreturn_t mt7915_irq_handler(int irq, void *dev_instance); 443 u64 __mt7915_get_tsf(struct ieee80211_hw *hw, struct mt7915_vif *mvif); 444 u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id); 445 446 int mt7915_register_device(struct mt7915_dev *dev); 447 void mt7915_unregister_device(struct mt7915_dev *dev); 448 int mt7915_eeprom_init(struct mt7915_dev *dev); 449 void mt7915_eeprom_parse_hw_cap(struct mt7915_dev *dev, 450 struct mt7915_phy *phy); 451 int mt7915_eeprom_get_target_power(struct mt7915_dev *dev, 452 struct ieee80211_channel *chan, 453 u8 chain_idx); 454 s8 mt7915_eeprom_get_power_delta(struct mt7915_dev *dev, int band); 455 int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2); 456 void mt7915_dma_prefetch(struct mt7915_dev *dev); 457 void mt7915_dma_cleanup(struct mt7915_dev *dev); 458 int mt7915_dma_reset(struct mt7915_dev *dev, bool force); 459 int mt7915_txbf_init(struct mt7915_dev *dev); 460 void mt7915_init_txpower(struct mt7915_dev *dev, 461 struct ieee80211_supported_band *sband); 462 void mt7915_reset(struct mt7915_dev *dev); 463 int mt7915_run(struct ieee80211_hw *hw); 464 int mt7915_mcu_init(struct mt7915_dev *dev); 465 int mt7915_mcu_init_firmware(struct mt7915_dev *dev); 466 int mt7915_mcu_twt_agrt_update(struct mt7915_dev *dev, 467 struct mt7915_vif *mvif, 468 struct mt7915_twt_flow *flow, 469 int cmd); 470 int mt7915_mcu_add_dev_info(struct mt7915_phy *phy, 471 struct ieee80211_vif *vif, bool enable); 472 int mt7915_mcu_add_bss_info(struct mt7915_phy *phy, 473 struct ieee80211_vif *vif, int enable); 474 int mt7915_mcu_add_sta(struct mt7915_dev *dev, struct ieee80211_vif *vif, 475 struct ieee80211_sta *sta, bool enable); 476 int mt7915_mcu_add_tx_ba(struct mt7915_dev *dev, 477 struct ieee80211_ampdu_params *params, 478 bool add); 479 int mt7915_mcu_add_rx_ba(struct mt7915_dev *dev, 480 struct ieee80211_ampdu_params *params, 481 bool add); 482 int mt7915_mcu_update_bss_color(struct mt7915_dev *dev, struct ieee80211_vif *vif, 483 struct cfg80211_he_bss_color *he_bss_color); 484 int mt7915_mcu_add_beacon(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 485 int enable, u32 changed); 486 int mt7915_mcu_add_obss_spr(struct mt7915_dev *dev, struct ieee80211_vif *vif, 487 bool enable); 488 int mt7915_mcu_add_rate_ctrl(struct mt7915_dev *dev, struct ieee80211_vif *vif, 489 struct ieee80211_sta *sta, bool changed); 490 int mt7915_mcu_add_smps(struct mt7915_dev *dev, struct ieee80211_vif *vif, 491 struct ieee80211_sta *sta); 492 int mt7915_set_channel(struct mt7915_phy *phy); 493 int mt7915_mcu_set_chan_info(struct mt7915_phy *phy, int cmd); 494 int mt7915_mcu_set_tx(struct mt7915_dev *dev, struct ieee80211_vif *vif); 495 int mt7915_mcu_update_edca(struct mt7915_dev *dev, void *req); 496 int mt7915_mcu_set_fixed_rate_ctrl(struct mt7915_dev *dev, 497 struct ieee80211_vif *vif, 498 struct ieee80211_sta *sta, 499 void *data, u32 field); 500 int mt7915_mcu_set_eeprom(struct mt7915_dev *dev); 501 int mt7915_mcu_get_eeprom(struct mt7915_dev *dev, u32 offset); 502 int mt7915_mcu_get_eeprom_free_block(struct mt7915_dev *dev, u8 *block_num); 503 int mt7915_mcu_set_mac(struct mt7915_dev *dev, int band, bool enable, 504 bool hdr_trans); 505 int mt7915_mcu_set_test_param(struct mt7915_dev *dev, u8 param, bool test_mode, 506 u8 en); 507 int mt7915_mcu_set_ser(struct mt7915_dev *dev, u8 action, u8 set, u8 band); 508 int mt7915_mcu_set_sku_en(struct mt7915_phy *phy, bool enable); 509 int mt7915_mcu_set_txpower_sku(struct mt7915_phy *phy); 510 int mt7915_mcu_get_txpower_sku(struct mt7915_phy *phy, s8 *txpower, int len); 511 int mt7915_mcu_set_txbf(struct mt7915_dev *dev, u8 action); 512 int mt7915_mcu_set_fcc5_lpn(struct mt7915_dev *dev, int val); 513 int mt7915_mcu_set_pulse_th(struct mt7915_dev *dev, 514 const struct mt7915_dfs_pulse *pulse); 515 int mt7915_mcu_set_radar_th(struct mt7915_dev *dev, int index, 516 const struct mt7915_dfs_pattern *pattern); 517 int mt7915_mcu_set_muru_ctrl(struct mt7915_dev *dev, u32 cmd, u32 val); 518 int mt7915_mcu_apply_group_cal(struct mt7915_dev *dev); 519 int mt7915_mcu_apply_tx_dpd(struct mt7915_phy *phy); 520 int mt7915_mcu_get_chan_mib_info(struct mt7915_phy *phy, bool chan_switch); 521 int mt7915_mcu_get_temperature(struct mt7915_phy *phy); 522 int mt7915_mcu_set_thermal_throttling(struct mt7915_phy *phy, u8 state); 523 int mt7915_mcu_get_rx_rate(struct mt7915_phy *phy, struct ieee80211_vif *vif, 524 struct ieee80211_sta *sta, struct rate_info *rate); 525 int mt7915_mcu_rdd_background_enable(struct mt7915_phy *phy, 526 struct cfg80211_chan_def *chandef); 527 int mt7915_mcu_rf_regval(struct mt7915_dev *dev, u32 regidx, u32 *val, bool set); 528 int mt7915_mcu_wa_cmd(struct mt7915_dev *dev, int cmd, u32 a1, u32 a2, u32 a3); 529 int mt7915_mcu_fw_log_2_host(struct mt7915_dev *dev, u8 type, u8 ctrl); 530 int mt7915_mcu_fw_dbg_ctrl(struct mt7915_dev *dev, u32 module, u8 level); 531 void mt7915_mcu_rx_event(struct mt7915_dev *dev, struct sk_buff *skb); 532 void mt7915_mcu_exit(struct mt7915_dev *dev); 533 534 static inline u16 mt7915_wtbl_size(struct mt7915_dev *dev) 535 { 536 return is_mt7915(&dev->mt76) ? MT7915_WTBL_SIZE : MT7916_WTBL_SIZE; 537 } 538 539 static inline u16 mt7915_eeprom_size(struct mt7915_dev *dev) 540 { 541 return is_mt7915(&dev->mt76) ? MT7915_EEPROM_SIZE : MT7916_EEPROM_SIZE; 542 } 543 544 void mt7915_dual_hif_set_irq_mask(struct mt7915_dev *dev, bool write_reg, 545 u32 clear, u32 set); 546 547 static inline void mt7915_irq_enable(struct mt7915_dev *dev, u32 mask) 548 { 549 if (dev->hif2) 550 mt7915_dual_hif_set_irq_mask(dev, false, 0, mask); 551 else 552 mt76_set_irq_mask(&dev->mt76, 0, 0, mask); 553 554 tasklet_schedule(&dev->irq_tasklet); 555 } 556 557 static inline void mt7915_irq_disable(struct mt7915_dev *dev, u32 mask) 558 { 559 if (dev->hif2) 560 mt7915_dual_hif_set_irq_mask(dev, true, mask, 0); 561 else 562 mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0); 563 } 564 565 void mt7915_mac_init(struct mt7915_dev *dev); 566 u32 mt7915_mac_wtbl_lmac_addr(struct mt7915_dev *dev, u16 wcid, u8 dw); 567 bool mt7915_mac_wtbl_update(struct mt7915_dev *dev, int idx, u32 mask); 568 void mt7915_mac_reset_counters(struct mt7915_phy *phy); 569 void mt7915_mac_cca_stats_reset(struct mt7915_phy *phy); 570 void mt7915_mac_enable_nf(struct mt7915_dev *dev, bool ext_phy); 571 void mt7915_mac_enable_rtscts(struct mt7915_dev *dev, 572 struct ieee80211_vif *vif, bool enable); 573 void mt7915_mac_write_txwi(struct mt76_dev *dev, __le32 *txwi, 574 struct sk_buff *skb, struct mt76_wcid *wcid, int pid, 575 struct ieee80211_key_conf *key, 576 enum mt76_txq_id qid, u32 changed); 577 void mt7915_mac_set_timing(struct mt7915_phy *phy); 578 int mt7915_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif, 579 struct ieee80211_sta *sta); 580 void mt7915_mac_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif, 581 struct ieee80211_sta *sta); 582 void mt7915_mac_work(struct work_struct *work); 583 void mt7915_mac_reset_work(struct work_struct *work); 584 void mt7915_mac_sta_rc_work(struct work_struct *work); 585 void mt7915_mac_update_stats(struct mt7915_phy *phy); 586 void mt7915_mac_twt_teardown_flow(struct mt7915_dev *dev, 587 struct mt7915_sta *msta, 588 u8 flowid); 589 void mt7915_mac_add_twt_setup(struct ieee80211_hw *hw, 590 struct ieee80211_sta *sta, 591 struct ieee80211_twt_setup *twt); 592 int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, 593 enum mt76_txq_id qid, struct mt76_wcid *wcid, 594 struct ieee80211_sta *sta, 595 struct mt76_tx_info *tx_info); 596 void mt7915_tx_token_put(struct mt7915_dev *dev); 597 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 598 struct sk_buff *skb); 599 bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len); 600 void mt7915_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps); 601 void mt7915_stats_work(struct work_struct *work); 602 int mt76_dfs_start_rdd(struct mt7915_dev *dev, bool force); 603 int mt7915_dfs_init_radar_detector(struct mt7915_phy *phy); 604 void mt7915_set_stream_he_caps(struct mt7915_phy *phy); 605 void mt7915_set_stream_vht_txbf_caps(struct mt7915_phy *phy); 606 void mt7915_update_channel(struct mt76_phy *mphy); 607 int mt7915_mcu_muru_debug_set(struct mt7915_dev *dev, bool enable); 608 int mt7915_mcu_muru_debug_get(struct mt7915_phy *phy, void *ms); 609 int mt7915_init_debugfs(struct mt7915_phy *phy); 610 void mt7915_debugfs_rx_fw_monitor(struct mt7915_dev *dev, const void *data, int len); 611 bool mt7915_debugfs_rx_log(struct mt7915_dev *dev, const void *data, int len); 612 #ifdef CONFIG_MAC80211_DEBUGFS 613 void mt7915_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 614 struct ieee80211_sta *sta, struct dentry *dir); 615 #endif 616 int mt7915_mmio_wed_init(struct mt7915_dev *dev, void *pdev_ptr, 617 bool pci, int *irq); 618 619 #endif 620