1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include "mt7915.h" 5 6 static u32 mt7915_reg_map_l1(struct mt7915_dev *dev, u32 addr) 7 { 8 u32 offset = FIELD_GET(MT_HIF_REMAP_L1_OFFSET, addr); 9 u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, addr); 10 11 mt76_rmw_field(dev, MT_HIF_REMAP_L1, MT_HIF_REMAP_L1_MASK, base); 12 /* use read to push write */ 13 mt76_rr(dev, MT_HIF_REMAP_L1); 14 15 return MT_HIF_REMAP_BASE_L1 + offset; 16 } 17 18 static u32 mt7915_reg_map_l2(struct mt7915_dev *dev, u32 addr) 19 { 20 u32 offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET, addr); 21 u32 base = FIELD_GET(MT_HIF_REMAP_L2_BASE, addr); 22 23 mt76_rmw_field(dev, MT_HIF_REMAP_L2, MT_HIF_REMAP_L2_MASK, base); 24 /* use read to push write */ 25 mt76_rr(dev, MT_HIF_REMAP_L2); 26 27 return MT_HIF_REMAP_BASE_L2 + offset; 28 } 29 30 static u32 __mt7915_reg_addr(struct mt7915_dev *dev, u32 addr) 31 { 32 static const struct { 33 u32 phys; 34 u32 mapped; 35 u32 size; 36 } fixed_map[] = { 37 { 0x54000000, 0x02000, 0x1000 }, /* WFDMA PCIE0 MCU DMA0 */ 38 { 0x55000000, 0x03000, 0x1000 }, /* WFDMA PCIE0 MCU DMA1 */ 39 { 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */ 40 { 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */ 41 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */ 42 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */ 43 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */ 44 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */ 45 { 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */ 46 { 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */ 47 { 0x820cc000, 0x0e000, 0x2000 }, /* WF_UMAC_TOP (PP) */ 48 { 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */ 49 { 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */ 50 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ 51 { 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */ 52 { 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */ 53 { 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ 54 { 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */ 55 { 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ 56 { 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */ 57 { 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ 58 { 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ 59 { 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */ 60 { 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ 61 { 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */ 62 { 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ 63 { 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */ 64 { 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */ 65 { 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */ 66 { 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */ 67 { 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */ 68 { 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */ 69 { 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */ 70 { 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ 71 { 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */ 72 { 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */ 73 { 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */ 74 { 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */ 75 }; 76 int i; 77 78 if (addr < 0x100000) 79 return addr; 80 81 for (i = 0; i < ARRAY_SIZE(fixed_map); i++) { 82 u32 ofs; 83 84 if (addr < fixed_map[i].phys) 85 continue; 86 87 ofs = addr - fixed_map[i].phys; 88 if (ofs > fixed_map[i].size) 89 continue; 90 91 return fixed_map[i].mapped + ofs; 92 } 93 94 if ((addr >= 0x18000000 && addr < 0x18c00000) || 95 (addr >= 0x70000000 && addr < 0x78000000) || 96 (addr >= 0x7c000000 && addr < 0x7c400000)) 97 return mt7915_reg_map_l1(dev, addr); 98 99 return mt7915_reg_map_l2(dev, addr); 100 } 101 102 static u32 mt7915_rr(struct mt76_dev *mdev, u32 offset) 103 { 104 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 105 u32 addr = __mt7915_reg_addr(dev, offset); 106 107 return dev->bus_ops->rr(mdev, addr); 108 } 109 110 static void mt7915_wr(struct mt76_dev *mdev, u32 offset, u32 val) 111 { 112 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 113 u32 addr = __mt7915_reg_addr(dev, offset); 114 115 dev->bus_ops->wr(mdev, addr, val); 116 } 117 118 static u32 mt7915_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val) 119 { 120 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 121 u32 addr = __mt7915_reg_addr(dev, offset); 122 123 return dev->bus_ops->rmw(mdev, addr, mask, val); 124 } 125 126 int mt7915_mmio_init(struct mt76_dev *mdev, void __iomem *mem_base, int irq) 127 { 128 struct mt76_bus_ops *bus_ops; 129 struct mt7915_dev *dev; 130 131 dev = container_of(mdev, struct mt7915_dev, mt76); 132 mt76_mmio_init(&dev->mt76, mem_base); 133 134 dev->bus_ops = dev->mt76.bus; 135 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops), 136 GFP_KERNEL); 137 if (!bus_ops) 138 return -ENOMEM; 139 140 bus_ops->rr = mt7915_rr; 141 bus_ops->wr = mt7915_wr; 142 bus_ops->rmw = mt7915_rmw; 143 dev->mt76.bus = bus_ops; 144 145 mdev->rev = (mt76_rr(dev, MT_HW_CHIPID) << 16) | 146 (mt76_rr(dev, MT_HW_REV) & 0xff); 147 dev_dbg(mdev->dev, "ASIC revision: %04x\n", mdev->rev); 148 149 mt76_wr(dev, MT_INT_MASK_CSR, 0); 150 151 return 0; 152 } 153