1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #ifndef __MT7915_MCU_H 5 #define __MT7915_MCU_H 6 7 struct mt7915_mcu_txd { 8 __le32 txd[8]; 9 10 __le16 len; 11 __le16 pq_id; 12 13 u8 cid; 14 u8 pkt_type; 15 u8 set_query; /* FW don't care */ 16 u8 seq; 17 18 u8 uc_d2b0_rev; 19 u8 ext_cid; 20 u8 s2d_index; 21 u8 ext_cid_ack; 22 23 u32 reserved[5]; 24 } __packed __aligned(4); 25 26 /* event table */ 27 enum { 28 MCU_EVENT_TARGET_ADDRESS_LEN = 0x01, 29 MCU_EVENT_FW_START = 0x01, 30 MCU_EVENT_GENERIC = 0x01, 31 MCU_EVENT_ACCESS_REG = 0x02, 32 MCU_EVENT_MT_PATCH_SEM = 0x04, 33 MCU_EVENT_CH_PRIVILEGE = 0x18, 34 MCU_EVENT_EXT = 0xed, 35 MCU_EVENT_RESTART_DL = 0xef, 36 }; 37 38 /* ext event table */ 39 enum { 40 MCU_EXT_EVENT_PS_SYNC = 0x5, 41 MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13, 42 MCU_EXT_EVENT_THERMAL_PROTECT = 0x22, 43 MCU_EXT_EVENT_ASSERT_DUMP = 0x23, 44 MCU_EXT_EVENT_RDD_REPORT = 0x3a, 45 MCU_EXT_EVENT_CSA_NOTIFY = 0x4f, 46 MCU_EXT_EVENT_BCC_NOTIFY = 0x75, 47 }; 48 49 enum { 50 MCU_ATE_SET_TRX = 0x1, 51 MCU_ATE_SET_FREQ_OFFSET = 0xa, 52 MCU_ATE_SET_SLOT_TIME = 0x13, 53 MCU_ATE_CLEAN_TXQUEUE = 0x1c, 54 }; 55 56 struct mt7915_mcu_rxd { 57 __le32 rxd[6]; 58 59 __le16 len; 60 __le16 pkt_type_id; 61 62 u8 eid; 63 u8 seq; 64 __le16 __rsv; 65 66 u8 ext_eid; 67 u8 __rsv1[2]; 68 u8 s2d_index; 69 }; 70 71 struct mt7915_mcu_thermal_ctrl { 72 u8 ctrl_id; 73 u8 band_idx; 74 union { 75 struct { 76 u8 protect_type; /* 1: duty admit, 2: radio off */ 77 u8 trigger_type; /* 0: low, 1: high */ 78 } __packed type; 79 struct { 80 u8 duty_level; /* level 0~3 */ 81 u8 duty_cycle; 82 } __packed duty; 83 }; 84 } __packed; 85 86 struct mt7915_mcu_thermal_notify { 87 struct mt7915_mcu_rxd rxd; 88 89 struct mt7915_mcu_thermal_ctrl ctrl; 90 __le32 temperature; 91 u8 rsv[8]; 92 } __packed; 93 94 struct mt7915_mcu_csa_notify { 95 struct mt7915_mcu_rxd rxd; 96 97 u8 omac_idx; 98 u8 csa_count; 99 u8 band_idx; 100 u8 rsv; 101 } __packed; 102 103 struct mt7915_mcu_rdd_report { 104 struct mt7915_mcu_rxd rxd; 105 106 u8 band_idx; 107 u8 long_detected; 108 u8 constant_prf_detected; 109 u8 staggered_prf_detected; 110 u8 radar_type_idx; 111 u8 periodic_pulse_num; 112 u8 long_pulse_num; 113 u8 hw_pulse_num; 114 115 u8 out_lpn; 116 u8 out_spn; 117 u8 out_crpn; 118 u8 out_crpw; 119 u8 out_crbn; 120 u8 out_stgpn; 121 u8 out_stgpw; 122 123 u8 rsv; 124 125 __le32 out_pri_const; 126 __le32 out_pri_stg[3]; 127 128 struct { 129 __le32 start; 130 __le16 pulse_width; 131 __le16 pulse_power; 132 u8 mdrdy_flag; 133 u8 rsv[3]; 134 } long_pulse[32]; 135 136 struct { 137 __le32 start; 138 __le16 pulse_width; 139 __le16 pulse_power; 140 u8 mdrdy_flag; 141 u8 rsv[3]; 142 } periodic_pulse[32]; 143 144 struct { 145 __le32 start; 146 __le16 pulse_width; 147 __le16 pulse_power; 148 u8 sc_pass; 149 u8 sw_reset; 150 u8 mdrdy_flag; 151 u8 tx_active; 152 } hw_pulse[32]; 153 } __packed; 154 155 struct mt7915_mcu_eeprom { 156 u8 buffer_mode; 157 u8 format; 158 __le16 len; 159 } __packed; 160 161 struct mt7915_mcu_eeprom_info { 162 __le32 addr; 163 __le32 valid; 164 u8 data[16]; 165 } __packed; 166 167 struct mt7915_mcu_phy_rx_info { 168 u8 category; 169 u8 rate; 170 u8 mode; 171 u8 nsts; 172 u8 gi; 173 u8 coding; 174 u8 stbc; 175 u8 bw; 176 }; 177 178 struct mt7915_mcu_mib { 179 __le32 band; 180 __le32 offs; 181 __le64 data; 182 } __packed; 183 184 enum mt7915_chan_mib_offs { 185 MIB_BUSY_TIME = 14, 186 MIB_TX_TIME = 81, 187 MIB_RX_TIME, 188 MIB_OBSS_AIRTIME = 86 189 }; 190 191 struct edca { 192 u8 queue; 193 u8 set; 194 u8 aifs; 195 u8 cw_min; 196 __le16 cw_max; 197 __le16 txop; 198 }; 199 200 struct mt7915_mcu_tx { 201 u8 total; 202 u8 action; 203 u8 valid; 204 u8 mode; 205 206 struct edca edca[IEEE80211_NUM_ACS]; 207 } __packed; 208 209 #define WMM_AIFS_SET BIT(0) 210 #define WMM_CW_MIN_SET BIT(1) 211 #define WMM_CW_MAX_SET BIT(2) 212 #define WMM_TXOP_SET BIT(3) 213 #define WMM_PARAM_SET GENMASK(3, 0) 214 215 #define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10)) 216 #define MCU_PKT_ID 0xa0 217 218 enum { 219 MCU_Q_QUERY, 220 MCU_Q_SET, 221 MCU_Q_RESERVED, 222 MCU_Q_NA 223 }; 224 225 enum { 226 MCU_S2D_H2N, 227 MCU_S2D_C2N, 228 MCU_S2D_H2C, 229 MCU_S2D_H2CN 230 }; 231 232 233 #define __MCU_CMD_FIELD_ID GENMASK(7, 0) 234 #define __MCU_CMD_FIELD_EXT_ID GENMASK(15, 8) 235 #define __MCU_CMD_FIELD_QUERY BIT(16) 236 #define __MCU_CMD_FIELD_WA BIT(17) 237 238 enum { 239 MCU_CMD_TARGET_ADDRESS_LEN_REQ = 0x01, 240 MCU_CMD_FW_START_REQ = 0x02, 241 MCU_CMD_INIT_ACCESS_REG = 0x3, 242 MCU_CMD_NIC_POWER_CTRL = 0x4, 243 MCU_CMD_PATCH_START_REQ = 0x05, 244 MCU_CMD_PATCH_FINISH_REQ = 0x07, 245 MCU_CMD_PATCH_SEM_CONTROL = 0x10, 246 MCU_CMD_WA_PARAM = 0xC4, 247 MCU_CMD_EXT_CID = 0xED, 248 MCU_CMD_FW_SCATTER = 0xEE, 249 MCU_CMD_RESTART_DL_REQ = 0xEF, 250 }; 251 252 enum { 253 MCU_EXT_CMD_EFUSE_ACCESS = 0x01, 254 MCU_EXT_CMD_RF_TEST = 0x04, 255 MCU_EXT_CMD_PM_STATE_CTRL = 0x07, 256 MCU_EXT_CMD_CHANNEL_SWITCH = 0x08, 257 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13, 258 MCU_EXT_CMD_TXBF_ACTION = 0x1e, 259 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21, 260 MCU_EXT_CMD_THERMAL_PROT = 0x23, 261 MCU_EXT_CMD_STA_REC_UPDATE = 0x25, 262 MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26, 263 MCU_EXT_CMD_EDCA_UPDATE = 0x27, 264 MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A, 265 MCU_EXT_CMD_THERMAL_CTRL = 0x2c, 266 MCU_EXT_CMD_WTBL_UPDATE = 0x32, 267 MCU_EXT_CMD_SET_DRR_CTRL = 0x36, 268 MCU_EXT_CMD_SET_RDD_CTRL = 0x3a, 269 MCU_EXT_CMD_ATE_CTRL = 0x3d, 270 MCU_EXT_CMD_PROTECT_CTRL = 0x3e, 271 MCU_EXT_CMD_MAC_INIT_CTRL = 0x46, 272 MCU_EXT_CMD_RX_HDR_TRANS = 0x47, 273 MCU_EXT_CMD_MUAR_UPDATE = 0x48, 274 MCU_EXT_CMD_RX_AIRTIME_CTRL = 0x4a, 275 MCU_EXT_CMD_SET_RX_PATH = 0x4e, 276 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58, 277 MCU_EXT_CMD_GET_MIB_INFO = 0x5a, 278 MCU_EXT_CMD_MWDS_SUPPORT = 0x80, 279 MCU_EXT_CMD_SET_SER_TRIGGER = 0x81, 280 MCU_EXT_CMD_SCS_CTRL = 0x82, 281 MCU_EXT_CMD_TWT_AGRT_UPDATE = 0x94, 282 MCU_EXT_CMD_FW_DBG_CTRL = 0x95, 283 MCU_EXT_CMD_SET_RDD_TH = 0x9d, 284 MCU_EXT_CMD_MURU_CTRL = 0x9f, 285 MCU_EXT_CMD_SET_SPR = 0xa8, 286 MCU_EXT_CMD_GROUP_PRE_CAL_INFO = 0xab, 287 MCU_EXT_CMD_DPD_PRE_CAL_INFO = 0xac, 288 MCU_EXT_CMD_PHY_STAT_INFO = 0xad, 289 }; 290 291 enum { 292 MCU_TWT_AGRT_ADD, 293 MCU_TWT_AGRT_MODIFY, 294 MCU_TWT_AGRT_DELETE, 295 MCU_TWT_AGRT_TEARDOWN, 296 MCU_TWT_AGRT_GET_TSF, 297 }; 298 299 enum { 300 MCU_WA_PARAM_CMD_QUERY, 301 MCU_WA_PARAM_CMD_SET, 302 MCU_WA_PARAM_CMD_CAPABILITY, 303 MCU_WA_PARAM_CMD_DEBUG, 304 }; 305 306 enum { 307 MCU_WA_PARAM_RED = 0x0e, 308 }; 309 310 #define MCU_CMD(_t) FIELD_PREP(__MCU_CMD_FIELD_ID, MCU_CMD_##_t) 311 #define MCU_EXT_CMD(_t) (MCU_CMD(EXT_CID) | \ 312 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \ 313 MCU_EXT_CMD_##_t)) 314 #define MCU_EXT_QUERY(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_QUERY) 315 316 #define MCU_WA_CMD(_t) (MCU_CMD(_t) | __MCU_CMD_FIELD_WA) 317 #define MCU_WA_EXT_CMD(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_WA) 318 #define MCU_WA_PARAM_CMD(_t) (MCU_WA_CMD(WA_PARAM) | \ 319 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \ 320 MCU_WA_PARAM_CMD_##_t)) 321 322 enum { 323 PATCH_SEM_RELEASE, 324 PATCH_SEM_GET 325 }; 326 327 enum { 328 PATCH_NOT_DL_SEM_FAIL, 329 PATCH_IS_DL, 330 PATCH_NOT_DL_SEM_SUCCESS, 331 PATCH_REL_SEM_SUCCESS 332 }; 333 334 enum { 335 FW_STATE_INITIAL, 336 FW_STATE_FW_DOWNLOAD, 337 FW_STATE_NORMAL_OPERATION, 338 FW_STATE_NORMAL_TRX, 339 FW_STATE_WACPU_RDY = 7 340 }; 341 342 enum { 343 EE_MODE_EFUSE, 344 EE_MODE_BUFFER, 345 }; 346 347 enum { 348 EE_FORMAT_BIN, 349 EE_FORMAT_WHOLE, 350 EE_FORMAT_MULTIPLE, 351 }; 352 353 enum { 354 MCU_PHY_STATE_TX_RATE, 355 MCU_PHY_STATE_RX_RATE, 356 MCU_PHY_STATE_RSSI, 357 MCU_PHY_STATE_CONTENTION_RX_RATE, 358 MCU_PHY_STATE_OFDMLQ_CNINFO, 359 }; 360 361 #define STA_TYPE_STA BIT(0) 362 #define STA_TYPE_AP BIT(1) 363 #define STA_TYPE_ADHOC BIT(2) 364 #define STA_TYPE_WDS BIT(4) 365 #define STA_TYPE_BC BIT(5) 366 367 #define NETWORK_INFRA BIT(16) 368 #define NETWORK_P2P BIT(17) 369 #define NETWORK_IBSS BIT(18) 370 #define NETWORK_WDS BIT(21) 371 372 #define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA) 373 #define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA) 374 #define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P) 375 #define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P) 376 #define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS) 377 #define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS) 378 #define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA) 379 380 #define CONN_STATE_DISCONNECT 0 381 #define CONN_STATE_CONNECT 1 382 #define CONN_STATE_PORT_SECURE 2 383 384 enum { 385 DEV_INFO_ACTIVE, 386 DEV_INFO_MAX_NUM 387 }; 388 389 enum { 390 SCS_SEND_DATA, 391 SCS_SET_MANUAL_PD_TH, 392 SCS_CONFIG, 393 SCS_ENABLE, 394 SCS_SHOW_INFO, 395 SCS_GET_GLO_ADDR, 396 SCS_GET_GLO_ADDR_EVENT, 397 }; 398 399 enum { 400 CMD_CBW_20MHZ = IEEE80211_STA_RX_BW_20, 401 CMD_CBW_40MHZ = IEEE80211_STA_RX_BW_40, 402 CMD_CBW_80MHZ = IEEE80211_STA_RX_BW_80, 403 CMD_CBW_160MHZ = IEEE80211_STA_RX_BW_160, 404 CMD_CBW_10MHZ, 405 CMD_CBW_5MHZ, 406 CMD_CBW_8080MHZ, 407 408 CMD_HE_MCS_BW80 = 0, 409 CMD_HE_MCS_BW160, 410 CMD_HE_MCS_BW8080, 411 CMD_HE_MCS_BW_NUM 412 }; 413 414 struct tlv { 415 __le16 tag; 416 __le16 len; 417 } __packed; 418 419 struct bss_info_omac { 420 __le16 tag; 421 __le16 len; 422 u8 hw_bss_idx; 423 u8 omac_idx; 424 u8 band_idx; 425 u8 rsv0; 426 __le32 conn_type; 427 u32 rsv1; 428 } __packed; 429 430 struct bss_info_basic { 431 __le16 tag; 432 __le16 len; 433 __le32 network_type; 434 u8 active; 435 u8 rsv0; 436 __le16 bcn_interval; 437 u8 bssid[ETH_ALEN]; 438 u8 wmm_idx; 439 u8 dtim_period; 440 u8 bmc_wcid_lo; 441 u8 cipher; 442 u8 phy_mode; 443 u8 max_bssid; /* max BSSID. range: 1 ~ 8, 0: MBSSID disabled */ 444 u8 non_tx_bssid;/* non-transmitted BSSID, 0: transmitted BSSID */ 445 u8 bmc_wcid_hi; /* high Byte and version */ 446 u8 rsv[2]; 447 } __packed; 448 449 struct bss_info_rf_ch { 450 __le16 tag; 451 __le16 len; 452 u8 pri_ch; 453 u8 center_ch0; 454 u8 center_ch1; 455 u8 bw; 456 u8 he_ru26_block; /* 1: don't send HETB in RU26, 0: allow */ 457 u8 he_all_disable; /* 1: disallow all HETB, 0: allow */ 458 u8 rsv[2]; 459 } __packed; 460 461 struct bss_info_ext_bss { 462 __le16 tag; 463 __le16 len; 464 __le32 mbss_tsf_offset; /* in unit of us */ 465 u8 rsv[8]; 466 } __packed; 467 468 struct bss_info_bmc_rate { 469 __le16 tag; 470 __le16 len; 471 __le16 bc_trans; 472 __le16 mc_trans; 473 u8 short_preamble; 474 u8 rsv[7]; 475 } __packed; 476 477 struct bss_info_ra { 478 __le16 tag; 479 __le16 len; 480 u8 op_mode; 481 u8 adhoc_en; 482 u8 short_preamble; 483 u8 tx_streams; 484 u8 rx_streams; 485 u8 algo; 486 u8 force_sgi; 487 u8 force_gf; 488 u8 ht_mode; 489 u8 has_20_sta; /* Check if any sta support GF. */ 490 u8 bss_width_trigger_events; 491 u8 vht_nss_cap; 492 u8 vht_bw_signal; /* not use */ 493 u8 vht_force_sgi; /* not use */ 494 u8 se_off; 495 u8 antenna_idx; 496 u8 train_up_rule; 497 u8 rsv[3]; 498 unsigned short train_up_high_thres; 499 short train_up_rule_rssi; 500 unsigned short low_traffic_thres; 501 __le16 max_phyrate; 502 __le32 phy_cap; 503 __le32 interval; 504 __le32 fast_interval; 505 } __packed; 506 507 struct bss_info_hw_amsdu { 508 __le16 tag; 509 __le16 len; 510 __le32 cmp_bitmap_0; 511 __le32 cmp_bitmap_1; 512 __le16 trig_thres; 513 u8 enable; 514 u8 rsv; 515 } __packed; 516 517 struct bss_info_color { 518 __le16 tag; 519 __le16 len; 520 u8 disable; 521 u8 color; 522 u8 rsv[2]; 523 } __packed; 524 525 struct bss_info_he { 526 __le16 tag; 527 __le16 len; 528 u8 he_pe_duration; 529 u8 vht_op_info_present; 530 __le16 he_rts_thres; 531 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 532 u8 rsv[6]; 533 } __packed; 534 535 struct bss_info_bcn { 536 __le16 tag; 537 __le16 len; 538 u8 ver; 539 u8 enable; 540 __le16 sub_ntlv; 541 } __packed __aligned(4); 542 543 struct bss_info_bcn_cntdwn { 544 __le16 tag; 545 __le16 len; 546 u8 cnt; 547 u8 rsv[3]; 548 } __packed __aligned(4); 549 550 struct bss_info_bcn_mbss { 551 #define MAX_BEACON_NUM 32 552 __le16 tag; 553 __le16 len; 554 __le32 bitmap; 555 __le16 offset[MAX_BEACON_NUM]; 556 u8 rsv[8]; 557 } __packed __aligned(4); 558 559 struct bss_info_bcn_cont { 560 __le16 tag; 561 __le16 len; 562 __le16 tim_ofs; 563 __le16 csa_ofs; 564 __le16 bcc_ofs; 565 __le16 pkt_len; 566 } __packed __aligned(4); 567 568 enum { 569 BSS_INFO_BCN_CSA, 570 BSS_INFO_BCN_BCC, 571 BSS_INFO_BCN_MBSSID, 572 BSS_INFO_BCN_CONTENT, 573 BSS_INFO_BCN_MAX 574 }; 575 576 enum { 577 BSS_INFO_OMAC, 578 BSS_INFO_BASIC, 579 BSS_INFO_RF_CH, /* optional, for BT/LTE coex */ 580 BSS_INFO_PM, /* sta only */ 581 BSS_INFO_UAPSD, /* sta only */ 582 BSS_INFO_ROAM_DETECT, /* obsoleted */ 583 BSS_INFO_LQ_RM, /* obsoleted */ 584 BSS_INFO_EXT_BSS, 585 BSS_INFO_BMC_RATE, /* for bmc rate control in CR4 */ 586 BSS_INFO_SYNC_MODE, /* obsoleted */ 587 BSS_INFO_RA, 588 BSS_INFO_HW_AMSDU, 589 BSS_INFO_BSS_COLOR, 590 BSS_INFO_HE_BASIC, 591 BSS_INFO_PROTECT_INFO, 592 BSS_INFO_OFFLOAD, 593 BSS_INFO_11V_MBSSID, 594 BSS_INFO_MAX_NUM 595 }; 596 597 enum { 598 WTBL_RESET_AND_SET = 1, 599 WTBL_SET, 600 WTBL_QUERY, 601 WTBL_RESET_ALL 602 }; 603 604 struct wtbl_req_hdr { 605 u8 wlan_idx_lo; 606 u8 operation; 607 __le16 tlv_num; 608 u8 wlan_idx_hi; 609 u8 rsv[3]; 610 } __packed; 611 612 struct wtbl_generic { 613 __le16 tag; 614 __le16 len; 615 u8 peer_addr[ETH_ALEN]; 616 u8 muar_idx; 617 u8 skip_tx; 618 u8 cf_ack; 619 u8 qos; 620 u8 mesh; 621 u8 adm; 622 __le16 partial_aid; 623 u8 baf_en; 624 u8 aad_om; 625 } __packed; 626 627 struct wtbl_rx { 628 __le16 tag; 629 __le16 len; 630 u8 rcid; 631 u8 rca1; 632 u8 rca2; 633 u8 rv; 634 u8 rsv[4]; 635 } __packed; 636 637 struct wtbl_ht { 638 __le16 tag; 639 __le16 len; 640 u8 ht; 641 u8 ldpc; 642 u8 af; 643 u8 mm; 644 u8 rsv[4]; 645 } __packed; 646 647 struct wtbl_vht { 648 __le16 tag; 649 __le16 len; 650 u8 ldpc; 651 u8 dyn_bw; 652 u8 vht; 653 u8 txop_ps; 654 u8 rsv[4]; 655 } __packed; 656 657 struct wtbl_hdr_trans { 658 __le16 tag; 659 __le16 len; 660 u8 to_ds; 661 u8 from_ds; 662 u8 no_rx_trans; 663 u8 _rsv; 664 }; 665 666 enum { 667 MT_BA_TYPE_INVALID, 668 MT_BA_TYPE_ORIGINATOR, 669 MT_BA_TYPE_RECIPIENT 670 }; 671 672 enum { 673 RST_BA_MAC_TID_MATCH, 674 RST_BA_MAC_MATCH, 675 RST_BA_NO_MATCH 676 }; 677 678 struct wtbl_ba { 679 __le16 tag; 680 __le16 len; 681 /* common */ 682 u8 tid; 683 u8 ba_type; 684 u8 rsv0[2]; 685 /* originator only */ 686 __le16 sn; 687 u8 ba_en; 688 u8 ba_winsize_idx; 689 /* originator & recipient */ 690 __le16 ba_winsize; 691 /* recipient only */ 692 u8 peer_addr[ETH_ALEN]; 693 u8 rst_ba_tid; 694 u8 rst_ba_sel; 695 u8 rst_ba_sb; 696 u8 band_idx; 697 u8 rsv1[4]; 698 } __packed; 699 700 struct wtbl_smps { 701 __le16 tag; 702 __le16 len; 703 u8 smps; 704 u8 rsv[3]; 705 } __packed; 706 707 enum { 708 WTBL_GENERIC, 709 WTBL_RX, 710 WTBL_HT, 711 WTBL_VHT, 712 WTBL_PEER_PS, /* not used */ 713 WTBL_TX_PS, 714 WTBL_HDR_TRANS, 715 WTBL_SEC_KEY, 716 WTBL_BA, 717 WTBL_RDG, /* obsoleted */ 718 WTBL_PROTECT, /* not used */ 719 WTBL_CLEAR, /* not used */ 720 WTBL_BF, 721 WTBL_SMPS, 722 WTBL_RAW_DATA, /* debug only */ 723 WTBL_PN, 724 WTBL_SPE, 725 WTBL_MAX_NUM 726 }; 727 728 struct sta_ntlv_hdr { 729 u8 rsv[2]; 730 __le16 tlv_num; 731 } __packed; 732 733 struct sta_req_hdr { 734 u8 bss_idx; 735 u8 wlan_idx_lo; 736 __le16 tlv_num; 737 u8 is_tlv_append; 738 u8 muar_idx; 739 u8 wlan_idx_hi; 740 u8 rsv; 741 } __packed; 742 743 struct sta_rec_basic { 744 __le16 tag; 745 __le16 len; 746 __le32 conn_type; 747 u8 conn_state; 748 u8 qos; 749 __le16 aid; 750 u8 peer_addr[ETH_ALEN]; 751 __le16 extra_info; 752 } __packed; 753 754 struct sta_rec_ht { 755 __le16 tag; 756 __le16 len; 757 __le16 ht_cap; 758 u16 rsv; 759 } __packed; 760 761 struct sta_rec_vht { 762 __le16 tag; 763 __le16 len; 764 __le32 vht_cap; 765 __le16 vht_rx_mcs_map; 766 __le16 vht_tx_mcs_map; 767 u8 rts_bw_sig; 768 u8 rsv[3]; 769 } __packed; 770 771 struct sta_rec_uapsd { 772 __le16 tag; 773 __le16 len; 774 u8 dac_map; 775 u8 tac_map; 776 u8 max_sp; 777 u8 rsv0; 778 __le16 listen_interval; 779 u8 rsv1[2]; 780 } __packed; 781 782 struct sta_rec_muru { 783 __le16 tag; 784 __le16 len; 785 786 struct { 787 bool ofdma_dl_en; 788 bool ofdma_ul_en; 789 bool mimo_dl_en; 790 bool mimo_ul_en; 791 u8 rsv[4]; 792 } cfg; 793 794 struct { 795 u8 punc_pream_rx; 796 bool he_20m_in_40m_2g; 797 bool he_20m_in_160m; 798 bool he_80m_in_160m; 799 bool lt16_sigb; 800 bool rx_su_comp_sigb; 801 bool rx_su_non_comp_sigb; 802 u8 rsv; 803 } ofdma_dl; 804 805 struct { 806 u8 t_frame_dur; 807 u8 mu_cascading; 808 u8 uo_ra; 809 u8 he_2x996_tone; 810 u8 rx_t_frame_11ac; 811 u8 rsv[3]; 812 } ofdma_ul; 813 814 struct { 815 bool vht_mu_bfee; 816 bool partial_bw_dl_mimo; 817 u8 rsv[2]; 818 } mimo_dl; 819 820 struct { 821 bool full_ul_mimo; 822 bool partial_ul_mimo; 823 u8 rsv[2]; 824 } mimo_ul; 825 } __packed; 826 827 struct sta_rec_he { 828 __le16 tag; 829 __le16 len; 830 831 __le32 he_cap; 832 833 u8 t_frame_dur; 834 u8 max_ampdu_exp; 835 u8 bw_set; 836 u8 device_class; 837 u8 dcm_tx_mode; 838 u8 dcm_tx_max_nss; 839 u8 dcm_rx_mode; 840 u8 dcm_rx_max_nss; 841 u8 dcm_max_ru; 842 u8 punc_pream_rx; 843 u8 pkt_ext; 844 u8 rsv1; 845 846 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 847 848 u8 rsv2[2]; 849 } __packed; 850 851 struct sta_rec_ba { 852 __le16 tag; 853 __le16 len; 854 u8 tid; 855 u8 ba_type; 856 u8 amsdu; 857 u8 ba_en; 858 __le16 ssn; 859 __le16 winsize; 860 } __packed; 861 862 struct sta_rec_amsdu { 863 __le16 tag; 864 __le16 len; 865 u8 max_amsdu_num; 866 u8 max_mpdu_size; 867 u8 amsdu_en; 868 u8 rsv; 869 } __packed; 870 871 struct sec_key { 872 u8 cipher_id; 873 u8 cipher_len; 874 u8 key_id; 875 u8 key_len; 876 u8 key[32]; 877 } __packed; 878 879 struct sta_rec_sec { 880 __le16 tag; 881 __le16 len; 882 u8 add; 883 u8 n_cipher; 884 u8 rsv[2]; 885 886 struct sec_key key[2]; 887 } __packed; 888 889 struct ra_phy { 890 u8 type; 891 u8 flag; 892 u8 stbc; 893 u8 sgi; 894 u8 bw; 895 u8 ldpc; 896 u8 mcs; 897 u8 nss; 898 u8 he_ltf; 899 }; 900 901 struct sta_rec_ra { 902 __le16 tag; 903 __le16 len; 904 905 u8 valid; 906 u8 auto_rate; 907 u8 phy_mode; 908 u8 channel; 909 u8 bw; 910 u8 disable_cck; 911 u8 ht_mcs32; 912 u8 ht_gf; 913 u8 ht_mcs[4]; 914 u8 mmps_mode; 915 u8 gband_256; 916 u8 af; 917 u8 auth_wapi_mode; 918 u8 rate_len; 919 920 u8 supp_mode; 921 u8 supp_cck_rate; 922 u8 supp_ofdm_rate; 923 __le32 supp_ht_mcs; 924 __le16 supp_vht_mcs[4]; 925 926 u8 op_mode; 927 u8 op_vht_chan_width; 928 u8 op_vht_rx_nss; 929 u8 op_vht_rx_nss_type; 930 931 __le32 sta_cap; 932 933 struct ra_phy phy; 934 } __packed; 935 936 struct sta_rec_ra_fixed { 937 __le16 tag; 938 __le16 len; 939 940 __le32 field; 941 u8 op_mode; 942 u8 op_vht_chan_width; 943 u8 op_vht_rx_nss; 944 u8 op_vht_rx_nss_type; 945 946 struct ra_phy phy; 947 948 u8 spe_en; 949 u8 short_preamble; 950 u8 is_5g; 951 u8 mmps_mode; 952 } __packed; 953 954 #define RATE_PARAM_FIXED 3 955 #define RATE_PARAM_AUTO 20 956 #define RATE_CFG_MCS GENMASK(3, 0) 957 #define RATE_CFG_NSS GENMASK(7, 4) 958 #define RATE_CFG_GI GENMASK(11, 8) 959 #define RATE_CFG_BW GENMASK(15, 12) 960 #define RATE_CFG_STBC GENMASK(19, 16) 961 #define RATE_CFG_LDPC GENMASK(23, 20) 962 #define RATE_CFG_PHY_TYPE GENMASK(27, 24) 963 #define RATE_CFG_HE_LTF GENMASK(31, 28) 964 965 struct sta_rec_bf { 966 __le16 tag; 967 __le16 len; 968 969 __le16 pfmu; /* 0xffff: no access right for PFMU */ 970 bool su_mu; /* 0: SU, 1: MU */ 971 u8 bf_cap; /* 0: iBF, 1: eBF */ 972 u8 sounding_phy; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT */ 973 u8 ndpa_rate; 974 u8 ndp_rate; 975 u8 rept_poll_rate; 976 u8 tx_mode; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT ... */ 977 u8 ncol; 978 u8 nrow; 979 u8 bw; /* 0: 20M, 1: 40M, 2: 80M, 3: 160M */ 980 981 u8 mem_total; 982 u8 mem_20m; 983 struct { 984 u8 row; 985 u8 col: 6, row_msb: 2; 986 } mem[4]; 987 988 __le16 smart_ant; 989 u8 se_idx; 990 u8 auto_sounding; /* b7: low traffic indicator 991 * b6: Stop sounding for this entry 992 * b5 ~ b0: postpone sounding 993 */ 994 u8 ibf_timeout; 995 u8 ibf_dbw; 996 u8 ibf_ncol; 997 u8 ibf_nrow; 998 u8 nrow_bw160; 999 u8 ncol_bw160; 1000 u8 ru_start_idx; 1001 u8 ru_end_idx; 1002 1003 bool trigger_su; 1004 bool trigger_mu; 1005 bool ng16_su; 1006 bool ng16_mu; 1007 bool codebook42_su; 1008 bool codebook75_mu; 1009 1010 u8 he_ltf; 1011 u8 rsv[3]; 1012 } __packed; 1013 1014 struct sta_rec_bfee { 1015 __le16 tag; 1016 __le16 len; 1017 bool fb_identity_matrix; /* 1: feedback identity matrix */ 1018 bool ignore_feedback; /* 1: ignore */ 1019 u8 rsv[2]; 1020 } __packed; 1021 1022 enum { 1023 STA_REC_BASIC, 1024 STA_REC_RA, 1025 STA_REC_RA_CMM_INFO, 1026 STA_REC_RA_UPDATE, 1027 STA_REC_BF, 1028 STA_REC_AMSDU, 1029 STA_REC_BA, 1030 STA_REC_RED, /* not used */ 1031 STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */ 1032 STA_REC_HT, 1033 STA_REC_VHT, 1034 STA_REC_APPS, 1035 STA_REC_KEY, 1036 STA_REC_WTBL, 1037 STA_REC_HE, 1038 STA_REC_HW_AMSDU, 1039 STA_REC_WTBL_AADOM, 1040 STA_REC_KEY_V2, 1041 STA_REC_MURU, 1042 STA_REC_MUEDCA, 1043 STA_REC_BFEE, 1044 STA_REC_MAX_NUM 1045 }; 1046 1047 enum mcu_cipher_type { 1048 MCU_CIPHER_NONE = 0, 1049 MCU_CIPHER_WEP40, 1050 MCU_CIPHER_WEP104, 1051 MCU_CIPHER_WEP128, 1052 MCU_CIPHER_TKIP, 1053 MCU_CIPHER_AES_CCMP, 1054 MCU_CIPHER_CCMP_256, 1055 MCU_CIPHER_GCMP, 1056 MCU_CIPHER_GCMP_256, 1057 MCU_CIPHER_WAPI, 1058 MCU_CIPHER_BIP_CMAC_128, 1059 }; 1060 1061 enum { 1062 CH_SWITCH_NORMAL = 0, 1063 CH_SWITCH_SCAN = 3, 1064 CH_SWITCH_MCC = 4, 1065 CH_SWITCH_DFS = 5, 1066 CH_SWITCH_BACKGROUND_SCAN_START = 6, 1067 CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7, 1068 CH_SWITCH_BACKGROUND_SCAN_STOP = 8, 1069 CH_SWITCH_SCAN_BYPASS_DPD = 9 1070 }; 1071 1072 enum { 1073 THERMAL_SENSOR_TEMP_QUERY, 1074 THERMAL_SENSOR_MANUAL_CTRL, 1075 THERMAL_SENSOR_INFO_QUERY, 1076 THERMAL_SENSOR_TASK_CTRL, 1077 }; 1078 1079 enum { 1080 THERMAL_PROTECT_PARAMETER_CTRL, 1081 THERMAL_PROTECT_BASIC_INFO, 1082 THERMAL_PROTECT_ENABLE, 1083 THERMAL_PROTECT_DISABLE, 1084 THERMAL_PROTECT_DUTY_CONFIG, 1085 THERMAL_PROTECT_MECH_INFO, 1086 THERMAL_PROTECT_DUTY_INFO, 1087 THERMAL_PROTECT_STATE_ACT, 1088 }; 1089 1090 enum { 1091 MT_BF_SOUNDING_ON = 1, 1092 MT_BF_TYPE_UPDATE = 20, 1093 MT_BF_MODULE_UPDATE = 25 1094 }; 1095 1096 enum { 1097 MURU_SET_ARB_OP_MODE = 14, 1098 MURU_SET_PLATFORM_TYPE = 25, 1099 }; 1100 1101 enum { 1102 MURU_PLATFORM_TYPE_PERF_LEVEL_1 = 1, 1103 MURU_PLATFORM_TYPE_PERF_LEVEL_2, 1104 }; 1105 1106 #define MT7915_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \ 1107 sizeof(struct wtbl_generic) + \ 1108 sizeof(struct wtbl_rx) + \ 1109 sizeof(struct wtbl_ht) + \ 1110 sizeof(struct wtbl_vht) + \ 1111 sizeof(struct wtbl_hdr_trans) +\ 1112 sizeof(struct wtbl_ba) + \ 1113 sizeof(struct wtbl_smps)) 1114 1115 #define MT7915_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \ 1116 sizeof(struct sta_rec_basic) + \ 1117 sizeof(struct sta_rec_bf) + \ 1118 sizeof(struct sta_rec_ht) + \ 1119 sizeof(struct sta_rec_he) + \ 1120 sizeof(struct sta_rec_ba) + \ 1121 sizeof(struct sta_rec_vht) + \ 1122 sizeof(struct sta_rec_uapsd) + \ 1123 sizeof(struct sta_rec_amsdu) + \ 1124 sizeof(struct sta_rec_muru) + \ 1125 sizeof(struct sta_rec_bfee) + \ 1126 sizeof(struct tlv) + \ 1127 MT7915_WTBL_UPDATE_MAX_SIZE) 1128 1129 #define MT7915_BSS_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \ 1130 sizeof(struct bss_info_omac) + \ 1131 sizeof(struct bss_info_basic) +\ 1132 sizeof(struct bss_info_rf_ch) +\ 1133 sizeof(struct bss_info_ra) + \ 1134 sizeof(struct bss_info_hw_amsdu) +\ 1135 sizeof(struct bss_info_he) + \ 1136 sizeof(struct bss_info_bmc_rate) +\ 1137 sizeof(struct bss_info_ext_bss)) 1138 1139 #define MT7915_BEACON_UPDATE_SIZE (sizeof(struct sta_req_hdr) + \ 1140 sizeof(struct bss_info_bcn_cntdwn) + \ 1141 sizeof(struct bss_info_bcn_mbss) + \ 1142 sizeof(struct bss_info_bcn_cont)) 1143 1144 #define PHY_MODE_A BIT(0) 1145 #define PHY_MODE_B BIT(1) 1146 #define PHY_MODE_G BIT(2) 1147 #define PHY_MODE_GN BIT(3) 1148 #define PHY_MODE_AN BIT(4) 1149 #define PHY_MODE_AC BIT(5) 1150 #define PHY_MODE_AX_24G BIT(6) 1151 #define PHY_MODE_AX_5G BIT(7) 1152 #define PHY_MODE_AX_6G BIT(8) 1153 1154 #define MODE_CCK BIT(0) 1155 #define MODE_OFDM BIT(1) 1156 #define MODE_HT BIT(2) 1157 #define MODE_VHT BIT(3) 1158 #define MODE_HE BIT(4) 1159 1160 #define STA_CAP_WMM BIT(0) 1161 #define STA_CAP_SGI_20 BIT(4) 1162 #define STA_CAP_SGI_40 BIT(5) 1163 #define STA_CAP_TX_STBC BIT(6) 1164 #define STA_CAP_RX_STBC BIT(7) 1165 #define STA_CAP_VHT_SGI_80 BIT(16) 1166 #define STA_CAP_VHT_SGI_160 BIT(17) 1167 #define STA_CAP_VHT_TX_STBC BIT(18) 1168 #define STA_CAP_VHT_RX_STBC BIT(19) 1169 #define STA_CAP_VHT_LDPC BIT(23) 1170 #define STA_CAP_LDPC BIT(24) 1171 #define STA_CAP_HT BIT(26) 1172 #define STA_CAP_VHT BIT(27) 1173 #define STA_CAP_HE BIT(28) 1174 1175 /* HE MAC */ 1176 #define STA_REC_HE_CAP_HTC BIT(0) 1177 #define STA_REC_HE_CAP_BQR BIT(1) 1178 #define STA_REC_HE_CAP_BSR BIT(2) 1179 #define STA_REC_HE_CAP_OM BIT(3) 1180 #define STA_REC_HE_CAP_AMSDU_IN_AMPDU BIT(4) 1181 /* HE PHY */ 1182 #define STA_REC_HE_CAP_DUAL_BAND BIT(5) 1183 #define STA_REC_HE_CAP_LDPC BIT(6) 1184 #define STA_REC_HE_CAP_TRIG_CQI_FK BIT(7) 1185 #define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE BIT(8) 1186 /* STBC */ 1187 #define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC BIT(9) 1188 #define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC BIT(10) 1189 #define STA_REC_HE_CAP_GT_80M_TX_STBC BIT(11) 1190 #define STA_REC_HE_CAP_GT_80M_RX_STBC BIT(12) 1191 /* GI */ 1192 #define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI BIT(13) 1193 #define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI BIT(14) 1194 #define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI BIT(15) 1195 #define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI BIT(16) 1196 #define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI BIT(17) 1197 /* 242 TONE */ 1198 #define STA_REC_HE_CAP_BW20_RU242_SUPPORT BIT(18) 1199 #define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242 BIT(19) 1200 #define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242 BIT(20) 1201 1202 #endif 1203