1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #ifndef __MT7915_MCU_H 5 #define __MT7915_MCU_H 6 7 #include "../mt76_connac_mcu.h" 8 9 struct mt7915_mcu_txd { 10 __le32 txd[8]; 11 12 __le16 len; 13 __le16 pq_id; 14 15 u8 cid; 16 u8 pkt_type; 17 u8 set_query; /* FW don't care */ 18 u8 seq; 19 20 u8 uc_d2b0_rev; 21 u8 ext_cid; 22 u8 s2d_index; 23 u8 ext_cid_ack; 24 25 u32 reserved[5]; 26 } __packed __aligned(4); 27 28 enum { 29 MCU_ATE_SET_TRX = 0x1, 30 MCU_ATE_SET_FREQ_OFFSET = 0xa, 31 MCU_ATE_SET_SLOT_TIME = 0x13, 32 MCU_ATE_CLEAN_TXQUEUE = 0x1c, 33 }; 34 35 struct mt7915_mcu_rxd { 36 __le32 rxd[6]; 37 38 __le16 len; 39 __le16 pkt_type_id; 40 41 u8 eid; 42 u8 seq; 43 __le16 __rsv; 44 45 u8 ext_eid; 46 u8 __rsv1[2]; 47 u8 s2d_index; 48 }; 49 50 struct mt7915_mcu_thermal_ctrl { 51 u8 ctrl_id; 52 u8 band_idx; 53 union { 54 struct { 55 u8 protect_type; /* 1: duty admit, 2: radio off */ 56 u8 trigger_type; /* 0: low, 1: high */ 57 } __packed type; 58 struct { 59 u8 duty_level; /* level 0~3 */ 60 u8 duty_cycle; 61 } __packed duty; 62 }; 63 } __packed; 64 65 struct mt7915_mcu_thermal_notify { 66 struct mt7915_mcu_rxd rxd; 67 68 struct mt7915_mcu_thermal_ctrl ctrl; 69 __le32 temperature; 70 u8 rsv[8]; 71 } __packed; 72 73 struct mt7915_mcu_csa_notify { 74 struct mt7915_mcu_rxd rxd; 75 76 u8 omac_idx; 77 u8 csa_count; 78 u8 band_idx; 79 u8 rsv; 80 } __packed; 81 82 struct mt7915_mcu_rdd_report { 83 struct mt7915_mcu_rxd rxd; 84 85 u8 band_idx; 86 u8 long_detected; 87 u8 constant_prf_detected; 88 u8 staggered_prf_detected; 89 u8 radar_type_idx; 90 u8 periodic_pulse_num; 91 u8 long_pulse_num; 92 u8 hw_pulse_num; 93 94 u8 out_lpn; 95 u8 out_spn; 96 u8 out_crpn; 97 u8 out_crpw; 98 u8 out_crbn; 99 u8 out_stgpn; 100 u8 out_stgpw; 101 102 u8 rsv; 103 104 __le32 out_pri_const; 105 __le32 out_pri_stg[3]; 106 107 struct { 108 __le32 start; 109 __le16 pulse_width; 110 __le16 pulse_power; 111 u8 mdrdy_flag; 112 u8 rsv[3]; 113 } long_pulse[32]; 114 115 struct { 116 __le32 start; 117 __le16 pulse_width; 118 __le16 pulse_power; 119 u8 mdrdy_flag; 120 u8 rsv[3]; 121 } periodic_pulse[32]; 122 123 struct { 124 __le32 start; 125 __le16 pulse_width; 126 __le16 pulse_power; 127 u8 sc_pass; 128 u8 sw_reset; 129 u8 mdrdy_flag; 130 u8 tx_active; 131 } hw_pulse[32]; 132 } __packed; 133 134 struct mt7915_mcu_background_chain_ctrl { 135 u8 chan; /* primary channel */ 136 u8 central_chan; /* central channel */ 137 u8 bw; 138 u8 tx_stream; 139 u8 rx_stream; 140 141 u8 monitor_chan; /* monitor channel */ 142 u8 monitor_central_chan;/* monitor central channel */ 143 u8 monitor_bw; 144 u8 monitor_tx_stream; 145 u8 monitor_rx_stream; 146 147 u8 scan_mode; /* 0: ScanStop 148 * 1: ScanStart 149 * 2: ScanRunning 150 */ 151 u8 band_idx; /* DBDC */ 152 u8 monitor_scan_type; 153 u8 band; /* 0: 2.4GHz, 1: 5GHz */ 154 u8 rsv[2]; 155 } __packed; 156 157 struct mt7915_mcu_eeprom { 158 u8 buffer_mode; 159 u8 format; 160 __le16 len; 161 } __packed; 162 163 struct mt7915_mcu_eeprom_info { 164 __le32 addr; 165 __le32 valid; 166 u8 data[16]; 167 } __packed; 168 169 struct mt7915_mcu_phy_rx_info { 170 u8 category; 171 u8 rate; 172 u8 mode; 173 u8 nsts; 174 u8 gi; 175 u8 coding; 176 u8 stbc; 177 u8 bw; 178 }; 179 180 struct mt7915_mcu_mib { 181 __le32 band; 182 __le32 offs; 183 __le64 data; 184 } __packed; 185 186 enum mt7915_chan_mib_offs { 187 /* mt7915 */ 188 MIB_BUSY_TIME = 14, 189 MIB_TX_TIME = 81, 190 MIB_RX_TIME, 191 MIB_OBSS_AIRTIME = 86, 192 /* mt7916 */ 193 MIB_BUSY_TIME_V2 = 0, 194 MIB_TX_TIME_V2 = 6, 195 MIB_RX_TIME_V2 = 8, 196 MIB_OBSS_AIRTIME_V2 = 490 197 }; 198 199 struct edca { 200 u8 queue; 201 u8 set; 202 u8 aifs; 203 u8 cw_min; 204 __le16 cw_max; 205 __le16 txop; 206 }; 207 208 struct mt7915_mcu_tx { 209 u8 total; 210 u8 action; 211 u8 valid; 212 u8 mode; 213 214 struct edca edca[IEEE80211_NUM_ACS]; 215 } __packed; 216 217 struct mt7915_mcu_muru_stats { 218 __le32 event_id; 219 struct { 220 __le32 cck_cnt; 221 __le32 ofdm_cnt; 222 __le32 htmix_cnt; 223 __le32 htgf_cnt; 224 __le32 vht_su_cnt; 225 __le32 vht_2mu_cnt; 226 __le32 vht_3mu_cnt; 227 __le32 vht_4mu_cnt; 228 __le32 he_su_cnt; 229 __le32 he_ext_su_cnt; 230 __le32 he_2ru_cnt; 231 __le32 he_2mu_cnt; 232 __le32 he_3ru_cnt; 233 __le32 he_3mu_cnt; 234 __le32 he_4ru_cnt; 235 __le32 he_4mu_cnt; 236 __le32 he_5to8ru_cnt; 237 __le32 he_9to16ru_cnt; 238 __le32 he_gtr16ru_cnt; 239 } dl; 240 241 struct { 242 __le32 hetrig_su_cnt; 243 __le32 hetrig_2ru_cnt; 244 __le32 hetrig_3ru_cnt; 245 __le32 hetrig_4ru_cnt; 246 __le32 hetrig_5to8ru_cnt; 247 __le32 hetrig_9to16ru_cnt; 248 __le32 hetrig_gtr16ru_cnt; 249 __le32 hetrig_2mu_cnt; 250 __le32 hetrig_3mu_cnt; 251 __le32 hetrig_4mu_cnt; 252 } ul; 253 }; 254 255 #define WMM_AIFS_SET BIT(0) 256 #define WMM_CW_MIN_SET BIT(1) 257 #define WMM_CW_MAX_SET BIT(2) 258 #define WMM_TXOP_SET BIT(3) 259 #define WMM_PARAM_SET GENMASK(3, 0) 260 261 #define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10)) 262 #define MCU_PKT_ID 0xa0 263 264 enum { 265 MCU_FW_LOG_WM, 266 MCU_FW_LOG_WA, 267 MCU_FW_LOG_TO_HOST, 268 }; 269 270 enum { 271 MCU_TWT_AGRT_ADD, 272 MCU_TWT_AGRT_MODIFY, 273 MCU_TWT_AGRT_DELETE, 274 MCU_TWT_AGRT_TEARDOWN, 275 MCU_TWT_AGRT_GET_TSF, 276 }; 277 278 enum { 279 MCU_WA_PARAM_CMD_QUERY, 280 MCU_WA_PARAM_CMD_SET, 281 MCU_WA_PARAM_CMD_CAPABILITY, 282 MCU_WA_PARAM_CMD_DEBUG, 283 }; 284 285 enum { 286 MCU_WA_PARAM_PDMA_RX = 0x04, 287 MCU_WA_PARAM_CPU_UTIL = 0x0b, 288 MCU_WA_PARAM_RED = 0x0e, 289 }; 290 291 enum mcu_mmps_mode { 292 MCU_MMPS_STATIC, 293 MCU_MMPS_DYNAMIC, 294 MCU_MMPS_RSV, 295 MCU_MMPS_DISABLE, 296 }; 297 298 enum { 299 SCS_SEND_DATA, 300 SCS_SET_MANUAL_PD_TH, 301 SCS_CONFIG, 302 SCS_ENABLE, 303 SCS_SHOW_INFO, 304 SCS_GET_GLO_ADDR, 305 SCS_GET_GLO_ADDR_EVENT, 306 }; 307 308 struct bss_info_bmc_rate { 309 __le16 tag; 310 __le16 len; 311 __le16 bc_trans; 312 __le16 mc_trans; 313 u8 short_preamble; 314 u8 rsv[7]; 315 } __packed; 316 317 struct bss_info_ra { 318 __le16 tag; 319 __le16 len; 320 u8 op_mode; 321 u8 adhoc_en; 322 u8 short_preamble; 323 u8 tx_streams; 324 u8 rx_streams; 325 u8 algo; 326 u8 force_sgi; 327 u8 force_gf; 328 u8 ht_mode; 329 u8 has_20_sta; /* Check if any sta support GF. */ 330 u8 bss_width_trigger_events; 331 u8 vht_nss_cap; 332 u8 vht_bw_signal; /* not use */ 333 u8 vht_force_sgi; /* not use */ 334 u8 se_off; 335 u8 antenna_idx; 336 u8 train_up_rule; 337 u8 rsv[3]; 338 unsigned short train_up_high_thres; 339 short train_up_rule_rssi; 340 unsigned short low_traffic_thres; 341 __le16 max_phyrate; 342 __le32 phy_cap; 343 __le32 interval; 344 __le32 fast_interval; 345 } __packed; 346 347 struct bss_info_hw_amsdu { 348 __le16 tag; 349 __le16 len; 350 __le32 cmp_bitmap_0; 351 __le32 cmp_bitmap_1; 352 __le16 trig_thres; 353 u8 enable; 354 u8 rsv; 355 } __packed; 356 357 struct bss_info_color { 358 __le16 tag; 359 __le16 len; 360 u8 disable; 361 u8 color; 362 u8 rsv[2]; 363 } __packed; 364 365 struct bss_info_he { 366 __le16 tag; 367 __le16 len; 368 u8 he_pe_duration; 369 u8 vht_op_info_present; 370 __le16 he_rts_thres; 371 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 372 u8 rsv[6]; 373 } __packed; 374 375 struct bss_info_bcn { 376 __le16 tag; 377 __le16 len; 378 u8 ver; 379 u8 enable; 380 __le16 sub_ntlv; 381 } __packed __aligned(4); 382 383 struct bss_info_bcn_cntdwn { 384 __le16 tag; 385 __le16 len; 386 u8 cnt; 387 u8 rsv[3]; 388 } __packed __aligned(4); 389 390 struct bss_info_bcn_mbss { 391 #define MAX_BEACON_NUM 32 392 __le16 tag; 393 __le16 len; 394 __le32 bitmap; 395 __le16 offset[MAX_BEACON_NUM]; 396 u8 rsv[8]; 397 } __packed __aligned(4); 398 399 struct bss_info_bcn_cont { 400 __le16 tag; 401 __le16 len; 402 __le16 tim_ofs; 403 __le16 csa_ofs; 404 __le16 bcc_ofs; 405 __le16 pkt_len; 406 } __packed __aligned(4); 407 408 enum { 409 BSS_INFO_BCN_CSA, 410 BSS_INFO_BCN_BCC, 411 BSS_INFO_BCN_MBSSID, 412 BSS_INFO_BCN_CONTENT, 413 BSS_INFO_BCN_MAX 414 }; 415 416 enum { 417 RATE_PARAM_FIXED = 3, 418 RATE_PARAM_MMPS_UPDATE = 5, 419 RATE_PARAM_FIXED_HE_LTF = 7, 420 RATE_PARAM_FIXED_MCS, 421 RATE_PARAM_FIXED_GI = 11, 422 RATE_PARAM_AUTO = 20, 423 }; 424 425 #define RATE_CFG_MCS GENMASK(3, 0) 426 #define RATE_CFG_NSS GENMASK(7, 4) 427 #define RATE_CFG_GI GENMASK(11, 8) 428 #define RATE_CFG_BW GENMASK(15, 12) 429 #define RATE_CFG_STBC GENMASK(19, 16) 430 #define RATE_CFG_LDPC GENMASK(23, 20) 431 #define RATE_CFG_PHY_TYPE GENMASK(27, 24) 432 #define RATE_CFG_HE_LTF GENMASK(31, 28) 433 434 enum { 435 THERMAL_PROTECT_PARAMETER_CTRL, 436 THERMAL_PROTECT_BASIC_INFO, 437 THERMAL_PROTECT_ENABLE, 438 THERMAL_PROTECT_DISABLE, 439 THERMAL_PROTECT_DUTY_CONFIG, 440 THERMAL_PROTECT_MECH_INFO, 441 THERMAL_PROTECT_DUTY_INFO, 442 THERMAL_PROTECT_STATE_ACT, 443 }; 444 445 enum { 446 MT_BF_SOUNDING_ON = 1, 447 MT_BF_TYPE_UPDATE = 20, 448 MT_BF_MODULE_UPDATE = 25 449 }; 450 451 enum { 452 MURU_SET_ARB_OP_MODE = 14, 453 MURU_SET_PLATFORM_TYPE = 25, 454 }; 455 456 enum { 457 MURU_PLATFORM_TYPE_PERF_LEVEL_1 = 1, 458 MURU_PLATFORM_TYPE_PERF_LEVEL_2, 459 }; 460 461 /* tx cmd tx statistics */ 462 enum { 463 MURU_SET_TXC_TX_STATS_EN = 150, 464 MURU_GET_TXC_TX_STATS = 151, 465 }; 466 467 #define MT7915_BSS_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \ 468 sizeof(struct bss_info_omac) + \ 469 sizeof(struct bss_info_basic) +\ 470 sizeof(struct bss_info_rf_ch) +\ 471 sizeof(struct bss_info_ra) + \ 472 sizeof(struct bss_info_hw_amsdu) +\ 473 sizeof(struct bss_info_he) + \ 474 sizeof(struct bss_info_bmc_rate) +\ 475 sizeof(struct bss_info_ext_bss)) 476 477 #define MT7915_BEACON_UPDATE_SIZE (sizeof(struct sta_req_hdr) + \ 478 sizeof(struct bss_info_bcn_cntdwn) + \ 479 sizeof(struct bss_info_bcn_mbss) + \ 480 sizeof(struct bss_info_bcn_cont)) 481 482 #endif 483