1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include <linux/etherdevice.h> 5 #include <linux/timekeeping.h> 6 #include "coredump.h" 7 #include "mt7915.h" 8 #include "../dma.h" 9 #include "mac.h" 10 #include "mcu.h" 11 12 #define to_rssi(field, rcpi) ((FIELD_GET(field, rcpi) - 220) / 2) 13 14 static const struct mt7915_dfs_radar_spec etsi_radar_specs = { 15 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 16 .radar_pattern = { 17 [5] = { 1, 0, 6, 32, 28, 0, 990, 5010, 17, 1, 1 }, 18 [6] = { 1, 0, 9, 32, 28, 0, 615, 5010, 27, 1, 1 }, 19 [7] = { 1, 0, 15, 32, 28, 0, 240, 445, 27, 1, 1 }, 20 [8] = { 1, 0, 12, 32, 28, 0, 240, 510, 42, 1, 1 }, 21 [9] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 12, 32, 28, { }, 126 }, 22 [10] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 15, 32, 24, { }, 126 }, 23 [11] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 18, 32, 28, { }, 54 }, 24 [12] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 27, 32, 24, { }, 54 }, 25 }, 26 }; 27 28 static const struct mt7915_dfs_radar_spec fcc_radar_specs = { 29 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 30 .radar_pattern = { 31 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 }, 32 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 }, 33 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 }, 34 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 }, 35 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 }, 36 }, 37 }; 38 39 static const struct mt7915_dfs_radar_spec jp_radar_specs = { 40 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 41 .radar_pattern = { 42 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 }, 43 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 }, 44 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 }, 45 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 }, 46 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 }, 47 [13] = { 1, 0, 7, 32, 28, 0, 3836, 3856, 14, 1, 1 }, 48 [14] = { 1, 0, 6, 32, 28, 0, 615, 5010, 110, 1, 1 }, 49 [15] = { 1, 1, 0, 0, 0, 0, 15, 5010, 110, 0, 0, 12, 32, 28 }, 50 }, 51 }; 52 53 static struct mt76_wcid *mt7915_rx_get_wcid(struct mt7915_dev *dev, 54 u16 idx, bool unicast) 55 { 56 struct mt7915_sta *sta; 57 struct mt76_wcid *wcid; 58 59 wcid = mt76_wcid_ptr(dev, idx); 60 if (unicast || !wcid) 61 return wcid; 62 63 if (!wcid->sta) 64 return NULL; 65 66 sta = container_of(wcid, struct mt7915_sta, wcid); 67 if (!sta->vif) 68 return NULL; 69 70 return &sta->vif->sta.wcid; 71 } 72 73 bool mt7915_mac_wtbl_update(struct mt7915_dev *dev, int idx, u32 mask) 74 { 75 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX, 76 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask); 77 78 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 79 0, 5000); 80 } 81 82 u32 mt7915_mac_wtbl_lmac_addr(struct mt7915_dev *dev, u16 wcid, u8 dw) 83 { 84 mt76_wr(dev, MT_WTBLON_TOP_WDUCR, 85 FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (wcid >> 7))); 86 87 return MT_WTBL_LMAC_OFFS(wcid, dw); 88 } 89 90 static void mt7915_mac_sta_poll(struct mt7915_dev *dev) 91 { 92 static const u8 ac_to_tid[] = { 93 [IEEE80211_AC_BE] = 0, 94 [IEEE80211_AC_BK] = 1, 95 [IEEE80211_AC_VI] = 4, 96 [IEEE80211_AC_VO] = 6 97 }; 98 struct ieee80211_sta *sta; 99 struct mt7915_sta *msta; 100 struct rate_info *rate; 101 u32 tx_time[IEEE80211_NUM_ACS], rx_time[IEEE80211_NUM_ACS]; 102 LIST_HEAD(sta_poll_list); 103 int i; 104 105 spin_lock_bh(&dev->mt76.sta_poll_lock); 106 list_splice_init(&dev->mt76.sta_poll_list, &sta_poll_list); 107 spin_unlock_bh(&dev->mt76.sta_poll_lock); 108 109 rcu_read_lock(); 110 111 while (true) { 112 bool clear = false; 113 u32 addr, val; 114 u16 idx; 115 s8 rssi[4]; 116 u8 bw; 117 118 spin_lock_bh(&dev->mt76.sta_poll_lock); 119 if (list_empty(&sta_poll_list)) { 120 spin_unlock_bh(&dev->mt76.sta_poll_lock); 121 break; 122 } 123 msta = list_first_entry(&sta_poll_list, 124 struct mt7915_sta, wcid.poll_list); 125 list_del_init(&msta->wcid.poll_list); 126 spin_unlock_bh(&dev->mt76.sta_poll_lock); 127 128 idx = msta->wcid.idx; 129 130 /* refresh peer's airtime reporting */ 131 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 20); 132 133 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 134 u32 tx_last = msta->airtime_ac[i]; 135 u32 rx_last = msta->airtime_ac[i + 4]; 136 137 msta->airtime_ac[i] = mt76_rr(dev, addr); 138 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4); 139 140 if (msta->airtime_ac[i] <= tx_last) 141 tx_time[i] = 0; 142 else 143 tx_time[i] = msta->airtime_ac[i] - tx_last; 144 145 if (msta->airtime_ac[i + 4] <= rx_last) 146 rx_time[i] = 0; 147 else 148 rx_time[i] = msta->airtime_ac[i + 4] - rx_last; 149 150 if ((tx_last | rx_last) & BIT(30)) 151 clear = true; 152 153 addr += 8; 154 } 155 156 if (clear) { 157 mt7915_mac_wtbl_update(dev, idx, 158 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 159 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac)); 160 } 161 162 if (!msta->wcid.sta) 163 continue; 164 165 sta = container_of((void *)msta, struct ieee80211_sta, 166 drv_priv); 167 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 168 u8 queue = mt76_connac_lmac_mapping(i); 169 u32 tx_cur = tx_time[queue]; 170 u32 rx_cur = rx_time[queue]; 171 u8 tid = ac_to_tid[i]; 172 173 if (!tx_cur && !rx_cur) 174 continue; 175 176 ieee80211_sta_register_airtime(sta, tid, tx_cur, 177 rx_cur); 178 } 179 180 /* 181 * We don't support reading GI info from txs packets. 182 * For accurate tx status reporting and AQL improvement, 183 * we need to make sure that flags match so polling GI 184 * from per-sta counters directly. 185 */ 186 rate = &msta->wcid.rate; 187 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 7); 188 val = mt76_rr(dev, addr); 189 190 switch (rate->bw) { 191 case RATE_INFO_BW_160: 192 bw = IEEE80211_STA_RX_BW_160; 193 break; 194 case RATE_INFO_BW_80: 195 bw = IEEE80211_STA_RX_BW_80; 196 break; 197 case RATE_INFO_BW_40: 198 bw = IEEE80211_STA_RX_BW_40; 199 break; 200 default: 201 bw = IEEE80211_STA_RX_BW_20; 202 break; 203 } 204 205 if (rate->flags & RATE_INFO_FLAGS_HE_MCS) { 206 u8 offs = 24 + 2 * bw; 207 208 rate->he_gi = (val & (0x3 << offs)) >> offs; 209 } else if (rate->flags & 210 (RATE_INFO_FLAGS_VHT_MCS | RATE_INFO_FLAGS_MCS)) { 211 if (val & BIT(12 + bw)) 212 rate->flags |= RATE_INFO_FLAGS_SHORT_GI; 213 else 214 rate->flags &= ~RATE_INFO_FLAGS_SHORT_GI; 215 } 216 217 /* get signal strength of resp frames (CTS/BA/ACK) */ 218 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 30); 219 val = mt76_rr(dev, addr); 220 221 rssi[0] = to_rssi(GENMASK(7, 0), val); 222 rssi[1] = to_rssi(GENMASK(15, 8), val); 223 rssi[2] = to_rssi(GENMASK(23, 16), val); 224 rssi[3] = to_rssi(GENMASK(31, 14), val); 225 226 msta->ack_signal = 227 mt76_rx_signal(msta->vif->phy->mt76->antenna_mask, rssi); 228 229 ewma_avg_signal_add(&msta->avg_ack_signal, -msta->ack_signal); 230 } 231 232 rcu_read_unlock(); 233 } 234 235 void mt7915_mac_enable_rtscts(struct mt7915_dev *dev, 236 struct ieee80211_vif *vif, bool enable) 237 { 238 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv; 239 u32 addr; 240 241 addr = mt7915_mac_wtbl_lmac_addr(dev, mvif->sta.wcid.idx, 5); 242 if (enable) 243 mt76_set(dev, addr, BIT(5)); 244 else 245 mt76_clear(dev, addr, BIT(5)); 246 } 247 248 static void 249 mt7915_wed_check_ppe(struct mt7915_dev *dev, struct mt76_queue *q, 250 struct mt7915_sta *msta, struct sk_buff *skb, 251 u32 info) 252 { 253 struct ieee80211_vif *vif; 254 struct wireless_dev *wdev; 255 256 if (!msta || !msta->vif) 257 return; 258 259 if (!mt76_queue_is_wed_rx(q)) 260 return; 261 262 if (!(info & MT_DMA_INFO_PPE_VLD)) 263 return; 264 265 vif = container_of((void *)msta->vif, struct ieee80211_vif, 266 drv_priv); 267 wdev = ieee80211_vif_to_wdev(vif); 268 skb->dev = wdev->netdev; 269 270 mtk_wed_device_ppe_check(&dev->mt76.mmio.wed, skb, 271 FIELD_GET(MT_DMA_PPE_CPU_REASON, info), 272 FIELD_GET(MT_DMA_PPE_ENTRY, info)); 273 } 274 275 static int 276 mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb, 277 enum mt76_rxq_id q, u32 *info) 278 { 279 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 280 struct mt76_phy *mphy = &dev->mt76.phy; 281 struct mt7915_phy *phy = &dev->phy; 282 struct ieee80211_supported_band *sband; 283 __le32 *rxd = (__le32 *)skb->data; 284 __le32 *rxv = NULL; 285 u32 rxd0 = le32_to_cpu(rxd[0]); 286 u32 rxd1 = le32_to_cpu(rxd[1]); 287 u32 rxd2 = le32_to_cpu(rxd[2]); 288 u32 rxd3 = le32_to_cpu(rxd[3]); 289 u32 rxd4 = le32_to_cpu(rxd[4]); 290 u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM; 291 bool unicast, insert_ccmp_hdr = false; 292 u8 remove_pad, amsdu_info; 293 u8 mode = 0, qos_ctl = 0; 294 struct mt7915_sta *msta = NULL; 295 u32 csum_status = *(u32 *)skb->cb; 296 bool hdr_trans; 297 u16 hdr_gap; 298 u16 seq_ctrl = 0; 299 __le16 fc = 0; 300 int idx; 301 302 memset(status, 0, sizeof(*status)); 303 304 if ((rxd1 & MT_RXD1_NORMAL_BAND_IDX) && !phy->mt76->band_idx) { 305 mphy = dev->mt76.phys[MT_BAND1]; 306 if (!mphy) 307 return -EINVAL; 308 309 phy = mphy->priv; 310 status->phy_idx = 1; 311 } 312 313 if (!test_bit(MT76_STATE_RUNNING, &mphy->state)) 314 return -EINVAL; 315 316 if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR) 317 return -EINVAL; 318 319 hdr_trans = rxd2 & MT_RXD2_NORMAL_HDR_TRANS; 320 if (hdr_trans && (rxd1 & MT_RXD1_NORMAL_CM)) 321 return -EINVAL; 322 323 /* ICV error or CCMP/BIP/WPI MIC error */ 324 if (rxd1 & MT_RXD1_NORMAL_ICV_ERR) 325 status->flag |= RX_FLAG_ONLY_MONITOR; 326 327 unicast = FIELD_GET(MT_RXD3_NORMAL_ADDR_TYPE, rxd3) == MT_RXD3_NORMAL_U2M; 328 idx = FIELD_GET(MT_RXD1_NORMAL_WLAN_IDX, rxd1); 329 status->wcid = mt7915_rx_get_wcid(dev, idx, unicast); 330 331 if (status->wcid) { 332 msta = container_of(status->wcid, struct mt7915_sta, wcid); 333 mt76_wcid_add_poll(&dev->mt76, &msta->wcid); 334 } 335 336 status->freq = mphy->chandef.chan->center_freq; 337 status->band = mphy->chandef.chan->band; 338 if (status->band == NL80211_BAND_5GHZ) 339 sband = &mphy->sband_5g.sband; 340 else if (status->band == NL80211_BAND_6GHZ) 341 sband = &mphy->sband_6g.sband; 342 else 343 sband = &mphy->sband_2g.sband; 344 345 if (!sband->channels) 346 return -EINVAL; 347 348 if ((rxd0 & csum_mask) == csum_mask && 349 !(csum_status & (BIT(0) | BIT(2) | BIT(3)))) 350 skb->ip_summed = CHECKSUM_UNNECESSARY; 351 352 if (rxd1 & MT_RXD1_NORMAL_FCS_ERR) 353 status->flag |= RX_FLAG_FAILED_FCS_CRC; 354 355 if (rxd1 & MT_RXD1_NORMAL_TKIP_MIC_ERR) 356 status->flag |= RX_FLAG_MMIC_ERROR; 357 358 if (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1) != 0 && 359 !(rxd1 & (MT_RXD1_NORMAL_CLM | MT_RXD1_NORMAL_CM))) { 360 status->flag |= RX_FLAG_DECRYPTED; 361 status->flag |= RX_FLAG_IV_STRIPPED; 362 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED; 363 } 364 365 remove_pad = FIELD_GET(MT_RXD2_NORMAL_HDR_OFFSET, rxd2); 366 367 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR) 368 return -EINVAL; 369 370 rxd += 6; 371 if (rxd1 & MT_RXD1_NORMAL_GROUP_4) { 372 u32 v0 = le32_to_cpu(rxd[0]); 373 u32 v2 = le32_to_cpu(rxd[2]); 374 375 fc = cpu_to_le16(FIELD_GET(MT_RXD6_FRAME_CONTROL, v0)); 376 qos_ctl = FIELD_GET(MT_RXD8_QOS_CTL, v2); 377 seq_ctrl = FIELD_GET(MT_RXD8_SEQ_CTRL, v2); 378 379 rxd += 4; 380 if ((u8 *)rxd - skb->data >= skb->len) 381 return -EINVAL; 382 } 383 384 if (rxd1 & MT_RXD1_NORMAL_GROUP_1) { 385 u8 *data = (u8 *)rxd; 386 387 if (status->flag & RX_FLAG_DECRYPTED) { 388 switch (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1)) { 389 case MT_CIPHER_AES_CCMP: 390 case MT_CIPHER_CCMP_CCX: 391 case MT_CIPHER_CCMP_256: 392 insert_ccmp_hdr = 393 FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2); 394 fallthrough; 395 case MT_CIPHER_TKIP: 396 case MT_CIPHER_TKIP_NO_MIC: 397 case MT_CIPHER_GCMP: 398 case MT_CIPHER_GCMP_256: 399 status->iv[0] = data[5]; 400 status->iv[1] = data[4]; 401 status->iv[2] = data[3]; 402 status->iv[3] = data[2]; 403 status->iv[4] = data[1]; 404 status->iv[5] = data[0]; 405 break; 406 default: 407 break; 408 } 409 } 410 rxd += 4; 411 if ((u8 *)rxd - skb->data >= skb->len) 412 return -EINVAL; 413 } 414 415 if (rxd1 & MT_RXD1_NORMAL_GROUP_2) { 416 status->timestamp = le32_to_cpu(rxd[0]); 417 status->flag |= RX_FLAG_MACTIME_START; 418 419 if (!(rxd2 & MT_RXD2_NORMAL_NON_AMPDU)) { 420 status->flag |= RX_FLAG_AMPDU_DETAILS; 421 422 /* all subframes of an A-MPDU have the same timestamp */ 423 if (phy->rx_ampdu_ts != status->timestamp) { 424 if (!++phy->ampdu_ref) 425 phy->ampdu_ref++; 426 } 427 phy->rx_ampdu_ts = status->timestamp; 428 429 status->ampdu_ref = phy->ampdu_ref; 430 } 431 432 rxd += 2; 433 if ((u8 *)rxd - skb->data >= skb->len) 434 return -EINVAL; 435 } 436 437 /* RXD Group 3 - P-RXV */ 438 if (rxd1 & MT_RXD1_NORMAL_GROUP_3) { 439 u32 v0, v1; 440 int ret; 441 442 rxv = rxd; 443 rxd += 2; 444 if ((u8 *)rxd - skb->data >= skb->len) 445 return -EINVAL; 446 447 v0 = le32_to_cpu(rxv[0]); 448 v1 = le32_to_cpu(rxv[1]); 449 450 if (v0 & MT_PRXV_HT_AD_CODE) 451 status->enc_flags |= RX_ENC_FLAG_LDPC; 452 453 status->chains = mphy->antenna_mask; 454 status->chain_signal[0] = to_rssi(MT_PRXV_RCPI0, v1); 455 status->chain_signal[1] = to_rssi(MT_PRXV_RCPI1, v1); 456 status->chain_signal[2] = to_rssi(MT_PRXV_RCPI2, v1); 457 status->chain_signal[3] = to_rssi(MT_PRXV_RCPI3, v1); 458 459 /* RXD Group 5 - C-RXV */ 460 if (rxd1 & MT_RXD1_NORMAL_GROUP_5) { 461 rxd += 18; 462 if ((u8 *)rxd - skb->data >= skb->len) 463 return -EINVAL; 464 } 465 466 if (!is_mt7915(&dev->mt76) || (rxd1 & MT_RXD1_NORMAL_GROUP_5)) { 467 ret = mt76_connac2_mac_fill_rx_rate(&dev->mt76, status, 468 sband, rxv, &mode); 469 if (ret < 0) 470 return ret; 471 } 472 } 473 474 amsdu_info = FIELD_GET(MT_RXD4_NORMAL_PAYLOAD_FORMAT, rxd4); 475 status->amsdu = !!amsdu_info; 476 if (status->amsdu) { 477 status->first_amsdu = amsdu_info == MT_RXD4_FIRST_AMSDU_FRAME; 478 status->last_amsdu = amsdu_info == MT_RXD4_LAST_AMSDU_FRAME; 479 } 480 481 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad; 482 if (hdr_trans && ieee80211_has_morefrags(fc)) { 483 struct ieee80211_vif *vif; 484 int err; 485 486 if (!msta || !msta->vif) 487 return -EINVAL; 488 489 vif = container_of((void *)msta->vif, struct ieee80211_vif, 490 drv_priv); 491 err = mt76_connac2_reverse_frag0_hdr_trans(vif, skb, hdr_gap); 492 if (err) 493 return err; 494 495 hdr_trans = false; 496 } else { 497 int pad_start = 0; 498 499 skb_pull(skb, hdr_gap); 500 if (!hdr_trans && status->amsdu) { 501 pad_start = ieee80211_get_hdrlen_from_skb(skb); 502 } else if (hdr_trans && (rxd2 & MT_RXD2_NORMAL_HDR_TRANS_ERROR)) { 503 /* 504 * When header translation failure is indicated, 505 * the hardware will insert an extra 2-byte field 506 * containing the data length after the protocol 507 * type field. This happens either when the LLC-SNAP 508 * pattern did not match, or if a VLAN header was 509 * detected. 510 */ 511 pad_start = 12; 512 if (get_unaligned_be16(skb->data + pad_start) == ETH_P_8021Q) 513 pad_start += 4; 514 else 515 pad_start = 0; 516 } 517 518 if (pad_start) { 519 memmove(skb->data + 2, skb->data, pad_start); 520 skb_pull(skb, 2); 521 } 522 } 523 524 if (!hdr_trans) { 525 struct ieee80211_hdr *hdr; 526 527 if (insert_ccmp_hdr) { 528 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1); 529 530 mt76_insert_ccmp_hdr(skb, key_id); 531 } 532 533 hdr = mt76_skb_get_hdr(skb); 534 fc = hdr->frame_control; 535 if (ieee80211_is_data_qos(fc)) { 536 seq_ctrl = le16_to_cpu(hdr->seq_ctrl); 537 qos_ctl = *ieee80211_get_qos_ctl(hdr); 538 } 539 } else { 540 status->flag |= RX_FLAG_8023; 541 mt7915_wed_check_ppe(dev, &dev->mt76.q_rx[q], msta, skb, 542 *info); 543 } 544 545 if (rxv && mode >= MT_PHY_TYPE_HE_SU && !(status->flag & RX_FLAG_8023)) 546 mt76_connac2_mac_decode_he_radiotap(&dev->mt76, skb, rxv, mode); 547 548 if (!status->wcid || !ieee80211_is_data_qos(fc)) 549 return 0; 550 551 status->aggr = unicast && 552 !ieee80211_is_qos_nullfunc(fc); 553 status->qos_ctl = qos_ctl; 554 status->seqno = IEEE80211_SEQ_TO_SN(seq_ctrl); 555 556 return 0; 557 } 558 559 static void 560 mt7915_mac_fill_rx_vector(struct mt7915_dev *dev, struct sk_buff *skb) 561 { 562 #ifdef CONFIG_NL80211_TESTMODE 563 struct mt7915_phy *phy = &dev->phy; 564 __le32 *rxd = (__le32 *)skb->data; 565 __le32 *rxv_hdr = rxd + 2; 566 __le32 *rxv = rxd + 4; 567 u32 rcpi, ib_rssi, wb_rssi, v20, v21; 568 u8 band_idx; 569 s32 foe; 570 u8 snr; 571 int i; 572 573 band_idx = le32_get_bits(rxv_hdr[1], MT_RXV_HDR_BAND_IDX); 574 if (band_idx && !phy->mt76->band_idx) { 575 phy = mt7915_ext_phy(dev); 576 if (!phy) 577 goto out; 578 } 579 580 rcpi = le32_to_cpu(rxv[6]); 581 ib_rssi = le32_to_cpu(rxv[7]); 582 wb_rssi = le32_to_cpu(rxv[8]) >> 5; 583 584 for (i = 0; i < 4; i++, rcpi >>= 8, ib_rssi >>= 8, wb_rssi >>= 9) { 585 if (i == 3) 586 wb_rssi = le32_to_cpu(rxv[9]); 587 588 phy->test.last_rcpi[i] = rcpi & 0xff; 589 phy->test.last_ib_rssi[i] = ib_rssi & 0xff; 590 phy->test.last_wb_rssi[i] = wb_rssi & 0xff; 591 } 592 593 v20 = le32_to_cpu(rxv[20]); 594 v21 = le32_to_cpu(rxv[21]); 595 596 foe = FIELD_GET(MT_CRXV_FOE_LO, v20) | 597 (FIELD_GET(MT_CRXV_FOE_HI, v21) << MT_CRXV_FOE_SHIFT); 598 599 snr = FIELD_GET(MT_CRXV_SNR, v20) - 16; 600 601 phy->test.last_freq_offset = foe; 602 phy->test.last_snr = snr; 603 out: 604 #endif 605 dev_kfree_skb(skb); 606 } 607 608 static void 609 mt7915_mac_write_txwi_tm(struct mt7915_phy *phy, __le32 *txwi, 610 struct sk_buff *skb) 611 { 612 #ifdef CONFIG_NL80211_TESTMODE 613 struct mt76_testmode_data *td = &phy->mt76->test; 614 const struct ieee80211_rate *r; 615 u8 bw, mode, nss = td->tx_rate_nss; 616 u8 rate_idx = td->tx_rate_idx; 617 u16 rateval = 0; 618 u32 val; 619 bool cck = false; 620 int band; 621 622 if (skb != phy->mt76->test.tx_skb) 623 return; 624 625 switch (td->tx_rate_mode) { 626 case MT76_TM_TX_MODE_HT: 627 nss = 1 + (rate_idx >> 3); 628 mode = MT_PHY_TYPE_HT; 629 break; 630 case MT76_TM_TX_MODE_VHT: 631 mode = MT_PHY_TYPE_VHT; 632 break; 633 case MT76_TM_TX_MODE_HE_SU: 634 mode = MT_PHY_TYPE_HE_SU; 635 break; 636 case MT76_TM_TX_MODE_HE_EXT_SU: 637 mode = MT_PHY_TYPE_HE_EXT_SU; 638 break; 639 case MT76_TM_TX_MODE_HE_TB: 640 mode = MT_PHY_TYPE_HE_TB; 641 break; 642 case MT76_TM_TX_MODE_HE_MU: 643 mode = MT_PHY_TYPE_HE_MU; 644 break; 645 case MT76_TM_TX_MODE_CCK: 646 cck = true; 647 fallthrough; 648 case MT76_TM_TX_MODE_OFDM: 649 band = phy->mt76->chandef.chan->band; 650 if (band == NL80211_BAND_2GHZ && !cck) 651 rate_idx += 4; 652 653 r = &phy->mt76->hw->wiphy->bands[band]->bitrates[rate_idx]; 654 val = cck ? r->hw_value_short : r->hw_value; 655 656 mode = val >> 8; 657 rate_idx = val & 0xff; 658 break; 659 default: 660 mode = MT_PHY_TYPE_OFDM; 661 break; 662 } 663 664 switch (phy->mt76->chandef.width) { 665 case NL80211_CHAN_WIDTH_40: 666 bw = 1; 667 break; 668 case NL80211_CHAN_WIDTH_80: 669 bw = 2; 670 break; 671 case NL80211_CHAN_WIDTH_80P80: 672 case NL80211_CHAN_WIDTH_160: 673 bw = 3; 674 break; 675 default: 676 bw = 0; 677 break; 678 } 679 680 if (td->tx_rate_stbc && nss == 1) { 681 nss++; 682 rateval |= MT_TX_RATE_STBC; 683 } 684 685 rateval |= FIELD_PREP(MT_TX_RATE_IDX, rate_idx) | 686 FIELD_PREP(MT_TX_RATE_MODE, mode) | 687 FIELD_PREP(MT_TX_RATE_NSS, nss - 1); 688 689 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE); 690 691 le32p_replace_bits(&txwi[3], 1, MT_TXD3_REM_TX_COUNT); 692 if (td->tx_rate_mode < MT76_TM_TX_MODE_HT) 693 txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE); 694 695 val = MT_TXD6_FIXED_BW | 696 FIELD_PREP(MT_TXD6_BW, bw) | 697 FIELD_PREP(MT_TXD6_TX_RATE, rateval) | 698 FIELD_PREP(MT_TXD6_SGI, td->tx_rate_sgi); 699 700 /* for HE_SU/HE_EXT_SU PPDU 701 * - 1x, 2x, 4x LTF + 0.8us GI 702 * - 2x LTF + 1.6us GI, 4x LTF + 3.2us GI 703 * for HE_MU PPDU 704 * - 2x, 4x LTF + 0.8us GI 705 * - 2x LTF + 1.6us GI, 4x LTF + 3.2us GI 706 * for HE_TB PPDU 707 * - 1x, 2x LTF + 1.6us GI 708 * - 4x LTF + 3.2us GI 709 */ 710 if (mode >= MT_PHY_TYPE_HE_SU) 711 val |= FIELD_PREP(MT_TXD6_HELTF, td->tx_ltf); 712 713 if (td->tx_rate_ldpc || (bw > 0 && mode >= MT_PHY_TYPE_HE_SU)) 714 val |= MT_TXD6_LDPC; 715 716 txwi[3] &= ~cpu_to_le32(MT_TXD3_SN_VALID); 717 txwi[6] |= cpu_to_le32(val); 718 txwi[7] |= cpu_to_le32(FIELD_PREP(MT_TXD7_SPE_IDX, 719 phy->test.spe_idx)); 720 #endif 721 } 722 723 void mt7915_mac_write_txwi(struct mt76_dev *dev, __le32 *txwi, 724 struct sk_buff *skb, struct mt76_wcid *wcid, int pid, 725 struct ieee80211_key_conf *key, 726 enum mt76_txq_id qid, u32 changed) 727 { 728 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 729 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2; 730 struct mt76_phy *mphy = &dev->phy; 731 732 if (phy_idx && dev->phys[MT_BAND1]) 733 mphy = dev->phys[MT_BAND1]; 734 735 mt76_connac2_mac_write_txwi(dev, txwi, skb, wcid, key, pid, qid, changed); 736 737 if (mt76_testmode_enabled(mphy)) 738 mt7915_mac_write_txwi_tm(mphy->priv, txwi, skb); 739 } 740 741 int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, 742 enum mt76_txq_id qid, struct mt76_wcid *wcid, 743 struct ieee80211_sta *sta, 744 struct mt76_tx_info *tx_info) 745 { 746 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_info->skb->data; 747 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 748 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb); 749 struct ieee80211_key_conf *key = info->control.hw_key; 750 struct ieee80211_vif *vif = info->control.vif; 751 struct mt76_connac_fw_txp *txp; 752 struct mt76_txwi_cache *t; 753 int id, i, nbuf = tx_info->nbuf - 1; 754 u8 *txwi = (u8 *)txwi_ptr; 755 int pid; 756 757 if (unlikely(tx_info->skb->len <= ETH_HLEN)) 758 return -EINVAL; 759 760 if (!wcid) 761 wcid = &dev->mt76.global_wcid; 762 763 if (sta) { 764 struct mt7915_sta *msta; 765 766 msta = (struct mt7915_sta *)sta->drv_priv; 767 768 if (time_after(jiffies, msta->jiffies + HZ / 4)) { 769 info->flags |= IEEE80211_TX_CTL_REQ_TX_STATUS; 770 msta->jiffies = jiffies; 771 } 772 } 773 774 t = (struct mt76_txwi_cache *)(txwi + mdev->drv->txwi_size); 775 t->skb = tx_info->skb; 776 777 id = mt76_token_consume(mdev, &t); 778 if (id < 0) 779 return id; 780 781 pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb); 782 mt7915_mac_write_txwi(mdev, txwi_ptr, tx_info->skb, wcid, pid, key, 783 qid, 0); 784 785 txp = (struct mt76_connac_fw_txp *)(txwi + MT_TXD_SIZE); 786 for (i = 0; i < nbuf; i++) { 787 txp->buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr); 788 txp->len[i] = cpu_to_le16(tx_info->buf[i + 1].len); 789 } 790 txp->nbuf = nbuf; 791 792 txp->flags = cpu_to_le16(MT_CT_INFO_APPLY_TXD | MT_CT_INFO_FROM_HOST); 793 794 if (!key) 795 txp->flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME); 796 797 if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && 798 ieee80211_is_mgmt(hdr->frame_control)) 799 txp->flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME); 800 801 if (vif) { 802 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv; 803 804 txp->bss_idx = mvif->mt76.idx; 805 } 806 807 txp->token = cpu_to_le16(id); 808 if (test_bit(MT_WCID_FLAG_4ADDR, &wcid->flags)) 809 txp->rept_wds_wcid = cpu_to_le16(wcid->idx); 810 else 811 txp->rept_wds_wcid = cpu_to_le16(0x3ff); 812 tx_info->skb = NULL; 813 814 /* pass partial skb header to fw */ 815 tx_info->buf[1].len = MT_CT_PARSE_LEN; 816 tx_info->buf[1].skip_unmap = true; 817 tx_info->nbuf = MT_CT_DMA_BUF_NUM; 818 819 return 0; 820 } 821 822 u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id) 823 { 824 struct mt76_connac_fw_txp *txp = ptr + MT_TXD_SIZE; 825 __le32 *txwi = ptr; 826 u32 val; 827 828 memset(ptr, 0, MT_TXD_SIZE + sizeof(*txp)); 829 830 val = FIELD_PREP(MT_TXD0_TX_BYTES, MT_TXD_SIZE) | 831 FIELD_PREP(MT_TXD0_PKT_FMT, MT_TX_TYPE_CT); 832 txwi[0] = cpu_to_le32(val); 833 834 val = MT_TXD1_LONG_FORMAT | 835 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_3); 836 txwi[1] = cpu_to_le32(val); 837 838 txp->token = cpu_to_le16(token_id); 839 txp->nbuf = 1; 840 txp->buf[0] = cpu_to_le32(phys + MT_TXD_SIZE + sizeof(*txp)); 841 842 return MT_TXD_SIZE + sizeof(*txp); 843 } 844 845 static void 846 mt7915_mac_tx_free_prepare(struct mt7915_dev *dev) 847 { 848 struct mt76_dev *mdev = &dev->mt76; 849 struct mt76_phy *mphy_ext = mdev->phys[MT_BAND1]; 850 851 /* clean DMA queues and unmap buffers first */ 852 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false); 853 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false); 854 if (mphy_ext) { 855 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_PSD], false); 856 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_BE], false); 857 } 858 } 859 860 static void 861 mt7915_mac_tx_free_done(struct mt7915_dev *dev, 862 struct list_head *free_list, bool wake) 863 { 864 struct sk_buff *skb, *tmp; 865 866 mt7915_mac_sta_poll(dev); 867 868 if (wake) 869 mt76_set_tx_blocked(&dev->mt76, false); 870 871 mt76_worker_schedule(&dev->mt76.tx_worker); 872 873 list_for_each_entry_safe(skb, tmp, free_list, list) { 874 skb_list_del_init(skb); 875 napi_consume_skb(skb, 1); 876 } 877 } 878 879 static void 880 mt7915_mac_tx_free(struct mt7915_dev *dev, void *data, int len) 881 { 882 struct mt76_connac_tx_free *free = data; 883 __le32 *tx_info = (__le32 *)(data + sizeof(*free)); 884 struct mt76_dev *mdev = &dev->mt76; 885 struct mt76_txwi_cache *txwi; 886 struct ieee80211_sta *sta = NULL; 887 struct mt76_wcid *wcid = NULL; 888 LIST_HEAD(free_list); 889 void *end = data + len; 890 bool v3, wake = false; 891 u16 total, count = 0; 892 u32 txd = le32_to_cpu(free->txd); 893 __le32 *cur_info; 894 895 mt7915_mac_tx_free_prepare(dev); 896 897 total = le16_get_bits(free->ctrl, MT_TX_FREE_MSDU_CNT); 898 v3 = (FIELD_GET(MT_TX_FREE_VER, txd) == 0x4); 899 900 for (cur_info = tx_info; count < total; cur_info++) { 901 u32 msdu, info; 902 u8 i; 903 904 if (WARN_ON_ONCE((void *)cur_info >= end)) 905 return; 906 907 /* 908 * 1'b1: new wcid pair. 909 * 1'b0: msdu_id with the same 'wcid pair' as above. 910 */ 911 info = le32_to_cpu(*cur_info); 912 if (info & MT_TX_FREE_PAIR) { 913 struct mt7915_sta *msta; 914 u16 idx; 915 916 idx = FIELD_GET(MT_TX_FREE_WLAN_ID, info); 917 wcid = mt76_wcid_ptr(dev, idx); 918 sta = wcid_to_sta(wcid); 919 if (!sta) 920 continue; 921 922 msta = container_of(wcid, struct mt7915_sta, wcid); 923 mt76_wcid_add_poll(&dev->mt76, &msta->wcid); 924 continue; 925 } 926 927 if (!mtk_wed_device_active(&mdev->mmio.wed) && wcid) { 928 u32 tx_retries = 0, tx_failed = 0; 929 930 if (v3 && (info & MT_TX_FREE_MPDU_HEADER_V3)) { 931 tx_retries = 932 FIELD_GET(MT_TX_FREE_COUNT_V3, info) - 1; 933 tx_failed = tx_retries + 934 !!FIELD_GET(MT_TX_FREE_STAT_V3, info); 935 } else if (!v3 && (info & MT_TX_FREE_MPDU_HEADER)) { 936 tx_retries = 937 FIELD_GET(MT_TX_FREE_COUNT, info) - 1; 938 tx_failed = tx_retries + 939 !!FIELD_GET(MT_TX_FREE_STAT, info); 940 } 941 wcid->stats.tx_retries += tx_retries; 942 wcid->stats.tx_failed += tx_failed; 943 } 944 945 if (v3 && (info & MT_TX_FREE_MPDU_HEADER_V3)) 946 continue; 947 948 for (i = 0; i < 1 + v3; i++) { 949 if (v3) { 950 msdu = (info >> (15 * i)) & MT_TX_FREE_MSDU_ID_V3; 951 if (msdu == MT_TX_FREE_MSDU_ID_V3) 952 continue; 953 } else { 954 msdu = FIELD_GET(MT_TX_FREE_MSDU_ID, info); 955 } 956 count++; 957 txwi = mt76_token_release(mdev, msdu, &wake); 958 if (!txwi) 959 continue; 960 961 mt76_connac2_txwi_free(mdev, txwi, sta, &free_list); 962 } 963 } 964 965 mt7915_mac_tx_free_done(dev, &free_list, wake); 966 } 967 968 static void 969 mt7915_mac_tx_free_v0(struct mt7915_dev *dev, void *data, int len) 970 { 971 struct mt76_connac_tx_free *free = data; 972 __le16 *info = (__le16 *)(data + sizeof(*free)); 973 struct mt76_dev *mdev = &dev->mt76; 974 void *end = data + len; 975 LIST_HEAD(free_list); 976 bool wake = false; 977 u8 i, count; 978 979 mt7915_mac_tx_free_prepare(dev); 980 981 count = FIELD_GET(MT_TX_FREE_MSDU_CNT_V0, le16_to_cpu(free->ctrl)); 982 if (WARN_ON_ONCE((void *)&info[count] > end)) 983 return; 984 985 for (i = 0; i < count; i++) { 986 struct mt76_txwi_cache *txwi; 987 u16 msdu = le16_to_cpu(info[i]); 988 989 txwi = mt76_token_release(mdev, msdu, &wake); 990 if (!txwi) 991 continue; 992 993 mt76_connac2_txwi_free(mdev, txwi, NULL, &free_list); 994 } 995 996 mt7915_mac_tx_free_done(dev, &free_list, wake); 997 } 998 999 static void mt7915_mac_add_txs(struct mt7915_dev *dev, void *data) 1000 { 1001 struct mt7915_sta *msta = NULL; 1002 struct mt76_wcid *wcid; 1003 __le32 *txs_data = data; 1004 u16 wcidx; 1005 u8 pid; 1006 1007 wcidx = le32_get_bits(txs_data[2], MT_TXS2_WCID); 1008 pid = le32_get_bits(txs_data[3], MT_TXS3_PID); 1009 1010 if (pid < MT_PACKET_ID_WED) 1011 return; 1012 1013 rcu_read_lock(); 1014 1015 wcid = mt76_wcid_ptr(dev, wcidx); 1016 if (!wcid) 1017 goto out; 1018 1019 msta = container_of(wcid, struct mt7915_sta, wcid); 1020 1021 if (pid == MT_PACKET_ID_WED) 1022 mt76_connac2_mac_fill_txs(&dev->mt76, wcid, txs_data); 1023 else 1024 mt76_connac2_mac_add_txs_skb(&dev->mt76, wcid, pid, txs_data); 1025 1026 if (!wcid->sta) 1027 goto out; 1028 1029 mt76_wcid_add_poll(&dev->mt76, &msta->wcid); 1030 1031 out: 1032 rcu_read_unlock(); 1033 } 1034 1035 bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len) 1036 { 1037 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 1038 __le32 *rxd = (__le32 *)data; 1039 __le32 *end = (__le32 *)&rxd[len / 4]; 1040 enum rx_pkt_type type; 1041 1042 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); 1043 1044 switch (type) { 1045 case PKT_TYPE_TXRX_NOTIFY: 1046 mt7915_mac_tx_free(dev, data, len); 1047 return false; 1048 case PKT_TYPE_TXRX_NOTIFY_V0: 1049 mt7915_mac_tx_free_v0(dev, data, len); 1050 return false; 1051 case PKT_TYPE_TXS: 1052 for (rxd += 2; rxd + 8 <= end; rxd += 8) 1053 mt7915_mac_add_txs(dev, rxd); 1054 return false; 1055 case PKT_TYPE_RX_FW_MONITOR: 1056 mt7915_debugfs_rx_fw_monitor(dev, data, len); 1057 return false; 1058 default: 1059 return true; 1060 } 1061 } 1062 1063 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 1064 struct sk_buff *skb, u32 *info) 1065 { 1066 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 1067 __le32 *rxd = (__le32 *)skb->data; 1068 __le32 *end = (__le32 *)&skb->data[skb->len]; 1069 enum rx_pkt_type type; 1070 1071 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); 1072 1073 switch (type) { 1074 case PKT_TYPE_TXRX_NOTIFY: 1075 mt7915_mac_tx_free(dev, skb->data, skb->len); 1076 napi_consume_skb(skb, 1); 1077 break; 1078 case PKT_TYPE_TXRX_NOTIFY_V0: 1079 mt7915_mac_tx_free_v0(dev, skb->data, skb->len); 1080 napi_consume_skb(skb, 1); 1081 break; 1082 case PKT_TYPE_RX_EVENT: 1083 mt7915_mcu_rx_event(dev, skb); 1084 break; 1085 case PKT_TYPE_TXRXV: 1086 mt7915_mac_fill_rx_vector(dev, skb); 1087 break; 1088 case PKT_TYPE_TXS: 1089 for (rxd += 2; rxd + 8 <= end; rxd += 8) 1090 mt7915_mac_add_txs(dev, rxd); 1091 dev_kfree_skb(skb); 1092 break; 1093 case PKT_TYPE_RX_FW_MONITOR: 1094 mt7915_debugfs_rx_fw_monitor(dev, skb->data, skb->len); 1095 dev_kfree_skb(skb); 1096 break; 1097 case PKT_TYPE_NORMAL: 1098 if (!mt7915_mac_fill_rx(dev, skb, q, info)) { 1099 mt76_rx(&dev->mt76, q, skb); 1100 return; 1101 } 1102 fallthrough; 1103 default: 1104 dev_kfree_skb(skb); 1105 break; 1106 } 1107 } 1108 1109 void mt7915_mac_cca_stats_reset(struct mt7915_phy *phy) 1110 { 1111 struct mt7915_dev *dev = phy->dev; 1112 u32 reg = MT_WF_PHY_RX_CTRL1(phy->mt76->band_idx); 1113 1114 mt76_clear(dev, reg, MT_WF_PHY_RX_CTRL1_STSCNT_EN); 1115 mt76_set(dev, reg, BIT(11) | BIT(9)); 1116 } 1117 1118 void mt7915_mac_reset_counters(struct mt7915_phy *phy) 1119 { 1120 struct mt7915_dev *dev = phy->dev; 1121 int i; 1122 1123 for (i = 0; i < 4; i++) { 1124 mt76_rr(dev, MT_TX_AGG_CNT(phy->mt76->band_idx, i)); 1125 mt76_rr(dev, MT_TX_AGG_CNT2(phy->mt76->band_idx, i)); 1126 } 1127 1128 phy->mt76->survey_time = ktime_get_boottime(); 1129 memset(phy->mt76->aggr_stats, 0, sizeof(phy->mt76->aggr_stats)); 1130 1131 /* reset airtime counters */ 1132 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(phy->mt76->band_idx), 1133 MT_WF_RMAC_MIB_RXTIME_CLR); 1134 1135 mt7915_mcu_get_chan_mib_info(phy, true); 1136 } 1137 1138 void mt7915_mac_set_timing(struct mt7915_phy *phy) 1139 { 1140 s16 coverage_class = phy->coverage_class; 1141 struct mt7915_dev *dev = phy->dev; 1142 struct mt7915_phy *ext_phy = mt7915_ext_phy(dev); 1143 u32 val, reg_offset; 1144 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | 1145 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); 1146 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | 1147 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28); 1148 u8 band = phy->mt76->band_idx; 1149 int eifs_ofdm = 84, sifs = 10, offset; 1150 bool a_band = !(phy->mt76->chandef.chan->band == NL80211_BAND_2GHZ); 1151 1152 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state)) 1153 return; 1154 1155 if (ext_phy) 1156 coverage_class = max_t(s16, dev->phy.coverage_class, 1157 ext_phy->coverage_class); 1158 1159 mt76_set(dev, MT_ARB_SCR(band), 1160 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1161 udelay(1); 1162 1163 offset = 3 * coverage_class; 1164 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | 1165 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); 1166 1167 if (!is_mt7915(&dev->mt76)) { 1168 if (!a_band) { 1169 mt76_wr(dev, MT_TMAC_ICR1(band), 1170 FIELD_PREP(MT_IFS_EIFS_CCK, 314)); 1171 eifs_ofdm = 78; 1172 } else { 1173 eifs_ofdm = 84; 1174 } 1175 } else if (a_band) { 1176 sifs = 16; 1177 } 1178 1179 mt76_wr(dev, MT_TMAC_CDTR(band), cck + reg_offset); 1180 mt76_wr(dev, MT_TMAC_ODTR(band), ofdm + reg_offset); 1181 mt76_wr(dev, MT_TMAC_ICR0(band), 1182 FIELD_PREP(MT_IFS_EIFS_OFDM, eifs_ofdm) | 1183 FIELD_PREP(MT_IFS_RIFS, 2) | 1184 FIELD_PREP(MT_IFS_SIFS, sifs) | 1185 FIELD_PREP(MT_IFS_SLOT, phy->slottime)); 1186 1187 if (phy->slottime < 20 || a_band) 1188 val = MT7915_CFEND_RATE_DEFAULT; 1189 else 1190 val = MT7915_CFEND_RATE_11B; 1191 1192 mt76_rmw_field(dev, MT_AGG_ACR0(band), MT_AGG_ACR_CFEND_RATE, val); 1193 mt76_clear(dev, MT_ARB_SCR(band), 1194 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1195 } 1196 1197 void mt7915_mac_enable_nf(struct mt7915_dev *dev, bool band) 1198 { 1199 u32 reg; 1200 1201 reg = is_mt7915(&dev->mt76) ? MT_WF_PHY_RXTD12(band) : 1202 MT_WF_PHY_RXTD12_MT7916(band); 1203 mt76_set(dev, reg, 1204 MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY | 1205 MT_WF_PHY_RXTD12_IRPI_SW_CLR); 1206 1207 reg = is_mt7915(&dev->mt76) ? MT_WF_PHY_RX_CTRL1(band) : 1208 MT_WF_PHY_RX_CTRL1_MT7916(band); 1209 mt76_set(dev, reg, FIELD_PREP(MT_WF_PHY_RX_CTRL1_IPI_EN, 0x5)); 1210 } 1211 1212 static u8 1213 mt7915_phy_get_nf(struct mt7915_phy *phy, int idx) 1214 { 1215 static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 }; 1216 struct mt7915_dev *dev = phy->dev; 1217 u32 val, sum = 0, n = 0; 1218 int nss, i; 1219 1220 for (nss = 0; nss < hweight8(phy->mt76->chainmask); nss++) { 1221 u32 reg = is_mt7915(&dev->mt76) ? 1222 MT_WF_IRPI_NSS(0, nss + (idx << dev->dbdc_support)) : 1223 MT_WF_IRPI_NSS_MT7916(idx, nss); 1224 1225 for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) { 1226 val = mt76_rr(dev, reg); 1227 sum += val * nf_power[i]; 1228 n += val; 1229 } 1230 } 1231 1232 if (!n) 1233 return 0; 1234 1235 return sum / n; 1236 } 1237 1238 void mt7915_update_channel(struct mt76_phy *mphy) 1239 { 1240 struct mt7915_phy *phy = mphy->priv; 1241 struct mt76_channel_state *state = mphy->chan_state; 1242 int nf; 1243 1244 mt7915_mcu_get_chan_mib_info(phy, false); 1245 1246 nf = mt7915_phy_get_nf(phy, phy->mt76->band_idx); 1247 if (!phy->noise) 1248 phy->noise = nf << 4; 1249 else if (nf) 1250 phy->noise += nf - (phy->noise >> 4); 1251 1252 state->noise = -(phy->noise >> 4); 1253 } 1254 1255 static bool 1256 mt7915_wait_reset_state(struct mt7915_dev *dev, u32 state) 1257 { 1258 bool ret; 1259 1260 ret = wait_event_timeout(dev->reset_wait, 1261 (READ_ONCE(dev->recovery.state) & state), 1262 MT7915_RESET_TIMEOUT); 1263 1264 WARN(!ret, "Timeout waiting for MCU reset state %x\n", state); 1265 return ret; 1266 } 1267 1268 static void 1269 mt7915_update_vif_beacon(void *priv, u8 *mac, struct ieee80211_vif *vif) 1270 { 1271 struct ieee80211_hw *hw = priv; 1272 1273 switch (vif->type) { 1274 case NL80211_IFTYPE_MESH_POINT: 1275 case NL80211_IFTYPE_ADHOC: 1276 case NL80211_IFTYPE_AP: 1277 mt7915_mcu_add_beacon(hw, vif, vif->bss_conf.enable_beacon, 1278 BSS_CHANGED_BEACON_ENABLED); 1279 break; 1280 default: 1281 break; 1282 } 1283 } 1284 1285 static void 1286 mt7915_update_beacons(struct mt7915_dev *dev) 1287 { 1288 struct mt76_phy *mphy_ext = dev->mt76.phys[MT_BAND1]; 1289 1290 ieee80211_iterate_active_interfaces(dev->mt76.hw, 1291 IEEE80211_IFACE_ITER_RESUME_ALL, 1292 mt7915_update_vif_beacon, dev->mt76.hw); 1293 1294 if (!mphy_ext) 1295 return; 1296 1297 ieee80211_iterate_active_interfaces(mphy_ext->hw, 1298 IEEE80211_IFACE_ITER_RESUME_ALL, 1299 mt7915_update_vif_beacon, mphy_ext->hw); 1300 } 1301 1302 static int 1303 mt7915_mac_restart(struct mt7915_dev *dev) 1304 { 1305 struct mt7915_phy *phy2; 1306 struct mt76_phy *ext_phy; 1307 struct mt76_dev *mdev = &dev->mt76; 1308 int i, ret; 1309 1310 ext_phy = dev->mt76.phys[MT_BAND1]; 1311 phy2 = ext_phy ? ext_phy->priv : NULL; 1312 1313 if (dev->hif2) { 1314 mt76_wr(dev, MT_INT1_MASK_CSR, 0x0); 1315 mt76_wr(dev, MT_INT1_SOURCE_CSR, ~0); 1316 } 1317 1318 if (dev_is_pci(mdev->dev)) { 1319 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0); 1320 if (dev->hif2) { 1321 if (is_mt7915(mdev)) 1322 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE, 0x0); 1323 else 1324 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE_MT7916, 0x0); 1325 } 1326 } 1327 1328 set_bit(MT76_RESET, &dev->mphy.state); 1329 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1330 wake_up(&dev->mt76.mcu.wait); 1331 if (ext_phy) 1332 set_bit(MT76_RESET, &ext_phy->state); 1333 1334 /* lock/unlock all queues to ensure that no tx is pending */ 1335 mt76_txq_schedule_all(&dev->mphy); 1336 if (ext_phy) 1337 mt76_txq_schedule_all(ext_phy); 1338 1339 /* disable all tx/rx napi */ 1340 mt76_worker_disable(&dev->mt76.tx_worker); 1341 mt76_for_each_q_rx(mdev, i) { 1342 if (mdev->q_rx[i].ndesc) 1343 napi_disable(&dev->mt76.napi[i]); 1344 } 1345 napi_disable(&dev->mt76.tx_napi); 1346 1347 /* token reinit */ 1348 mt76_connac2_tx_token_put(&dev->mt76); 1349 idr_init(&dev->mt76.token); 1350 1351 mt7915_dma_reset(dev, true); 1352 1353 mt76_for_each_q_rx(mdev, i) { 1354 if (mdev->q_rx[i].ndesc) { 1355 napi_enable(&dev->mt76.napi[i]); 1356 } 1357 } 1358 1359 local_bh_disable(); 1360 mt76_for_each_q_rx(mdev, i) { 1361 if (mdev->q_rx[i].ndesc) { 1362 napi_schedule(&dev->mt76.napi[i]); 1363 } 1364 } 1365 local_bh_enable(); 1366 clear_bit(MT76_MCU_RESET, &dev->mphy.state); 1367 clear_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state); 1368 1369 mt76_wr(dev, MT_INT_MASK_CSR, dev->mt76.mmio.irqmask); 1370 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 1371 1372 if (dev->hif2) { 1373 mt76_wr(dev, MT_INT1_MASK_CSR, dev->mt76.mmio.irqmask); 1374 mt76_wr(dev, MT_INT1_SOURCE_CSR, ~0); 1375 } 1376 if (dev_is_pci(mdev->dev)) { 1377 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff); 1378 if (dev->hif2) { 1379 mt76_wr(dev, MT_PCIE_RECOG_ID, 1380 dev->hif2->index | MT_PCIE_RECOG_ID_SEM); 1381 if (is_mt7915(mdev)) 1382 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE, 0xff); 1383 else 1384 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE_MT7916, 0xff); 1385 } 1386 } 1387 1388 /* load firmware */ 1389 ret = mt7915_mcu_init_firmware(dev); 1390 if (ret) 1391 goto out; 1392 1393 /* set the necessary init items */ 1394 ret = mt7915_mcu_set_eeprom(dev); 1395 if (ret) 1396 goto out; 1397 1398 mt7915_mac_init(dev); 1399 mt7915_init_txpower(&dev->phy); 1400 mt7915_init_txpower(phy2); 1401 ret = mt7915_txbf_init(dev); 1402 1403 if (test_bit(MT76_STATE_RUNNING, &dev->mphy.state)) { 1404 ret = mt7915_run(dev->mphy.hw); 1405 if (ret) 1406 goto out; 1407 } 1408 1409 if (ext_phy && test_bit(MT76_STATE_RUNNING, &ext_phy->state)) { 1410 ret = mt7915_run(ext_phy->hw); 1411 if (ret) 1412 goto out; 1413 } 1414 1415 out: 1416 /* reset done */ 1417 clear_bit(MT76_RESET, &dev->mphy.state); 1418 if (phy2) 1419 clear_bit(MT76_RESET, &phy2->mt76->state); 1420 1421 napi_enable(&dev->mt76.tx_napi); 1422 1423 local_bh_disable(); 1424 napi_schedule(&dev->mt76.tx_napi); 1425 local_bh_enable(); 1426 1427 mt76_worker_enable(&dev->mt76.tx_worker); 1428 1429 return ret; 1430 } 1431 1432 static void 1433 mt7915_mac_full_reset(struct mt7915_dev *dev) 1434 { 1435 struct mt76_phy *ext_phy; 1436 struct mt7915_phy *phy2; 1437 int i; 1438 1439 ext_phy = dev->mt76.phys[MT_BAND1]; 1440 phy2 = ext_phy ? ext_phy->priv : NULL; 1441 1442 dev->recovery.hw_full_reset = true; 1443 1444 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1445 wake_up(&dev->mt76.mcu.wait); 1446 ieee80211_stop_queues(mt76_hw(dev)); 1447 if (ext_phy) 1448 ieee80211_stop_queues(ext_phy->hw); 1449 1450 cancel_delayed_work_sync(&dev->mphy.mac_work); 1451 if (ext_phy) 1452 cancel_delayed_work_sync(&ext_phy->mac_work); 1453 1454 mutex_lock(&dev->mt76.mutex); 1455 for (i = 0; i < 10; i++) { 1456 if (!mt7915_mac_restart(dev)) 1457 break; 1458 } 1459 1460 if (i == 10) 1461 dev_err(dev->mt76.dev, "chip full reset failed\n"); 1462 1463 spin_lock_bh(&dev->mt76.sta_poll_lock); 1464 while (!list_empty(&dev->mt76.sta_poll_list)) 1465 list_del_init(dev->mt76.sta_poll_list.next); 1466 spin_unlock_bh(&dev->mt76.sta_poll_lock); 1467 1468 memset(dev->mt76.wcid_mask, 0, sizeof(dev->mt76.wcid_mask)); 1469 dev->mt76.vif_mask = 0; 1470 dev->phy.omac_mask = 0; 1471 if (phy2) 1472 phy2->omac_mask = 0; 1473 1474 i = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7915_WTBL_STA); 1475 dev->mt76.global_wcid.idx = i; 1476 dev->recovery.hw_full_reset = false; 1477 1478 mutex_unlock(&dev->mt76.mutex); 1479 1480 ieee80211_restart_hw(mt76_hw(dev)); 1481 if (ext_phy) 1482 ieee80211_restart_hw(ext_phy->hw); 1483 } 1484 1485 /* system error recovery */ 1486 void mt7915_mac_reset_work(struct work_struct *work) 1487 { 1488 struct mt7915_phy *phy2; 1489 struct mt76_phy *ext_phy; 1490 struct mt7915_dev *dev; 1491 int i; 1492 1493 dev = container_of(work, struct mt7915_dev, reset_work); 1494 ext_phy = dev->mt76.phys[MT_BAND1]; 1495 phy2 = ext_phy ? ext_phy->priv : NULL; 1496 1497 /* chip full reset */ 1498 if (dev->recovery.restart) { 1499 /* disable WA/WM WDT */ 1500 mt76_clear(dev, MT_WFDMA0_MCU_HOST_INT_ENA, 1501 MT_MCU_CMD_WDT_MASK); 1502 1503 if (READ_ONCE(dev->recovery.state) & MT_MCU_CMD_WA_WDT) 1504 dev->recovery.wa_reset_count++; 1505 else 1506 dev->recovery.wm_reset_count++; 1507 1508 mt7915_mac_full_reset(dev); 1509 1510 /* enable mcu irq */ 1511 mt7915_irq_enable(dev, MT_INT_MCU_CMD); 1512 mt7915_irq_disable(dev, 0); 1513 1514 /* enable WA/WM WDT */ 1515 mt76_set(dev, MT_WFDMA0_MCU_HOST_INT_ENA, MT_MCU_CMD_WDT_MASK); 1516 1517 dev->recovery.state = MT_MCU_CMD_NORMAL_STATE; 1518 dev->recovery.restart = false; 1519 return; 1520 } 1521 1522 /* chip partial reset */ 1523 if (!(READ_ONCE(dev->recovery.state) & MT_MCU_CMD_STOP_DMA)) 1524 return; 1525 1526 ieee80211_stop_queues(mt76_hw(dev)); 1527 if (ext_phy) 1528 ieee80211_stop_queues(ext_phy->hw); 1529 1530 set_bit(MT76_RESET, &dev->mphy.state); 1531 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1532 wake_up(&dev->mt76.mcu.wait); 1533 cancel_delayed_work_sync(&dev->mphy.mac_work); 1534 if (phy2) { 1535 set_bit(MT76_RESET, &phy2->mt76->state); 1536 cancel_delayed_work_sync(&phy2->mt76->mac_work); 1537 } 1538 1539 mutex_lock(&dev->mt76.mutex); 1540 1541 mt76_worker_disable(&dev->mt76.tx_worker); 1542 mt76_for_each_q_rx(&dev->mt76, i) 1543 napi_disable(&dev->mt76.napi[i]); 1544 napi_disable(&dev->mt76.tx_napi); 1545 1546 1547 if (mtk_wed_device_active(&dev->mt76.mmio.wed)) 1548 mtk_wed_device_stop(&dev->mt76.mmio.wed); 1549 1550 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_STOPPED); 1551 1552 if (mt7915_wait_reset_state(dev, MT_MCU_CMD_RESET_DONE)) { 1553 mt7915_dma_reset(dev, false); 1554 1555 mt76_connac2_tx_token_put(&dev->mt76); 1556 idr_init(&dev->mt76.token); 1557 1558 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_INIT); 1559 mt7915_wait_reset_state(dev, MT_MCU_CMD_RECOVERY_DONE); 1560 } 1561 1562 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_RESET_DONE); 1563 mt7915_wait_reset_state(dev, MT_MCU_CMD_NORMAL_STATE); 1564 1565 /* enable DMA Tx/Rx and interrupt */ 1566 mt7915_dma_start(dev, false, false); 1567 1568 clear_bit(MT76_MCU_RESET, &dev->mphy.state); 1569 clear_bit(MT76_RESET, &dev->mphy.state); 1570 if (phy2) 1571 clear_bit(MT76_RESET, &phy2->mt76->state); 1572 1573 mt76_for_each_q_rx(&dev->mt76, i) { 1574 napi_enable(&dev->mt76.napi[i]); 1575 } 1576 1577 local_bh_disable(); 1578 mt76_for_each_q_rx(&dev->mt76, i) { 1579 napi_schedule(&dev->mt76.napi[i]); 1580 } 1581 local_bh_enable(); 1582 1583 tasklet_schedule(&dev->mt76.irq_tasklet); 1584 1585 mt76_worker_enable(&dev->mt76.tx_worker); 1586 1587 napi_enable(&dev->mt76.tx_napi); 1588 local_bh_disable(); 1589 napi_schedule(&dev->mt76.tx_napi); 1590 local_bh_enable(); 1591 1592 ieee80211_wake_queues(mt76_hw(dev)); 1593 if (ext_phy) 1594 ieee80211_wake_queues(ext_phy->hw); 1595 1596 mutex_unlock(&dev->mt76.mutex); 1597 1598 mt7915_update_beacons(dev); 1599 1600 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work, 1601 MT7915_WATCHDOG_TIME); 1602 if (phy2) 1603 ieee80211_queue_delayed_work(ext_phy->hw, 1604 &phy2->mt76->mac_work, 1605 MT7915_WATCHDOG_TIME); 1606 } 1607 1608 /* firmware coredump */ 1609 void mt7915_mac_dump_work(struct work_struct *work) 1610 { 1611 const struct mt7915_mem_region *mem_region; 1612 struct mt7915_crash_data *crash_data; 1613 struct mt7915_dev *dev; 1614 struct mt7915_mem_hdr *hdr; 1615 size_t buf_len; 1616 int i; 1617 u32 num; 1618 u8 *buf; 1619 1620 dev = container_of(work, struct mt7915_dev, dump_work); 1621 1622 mutex_lock(&dev->dump_mutex); 1623 1624 crash_data = mt7915_coredump_new(dev); 1625 if (!crash_data) { 1626 mutex_unlock(&dev->dump_mutex); 1627 goto skip_coredump; 1628 } 1629 1630 mem_region = mt7915_coredump_get_mem_layout(dev, &num); 1631 if (!mem_region || !crash_data->memdump_buf_len) { 1632 mutex_unlock(&dev->dump_mutex); 1633 goto skip_memdump; 1634 } 1635 1636 buf = crash_data->memdump_buf; 1637 buf_len = crash_data->memdump_buf_len; 1638 1639 /* dumping memory content... */ 1640 memset(buf, 0, buf_len); 1641 for (i = 0; i < num; i++) { 1642 if (mem_region->len > buf_len) { 1643 dev_warn(dev->mt76.dev, "%s len %lu is too large\n", 1644 mem_region->name, 1645 (unsigned long)mem_region->len); 1646 break; 1647 } 1648 1649 /* reserve space for the header */ 1650 hdr = (void *)buf; 1651 buf += sizeof(*hdr); 1652 buf_len -= sizeof(*hdr); 1653 1654 mt7915_memcpy_fromio(dev, buf, mem_region->start, 1655 mem_region->len); 1656 1657 hdr->start = mem_region->start; 1658 hdr->len = mem_region->len; 1659 1660 if (!mem_region->len) 1661 /* note: the header remains, just with zero length */ 1662 break; 1663 1664 buf += mem_region->len; 1665 buf_len -= mem_region->len; 1666 1667 mem_region++; 1668 } 1669 1670 mutex_unlock(&dev->dump_mutex); 1671 1672 skip_memdump: 1673 mt7915_coredump_submit(dev); 1674 skip_coredump: 1675 queue_work(dev->mt76.wq, &dev->reset_work); 1676 } 1677 1678 void mt7915_reset(struct mt7915_dev *dev) 1679 { 1680 if (!dev->recovery.hw_init_done) 1681 return; 1682 1683 if (dev->recovery.hw_full_reset) 1684 return; 1685 1686 /* wm/wa exception: do full recovery */ 1687 if (READ_ONCE(dev->recovery.state) & MT_MCU_CMD_WDT_MASK) { 1688 dev->recovery.restart = true; 1689 dev_info(dev->mt76.dev, 1690 "%s indicated firmware crash, attempting recovery\n", 1691 wiphy_name(dev->mt76.hw->wiphy)); 1692 1693 mt7915_irq_disable(dev, MT_INT_MCU_CMD); 1694 queue_work(dev->mt76.wq, &dev->dump_work); 1695 return; 1696 } 1697 1698 if ((READ_ONCE(dev->recovery.state) & MT_MCU_CMD_STOP_DMA)) { 1699 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1700 wake_up(&dev->mt76.mcu.wait); 1701 } 1702 1703 queue_work(dev->mt76.wq, &dev->reset_work); 1704 wake_up(&dev->reset_wait); 1705 } 1706 1707 void mt7915_mac_update_stats(struct mt7915_phy *phy) 1708 { 1709 struct mt76_mib_stats *mib = &phy->mib; 1710 struct mt7915_dev *dev = phy->dev; 1711 int i, aggr0 = 0, aggr1, cnt; 1712 u8 band = phy->mt76->band_idx; 1713 u32 val; 1714 1715 cnt = mt76_rr(dev, MT_MIB_SDR3(band)); 1716 mib->fcs_err_cnt += is_mt7915(&dev->mt76) ? 1717 FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK, cnt) : 1718 FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK_MT7916, cnt); 1719 1720 cnt = mt76_rr(dev, MT_MIB_SDR4(band)); 1721 mib->rx_fifo_full_cnt += FIELD_GET(MT_MIB_SDR4_RX_FIFO_FULL_MASK, cnt); 1722 1723 cnt = mt76_rr(dev, MT_MIB_SDR5(band)); 1724 mib->rx_mpdu_cnt += cnt; 1725 1726 cnt = mt76_rr(dev, MT_MIB_SDR6(band)); 1727 mib->channel_idle_cnt += FIELD_GET(MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK, cnt); 1728 1729 cnt = mt76_rr(dev, MT_MIB_SDR7(band)); 1730 mib->rx_vector_mismatch_cnt += 1731 FIELD_GET(MT_MIB_SDR7_RX_VECTOR_MISMATCH_CNT_MASK, cnt); 1732 1733 cnt = mt76_rr(dev, MT_MIB_SDR8(band)); 1734 mib->rx_delimiter_fail_cnt += 1735 FIELD_GET(MT_MIB_SDR8_RX_DELIMITER_FAIL_CNT_MASK, cnt); 1736 1737 cnt = mt76_rr(dev, MT_MIB_SDR10(band)); 1738 mib->rx_mrdy_cnt += is_mt7915(&dev->mt76) ? 1739 FIELD_GET(MT_MIB_SDR10_MRDY_COUNT_MASK, cnt) : 1740 FIELD_GET(MT_MIB_SDR10_MRDY_COUNT_MASK_MT7916, cnt); 1741 1742 cnt = mt76_rr(dev, MT_MIB_SDR11(band)); 1743 mib->rx_len_mismatch_cnt += 1744 FIELD_GET(MT_MIB_SDR11_RX_LEN_MISMATCH_CNT_MASK, cnt); 1745 1746 cnt = mt76_rr(dev, MT_MIB_SDR12(band)); 1747 mib->tx_ampdu_cnt += cnt; 1748 1749 cnt = mt76_rr(dev, MT_MIB_SDR13(band)); 1750 mib->tx_stop_q_empty_cnt += 1751 FIELD_GET(MT_MIB_SDR13_TX_STOP_Q_EMPTY_CNT_MASK, cnt); 1752 1753 cnt = mt76_rr(dev, MT_MIB_SDR14(band)); 1754 mib->tx_mpdu_attempts_cnt += is_mt7915(&dev->mt76) ? 1755 FIELD_GET(MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK, cnt) : 1756 FIELD_GET(MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK_MT7916, cnt); 1757 1758 cnt = mt76_rr(dev, MT_MIB_SDR15(band)); 1759 mib->tx_mpdu_success_cnt += is_mt7915(&dev->mt76) ? 1760 FIELD_GET(MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK, cnt) : 1761 FIELD_GET(MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK_MT7916, cnt); 1762 1763 cnt = mt76_rr(dev, MT_MIB_SDR16(band)); 1764 mib->primary_cca_busy_time += 1765 FIELD_GET(MT_MIB_SDR16_PRIMARY_CCA_BUSY_TIME_MASK, cnt); 1766 1767 cnt = mt76_rr(dev, MT_MIB_SDR17(band)); 1768 mib->secondary_cca_busy_time += 1769 FIELD_GET(MT_MIB_SDR17_SECONDARY_CCA_BUSY_TIME_MASK, cnt); 1770 1771 cnt = mt76_rr(dev, MT_MIB_SDR18(band)); 1772 mib->primary_energy_detect_time += 1773 FIELD_GET(MT_MIB_SDR18_PRIMARY_ENERGY_DETECT_TIME_MASK, cnt); 1774 1775 cnt = mt76_rr(dev, MT_MIB_SDR19(band)); 1776 mib->cck_mdrdy_time += FIELD_GET(MT_MIB_SDR19_CCK_MDRDY_TIME_MASK, cnt); 1777 1778 cnt = mt76_rr(dev, MT_MIB_SDR20(band)); 1779 mib->ofdm_mdrdy_time += 1780 FIELD_GET(MT_MIB_SDR20_OFDM_VHT_MDRDY_TIME_MASK, cnt); 1781 1782 cnt = mt76_rr(dev, MT_MIB_SDR21(band)); 1783 mib->green_mdrdy_time += 1784 FIELD_GET(MT_MIB_SDR21_GREEN_MDRDY_TIME_MASK, cnt); 1785 1786 cnt = mt76_rr(dev, MT_MIB_SDR22(band)); 1787 mib->rx_ampdu_cnt += cnt; 1788 1789 cnt = mt76_rr(dev, MT_MIB_SDR23(band)); 1790 mib->rx_ampdu_bytes_cnt += cnt; 1791 1792 cnt = mt76_rr(dev, MT_MIB_SDR24(band)); 1793 mib->rx_ampdu_valid_subframe_cnt += is_mt7915(&dev->mt76) ? 1794 FIELD_GET(MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK, cnt) : 1795 FIELD_GET(MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK_MT7916, cnt); 1796 1797 cnt = mt76_rr(dev, MT_MIB_SDR25(band)); 1798 mib->rx_ampdu_valid_subframe_bytes_cnt += cnt; 1799 1800 cnt = mt76_rr(dev, MT_MIB_SDR27(band)); 1801 mib->tx_rwp_fail_cnt += 1802 FIELD_GET(MT_MIB_SDR27_TX_RWP_FAIL_CNT_MASK, cnt); 1803 1804 cnt = mt76_rr(dev, MT_MIB_SDR28(band)); 1805 mib->tx_rwp_need_cnt += 1806 FIELD_GET(MT_MIB_SDR28_TX_RWP_NEED_CNT_MASK, cnt); 1807 1808 cnt = mt76_rr(dev, MT_MIB_SDR29(band)); 1809 mib->rx_pfdrop_cnt += is_mt7915(&dev->mt76) ? 1810 FIELD_GET(MT_MIB_SDR29_RX_PFDROP_CNT_MASK, cnt) : 1811 FIELD_GET(MT_MIB_SDR29_RX_PFDROP_CNT_MASK_MT7916, cnt); 1812 1813 cnt = mt76_rr(dev, MT_MIB_SDRVEC(band)); 1814 mib->rx_vec_queue_overflow_drop_cnt += is_mt7915(&dev->mt76) ? 1815 FIELD_GET(MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK, cnt) : 1816 FIELD_GET(MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK_MT7916, cnt); 1817 1818 cnt = mt76_rr(dev, MT_MIB_SDR31(band)); 1819 mib->rx_ba_cnt += cnt; 1820 1821 cnt = mt76_rr(dev, MT_MIB_SDRMUBF(band)); 1822 mib->tx_bf_cnt += FIELD_GET(MT_MIB_MU_BF_TX_CNT, cnt); 1823 1824 cnt = mt76_rr(dev, MT_MIB_DR8(band)); 1825 mib->tx_mu_mpdu_cnt += cnt; 1826 1827 cnt = mt76_rr(dev, MT_MIB_DR9(band)); 1828 mib->tx_mu_acked_mpdu_cnt += cnt; 1829 1830 cnt = mt76_rr(dev, MT_MIB_DR11(band)); 1831 mib->tx_su_acked_mpdu_cnt += cnt; 1832 1833 cnt = mt76_rr(dev, MT_ETBF_PAR_RPT0(band)); 1834 mib->tx_bf_rx_fb_bw = FIELD_GET(MT_ETBF_PAR_RPT0_FB_BW, cnt); 1835 mib->tx_bf_rx_fb_nc_cnt += FIELD_GET(MT_ETBF_PAR_RPT0_FB_NC, cnt); 1836 mib->tx_bf_rx_fb_nr_cnt += FIELD_GET(MT_ETBF_PAR_RPT0_FB_NR, cnt); 1837 1838 for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) { 1839 cnt = mt76_rr(dev, MT_PLE_AMSDU_PACK_MSDU_CNT(i)); 1840 mib->tx_amsdu[i] += cnt; 1841 mib->tx_amsdu_cnt += cnt; 1842 } 1843 1844 if (is_mt7915(&dev->mt76)) { 1845 for (i = 0, aggr1 = aggr0 + 8; i < 4; i++) { 1846 val = mt76_rr(dev, MT_MIB_MB_SDR1(band, (i << 4))); 1847 mib->ba_miss_cnt += 1848 FIELD_GET(MT_MIB_BA_MISS_COUNT_MASK, val); 1849 mib->ack_fail_cnt += 1850 FIELD_GET(MT_MIB_ACK_FAIL_COUNT_MASK, val); 1851 1852 val = mt76_rr(dev, MT_MIB_MB_SDR0(band, (i << 4))); 1853 mib->rts_cnt += FIELD_GET(MT_MIB_RTS_COUNT_MASK, val); 1854 mib->rts_retries_cnt += 1855 FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, val); 1856 1857 val = mt76_rr(dev, MT_TX_AGG_CNT(band, i)); 1858 phy->mt76->aggr_stats[aggr0++] += val & 0xffff; 1859 phy->mt76->aggr_stats[aggr0++] += val >> 16; 1860 1861 val = mt76_rr(dev, MT_TX_AGG_CNT2(band, i)); 1862 phy->mt76->aggr_stats[aggr1++] += val & 0xffff; 1863 phy->mt76->aggr_stats[aggr1++] += val >> 16; 1864 } 1865 1866 cnt = mt76_rr(dev, MT_MIB_SDR32(band)); 1867 mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt); 1868 1869 cnt = mt76_rr(dev, MT_MIB_SDR33(band)); 1870 mib->tx_pkt_ibf_cnt += FIELD_GET(MT_MIB_SDR33_TX_PKT_IBF_CNT, cnt); 1871 1872 cnt = mt76_rr(dev, MT_ETBF_TX_APP_CNT(band)); 1873 mib->tx_bf_ibf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_IBF_CNT, cnt); 1874 mib->tx_bf_ebf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_EBF_CNT, cnt); 1875 1876 cnt = mt76_rr(dev, MT_ETBF_TX_NDP_BFRP(band)); 1877 mib->tx_bf_fb_cpl_cnt += FIELD_GET(MT_ETBF_TX_FB_CPL, cnt); 1878 mib->tx_bf_fb_trig_cnt += FIELD_GET(MT_ETBF_TX_FB_TRI, cnt); 1879 1880 cnt = mt76_rr(dev, MT_ETBF_RX_FB_CNT(band)); 1881 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_ETBF_RX_FB_ALL, cnt); 1882 mib->tx_bf_rx_fb_he_cnt += FIELD_GET(MT_ETBF_RX_FB_HE, cnt); 1883 mib->tx_bf_rx_fb_vht_cnt += FIELD_GET(MT_ETBF_RX_FB_VHT, cnt); 1884 mib->tx_bf_rx_fb_ht_cnt += FIELD_GET(MT_ETBF_RX_FB_HT, cnt); 1885 } else { 1886 for (i = 0; i < 2; i++) { 1887 /* rts count */ 1888 val = mt76_rr(dev, MT_MIB_MB_SDR0(band, (i << 2))); 1889 mib->rts_cnt += FIELD_GET(GENMASK(15, 0), val); 1890 mib->rts_cnt += FIELD_GET(GENMASK(31, 16), val); 1891 1892 /* rts retry count */ 1893 val = mt76_rr(dev, MT_MIB_MB_SDR1(band, (i << 2))); 1894 mib->rts_retries_cnt += FIELD_GET(GENMASK(15, 0), val); 1895 mib->rts_retries_cnt += FIELD_GET(GENMASK(31, 16), val); 1896 1897 /* ba miss count */ 1898 val = mt76_rr(dev, MT_MIB_MB_SDR2(band, (i << 2))); 1899 mib->ba_miss_cnt += FIELD_GET(GENMASK(15, 0), val); 1900 mib->ba_miss_cnt += FIELD_GET(GENMASK(31, 16), val); 1901 1902 /* ack fail count */ 1903 val = mt76_rr(dev, MT_MIB_MB_BFTF(band, (i << 2))); 1904 mib->ack_fail_cnt += FIELD_GET(GENMASK(15, 0), val); 1905 mib->ack_fail_cnt += FIELD_GET(GENMASK(31, 16), val); 1906 } 1907 1908 for (i = 0; i < 8; i++) { 1909 val = mt76_rr(dev, MT_TX_AGG_CNT(band, i)); 1910 phy->mt76->aggr_stats[aggr0++] += FIELD_GET(GENMASK(15, 0), val); 1911 phy->mt76->aggr_stats[aggr0++] += FIELD_GET(GENMASK(31, 16), val); 1912 } 1913 1914 cnt = mt76_rr(dev, MT_MIB_SDR32(band)); 1915 mib->tx_pkt_ibf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_IBF_CNT, cnt); 1916 mib->tx_bf_ibf_ppdu_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_IBF_CNT, cnt); 1917 mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt); 1918 mib->tx_bf_ebf_ppdu_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt); 1919 1920 cnt = mt76_rr(dev, MT_MIB_BFCR7(band)); 1921 mib->tx_bf_fb_cpl_cnt += FIELD_GET(MT_MIB_BFCR7_BFEE_TX_FB_CPL, cnt); 1922 1923 cnt = mt76_rr(dev, MT_MIB_BFCR2(band)); 1924 mib->tx_bf_fb_trig_cnt += FIELD_GET(MT_MIB_BFCR2_BFEE_TX_FB_TRIG, cnt); 1925 1926 cnt = mt76_rr(dev, MT_MIB_BFCR0(band)); 1927 mib->tx_bf_rx_fb_vht_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_VHT, cnt); 1928 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_VHT, cnt); 1929 mib->tx_bf_rx_fb_ht_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_HT, cnt); 1930 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_HT, cnt); 1931 1932 cnt = mt76_rr(dev, MT_MIB_BFCR1(band)); 1933 mib->tx_bf_rx_fb_he_cnt += FIELD_GET(MT_MIB_BFCR1_RX_FB_HE, cnt); 1934 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR1_RX_FB_HE, cnt); 1935 } 1936 } 1937 1938 static void mt7915_mac_severe_check(struct mt7915_phy *phy) 1939 { 1940 struct mt7915_dev *dev = phy->dev; 1941 u32 trb; 1942 1943 if (!phy->omac_mask) 1944 return; 1945 1946 /* In rare cases, TRB pointers might be out of sync leads to RMAC 1947 * stopping Rx, so check status periodically to see if TRB hardware 1948 * requires minimal recovery. 1949 */ 1950 trb = mt76_rr(dev, MT_TRB_RXPSR0(phy->mt76->band_idx)); 1951 1952 if ((FIELD_GET(MT_TRB_RXPSR0_RX_RMAC_PTR, trb) != 1953 FIELD_GET(MT_TRB_RXPSR0_RX_WTBL_PTR, trb)) && 1954 (FIELD_GET(MT_TRB_RXPSR0_RX_RMAC_PTR, phy->trb_ts) != 1955 FIELD_GET(MT_TRB_RXPSR0_RX_WTBL_PTR, phy->trb_ts)) && 1956 trb == phy->trb_ts) 1957 mt7915_mcu_set_ser(dev, SER_RECOVER, SER_SET_RECOVER_L3_RX_ABORT, 1958 phy->mt76->band_idx); 1959 1960 phy->trb_ts = trb; 1961 } 1962 1963 void mt7915_mac_sta_rc_work(struct work_struct *work) 1964 { 1965 struct mt7915_dev *dev = container_of(work, struct mt7915_dev, rc_work); 1966 struct ieee80211_sta *sta; 1967 struct ieee80211_vif *vif; 1968 struct mt7915_sta *msta; 1969 u32 changed; 1970 LIST_HEAD(list); 1971 1972 spin_lock_bh(&dev->mt76.sta_poll_lock); 1973 list_splice_init(&dev->sta_rc_list, &list); 1974 1975 while (!list_empty(&list)) { 1976 msta = list_first_entry(&list, struct mt7915_sta, rc_list); 1977 list_del_init(&msta->rc_list); 1978 changed = msta->changed; 1979 msta->changed = 0; 1980 spin_unlock_bh(&dev->mt76.sta_poll_lock); 1981 1982 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv); 1983 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); 1984 1985 if (changed & (IEEE80211_RC_SUPP_RATES_CHANGED | 1986 IEEE80211_RC_NSS_CHANGED | 1987 IEEE80211_RC_BW_CHANGED)) 1988 mt7915_mcu_add_rate_ctrl(dev, vif, sta, true); 1989 1990 if (changed & IEEE80211_RC_SMPS_CHANGED) 1991 mt7915_mcu_add_smps(dev, vif, sta); 1992 1993 spin_lock_bh(&dev->mt76.sta_poll_lock); 1994 } 1995 1996 spin_unlock_bh(&dev->mt76.sta_poll_lock); 1997 } 1998 1999 void mt7915_mac_work(struct work_struct *work) 2000 { 2001 struct mt7915_phy *phy; 2002 struct mt76_phy *mphy; 2003 2004 mphy = (struct mt76_phy *)container_of(work, struct mt76_phy, 2005 mac_work.work); 2006 phy = mphy->priv; 2007 2008 mutex_lock(&mphy->dev->mutex); 2009 2010 mt76_update_survey(mphy); 2011 if (++mphy->mac_work_count == 5) { 2012 mphy->mac_work_count = 0; 2013 2014 mt7915_mac_update_stats(phy); 2015 mt7915_mac_severe_check(phy); 2016 2017 if (phy->dev->muru_debug) 2018 mt7915_mcu_muru_debug_get(phy); 2019 } 2020 2021 mutex_unlock(&mphy->dev->mutex); 2022 2023 mt76_tx_status_check(mphy->dev, false); 2024 2025 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, 2026 MT7915_WATCHDOG_TIME); 2027 } 2028 2029 static void mt7915_dfs_stop_radar_detector(struct mt7915_phy *phy) 2030 { 2031 struct mt7915_dev *dev = phy->dev; 2032 int rdd_idx = mt7915_get_rdd_idx(phy, false); 2033 2034 if (rdd_idx < 0) 2035 return; 2036 2037 mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_STOP, rdd_idx, 0, 0); 2038 } 2039 2040 static int mt7915_dfs_start_rdd(struct mt7915_dev *dev, int rdd_idx) 2041 { 2042 int err, region; 2043 2044 switch (dev->mt76.region) { 2045 case NL80211_DFS_ETSI: 2046 region = 0; 2047 break; 2048 case NL80211_DFS_JP: 2049 region = 2; 2050 break; 2051 case NL80211_DFS_FCC: 2052 default: 2053 region = 1; 2054 break; 2055 } 2056 2057 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_START, rdd_idx, 0, region); 2058 if (err < 0) 2059 return err; 2060 2061 if (is_mt7915(&dev->mt76)) { 2062 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_SET_WF_ANT, rdd_idx, 2063 0, dev->dbdc_support ? 2 : 0); 2064 if (err < 0) 2065 return err; 2066 } 2067 2068 return mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_DET_MODE, rdd_idx, 0, 1); 2069 } 2070 2071 static int mt7915_dfs_start_radar_detector(struct mt7915_phy *phy) 2072 { 2073 struct mt7915_dev *dev = phy->dev; 2074 int err, rdd_idx; 2075 2076 rdd_idx = mt7915_get_rdd_idx(phy, false); 2077 if (rdd_idx < 0) 2078 return -EINVAL; 2079 2080 /* start CAC */ 2081 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_START, rdd_idx, 0, 0); 2082 if (err < 0) 2083 return err; 2084 2085 err = mt7915_dfs_start_rdd(dev, rdd_idx); 2086 if (err < 0) 2087 return err; 2088 2089 return 0; 2090 } 2091 2092 static int 2093 mt7915_dfs_init_radar_specs(struct mt7915_phy *phy) 2094 { 2095 const struct mt7915_dfs_radar_spec *radar_specs; 2096 struct mt7915_dev *dev = phy->dev; 2097 int err, i; 2098 2099 switch (dev->mt76.region) { 2100 case NL80211_DFS_FCC: 2101 radar_specs = &fcc_radar_specs; 2102 err = mt7915_mcu_set_fcc5_lpn(dev, 8); 2103 if (err < 0) 2104 return err; 2105 break; 2106 case NL80211_DFS_ETSI: 2107 radar_specs = &etsi_radar_specs; 2108 break; 2109 case NL80211_DFS_JP: 2110 radar_specs = &jp_radar_specs; 2111 break; 2112 default: 2113 return -EINVAL; 2114 } 2115 2116 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) { 2117 err = mt7915_mcu_set_radar_th(dev, i, 2118 &radar_specs->radar_pattern[i]); 2119 if (err < 0) 2120 return err; 2121 } 2122 2123 return mt7915_mcu_set_pulse_th(dev, &radar_specs->pulse_th); 2124 } 2125 2126 int mt7915_dfs_init_radar_detector(struct mt7915_phy *phy) 2127 { 2128 struct mt7915_dev *dev = phy->dev; 2129 enum mt76_dfs_state dfs_state, prev_state; 2130 int err, rdd_idx = mt7915_get_rdd_idx(phy, false); 2131 2132 prev_state = phy->mt76->dfs_state; 2133 dfs_state = mt76_phy_dfs_state(phy->mt76); 2134 2135 if (prev_state == dfs_state || rdd_idx < 0) 2136 return 0; 2137 2138 if (prev_state == MT_DFS_STATE_UNKNOWN) 2139 mt7915_dfs_stop_radar_detector(phy); 2140 2141 if (dfs_state == MT_DFS_STATE_DISABLED) 2142 goto stop; 2143 2144 if (prev_state <= MT_DFS_STATE_DISABLED) { 2145 err = mt7915_dfs_init_radar_specs(phy); 2146 if (err < 0) 2147 return err; 2148 2149 err = mt7915_dfs_start_radar_detector(phy); 2150 if (err < 0) 2151 return err; 2152 2153 phy->mt76->dfs_state = MT_DFS_STATE_CAC; 2154 } 2155 2156 if (dfs_state == MT_DFS_STATE_CAC) 2157 return 0; 2158 2159 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_END, rdd_idx, 0, 0); 2160 if (err < 0) { 2161 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN; 2162 return err; 2163 } 2164 2165 phy->mt76->dfs_state = MT_DFS_STATE_ACTIVE; 2166 return 0; 2167 2168 stop: 2169 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_NORMAL_START, rdd_idx, 0, 0); 2170 if (err < 0) 2171 return err; 2172 2173 if (is_mt7915(&dev->mt76)) { 2174 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_SET_WF_ANT, 2175 rdd_idx, 0, dev->dbdc_support ? 2 : 0); 2176 if (err < 0) 2177 return err; 2178 } 2179 2180 mt7915_dfs_stop_radar_detector(phy); 2181 phy->mt76->dfs_state = MT_DFS_STATE_DISABLED; 2182 2183 return 0; 2184 } 2185 2186 static int 2187 mt7915_mac_twt_duration_align(int duration) 2188 { 2189 return duration << 8; 2190 } 2191 2192 static u64 2193 mt7915_mac_twt_sched_list_add(struct mt7915_dev *dev, 2194 struct mt7915_twt_flow *flow) 2195 { 2196 struct mt7915_twt_flow *iter, *iter_next; 2197 u32 duration = flow->duration << 8; 2198 u64 start_tsf; 2199 2200 iter = list_first_entry_or_null(&dev->twt_list, 2201 struct mt7915_twt_flow, list); 2202 if (!iter || !iter->sched || iter->start_tsf > duration) { 2203 /* add flow as first entry in the list */ 2204 list_add(&flow->list, &dev->twt_list); 2205 return 0; 2206 } 2207 2208 list_for_each_entry_safe(iter, iter_next, &dev->twt_list, list) { 2209 start_tsf = iter->start_tsf + 2210 mt7915_mac_twt_duration_align(iter->duration); 2211 if (list_is_last(&iter->list, &dev->twt_list)) 2212 break; 2213 2214 if (!iter_next->sched || 2215 iter_next->start_tsf > start_tsf + duration) { 2216 list_add(&flow->list, &iter->list); 2217 goto out; 2218 } 2219 } 2220 2221 /* add flow as last entry in the list */ 2222 list_add_tail(&flow->list, &dev->twt_list); 2223 out: 2224 return start_tsf; 2225 } 2226 2227 static int mt7915_mac_check_twt_req(struct ieee80211_twt_setup *twt) 2228 { 2229 struct ieee80211_twt_params *twt_agrt; 2230 u64 interval, duration; 2231 u16 mantissa; 2232 u8 exp; 2233 2234 /* only individual agreement supported */ 2235 if (twt->control & IEEE80211_TWT_CONTROL_NEG_TYPE_BROADCAST) 2236 return -EOPNOTSUPP; 2237 2238 /* only 256us unit supported */ 2239 if (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT) 2240 return -EOPNOTSUPP; 2241 2242 twt_agrt = (struct ieee80211_twt_params *)twt->params; 2243 2244 /* explicit agreement not supported */ 2245 if (!(twt_agrt->req_type & cpu_to_le16(IEEE80211_TWT_REQTYPE_IMPLICIT))) 2246 return -EOPNOTSUPP; 2247 2248 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, 2249 le16_to_cpu(twt_agrt->req_type)); 2250 mantissa = le16_to_cpu(twt_agrt->mantissa); 2251 duration = twt_agrt->min_twt_dur << 8; 2252 2253 interval = (u64)mantissa << exp; 2254 if (interval < duration) 2255 return -EOPNOTSUPP; 2256 2257 return 0; 2258 } 2259 2260 static bool 2261 mt7915_mac_twt_param_equal(struct mt7915_sta *msta, 2262 struct ieee80211_twt_params *twt_agrt) 2263 { 2264 u16 type = le16_to_cpu(twt_agrt->req_type); 2265 u8 exp; 2266 int i; 2267 2268 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, type); 2269 for (i = 0; i < MT7915_MAX_STA_TWT_AGRT; i++) { 2270 struct mt7915_twt_flow *f; 2271 2272 if (!(msta->twt.flowid_mask & BIT(i))) 2273 continue; 2274 2275 f = &msta->twt.flow[i]; 2276 if (f->duration == twt_agrt->min_twt_dur && 2277 f->mantissa == twt_agrt->mantissa && 2278 f->exp == exp && 2279 f->protection == !!(type & IEEE80211_TWT_REQTYPE_PROTECTION) && 2280 f->flowtype == !!(type & IEEE80211_TWT_REQTYPE_FLOWTYPE) && 2281 f->trigger == !!(type & IEEE80211_TWT_REQTYPE_TRIGGER)) 2282 return true; 2283 } 2284 2285 return false; 2286 } 2287 2288 void mt7915_mac_add_twt_setup(struct ieee80211_hw *hw, 2289 struct ieee80211_sta *sta, 2290 struct ieee80211_twt_setup *twt) 2291 { 2292 enum ieee80211_twt_setup_cmd setup_cmd = TWT_SETUP_CMD_REJECT; 2293 struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv; 2294 struct ieee80211_twt_params *twt_agrt = (void *)twt->params; 2295 u16 req_type = le16_to_cpu(twt_agrt->req_type); 2296 enum ieee80211_twt_setup_cmd sta_setup_cmd; 2297 struct mt7915_dev *dev = mt7915_hw_dev(hw); 2298 struct mt7915_twt_flow *flow; 2299 int flowid, table_id; 2300 u8 exp; 2301 2302 if (mt7915_mac_check_twt_req(twt)) 2303 goto out; 2304 2305 mutex_lock(&dev->mt76.mutex); 2306 2307 if (dev->twt.n_agrt == MT7915_MAX_TWT_AGRT) 2308 goto unlock; 2309 2310 if (hweight8(msta->twt.flowid_mask) == ARRAY_SIZE(msta->twt.flow)) 2311 goto unlock; 2312 2313 if (twt_agrt->min_twt_dur < MT7915_MIN_TWT_DUR) { 2314 setup_cmd = TWT_SETUP_CMD_DICTATE; 2315 twt_agrt->min_twt_dur = MT7915_MIN_TWT_DUR; 2316 goto unlock; 2317 } 2318 2319 flowid = ffs(~msta->twt.flowid_mask) - 1; 2320 twt_agrt->req_type &= ~cpu_to_le16(IEEE80211_TWT_REQTYPE_FLOWID); 2321 twt_agrt->req_type |= le16_encode_bits(flowid, 2322 IEEE80211_TWT_REQTYPE_FLOWID); 2323 2324 table_id = ffs(~dev->twt.table_mask) - 1; 2325 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, req_type); 2326 sta_setup_cmd = FIELD_GET(IEEE80211_TWT_REQTYPE_SETUP_CMD, req_type); 2327 2328 if (mt7915_mac_twt_param_equal(msta, twt_agrt)) 2329 goto unlock; 2330 2331 flow = &msta->twt.flow[flowid]; 2332 memset(flow, 0, sizeof(*flow)); 2333 INIT_LIST_HEAD(&flow->list); 2334 flow->wcid = msta->wcid.idx; 2335 flow->table_id = table_id; 2336 flow->id = flowid; 2337 flow->duration = twt_agrt->min_twt_dur; 2338 flow->mantissa = twt_agrt->mantissa; 2339 flow->exp = exp; 2340 flow->protection = !!(req_type & IEEE80211_TWT_REQTYPE_PROTECTION); 2341 flow->flowtype = !!(req_type & IEEE80211_TWT_REQTYPE_FLOWTYPE); 2342 flow->trigger = !!(req_type & IEEE80211_TWT_REQTYPE_TRIGGER); 2343 2344 if (sta_setup_cmd == TWT_SETUP_CMD_REQUEST || 2345 sta_setup_cmd == TWT_SETUP_CMD_SUGGEST) { 2346 u64 interval = (u64)le16_to_cpu(twt_agrt->mantissa) << exp; 2347 u64 flow_tsf, curr_tsf; 2348 u32 rem; 2349 2350 flow->sched = true; 2351 flow->start_tsf = mt7915_mac_twt_sched_list_add(dev, flow); 2352 curr_tsf = __mt7915_get_tsf(hw, msta->vif); 2353 div_u64_rem(curr_tsf - flow->start_tsf, interval, &rem); 2354 flow_tsf = curr_tsf + interval - rem; 2355 twt_agrt->twt = cpu_to_le64(flow_tsf); 2356 } else { 2357 list_add_tail(&flow->list, &dev->twt_list); 2358 } 2359 flow->tsf = le64_to_cpu(twt_agrt->twt); 2360 2361 if (mt7915_mcu_twt_agrt_update(dev, msta->vif, flow, MCU_TWT_AGRT_ADD)) 2362 goto unlock; 2363 2364 setup_cmd = TWT_SETUP_CMD_ACCEPT; 2365 dev->twt.table_mask |= BIT(table_id); 2366 msta->twt.flowid_mask |= BIT(flowid); 2367 dev->twt.n_agrt++; 2368 2369 unlock: 2370 mutex_unlock(&dev->mt76.mutex); 2371 out: 2372 twt_agrt->req_type &= ~cpu_to_le16(IEEE80211_TWT_REQTYPE_SETUP_CMD); 2373 twt_agrt->req_type |= 2374 le16_encode_bits(setup_cmd, IEEE80211_TWT_REQTYPE_SETUP_CMD); 2375 twt->control = (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT) | 2376 (twt->control & IEEE80211_TWT_CONTROL_RX_DISABLED); 2377 } 2378 2379 void mt7915_mac_twt_teardown_flow(struct mt7915_dev *dev, 2380 struct mt7915_sta *msta, 2381 u8 flowid) 2382 { 2383 struct mt7915_twt_flow *flow; 2384 2385 lockdep_assert_held(&dev->mt76.mutex); 2386 2387 if (flowid >= ARRAY_SIZE(msta->twt.flow)) 2388 return; 2389 2390 if (!(msta->twt.flowid_mask & BIT(flowid))) 2391 return; 2392 2393 flow = &msta->twt.flow[flowid]; 2394 if (mt7915_mcu_twt_agrt_update(dev, msta->vif, flow, 2395 MCU_TWT_AGRT_DELETE)) 2396 return; 2397 2398 list_del_init(&flow->list); 2399 msta->twt.flowid_mask &= ~BIT(flowid); 2400 dev->twt.table_mask &= ~BIT(flow->table_id); 2401 dev->twt.n_agrt--; 2402 } 2403