1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include <linux/etherdevice.h> 5 #include <linux/timekeeping.h> 6 #include "coredump.h" 7 #include "mt7915.h" 8 #include "../dma.h" 9 #include "mac.h" 10 #include "mcu.h" 11 12 #define to_rssi(field, rcpi) ((FIELD_GET(field, rcpi) - 220) / 2) 13 14 static const struct mt7915_dfs_radar_spec etsi_radar_specs = { 15 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 16 .radar_pattern = { 17 [5] = { 1, 0, 6, 32, 28, 0, 990, 5010, 17, 1, 1 }, 18 [6] = { 1, 0, 9, 32, 28, 0, 615, 5010, 27, 1, 1 }, 19 [7] = { 1, 0, 15, 32, 28, 0, 240, 445, 27, 1, 1 }, 20 [8] = { 1, 0, 12, 32, 28, 0, 240, 510, 42, 1, 1 }, 21 [9] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 12, 32, 28, { }, 126 }, 22 [10] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 15, 32, 24, { }, 126 }, 23 [11] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 18, 32, 28, { }, 54 }, 24 [12] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 27, 32, 24, { }, 54 }, 25 }, 26 }; 27 28 static const struct mt7915_dfs_radar_spec fcc_radar_specs = { 29 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 30 .radar_pattern = { 31 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 }, 32 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 }, 33 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 }, 34 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 }, 35 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 }, 36 }, 37 }; 38 39 static const struct mt7915_dfs_radar_spec jp_radar_specs = { 40 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 41 .radar_pattern = { 42 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 }, 43 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 }, 44 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 }, 45 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 }, 46 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 }, 47 [13] = { 1, 0, 7, 32, 28, 0, 3836, 3856, 14, 1, 1 }, 48 [14] = { 1, 0, 6, 32, 28, 0, 615, 5010, 110, 1, 1 }, 49 [15] = { 1, 1, 0, 0, 0, 0, 15, 5010, 110, 0, 0, 12, 32, 28 }, 50 }, 51 }; 52 53 static struct mt76_wcid *mt7915_rx_get_wcid(struct mt7915_dev *dev, 54 u16 idx, bool unicast) 55 { 56 struct mt7915_sta *sta; 57 struct mt76_wcid *wcid; 58 59 wcid = mt76_wcid_ptr(dev, idx); 60 if (unicast || !wcid) 61 return wcid; 62 63 if (!wcid->sta) 64 return NULL; 65 66 sta = container_of(wcid, struct mt7915_sta, wcid); 67 if (!sta->vif) 68 return NULL; 69 70 return &sta->vif->sta.wcid; 71 } 72 73 bool mt7915_mac_wtbl_update(struct mt7915_dev *dev, int idx, u32 mask) 74 { 75 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX, 76 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask); 77 78 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 79 0, 5000); 80 } 81 82 u32 mt7915_mac_wtbl_lmac_addr(struct mt7915_dev *dev, u16 wcid, u8 dw) 83 { 84 mt76_wr(dev, MT_WTBLON_TOP_WDUCR, 85 FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (wcid >> 7))); 86 87 return MT_WTBL_LMAC_OFFS(wcid, dw); 88 } 89 90 static void mt7915_mac_sta_poll(struct mt7915_dev *dev) 91 { 92 static const u8 ac_to_tid[] = { 93 [IEEE80211_AC_BE] = 0, 94 [IEEE80211_AC_BK] = 1, 95 [IEEE80211_AC_VI] = 4, 96 [IEEE80211_AC_VO] = 6 97 }; 98 struct ieee80211_sta *sta; 99 struct mt7915_sta *msta; 100 struct rate_info *rate; 101 u32 tx_time[IEEE80211_NUM_ACS], rx_time[IEEE80211_NUM_ACS]; 102 LIST_HEAD(sta_poll_list); 103 int i; 104 105 spin_lock_bh(&dev->mt76.sta_poll_lock); 106 list_splice_init(&dev->mt76.sta_poll_list, &sta_poll_list); 107 spin_unlock_bh(&dev->mt76.sta_poll_lock); 108 109 rcu_read_lock(); 110 111 while (true) { 112 bool clear = false; 113 u32 addr, val; 114 u16 idx; 115 s8 rssi[4]; 116 u8 bw; 117 118 spin_lock_bh(&dev->mt76.sta_poll_lock); 119 if (list_empty(&sta_poll_list)) { 120 spin_unlock_bh(&dev->mt76.sta_poll_lock); 121 break; 122 } 123 msta = list_first_entry(&sta_poll_list, 124 struct mt7915_sta, wcid.poll_list); 125 list_del_init(&msta->wcid.poll_list); 126 spin_unlock_bh(&dev->mt76.sta_poll_lock); 127 128 idx = msta->wcid.idx; 129 130 /* refresh peer's airtime reporting */ 131 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 20); 132 133 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 134 u32 tx_last = msta->airtime_ac[i]; 135 u32 rx_last = msta->airtime_ac[i + 4]; 136 137 msta->airtime_ac[i] = mt76_rr(dev, addr); 138 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4); 139 140 if (msta->airtime_ac[i] <= tx_last) 141 tx_time[i] = 0; 142 else 143 tx_time[i] = msta->airtime_ac[i] - tx_last; 144 145 if (msta->airtime_ac[i + 4] <= rx_last) 146 rx_time[i] = 0; 147 else 148 rx_time[i] = msta->airtime_ac[i + 4] - rx_last; 149 150 if ((tx_last | rx_last) & BIT(30)) 151 clear = true; 152 153 addr += 8; 154 } 155 156 if (clear) { 157 mt7915_mac_wtbl_update(dev, idx, 158 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 159 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac)); 160 } 161 162 if (!msta->wcid.sta) 163 continue; 164 165 sta = container_of((void *)msta, struct ieee80211_sta, 166 drv_priv); 167 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 168 u8 queue = mt76_connac_lmac_mapping(i); 169 u32 tx_cur = tx_time[queue]; 170 u32 rx_cur = rx_time[queue]; 171 u8 tid = ac_to_tid[i]; 172 173 if (!tx_cur && !rx_cur) 174 continue; 175 176 ieee80211_sta_register_airtime(sta, tid, tx_cur, 177 rx_cur); 178 } 179 180 /* 181 * We don't support reading GI info from txs packets. 182 * For accurate tx status reporting and AQL improvement, 183 * we need to make sure that flags match so polling GI 184 * from per-sta counters directly. 185 */ 186 rate = &msta->wcid.rate; 187 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 7); 188 val = mt76_rr(dev, addr); 189 190 switch (rate->bw) { 191 case RATE_INFO_BW_160: 192 bw = IEEE80211_STA_RX_BW_160; 193 break; 194 case RATE_INFO_BW_80: 195 bw = IEEE80211_STA_RX_BW_80; 196 break; 197 case RATE_INFO_BW_40: 198 bw = IEEE80211_STA_RX_BW_40; 199 break; 200 default: 201 bw = IEEE80211_STA_RX_BW_20; 202 break; 203 } 204 205 if (rate->flags & RATE_INFO_FLAGS_HE_MCS) { 206 u8 offs = 24 + 2 * bw; 207 208 rate->he_gi = (val & (0x3 << offs)) >> offs; 209 } else if (rate->flags & 210 (RATE_INFO_FLAGS_VHT_MCS | RATE_INFO_FLAGS_MCS)) { 211 if (val & BIT(12 + bw)) 212 rate->flags |= RATE_INFO_FLAGS_SHORT_GI; 213 else 214 rate->flags &= ~RATE_INFO_FLAGS_SHORT_GI; 215 } 216 217 /* get signal strength of resp frames (CTS/BA/ACK) */ 218 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 30); 219 val = mt76_rr(dev, addr); 220 221 rssi[0] = to_rssi(GENMASK(7, 0), val); 222 rssi[1] = to_rssi(GENMASK(15, 8), val); 223 rssi[2] = to_rssi(GENMASK(23, 16), val); 224 rssi[3] = to_rssi(GENMASK(31, 24), val); 225 226 msta->ack_signal = 227 mt76_rx_signal(msta->vif->phy->mt76->antenna_mask, rssi); 228 229 ewma_avg_signal_add(&msta->avg_ack_signal, -msta->ack_signal); 230 } 231 232 rcu_read_unlock(); 233 } 234 235 static void 236 mt7915_wed_check_ppe(struct mt7915_dev *dev, struct mt76_queue *q, 237 struct mt7915_sta *msta, struct sk_buff *skb, 238 u32 info) 239 { 240 struct ieee80211_vif *vif; 241 struct wireless_dev *wdev; 242 243 if (!msta || !msta->vif) 244 return; 245 246 if (!mt76_queue_is_wed_rx(q)) 247 return; 248 249 if (!(info & MT_DMA_INFO_PPE_VLD)) 250 return; 251 252 vif = container_of((void *)msta->vif, struct ieee80211_vif, 253 drv_priv); 254 wdev = ieee80211_vif_to_wdev(vif); 255 skb->dev = wdev->netdev; 256 257 mtk_wed_device_ppe_check(&dev->mt76.mmio.wed, skb, 258 FIELD_GET(MT_DMA_PPE_CPU_REASON, info), 259 FIELD_GET(MT_DMA_PPE_ENTRY, info)); 260 } 261 262 static int 263 mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb, 264 enum mt76_rxq_id q, u32 *info) 265 { 266 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 267 struct mt76_phy *mphy = &dev->mt76.phy; 268 struct mt7915_phy *phy = &dev->phy; 269 struct ieee80211_supported_band *sband; 270 __le32 *rxd = (__le32 *)skb->data; 271 __le32 *rxv = NULL; 272 u32 rxd0 = le32_to_cpu(rxd[0]); 273 u32 rxd1 = le32_to_cpu(rxd[1]); 274 u32 rxd2 = le32_to_cpu(rxd[2]); 275 u32 rxd3 = le32_to_cpu(rxd[3]); 276 u32 rxd4 = le32_to_cpu(rxd[4]); 277 u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM; 278 bool unicast, insert_ccmp_hdr = false; 279 u8 remove_pad, amsdu_info; 280 u8 mode = 0, qos_ctl = 0; 281 struct mt7915_sta *msta = NULL; 282 u32 csum_status = *(u32 *)skb->cb; 283 bool hdr_trans; 284 u16 hdr_gap; 285 u16 seq_ctrl = 0; 286 __le16 fc = 0; 287 int idx; 288 289 memset(status, 0, sizeof(*status)); 290 291 if ((rxd1 & MT_RXD1_NORMAL_BAND_IDX) && !phy->mt76->band_idx) { 292 mphy = dev->mt76.phys[MT_BAND1]; 293 if (!mphy) 294 return -EINVAL; 295 296 phy = mphy->priv; 297 status->phy_idx = 1; 298 } 299 300 if (!test_bit(MT76_STATE_RUNNING, &mphy->state)) 301 return -EINVAL; 302 303 if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR) 304 return -EINVAL; 305 306 hdr_trans = rxd2 & MT_RXD2_NORMAL_HDR_TRANS; 307 if (hdr_trans && (rxd1 & MT_RXD1_NORMAL_CM)) 308 return -EINVAL; 309 310 /* ICV error or CCMP/BIP/WPI MIC error */ 311 if (rxd1 & MT_RXD1_NORMAL_ICV_ERR) 312 status->flag |= RX_FLAG_ONLY_MONITOR; 313 314 unicast = FIELD_GET(MT_RXD3_NORMAL_ADDR_TYPE, rxd3) == MT_RXD3_NORMAL_U2M; 315 idx = FIELD_GET(MT_RXD1_NORMAL_WLAN_IDX, rxd1); 316 status->wcid = mt7915_rx_get_wcid(dev, idx, unicast); 317 318 if (status->wcid) { 319 msta = container_of(status->wcid, struct mt7915_sta, wcid); 320 mt76_wcid_add_poll(&dev->mt76, &msta->wcid); 321 } 322 323 status->freq = mphy->chandef.chan->center_freq; 324 status->band = mphy->chandef.chan->band; 325 if (status->band == NL80211_BAND_5GHZ) 326 sband = &mphy->sband_5g.sband; 327 else if (status->band == NL80211_BAND_6GHZ) 328 sband = &mphy->sband_6g.sband; 329 else 330 sband = &mphy->sband_2g.sband; 331 332 if (!sband->channels) 333 return -EINVAL; 334 335 if ((rxd0 & csum_mask) == csum_mask && 336 !(csum_status & (BIT(0) | BIT(2) | BIT(3)))) 337 skb->ip_summed = CHECKSUM_UNNECESSARY; 338 339 if (rxd1 & MT_RXD1_NORMAL_FCS_ERR) 340 status->flag |= RX_FLAG_FAILED_FCS_CRC; 341 342 if (rxd1 & MT_RXD1_NORMAL_TKIP_MIC_ERR) 343 status->flag |= RX_FLAG_MMIC_ERROR; 344 345 if (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1) != 0 && 346 !(rxd1 & (MT_RXD1_NORMAL_CLM | MT_RXD1_NORMAL_CM))) { 347 status->flag |= RX_FLAG_DECRYPTED; 348 status->flag |= RX_FLAG_IV_STRIPPED; 349 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED; 350 } 351 352 remove_pad = FIELD_GET(MT_RXD2_NORMAL_HDR_OFFSET, rxd2); 353 354 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR) 355 return -EINVAL; 356 357 rxd += 6; 358 if (rxd1 & MT_RXD1_NORMAL_GROUP_4) { 359 u32 v0 = le32_to_cpu(rxd[0]); 360 u32 v2 = le32_to_cpu(rxd[2]); 361 362 fc = cpu_to_le16(FIELD_GET(MT_RXD6_FRAME_CONTROL, v0)); 363 qos_ctl = FIELD_GET(MT_RXD8_QOS_CTL, v2); 364 seq_ctrl = FIELD_GET(MT_RXD8_SEQ_CTRL, v2); 365 366 rxd += 4; 367 if ((u8 *)rxd - skb->data >= skb->len) 368 return -EINVAL; 369 } 370 371 if (rxd1 & MT_RXD1_NORMAL_GROUP_1) { 372 u8 *data = (u8 *)rxd; 373 374 if (status->flag & RX_FLAG_DECRYPTED) { 375 switch (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1)) { 376 case MT_CIPHER_AES_CCMP: 377 case MT_CIPHER_CCMP_CCX: 378 case MT_CIPHER_CCMP_256: 379 insert_ccmp_hdr = 380 FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2); 381 fallthrough; 382 case MT_CIPHER_TKIP: 383 case MT_CIPHER_TKIP_NO_MIC: 384 case MT_CIPHER_GCMP: 385 case MT_CIPHER_GCMP_256: 386 status->iv[0] = data[5]; 387 status->iv[1] = data[4]; 388 status->iv[2] = data[3]; 389 status->iv[3] = data[2]; 390 status->iv[4] = data[1]; 391 status->iv[5] = data[0]; 392 break; 393 default: 394 break; 395 } 396 } 397 rxd += 4; 398 if ((u8 *)rxd - skb->data >= skb->len) 399 return -EINVAL; 400 } 401 402 if (rxd1 & MT_RXD1_NORMAL_GROUP_2) { 403 status->timestamp = le32_to_cpu(rxd[0]); 404 status->flag |= RX_FLAG_MACTIME_START; 405 406 if (!(rxd2 & MT_RXD2_NORMAL_NON_AMPDU)) { 407 status->flag |= RX_FLAG_AMPDU_DETAILS; 408 409 /* all subframes of an A-MPDU have the same timestamp */ 410 if (phy->rx_ampdu_ts != status->timestamp) { 411 if (!++phy->ampdu_ref) 412 phy->ampdu_ref++; 413 } 414 phy->rx_ampdu_ts = status->timestamp; 415 416 status->ampdu_ref = phy->ampdu_ref; 417 } 418 419 rxd += 2; 420 if ((u8 *)rxd - skb->data >= skb->len) 421 return -EINVAL; 422 } 423 424 /* RXD Group 3 - P-RXV */ 425 if (rxd1 & MT_RXD1_NORMAL_GROUP_3) { 426 u32 v0, v1; 427 int ret; 428 429 rxv = rxd; 430 rxd += 2; 431 if ((u8 *)rxd - skb->data >= skb->len) 432 return -EINVAL; 433 434 v0 = le32_to_cpu(rxv[0]); 435 v1 = le32_to_cpu(rxv[1]); 436 437 if (v0 & MT_PRXV_HT_AD_CODE) 438 status->enc_flags |= RX_ENC_FLAG_LDPC; 439 440 status->chains = mt7915_band_chainmask(phy); 441 status->chain_signal[0] = to_rssi(MT_PRXV_RCPI0, v1); 442 status->chain_signal[1] = to_rssi(MT_PRXV_RCPI1, v1); 443 status->chain_signal[2] = to_rssi(MT_PRXV_RCPI2, v1); 444 status->chain_signal[3] = to_rssi(MT_PRXV_RCPI3, v1); 445 446 /* RXD Group 5 - C-RXV */ 447 if (rxd1 & MT_RXD1_NORMAL_GROUP_5) { 448 rxd += 18; 449 if ((u8 *)rxd - skb->data >= skb->len) 450 return -EINVAL; 451 } 452 453 if (!is_mt7915(&dev->mt76) || (rxd1 & MT_RXD1_NORMAL_GROUP_5)) { 454 ret = mt76_connac2_mac_fill_rx_rate(&dev->mt76, status, 455 sband, rxv, &mode); 456 if (ret < 0) 457 return ret; 458 } 459 } 460 461 amsdu_info = FIELD_GET(MT_RXD4_NORMAL_PAYLOAD_FORMAT, rxd4); 462 status->amsdu = !!amsdu_info; 463 if (status->amsdu) { 464 status->first_amsdu = amsdu_info == MT_RXD4_FIRST_AMSDU_FRAME; 465 status->last_amsdu = amsdu_info == MT_RXD4_LAST_AMSDU_FRAME; 466 } 467 468 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad; 469 if (hdr_trans && ieee80211_has_morefrags(fc)) { 470 struct ieee80211_vif *vif; 471 int err; 472 473 if (!msta || !msta->vif) 474 return -EINVAL; 475 476 vif = container_of((void *)msta->vif, struct ieee80211_vif, 477 drv_priv); 478 err = mt76_connac2_reverse_frag0_hdr_trans(vif, skb, hdr_gap); 479 if (err) 480 return err; 481 482 hdr_trans = false; 483 } else { 484 int pad_start = 0; 485 486 skb_pull(skb, hdr_gap); 487 if (!hdr_trans && status->amsdu) { 488 pad_start = ieee80211_get_hdrlen_from_skb(skb); 489 } else if (hdr_trans && (rxd2 & MT_RXD2_NORMAL_HDR_TRANS_ERROR)) { 490 /* 491 * When header translation failure is indicated, 492 * the hardware will insert an extra 2-byte field 493 * containing the data length after the protocol 494 * type field. This happens either when the LLC-SNAP 495 * pattern did not match, or if a VLAN header was 496 * detected. 497 */ 498 pad_start = 12; 499 if (get_unaligned_be16(skb->data + pad_start) == ETH_P_8021Q) 500 pad_start += 4; 501 else 502 pad_start = 0; 503 } 504 505 if (pad_start) { 506 memmove(skb->data + 2, skb->data, pad_start); 507 skb_pull(skb, 2); 508 } 509 } 510 511 if (!hdr_trans) { 512 struct ieee80211_hdr *hdr; 513 514 if (insert_ccmp_hdr) { 515 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1); 516 517 mt76_insert_ccmp_hdr(skb, key_id); 518 } 519 520 hdr = mt76_skb_get_hdr(skb); 521 fc = hdr->frame_control; 522 if (ieee80211_is_data_qos(fc)) { 523 seq_ctrl = le16_to_cpu(hdr->seq_ctrl); 524 qos_ctl = *ieee80211_get_qos_ctl(hdr); 525 } 526 } else { 527 status->flag |= RX_FLAG_8023; 528 mt7915_wed_check_ppe(dev, &dev->mt76.q_rx[q], msta, skb, 529 *info); 530 } 531 532 if (rxv && mode >= MT_PHY_TYPE_HE_SU && !(status->flag & RX_FLAG_8023)) 533 mt76_connac2_mac_decode_he_radiotap(&dev->mt76, skb, rxv, mode); 534 535 if (!status->wcid || !ieee80211_is_data_qos(fc)) 536 return 0; 537 538 status->aggr = unicast && 539 !ieee80211_is_qos_nullfunc(fc); 540 status->qos_ctl = qos_ctl; 541 status->seqno = IEEE80211_SEQ_TO_SN(seq_ctrl); 542 543 return 0; 544 } 545 546 static void 547 mt7915_mac_fill_rx_vector(struct mt7915_dev *dev, struct sk_buff *skb) 548 { 549 #ifdef CONFIG_NL80211_TESTMODE 550 struct mt7915_phy *phy = &dev->phy; 551 __le32 *rxd = (__le32 *)skb->data; 552 __le32 *rxv_hdr = rxd + 2; 553 __le32 *rxv = rxd + 4; 554 u32 rcpi, ib_rssi, wb_rssi, v20, v21; 555 u8 band_idx; 556 s32 foe; 557 u8 snr; 558 int i; 559 560 band_idx = le32_get_bits(rxv_hdr[1], MT_RXV_HDR_BAND_IDX); 561 if (band_idx && !phy->mt76->band_idx) { 562 phy = mt7915_ext_phy(dev); 563 if (!phy) 564 goto out; 565 } 566 567 rcpi = le32_to_cpu(rxv[6]); 568 ib_rssi = le32_to_cpu(rxv[7]); 569 wb_rssi = le32_to_cpu(rxv[8]) >> 5; 570 571 for (i = 0; i < 4; i++, rcpi >>= 8, ib_rssi >>= 8, wb_rssi >>= 9) { 572 if (i == 3) 573 wb_rssi = le32_to_cpu(rxv[9]); 574 575 phy->test.last_rcpi[i] = rcpi & 0xff; 576 phy->test.last_ib_rssi[i] = ib_rssi & 0xff; 577 phy->test.last_wb_rssi[i] = wb_rssi & 0xff; 578 } 579 580 v20 = le32_to_cpu(rxv[20]); 581 v21 = le32_to_cpu(rxv[21]); 582 583 foe = FIELD_GET(MT_CRXV_FOE_LO, v20) | 584 (FIELD_GET(MT_CRXV_FOE_HI, v21) << MT_CRXV_FOE_SHIFT); 585 586 snr = FIELD_GET(MT_CRXV_SNR, v20) - 16; 587 588 phy->test.last_freq_offset = foe; 589 phy->test.last_snr = snr; 590 out: 591 #endif 592 dev_kfree_skb(skb); 593 } 594 595 static void 596 mt7915_mac_write_txwi_tm(struct mt7915_phy *phy, __le32 *txwi, 597 struct sk_buff *skb) 598 { 599 #ifdef CONFIG_NL80211_TESTMODE 600 struct mt76_testmode_data *td = &phy->mt76->test; 601 const struct ieee80211_rate *r; 602 u8 bw, mode, nss = td->tx_rate_nss; 603 u8 rate_idx = td->tx_rate_idx; 604 u16 rateval = 0; 605 u32 val; 606 bool cck = false; 607 int band; 608 609 if (skb != phy->mt76->test.tx_skb) 610 return; 611 612 switch (td->tx_rate_mode) { 613 case MT76_TM_TX_MODE_HT: 614 nss = 1 + (rate_idx >> 3); 615 mode = MT_PHY_TYPE_HT; 616 break; 617 case MT76_TM_TX_MODE_VHT: 618 mode = MT_PHY_TYPE_VHT; 619 break; 620 case MT76_TM_TX_MODE_HE_SU: 621 mode = MT_PHY_TYPE_HE_SU; 622 break; 623 case MT76_TM_TX_MODE_HE_EXT_SU: 624 mode = MT_PHY_TYPE_HE_EXT_SU; 625 break; 626 case MT76_TM_TX_MODE_HE_TB: 627 mode = MT_PHY_TYPE_HE_TB; 628 break; 629 case MT76_TM_TX_MODE_HE_MU: 630 mode = MT_PHY_TYPE_HE_MU; 631 break; 632 case MT76_TM_TX_MODE_CCK: 633 cck = true; 634 fallthrough; 635 case MT76_TM_TX_MODE_OFDM: 636 band = phy->mt76->chandef.chan->band; 637 if (band == NL80211_BAND_2GHZ && !cck) 638 rate_idx += 4; 639 640 r = &phy->mt76->hw->wiphy->bands[band]->bitrates[rate_idx]; 641 val = cck ? r->hw_value_short : r->hw_value; 642 643 mode = val >> 8; 644 rate_idx = val & 0xff; 645 break; 646 default: 647 mode = MT_PHY_TYPE_OFDM; 648 break; 649 } 650 651 switch (phy->mt76->chandef.width) { 652 case NL80211_CHAN_WIDTH_40: 653 bw = 1; 654 break; 655 case NL80211_CHAN_WIDTH_80: 656 bw = 2; 657 break; 658 case NL80211_CHAN_WIDTH_80P80: 659 case NL80211_CHAN_WIDTH_160: 660 bw = 3; 661 break; 662 default: 663 bw = 0; 664 break; 665 } 666 667 if (td->tx_rate_stbc && nss == 1) { 668 nss++; 669 rateval |= MT_TX_RATE_STBC; 670 } 671 672 rateval |= FIELD_PREP(MT_TX_RATE_IDX, rate_idx) | 673 FIELD_PREP(MT_TX_RATE_MODE, mode) | 674 FIELD_PREP(MT_TX_RATE_NSS, nss - 1); 675 676 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE); 677 678 le32p_replace_bits(&txwi[3], 1, MT_TXD3_REM_TX_COUNT); 679 if (td->tx_rate_mode < MT76_TM_TX_MODE_HT) 680 txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE); 681 682 val = MT_TXD6_FIXED_BW | 683 FIELD_PREP(MT_TXD6_BW, bw) | 684 FIELD_PREP(MT_TXD6_TX_RATE, rateval) | 685 FIELD_PREP(MT_TXD6_SGI, td->tx_rate_sgi); 686 687 /* for HE_SU/HE_EXT_SU PPDU 688 * - 1x, 2x, 4x LTF + 0.8us GI 689 * - 2x LTF + 1.6us GI, 4x LTF + 3.2us GI 690 * for HE_MU PPDU 691 * - 2x, 4x LTF + 0.8us GI 692 * - 2x LTF + 1.6us GI, 4x LTF + 3.2us GI 693 * for HE_TB PPDU 694 * - 1x, 2x LTF + 1.6us GI 695 * - 4x LTF + 3.2us GI 696 */ 697 if (mode >= MT_PHY_TYPE_HE_SU) 698 val |= FIELD_PREP(MT_TXD6_HELTF, td->tx_ltf); 699 700 if (td->tx_rate_ldpc || (bw > 0 && mode >= MT_PHY_TYPE_HE_SU)) 701 val |= MT_TXD6_LDPC; 702 703 txwi[3] &= ~cpu_to_le32(MT_TXD3_SN_VALID); 704 txwi[6] |= cpu_to_le32(val); 705 txwi[7] |= cpu_to_le32(FIELD_PREP(MT_TXD7_SPE_IDX, 706 phy->test.spe_idx)); 707 #endif 708 } 709 710 void mt7915_mac_write_txwi(struct mt76_dev *dev, __le32 *txwi, 711 struct sk_buff *skb, struct mt76_wcid *wcid, int pid, 712 struct ieee80211_key_conf *key, 713 enum mt76_txq_id qid, u32 changed) 714 { 715 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 716 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2; 717 struct mt76_phy *mphy = &dev->phy; 718 719 if (phy_idx && dev->phys[MT_BAND1]) 720 mphy = dev->phys[MT_BAND1]; 721 722 mt76_connac2_mac_write_txwi(dev, txwi, skb, wcid, key, pid, qid, changed); 723 724 if (mt76_testmode_enabled(mphy)) 725 mt7915_mac_write_txwi_tm(mphy->priv, txwi, skb); 726 } 727 728 int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, 729 enum mt76_txq_id qid, struct mt76_wcid *wcid, 730 struct ieee80211_sta *sta, 731 struct mt76_tx_info *tx_info) 732 { 733 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_info->skb->data; 734 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 735 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb); 736 struct ieee80211_key_conf *key = info->control.hw_key; 737 struct ieee80211_vif *vif = info->control.vif; 738 struct mt76_connac_fw_txp *txp; 739 struct mt76_txwi_cache *t; 740 int id, i, nbuf = tx_info->nbuf - 1; 741 u8 *txwi = (u8 *)txwi_ptr; 742 int pid; 743 744 if (unlikely(tx_info->skb->len <= ETH_HLEN)) 745 return -EINVAL; 746 747 if (!wcid) 748 wcid = &dev->mt76.global_wcid; 749 750 if (sta) { 751 struct mt7915_sta *msta; 752 753 msta = (struct mt7915_sta *)sta->drv_priv; 754 755 if (time_after(jiffies, msta->jiffies + HZ / 4)) { 756 info->flags |= IEEE80211_TX_CTL_REQ_TX_STATUS; 757 msta->jiffies = jiffies; 758 } 759 } 760 761 t = (struct mt76_txwi_cache *)(txwi + mdev->drv->txwi_size); 762 t->skb = tx_info->skb; 763 764 id = mt76_token_consume(mdev, &t); 765 if (id < 0) 766 return id; 767 768 pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb); 769 mt7915_mac_write_txwi(mdev, txwi_ptr, tx_info->skb, wcid, pid, key, 770 qid, 0); 771 772 txp = (struct mt76_connac_fw_txp *)(txwi + MT_TXD_SIZE); 773 for (i = 0; i < nbuf; i++) { 774 txp->buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr); 775 txp->len[i] = cpu_to_le16(tx_info->buf[i + 1].len); 776 } 777 txp->nbuf = nbuf; 778 779 txp->flags = cpu_to_le16(MT_CT_INFO_APPLY_TXD | MT_CT_INFO_FROM_HOST); 780 781 if (!key) 782 txp->flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME); 783 784 if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && 785 ieee80211_is_mgmt(hdr->frame_control)) 786 txp->flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME); 787 788 if (vif) { 789 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv; 790 791 txp->bss_idx = mvif->mt76.idx; 792 } 793 794 txp->token = cpu_to_le16(id); 795 if (test_bit(MT_WCID_FLAG_4ADDR, &wcid->flags)) 796 txp->rept_wds_wcid = cpu_to_le16(wcid->idx); 797 else 798 txp->rept_wds_wcid = cpu_to_le16(0x3ff); 799 tx_info->skb = NULL; 800 801 /* pass partial skb header to fw */ 802 tx_info->buf[1].len = MT_CT_PARSE_LEN; 803 tx_info->buf[1].skip_unmap = true; 804 tx_info->nbuf = MT_CT_DMA_BUF_NUM; 805 806 return 0; 807 } 808 809 u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id) 810 { 811 struct mt76_connac_fw_txp *txp = ptr + MT_TXD_SIZE; 812 __le32 *txwi = ptr; 813 u32 val; 814 815 memset(ptr, 0, MT_TXD_SIZE + sizeof(*txp)); 816 817 val = FIELD_PREP(MT_TXD0_TX_BYTES, MT_TXD_SIZE) | 818 FIELD_PREP(MT_TXD0_PKT_FMT, MT_TX_TYPE_CT); 819 txwi[0] = cpu_to_le32(val); 820 821 val = MT_TXD1_LONG_FORMAT | 822 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_3); 823 txwi[1] = cpu_to_le32(val); 824 825 txp->token = cpu_to_le16(token_id); 826 txp->nbuf = 1; 827 txp->buf[0] = cpu_to_le32(phys + MT_TXD_SIZE + sizeof(*txp)); 828 829 return MT_TXD_SIZE + sizeof(*txp); 830 } 831 832 static void 833 mt7915_mac_tx_free_prepare(struct mt7915_dev *dev) 834 { 835 struct mt76_dev *mdev = &dev->mt76; 836 struct mt76_phy *mphy_ext = mdev->phys[MT_BAND1]; 837 838 /* clean DMA queues and unmap buffers first */ 839 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false); 840 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false); 841 if (mphy_ext) { 842 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_PSD], false); 843 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_BE], false); 844 } 845 } 846 847 static void 848 mt7915_mac_tx_free_done(struct mt7915_dev *dev, 849 struct list_head *free_list, bool wake) 850 { 851 struct sk_buff *skb, *tmp; 852 853 mt7915_mac_sta_poll(dev); 854 855 if (wake) 856 mt76_set_tx_blocked(&dev->mt76, false); 857 858 mt76_worker_schedule(&dev->mt76.tx_worker); 859 860 list_for_each_entry_safe(skb, tmp, free_list, list) { 861 skb_list_del_init(skb); 862 napi_consume_skb(skb, 1); 863 } 864 } 865 866 static void 867 mt7915_mac_tx_free(struct mt7915_dev *dev, void *data, int len) 868 { 869 struct mt76_connac_tx_free *free = data; 870 __le32 *tx_info = (__le32 *)(data + sizeof(*free)); 871 struct mt76_dev *mdev = &dev->mt76; 872 struct mt76_txwi_cache *txwi; 873 struct ieee80211_sta *sta = NULL; 874 struct mt76_wcid *wcid = NULL; 875 LIST_HEAD(free_list); 876 void *end = data + len; 877 bool v3, wake = false; 878 u16 total, count = 0; 879 u32 txd = le32_to_cpu(free->txd); 880 __le32 *cur_info; 881 882 mt7915_mac_tx_free_prepare(dev); 883 884 total = le16_get_bits(free->ctrl, MT_TX_FREE_MSDU_CNT); 885 v3 = (FIELD_GET(MT_TX_FREE_VER, txd) == 0x4); 886 887 for (cur_info = tx_info; count < total; cur_info++) { 888 u32 msdu, info; 889 u8 i; 890 891 if (WARN_ON_ONCE((void *)cur_info >= end)) 892 return; 893 894 /* 895 * 1'b1: new wcid pair. 896 * 1'b0: msdu_id with the same 'wcid pair' as above. 897 */ 898 info = le32_to_cpu(*cur_info); 899 if (info & MT_TX_FREE_PAIR) { 900 struct mt7915_sta *msta; 901 u16 idx; 902 903 idx = FIELD_GET(MT_TX_FREE_WLAN_ID, info); 904 wcid = mt76_wcid_ptr(dev, idx); 905 sta = wcid_to_sta(wcid); 906 if (!sta) 907 continue; 908 909 msta = container_of(wcid, struct mt7915_sta, wcid); 910 mt76_wcid_add_poll(&dev->mt76, &msta->wcid); 911 continue; 912 } 913 914 if (!mtk_wed_device_active(&mdev->mmio.wed) && wcid) { 915 u32 tx_retries = 0, tx_failed = 0, count; 916 917 if (v3 && (info & MT_TX_FREE_MPDU_HEADER_V3)) { 918 count = FIELD_GET(MT_TX_FREE_COUNT_V3, info); 919 tx_retries = count ? count - 1 : 0; 920 tx_failed = tx_retries + 921 !!FIELD_GET(MT_TX_FREE_STAT_V3, info); 922 } else if (!v3 && (info & MT_TX_FREE_MPDU_HEADER)) { 923 count = FIELD_GET(MT_TX_FREE_COUNT, info); 924 tx_retries = count ? count - 1 : 0; 925 tx_failed = tx_retries + 926 !!FIELD_GET(MT_TX_FREE_STAT, info); 927 } 928 wcid->stats.tx_retries += tx_retries; 929 wcid->stats.tx_failed += tx_failed; 930 } 931 932 if (v3 && (info & MT_TX_FREE_MPDU_HEADER_V3)) 933 continue; 934 935 for (i = 0; i < 1 + v3; i++) { 936 if (v3) { 937 msdu = (info >> (15 * i)) & MT_TX_FREE_MSDU_ID_V3; 938 if (msdu == MT_TX_FREE_MSDU_ID_V3) 939 continue; 940 } else { 941 msdu = FIELD_GET(MT_TX_FREE_MSDU_ID, info); 942 } 943 count++; 944 txwi = mt76_token_release(mdev, msdu, &wake); 945 if (!txwi) 946 continue; 947 948 mt76_connac2_txwi_free(mdev, txwi, sta, &free_list); 949 } 950 } 951 952 mt7915_mac_tx_free_done(dev, &free_list, wake); 953 } 954 955 static void 956 mt7915_mac_tx_free_v0(struct mt7915_dev *dev, void *data, int len) 957 { 958 struct mt76_connac_tx_free *free = data; 959 __le16 *info = (__le16 *)(data + sizeof(*free)); 960 struct mt76_dev *mdev = &dev->mt76; 961 void *end = data + len; 962 LIST_HEAD(free_list); 963 bool wake = false; 964 u8 i, count; 965 966 mt7915_mac_tx_free_prepare(dev); 967 968 count = FIELD_GET(MT_TX_FREE_MSDU_CNT_V0, le16_to_cpu(free->ctrl)); 969 if (WARN_ON_ONCE((void *)&info[count] > end)) 970 return; 971 972 for (i = 0; i < count; i++) { 973 struct mt76_txwi_cache *txwi; 974 u16 msdu = le16_to_cpu(info[i]); 975 976 txwi = mt76_token_release(mdev, msdu, &wake); 977 if (!txwi) 978 continue; 979 980 mt76_connac2_txwi_free(mdev, txwi, NULL, &free_list); 981 } 982 983 mt7915_mac_tx_free_done(dev, &free_list, wake); 984 } 985 986 static void mt7915_mac_add_txs(struct mt7915_dev *dev, void *data) 987 { 988 struct mt7915_sta *msta = NULL; 989 struct mt76_wcid *wcid; 990 __le32 *txs_data = data; 991 u16 wcidx; 992 u8 pid; 993 994 wcidx = le32_get_bits(txs_data[2], MT_TXS2_WCID); 995 pid = le32_get_bits(txs_data[3], MT_TXS3_PID); 996 997 if (pid < MT_PACKET_ID_WED) 998 return; 999 1000 rcu_read_lock(); 1001 1002 wcid = mt76_wcid_ptr(dev, wcidx); 1003 if (!wcid) 1004 goto out; 1005 1006 msta = container_of(wcid, struct mt7915_sta, wcid); 1007 1008 if (pid == MT_PACKET_ID_WED) 1009 mt76_connac2_mac_fill_txs(&dev->mt76, wcid, txs_data); 1010 else 1011 mt76_connac2_mac_add_txs_skb(&dev->mt76, wcid, pid, txs_data); 1012 1013 if (!wcid->sta) 1014 goto out; 1015 1016 mt76_wcid_add_poll(&dev->mt76, &msta->wcid); 1017 1018 out: 1019 rcu_read_unlock(); 1020 } 1021 1022 bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len) 1023 { 1024 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 1025 __le32 *rxd = (__le32 *)data; 1026 __le32 *end = (__le32 *)&rxd[len / 4]; 1027 enum rx_pkt_type type; 1028 1029 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); 1030 1031 switch (type) { 1032 case PKT_TYPE_TXRX_NOTIFY: 1033 mt7915_mac_tx_free(dev, data, len); 1034 return false; 1035 case PKT_TYPE_TXRX_NOTIFY_V0: 1036 mt7915_mac_tx_free_v0(dev, data, len); 1037 return false; 1038 case PKT_TYPE_TXS: 1039 for (rxd += 2; rxd + 8 <= end; rxd += 8) 1040 mt7915_mac_add_txs(dev, rxd); 1041 return false; 1042 case PKT_TYPE_RX_FW_MONITOR: 1043 mt7915_debugfs_rx_fw_monitor(dev, data, len); 1044 return false; 1045 default: 1046 return true; 1047 } 1048 } 1049 1050 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 1051 struct sk_buff *skb, u32 *info) 1052 { 1053 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 1054 __le32 *rxd = (__le32 *)skb->data; 1055 __le32 *end = (__le32 *)&skb->data[skb->len]; 1056 enum rx_pkt_type type; 1057 1058 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); 1059 1060 switch (type) { 1061 case PKT_TYPE_TXRX_NOTIFY: 1062 mt7915_mac_tx_free(dev, skb->data, skb->len); 1063 napi_consume_skb(skb, 1); 1064 break; 1065 case PKT_TYPE_TXRX_NOTIFY_V0: 1066 mt7915_mac_tx_free_v0(dev, skb->data, skb->len); 1067 napi_consume_skb(skb, 1); 1068 break; 1069 case PKT_TYPE_RX_EVENT: 1070 mt7915_mcu_rx_event(dev, skb); 1071 break; 1072 case PKT_TYPE_TXRXV: 1073 mt7915_mac_fill_rx_vector(dev, skb); 1074 break; 1075 case PKT_TYPE_TXS: 1076 for (rxd += 2; rxd + 8 <= end; rxd += 8) 1077 mt7915_mac_add_txs(dev, rxd); 1078 dev_kfree_skb(skb); 1079 break; 1080 case PKT_TYPE_RX_FW_MONITOR: 1081 mt7915_debugfs_rx_fw_monitor(dev, skb->data, skb->len); 1082 dev_kfree_skb(skb); 1083 break; 1084 case PKT_TYPE_NORMAL: 1085 if (!mt7915_mac_fill_rx(dev, skb, q, info)) { 1086 mt76_rx(&dev->mt76, q, skb); 1087 return; 1088 } 1089 fallthrough; 1090 default: 1091 dev_kfree_skb(skb); 1092 break; 1093 } 1094 } 1095 1096 void mt7915_mac_cca_stats_reset(struct mt7915_phy *phy) 1097 { 1098 struct mt7915_dev *dev = phy->dev; 1099 u32 reg = MT_WF_PHY_RX_CTRL1(phy->mt76->band_idx); 1100 1101 mt76_clear(dev, reg, MT_WF_PHY_RX_CTRL1_STSCNT_EN); 1102 mt76_set(dev, reg, BIT(11) | BIT(9)); 1103 } 1104 1105 void mt7915_mac_reset_counters(struct mt7915_phy *phy) 1106 { 1107 struct mt7915_dev *dev = phy->dev; 1108 int i; 1109 1110 for (i = 0; i < 4; i++) { 1111 mt76_rr(dev, MT_TX_AGG_CNT(phy->mt76->band_idx, i)); 1112 mt76_rr(dev, MT_TX_AGG_CNT2(phy->mt76->band_idx, i)); 1113 } 1114 1115 phy->mt76->survey_time = ktime_get_boottime(); 1116 memset(phy->mt76->aggr_stats, 0, sizeof(phy->mt76->aggr_stats)); 1117 1118 /* reset airtime counters */ 1119 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(phy->mt76->band_idx), 1120 MT_WF_RMAC_MIB_RXTIME_CLR); 1121 1122 mt7915_mcu_get_chan_mib_info(phy, true); 1123 } 1124 1125 void mt7915_mac_set_timing(struct mt7915_phy *phy) 1126 { 1127 s16 coverage_class = phy->coverage_class; 1128 struct mt7915_dev *dev = phy->dev; 1129 struct mt7915_phy *ext_phy = mt7915_ext_phy(dev); 1130 u32 val, reg_offset; 1131 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | 1132 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); 1133 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | 1134 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28); 1135 u8 band = phy->mt76->band_idx; 1136 int eifs_ofdm = 84, sifs = 10, offset; 1137 bool a_band = !(phy->mt76->chandef.chan->band == NL80211_BAND_2GHZ); 1138 1139 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state)) 1140 return; 1141 1142 if (ext_phy) 1143 coverage_class = max_t(s16, dev->phy.coverage_class, 1144 ext_phy->coverage_class); 1145 1146 mt76_set(dev, MT_ARB_SCR(band), 1147 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1148 udelay(1); 1149 1150 offset = 3 * coverage_class; 1151 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | 1152 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); 1153 1154 if (!is_mt7915(&dev->mt76)) { 1155 if (!a_band) { 1156 mt76_wr(dev, MT_TMAC_ICR1(band), 1157 FIELD_PREP(MT_IFS_EIFS_CCK, 314)); 1158 eifs_ofdm = 78; 1159 } else { 1160 eifs_ofdm = 84; 1161 } 1162 } else if (a_band) { 1163 sifs = 16; 1164 } 1165 1166 mt76_wr(dev, MT_TMAC_CDTR(band), cck + reg_offset); 1167 mt76_wr(dev, MT_TMAC_ODTR(band), ofdm + reg_offset); 1168 mt76_wr(dev, MT_TMAC_ICR0(band), 1169 FIELD_PREP(MT_IFS_EIFS_OFDM, eifs_ofdm) | 1170 FIELD_PREP(MT_IFS_RIFS, 2) | 1171 FIELD_PREP(MT_IFS_SIFS, sifs) | 1172 FIELD_PREP(MT_IFS_SLOT, phy->slottime)); 1173 1174 if (phy->slottime < 20 || a_band) 1175 val = MT7915_CFEND_RATE_DEFAULT; 1176 else 1177 val = MT7915_CFEND_RATE_11B; 1178 1179 mt76_rmw_field(dev, MT_AGG_ACR0(band), MT_AGG_ACR_CFEND_RATE, val); 1180 mt76_clear(dev, MT_ARB_SCR(band), 1181 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1182 } 1183 1184 void mt7915_mac_enable_nf(struct mt7915_dev *dev, bool band) 1185 { 1186 u32 reg; 1187 1188 reg = is_mt7915(&dev->mt76) ? MT_WF_PHY_RXTD12(band) : 1189 MT_WF_PHY_RXTD12_MT7916(band); 1190 mt76_set(dev, reg, 1191 MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY | 1192 MT_WF_PHY_RXTD12_IRPI_SW_CLR); 1193 1194 reg = is_mt7915(&dev->mt76) ? MT_WF_PHY_RX_CTRL1(band) : 1195 MT_WF_PHY_RX_CTRL1_MT7916(band); 1196 mt76_set(dev, reg, FIELD_PREP(MT_WF_PHY_RX_CTRL1_IPI_EN, 0x5)); 1197 } 1198 1199 static u8 1200 mt7915_phy_get_nf(struct mt7915_phy *phy, int idx) 1201 { 1202 static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 }; 1203 struct mt7915_dev *dev = phy->dev; 1204 u32 val, sum = 0, n = 0; 1205 int nss, i; 1206 1207 for (nss = 0; nss < hweight8(phy->mt76->chainmask); nss++) { 1208 u32 reg = is_mt7915(&dev->mt76) ? 1209 MT_WF_IRPI_NSS(0, nss + (idx << dev->dbdc_support)) : 1210 MT_WF_IRPI_NSS_MT7916(idx, nss); 1211 1212 for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) { 1213 val = mt76_rr(dev, reg); 1214 sum += val * nf_power[i]; 1215 n += val; 1216 } 1217 } 1218 1219 if (!n) 1220 return 0; 1221 1222 return sum / n; 1223 } 1224 1225 void mt7915_update_channel(struct mt76_phy *mphy) 1226 { 1227 struct mt7915_phy *phy = mphy->priv; 1228 struct mt76_channel_state *state = mphy->chan_state; 1229 int nf; 1230 1231 mt7915_mcu_get_chan_mib_info(phy, false); 1232 1233 nf = mt7915_phy_get_nf(phy, phy->mt76->band_idx); 1234 if (!phy->noise) 1235 phy->noise = nf << 4; 1236 else if (nf) 1237 phy->noise += nf - (phy->noise >> 4); 1238 1239 state->noise = -(phy->noise >> 4); 1240 } 1241 1242 static bool 1243 mt7915_wait_reset_state(struct mt7915_dev *dev, u32 state) 1244 { 1245 bool ret; 1246 1247 ret = wait_event_timeout(dev->reset_wait, 1248 (READ_ONCE(dev->recovery.state) & state), 1249 MT7915_RESET_TIMEOUT); 1250 1251 WARN(!ret, "Timeout waiting for MCU reset state %x\n", state); 1252 return ret; 1253 } 1254 1255 static void 1256 mt7915_update_vif_beacon(void *priv, u8 *mac, struct ieee80211_vif *vif) 1257 { 1258 struct ieee80211_hw *hw = priv; 1259 1260 switch (vif->type) { 1261 case NL80211_IFTYPE_MESH_POINT: 1262 case NL80211_IFTYPE_ADHOC: 1263 case NL80211_IFTYPE_AP: 1264 mt7915_mcu_add_beacon(hw, vif, vif->bss_conf.enable_beacon, 1265 BSS_CHANGED_BEACON_ENABLED); 1266 break; 1267 default: 1268 break; 1269 } 1270 } 1271 1272 static void 1273 mt7915_update_beacons(struct mt7915_dev *dev) 1274 { 1275 struct mt76_phy *mphy_ext = dev->mt76.phys[MT_BAND1]; 1276 1277 ieee80211_iterate_active_interfaces(dev->mt76.hw, 1278 IEEE80211_IFACE_ITER_RESUME_ALL, 1279 mt7915_update_vif_beacon, dev->mt76.hw); 1280 1281 if (!mphy_ext) 1282 return; 1283 1284 ieee80211_iterate_active_interfaces(mphy_ext->hw, 1285 IEEE80211_IFACE_ITER_RESUME_ALL, 1286 mt7915_update_vif_beacon, mphy_ext->hw); 1287 } 1288 1289 static int 1290 mt7915_mac_restart(struct mt7915_dev *dev) 1291 { 1292 struct mt7915_phy *phy2; 1293 struct mt76_phy *ext_phy; 1294 struct mt76_dev *mdev = &dev->mt76; 1295 bool run_main, run_ext; 1296 int i, ret; 1297 1298 ext_phy = dev->mt76.phys[MT_BAND1]; 1299 phy2 = ext_phy ? ext_phy->priv : NULL; 1300 1301 if (dev->hif2) { 1302 mt76_wr(dev, MT_INT1_MASK_CSR, 0x0); 1303 mt76_wr(dev, MT_INT1_SOURCE_CSR, ~0); 1304 } 1305 1306 if (dev_is_pci(mdev->dev)) { 1307 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0); 1308 if (dev->hif2) { 1309 if (is_mt7915(mdev)) 1310 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE, 0x0); 1311 else 1312 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE_MT7916, 0x0); 1313 } 1314 } 1315 1316 set_bit(MT76_RESET, &dev->mphy.state); 1317 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1318 wake_up(&dev->mt76.mcu.wait); 1319 if (ext_phy) 1320 set_bit(MT76_RESET, &ext_phy->state); 1321 1322 /* lock/unlock all queues to ensure that no tx is pending */ 1323 mt76_txq_schedule_all(&dev->mphy); 1324 if (ext_phy) 1325 mt76_txq_schedule_all(ext_phy); 1326 1327 /* disable all tx/rx napi */ 1328 mt76_worker_disable(&dev->mt76.tx_worker); 1329 mt76_for_each_q_rx(mdev, i) { 1330 if (mdev->q_rx[i].ndesc) 1331 napi_disable(&dev->mt76.napi[i]); 1332 } 1333 napi_disable(&dev->mt76.tx_napi); 1334 1335 /* token reinit */ 1336 mt76_connac2_tx_token_put(&dev->mt76); 1337 idr_init(&dev->mt76.token); 1338 1339 mt7915_dma_reset(dev, true); 1340 1341 mt76_for_each_q_rx(mdev, i) { 1342 if (mdev->q_rx[i].ndesc) { 1343 napi_enable(&dev->mt76.napi[i]); 1344 } 1345 } 1346 1347 local_bh_disable(); 1348 mt76_for_each_q_rx(mdev, i) { 1349 if (mdev->q_rx[i].ndesc) { 1350 napi_schedule(&dev->mt76.napi[i]); 1351 } 1352 } 1353 local_bh_enable(); 1354 clear_bit(MT76_MCU_RESET, &dev->mphy.state); 1355 clear_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state); 1356 1357 mt76_wr(dev, MT_INT_MASK_CSR, dev->mt76.mmio.irqmask); 1358 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 1359 1360 if (dev->hif2) { 1361 mt76_wr(dev, MT_INT1_MASK_CSR, dev->mt76.mmio.irqmask); 1362 mt76_wr(dev, MT_INT1_SOURCE_CSR, ~0); 1363 } 1364 if (dev_is_pci(mdev->dev)) { 1365 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff); 1366 if (dev->hif2) { 1367 mt76_wr(dev, MT_PCIE_RECOG_ID, 1368 dev->hif2->index | MT_PCIE_RECOG_ID_SEM); 1369 if (is_mt7915(mdev)) 1370 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE, 0xff); 1371 else 1372 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE_MT7916, 0xff); 1373 } 1374 } 1375 1376 /* load firmware */ 1377 ret = mt7915_mcu_init_firmware(dev); 1378 if (ret) 1379 goto out; 1380 1381 /* set the necessary init items */ 1382 ret = mt7915_mcu_set_eeprom(dev); 1383 if (ret) 1384 goto out; 1385 1386 mt7915_mac_init(dev); 1387 mt7915_init_txpower(&dev->phy); 1388 mt7915_init_txpower(phy2); 1389 ret = mt7915_txbf_init(dev); 1390 1391 run_main = test_and_clear_bit(MT76_STATE_RUNNING, &dev->mphy.state); 1392 run_ext = ext_phy && 1393 test_and_clear_bit(MT76_STATE_RUNNING, &ext_phy->state); 1394 1395 if (run_main) { 1396 ret = mt7915_run(dev->mphy.hw); 1397 if (ret) 1398 goto out; 1399 } 1400 1401 if (run_ext) { 1402 ret = mt7915_run(ext_phy->hw); 1403 if (ret) 1404 goto out; 1405 } 1406 1407 out: 1408 /* reset done */ 1409 clear_bit(MT76_RESET, &dev->mphy.state); 1410 if (phy2) 1411 clear_bit(MT76_RESET, &phy2->mt76->state); 1412 1413 napi_enable(&dev->mt76.tx_napi); 1414 1415 local_bh_disable(); 1416 napi_schedule(&dev->mt76.tx_napi); 1417 local_bh_enable(); 1418 1419 mt76_worker_enable(&dev->mt76.tx_worker); 1420 1421 return ret; 1422 } 1423 1424 static void 1425 mt7915_mac_full_reset(struct mt7915_dev *dev) 1426 { 1427 struct mt76_phy *ext_phy; 1428 struct mt7915_phy *phy2; 1429 int i; 1430 1431 ext_phy = dev->mt76.phys[MT_BAND1]; 1432 phy2 = ext_phy ? ext_phy->priv : NULL; 1433 1434 dev->recovery.hw_full_reset = true; 1435 1436 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1437 wake_up(&dev->mt76.mcu.wait); 1438 ieee80211_stop_queues(mt76_hw(dev)); 1439 if (ext_phy) 1440 ieee80211_stop_queues(ext_phy->hw); 1441 1442 cancel_delayed_work_sync(&dev->mphy.mac_work); 1443 if (ext_phy) 1444 cancel_delayed_work_sync(&ext_phy->mac_work); 1445 1446 mt76_abort_scan(&dev->mt76); 1447 1448 mutex_lock(&dev->mt76.mutex); 1449 for (i = 0; i < 10; i++) { 1450 if (!mt7915_mac_restart(dev)) 1451 break; 1452 } 1453 1454 if (i == 10) 1455 dev_err(dev->mt76.dev, "chip full reset failed\n"); 1456 1457 dev->phy.omac_mask = 0; 1458 if (phy2) 1459 phy2->omac_mask = 0; 1460 1461 mt76_reset_device(&dev->mt76); 1462 1463 INIT_LIST_HEAD(&dev->sta_rc_list); 1464 INIT_LIST_HEAD(&dev->twt_list); 1465 1466 i = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7915_WTBL_STA); 1467 dev->mt76.global_wcid.idx = i; 1468 dev->recovery.hw_full_reset = false; 1469 1470 mutex_unlock(&dev->mt76.mutex); 1471 1472 ieee80211_wake_queues(mt76_hw(dev)); 1473 if (ext_phy) 1474 ieee80211_wake_queues(ext_phy->hw); 1475 1476 ieee80211_restart_hw(mt76_hw(dev)); 1477 if (ext_phy) 1478 ieee80211_restart_hw(ext_phy->hw); 1479 } 1480 1481 /* system error recovery */ 1482 void mt7915_mac_reset_work(struct work_struct *work) 1483 { 1484 struct mt7915_phy *phy2; 1485 struct mt76_phy *ext_phy; 1486 struct mt7915_dev *dev; 1487 int i; 1488 1489 dev = container_of(work, struct mt7915_dev, reset_work); 1490 ext_phy = dev->mt76.phys[MT_BAND1]; 1491 phy2 = ext_phy ? ext_phy->priv : NULL; 1492 1493 /* chip full reset */ 1494 if (dev->recovery.restart) { 1495 /* disable WA/WM WDT */ 1496 mt76_clear(dev, MT_WFDMA0_MCU_HOST_INT_ENA, 1497 MT_MCU_CMD_WDT_MASK); 1498 1499 if (READ_ONCE(dev->recovery.state) & MT_MCU_CMD_WA_WDT) 1500 dev->recovery.wa_reset_count++; 1501 else 1502 dev->recovery.wm_reset_count++; 1503 1504 mt7915_mac_full_reset(dev); 1505 1506 /* enable mcu irq */ 1507 mt7915_irq_enable(dev, MT_INT_MCU_CMD); 1508 mt7915_irq_disable(dev, 0); 1509 1510 /* enable WA/WM WDT */ 1511 mt76_set(dev, MT_WFDMA0_MCU_HOST_INT_ENA, MT_MCU_CMD_WDT_MASK); 1512 1513 dev->recovery.state = MT_MCU_CMD_NORMAL_STATE; 1514 dev->recovery.restart = false; 1515 return; 1516 } 1517 1518 /* chip partial reset */ 1519 if (!(READ_ONCE(dev->recovery.state) & MT_MCU_CMD_STOP_DMA)) 1520 return; 1521 1522 ieee80211_stop_queues(mt76_hw(dev)); 1523 if (ext_phy) 1524 ieee80211_stop_queues(ext_phy->hw); 1525 1526 set_bit(MT76_RESET, &dev->mphy.state); 1527 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1528 wake_up(&dev->mt76.mcu.wait); 1529 cancel_delayed_work_sync(&dev->mphy.mac_work); 1530 if (phy2) { 1531 set_bit(MT76_RESET, &phy2->mt76->state); 1532 cancel_delayed_work_sync(&phy2->mt76->mac_work); 1533 } 1534 1535 mutex_lock(&dev->mt76.mutex); 1536 1537 mt76_worker_disable(&dev->mt76.tx_worker); 1538 mt76_for_each_q_rx(&dev->mt76, i) 1539 napi_disable(&dev->mt76.napi[i]); 1540 napi_disable(&dev->mt76.tx_napi); 1541 1542 1543 if (mtk_wed_device_active(&dev->mt76.mmio.wed)) 1544 mtk_wed_device_stop(&dev->mt76.mmio.wed); 1545 1546 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_STOPPED); 1547 1548 if (mt7915_wait_reset_state(dev, MT_MCU_CMD_RESET_DONE)) { 1549 mt7915_dma_reset(dev, false); 1550 1551 mt76_connac2_tx_token_put(&dev->mt76); 1552 idr_init(&dev->mt76.token); 1553 1554 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_INIT); 1555 mt7915_wait_reset_state(dev, MT_MCU_CMD_RECOVERY_DONE); 1556 } 1557 1558 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_RESET_DONE); 1559 mt7915_wait_reset_state(dev, MT_MCU_CMD_NORMAL_STATE); 1560 1561 /* enable DMA Tx/Rx and interrupt */ 1562 mt7915_dma_start(dev, false, false); 1563 1564 clear_bit(MT76_MCU_RESET, &dev->mphy.state); 1565 clear_bit(MT76_RESET, &dev->mphy.state); 1566 if (phy2) 1567 clear_bit(MT76_RESET, &phy2->mt76->state); 1568 1569 mt76_for_each_q_rx(&dev->mt76, i) { 1570 napi_enable(&dev->mt76.napi[i]); 1571 } 1572 1573 local_bh_disable(); 1574 mt76_for_each_q_rx(&dev->mt76, i) { 1575 napi_schedule(&dev->mt76.napi[i]); 1576 } 1577 local_bh_enable(); 1578 1579 tasklet_schedule(&dev->mt76.irq_tasklet); 1580 1581 mt76_worker_enable(&dev->mt76.tx_worker); 1582 1583 napi_enable(&dev->mt76.tx_napi); 1584 local_bh_disable(); 1585 napi_schedule(&dev->mt76.tx_napi); 1586 local_bh_enable(); 1587 1588 ieee80211_wake_queues(mt76_hw(dev)); 1589 if (ext_phy) 1590 ieee80211_wake_queues(ext_phy->hw); 1591 1592 mutex_unlock(&dev->mt76.mutex); 1593 1594 mt7915_update_beacons(dev); 1595 1596 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work, 1597 MT7915_WATCHDOG_TIME); 1598 if (phy2) 1599 ieee80211_queue_delayed_work(ext_phy->hw, 1600 &phy2->mt76->mac_work, 1601 MT7915_WATCHDOG_TIME); 1602 } 1603 1604 /* firmware coredump */ 1605 void mt7915_mac_dump_work(struct work_struct *work) 1606 { 1607 const struct mt7915_mem_region *mem_region; 1608 struct mt7915_crash_data *crash_data; 1609 struct mt7915_dev *dev; 1610 struct mt7915_mem_hdr *hdr; 1611 size_t buf_len; 1612 int i; 1613 u32 num; 1614 u8 *buf; 1615 1616 dev = container_of(work, struct mt7915_dev, dump_work); 1617 1618 mutex_lock(&dev->dump_mutex); 1619 1620 crash_data = mt7915_coredump_new(dev); 1621 if (!crash_data) { 1622 mutex_unlock(&dev->dump_mutex); 1623 goto skip_coredump; 1624 } 1625 1626 mem_region = mt7915_coredump_get_mem_layout(dev, &num); 1627 if (!mem_region || !crash_data->memdump_buf_len) { 1628 mutex_unlock(&dev->dump_mutex); 1629 goto skip_memdump; 1630 } 1631 1632 buf = crash_data->memdump_buf; 1633 buf_len = crash_data->memdump_buf_len; 1634 1635 /* dumping memory content... */ 1636 memset(buf, 0, buf_len); 1637 for (i = 0; i < num; i++) { 1638 if (mem_region->len > buf_len) { 1639 dev_warn(dev->mt76.dev, "%s len %lu is too large\n", 1640 mem_region->name, 1641 (unsigned long)mem_region->len); 1642 break; 1643 } 1644 1645 /* reserve space for the header */ 1646 hdr = (void *)buf; 1647 buf += sizeof(*hdr); 1648 buf_len -= sizeof(*hdr); 1649 1650 mt7915_memcpy_fromio(dev, buf, mem_region->start, 1651 mem_region->len); 1652 1653 hdr->start = mem_region->start; 1654 hdr->len = mem_region->len; 1655 1656 if (!mem_region->len) 1657 /* note: the header remains, just with zero length */ 1658 break; 1659 1660 buf += mem_region->len; 1661 buf_len -= mem_region->len; 1662 1663 mem_region++; 1664 } 1665 1666 mutex_unlock(&dev->dump_mutex); 1667 1668 skip_memdump: 1669 mt7915_coredump_submit(dev); 1670 skip_coredump: 1671 queue_work(dev->mt76.wq, &dev->reset_work); 1672 } 1673 1674 void mt7915_reset(struct mt7915_dev *dev) 1675 { 1676 if (!dev->recovery.hw_init_done) 1677 return; 1678 1679 if (dev->recovery.hw_full_reset) 1680 return; 1681 1682 /* wm/wa exception: do full recovery */ 1683 if (READ_ONCE(dev->recovery.state) & MT_MCU_CMD_WDT_MASK) { 1684 dev->recovery.restart = true; 1685 dev_info(dev->mt76.dev, 1686 "%s indicated firmware crash, attempting recovery\n", 1687 wiphy_name(dev->mt76.hw->wiphy)); 1688 1689 mt7915_irq_disable(dev, MT_INT_MCU_CMD); 1690 queue_work(dev->mt76.wq, &dev->dump_work); 1691 return; 1692 } 1693 1694 if ((READ_ONCE(dev->recovery.state) & MT_MCU_CMD_STOP_DMA)) { 1695 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1696 wake_up(&dev->mt76.mcu.wait); 1697 } 1698 1699 queue_work(dev->mt76.wq, &dev->reset_work); 1700 wake_up(&dev->reset_wait); 1701 } 1702 1703 void mt7915_mac_update_stats(struct mt7915_phy *phy) 1704 { 1705 struct mt76_mib_stats *mib = &phy->mib; 1706 struct mt7915_dev *dev = phy->dev; 1707 int i, aggr0 = 0, aggr1, cnt; 1708 u8 band = phy->mt76->band_idx; 1709 u32 val; 1710 1711 cnt = mt76_rr(dev, MT_MIB_SDR3(band)); 1712 mib->fcs_err_cnt += is_mt7915(&dev->mt76) ? 1713 FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK, cnt) : 1714 FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK_MT7916, cnt); 1715 1716 cnt = mt76_rr(dev, MT_MIB_SDR4(band)); 1717 mib->rx_fifo_full_cnt += FIELD_GET(MT_MIB_SDR4_RX_FIFO_FULL_MASK, cnt); 1718 1719 cnt = mt76_rr(dev, MT_MIB_SDR5(band)); 1720 mib->rx_mpdu_cnt += cnt; 1721 1722 cnt = mt76_rr(dev, MT_MIB_SDR6(band)); 1723 mib->channel_idle_cnt += FIELD_GET(MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK, cnt); 1724 1725 cnt = mt76_rr(dev, MT_MIB_SDR7(band)); 1726 mib->rx_vector_mismatch_cnt += 1727 FIELD_GET(MT_MIB_SDR7_RX_VECTOR_MISMATCH_CNT_MASK, cnt); 1728 1729 cnt = mt76_rr(dev, MT_MIB_SDR8(band)); 1730 mib->rx_delimiter_fail_cnt += 1731 FIELD_GET(MT_MIB_SDR8_RX_DELIMITER_FAIL_CNT_MASK, cnt); 1732 1733 cnt = mt76_rr(dev, MT_MIB_SDR10(band)); 1734 mib->rx_mrdy_cnt += is_mt7915(&dev->mt76) ? 1735 FIELD_GET(MT_MIB_SDR10_MRDY_COUNT_MASK, cnt) : 1736 FIELD_GET(MT_MIB_SDR10_MRDY_COUNT_MASK_MT7916, cnt); 1737 1738 cnt = mt76_rr(dev, MT_MIB_SDR11(band)); 1739 mib->rx_len_mismatch_cnt += 1740 FIELD_GET(MT_MIB_SDR11_RX_LEN_MISMATCH_CNT_MASK, cnt); 1741 1742 cnt = mt76_rr(dev, MT_MIB_SDR12(band)); 1743 mib->tx_ampdu_cnt += cnt; 1744 1745 cnt = mt76_rr(dev, MT_MIB_SDR13(band)); 1746 mib->tx_stop_q_empty_cnt += 1747 FIELD_GET(MT_MIB_SDR13_TX_STOP_Q_EMPTY_CNT_MASK, cnt); 1748 1749 cnt = mt76_rr(dev, MT_MIB_SDR14(band)); 1750 mib->tx_mpdu_attempts_cnt += is_mt7915(&dev->mt76) ? 1751 FIELD_GET(MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK, cnt) : 1752 FIELD_GET(MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK_MT7916, cnt); 1753 1754 cnt = mt76_rr(dev, MT_MIB_SDR15(band)); 1755 mib->tx_mpdu_success_cnt += is_mt7915(&dev->mt76) ? 1756 FIELD_GET(MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK, cnt) : 1757 FIELD_GET(MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK_MT7916, cnt); 1758 1759 cnt = mt76_rr(dev, MT_MIB_SDR16(band)); 1760 mib->primary_cca_busy_time += 1761 FIELD_GET(MT_MIB_SDR16_PRIMARY_CCA_BUSY_TIME_MASK, cnt); 1762 1763 cnt = mt76_rr(dev, MT_MIB_SDR17(band)); 1764 mib->secondary_cca_busy_time += 1765 FIELD_GET(MT_MIB_SDR17_SECONDARY_CCA_BUSY_TIME_MASK, cnt); 1766 1767 cnt = mt76_rr(dev, MT_MIB_SDR18(band)); 1768 mib->primary_energy_detect_time += 1769 FIELD_GET(MT_MIB_SDR18_PRIMARY_ENERGY_DETECT_TIME_MASK, cnt); 1770 1771 cnt = mt76_rr(dev, MT_MIB_SDR19(band)); 1772 mib->cck_mdrdy_time += FIELD_GET(MT_MIB_SDR19_CCK_MDRDY_TIME_MASK, cnt); 1773 1774 cnt = mt76_rr(dev, MT_MIB_SDR20(band)); 1775 mib->ofdm_mdrdy_time += 1776 FIELD_GET(MT_MIB_SDR20_OFDM_VHT_MDRDY_TIME_MASK, cnt); 1777 1778 cnt = mt76_rr(dev, MT_MIB_SDR21(band)); 1779 mib->green_mdrdy_time += 1780 FIELD_GET(MT_MIB_SDR21_GREEN_MDRDY_TIME_MASK, cnt); 1781 1782 cnt = mt76_rr(dev, MT_MIB_SDR22(band)); 1783 mib->rx_ampdu_cnt += cnt; 1784 1785 cnt = mt76_rr(dev, MT_MIB_SDR23(band)); 1786 mib->rx_ampdu_bytes_cnt += cnt; 1787 1788 cnt = mt76_rr(dev, MT_MIB_SDR24(band)); 1789 mib->rx_ampdu_valid_subframe_cnt += is_mt7915(&dev->mt76) ? 1790 FIELD_GET(MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK, cnt) : 1791 FIELD_GET(MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK_MT7916, cnt); 1792 1793 cnt = mt76_rr(dev, MT_MIB_SDR25(band)); 1794 mib->rx_ampdu_valid_subframe_bytes_cnt += cnt; 1795 1796 cnt = mt76_rr(dev, MT_MIB_SDR27(band)); 1797 mib->tx_rwp_fail_cnt += 1798 FIELD_GET(MT_MIB_SDR27_TX_RWP_FAIL_CNT_MASK, cnt); 1799 1800 cnt = mt76_rr(dev, MT_MIB_SDR28(band)); 1801 mib->tx_rwp_need_cnt += 1802 FIELD_GET(MT_MIB_SDR28_TX_RWP_NEED_CNT_MASK, cnt); 1803 1804 cnt = mt76_rr(dev, MT_MIB_SDR29(band)); 1805 mib->rx_pfdrop_cnt += is_mt7915(&dev->mt76) ? 1806 FIELD_GET(MT_MIB_SDR29_RX_PFDROP_CNT_MASK, cnt) : 1807 FIELD_GET(MT_MIB_SDR29_RX_PFDROP_CNT_MASK_MT7916, cnt); 1808 1809 cnt = mt76_rr(dev, MT_MIB_SDRVEC(band)); 1810 mib->rx_vec_queue_overflow_drop_cnt += is_mt7915(&dev->mt76) ? 1811 FIELD_GET(MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK, cnt) : 1812 FIELD_GET(MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK_MT7916, cnt); 1813 1814 cnt = mt76_rr(dev, MT_MIB_SDR31(band)); 1815 mib->rx_ba_cnt += cnt; 1816 1817 cnt = mt76_rr(dev, MT_MIB_SDRMUBF(band)); 1818 mib->tx_bf_cnt += FIELD_GET(MT_MIB_MU_BF_TX_CNT, cnt); 1819 1820 cnt = mt76_rr(dev, MT_MIB_DR8(band)); 1821 mib->tx_mu_mpdu_cnt += cnt; 1822 1823 cnt = mt76_rr(dev, MT_MIB_DR9(band)); 1824 mib->tx_mu_acked_mpdu_cnt += cnt; 1825 1826 cnt = mt76_rr(dev, MT_MIB_DR11(band)); 1827 mib->tx_su_acked_mpdu_cnt += cnt; 1828 1829 cnt = mt76_rr(dev, MT_ETBF_PAR_RPT0(band)); 1830 mib->tx_bf_rx_fb_bw = FIELD_GET(MT_ETBF_PAR_RPT0_FB_BW, cnt); 1831 mib->tx_bf_rx_fb_nc_cnt += FIELD_GET(MT_ETBF_PAR_RPT0_FB_NC, cnt); 1832 mib->tx_bf_rx_fb_nr_cnt += FIELD_GET(MT_ETBF_PAR_RPT0_FB_NR, cnt); 1833 1834 for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) { 1835 cnt = mt76_rr(dev, MT_PLE_AMSDU_PACK_MSDU_CNT(i)); 1836 mib->tx_amsdu[i] += cnt; 1837 mib->tx_amsdu_cnt += cnt; 1838 } 1839 1840 if (is_mt7915(&dev->mt76)) { 1841 for (i = 0, aggr1 = aggr0 + 8; i < 4; i++) { 1842 val = mt76_rr(dev, MT_MIB_MB_SDR1(band, (i << 4))); 1843 mib->ba_miss_cnt += 1844 FIELD_GET(MT_MIB_BA_MISS_COUNT_MASK, val); 1845 mib->ack_fail_cnt += 1846 FIELD_GET(MT_MIB_ACK_FAIL_COUNT_MASK, val); 1847 1848 val = mt76_rr(dev, MT_MIB_MB_SDR0(band, (i << 4))); 1849 mib->rts_cnt += FIELD_GET(MT_MIB_RTS_COUNT_MASK, val); 1850 mib->rts_retries_cnt += 1851 FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, val); 1852 1853 val = mt76_rr(dev, MT_TX_AGG_CNT(band, i)); 1854 phy->mt76->aggr_stats[aggr0++] += val & 0xffff; 1855 phy->mt76->aggr_stats[aggr0++] += val >> 16; 1856 1857 val = mt76_rr(dev, MT_TX_AGG_CNT2(band, i)); 1858 phy->mt76->aggr_stats[aggr1++] += val & 0xffff; 1859 phy->mt76->aggr_stats[aggr1++] += val >> 16; 1860 } 1861 1862 cnt = mt76_rr(dev, MT_MIB_SDR32(band)); 1863 mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt); 1864 1865 cnt = mt76_rr(dev, MT_MIB_SDR33(band)); 1866 mib->tx_pkt_ibf_cnt += FIELD_GET(MT_MIB_SDR33_TX_PKT_IBF_CNT, cnt); 1867 1868 cnt = mt76_rr(dev, MT_ETBF_TX_APP_CNT(band)); 1869 mib->tx_bf_ibf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_IBF_CNT, cnt); 1870 mib->tx_bf_ebf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_EBF_CNT, cnt); 1871 1872 cnt = mt76_rr(dev, MT_ETBF_TX_NDP_BFRP(band)); 1873 mib->tx_bf_fb_cpl_cnt += FIELD_GET(MT_ETBF_TX_FB_CPL, cnt); 1874 mib->tx_bf_fb_trig_cnt += FIELD_GET(MT_ETBF_TX_FB_TRI, cnt); 1875 1876 cnt = mt76_rr(dev, MT_ETBF_RX_FB_CNT(band)); 1877 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_ETBF_RX_FB_ALL, cnt); 1878 mib->tx_bf_rx_fb_he_cnt += FIELD_GET(MT_ETBF_RX_FB_HE, cnt); 1879 mib->tx_bf_rx_fb_vht_cnt += FIELD_GET(MT_ETBF_RX_FB_VHT, cnt); 1880 mib->tx_bf_rx_fb_ht_cnt += FIELD_GET(MT_ETBF_RX_FB_HT, cnt); 1881 } else { 1882 for (i = 0; i < 2; i++) { 1883 /* rts count */ 1884 val = mt76_rr(dev, MT_MIB_MB_SDR0(band, (i << 2))); 1885 mib->rts_cnt += FIELD_GET(GENMASK(15, 0), val); 1886 mib->rts_cnt += FIELD_GET(GENMASK(31, 16), val); 1887 1888 /* rts retry count */ 1889 val = mt76_rr(dev, MT_MIB_MB_SDR1(band, (i << 2))); 1890 mib->rts_retries_cnt += FIELD_GET(GENMASK(15, 0), val); 1891 mib->rts_retries_cnt += FIELD_GET(GENMASK(31, 16), val); 1892 1893 /* ba miss count */ 1894 val = mt76_rr(dev, MT_MIB_MB_SDR2(band, (i << 2))); 1895 mib->ba_miss_cnt += FIELD_GET(GENMASK(15, 0), val); 1896 mib->ba_miss_cnt += FIELD_GET(GENMASK(31, 16), val); 1897 1898 /* ack fail count */ 1899 val = mt76_rr(dev, MT_MIB_MB_BFTF(band, (i << 2))); 1900 mib->ack_fail_cnt += FIELD_GET(GENMASK(15, 0), val); 1901 mib->ack_fail_cnt += FIELD_GET(GENMASK(31, 16), val); 1902 } 1903 1904 for (i = 0; i < 8; i++) { 1905 val = mt76_rr(dev, MT_TX_AGG_CNT(band, i)); 1906 phy->mt76->aggr_stats[aggr0++] += FIELD_GET(GENMASK(15, 0), val); 1907 phy->mt76->aggr_stats[aggr0++] += FIELD_GET(GENMASK(31, 16), val); 1908 } 1909 1910 cnt = mt76_rr(dev, MT_MIB_SDR32(band)); 1911 mib->tx_pkt_ibf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_IBF_CNT, cnt); 1912 mib->tx_bf_ibf_ppdu_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_IBF_CNT, cnt); 1913 mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt); 1914 mib->tx_bf_ebf_ppdu_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt); 1915 1916 cnt = mt76_rr(dev, MT_MIB_BFCR7(band)); 1917 mib->tx_bf_fb_cpl_cnt += FIELD_GET(MT_MIB_BFCR7_BFEE_TX_FB_CPL, cnt); 1918 1919 cnt = mt76_rr(dev, MT_MIB_BFCR2(band)); 1920 mib->tx_bf_fb_trig_cnt += FIELD_GET(MT_MIB_BFCR2_BFEE_TX_FB_TRIG, cnt); 1921 1922 cnt = mt76_rr(dev, MT_MIB_BFCR0(band)); 1923 mib->tx_bf_rx_fb_vht_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_VHT, cnt); 1924 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_VHT, cnt); 1925 mib->tx_bf_rx_fb_ht_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_HT, cnt); 1926 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_HT, cnt); 1927 1928 cnt = mt76_rr(dev, MT_MIB_BFCR1(band)); 1929 mib->tx_bf_rx_fb_he_cnt += FIELD_GET(MT_MIB_BFCR1_RX_FB_HE, cnt); 1930 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR1_RX_FB_HE, cnt); 1931 } 1932 } 1933 1934 static void mt7915_mac_severe_check(struct mt7915_phy *phy) 1935 { 1936 struct mt7915_dev *dev = phy->dev; 1937 u32 trb, ple_err; 1938 1939 if (!phy->omac_mask) 1940 return; 1941 1942 /* In rare cases, TRB pointers might be out of sync leads to RMAC 1943 * stopping Rx, so check status periodically to see if TRB hardware 1944 * requires minimal recovery. 1945 */ 1946 trb = mt76_rr(dev, MT_TRB_RXPSR0(phy->mt76->band_idx)); 1947 1948 if ((FIELD_GET(MT_TRB_RXPSR0_RX_RMAC_PTR, trb) != 1949 FIELD_GET(MT_TRB_RXPSR0_RX_WTBL_PTR, trb)) && 1950 (FIELD_GET(MT_TRB_RXPSR0_RX_RMAC_PTR, phy->trb_ts) != 1951 FIELD_GET(MT_TRB_RXPSR0_RX_WTBL_PTR, phy->trb_ts)) && 1952 trb == phy->trb_ts) 1953 mt7915_mcu_set_ser(dev, SER_RECOVER, SER_SET_RECOVER_L3_RX_ABORT, 1954 phy->mt76->band_idx); 1955 1956 phy->trb_ts = trb; 1957 1958 ple_err = mt76_rr(dev, MT_SWDEF_PLE1_STATS); 1959 if ((ple_err & MT_SWDEF_PLE1_MDP_RIOC_HANG_ERR) && 1960 !(dev->ple1_sts & MT_SWDEF_PLE1_MDP_RIOC_HANG_ERR)) { 1961 dev_warn(dev->mt76.dev, 1962 "band%d: PLE error 0x%x detected, triggering L1 SER\n", 1963 phy->mt76->band_idx, ple_err); 1964 mt7915_mcu_set_ser(dev, SER_RECOVER, SER_SET_RECOVER_L1, 1965 phy->mt76->band_idx); 1966 } 1967 dev->ple1_sts = ple_err; 1968 } 1969 1970 void mt7915_mac_sta_rc_work(struct work_struct *work) 1971 { 1972 struct mt7915_dev *dev = container_of(work, struct mt7915_dev, rc_work); 1973 struct ieee80211_sta *sta; 1974 struct ieee80211_vif *vif; 1975 struct mt7915_sta *msta; 1976 u32 changed; 1977 LIST_HEAD(list); 1978 1979 spin_lock_bh(&dev->mt76.sta_poll_lock); 1980 list_splice_init(&dev->sta_rc_list, &list); 1981 1982 while (!list_empty(&list)) { 1983 msta = list_first_entry(&list, struct mt7915_sta, rc_list); 1984 list_del_init(&msta->rc_list); 1985 changed = msta->changed; 1986 msta->changed = 0; 1987 spin_unlock_bh(&dev->mt76.sta_poll_lock); 1988 1989 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv); 1990 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); 1991 1992 if (changed & (IEEE80211_RC_SUPP_RATES_CHANGED | 1993 IEEE80211_RC_NSS_CHANGED | 1994 IEEE80211_RC_BW_CHANGED)) 1995 mt7915_mcu_add_rate_ctrl(dev, vif, sta, true); 1996 1997 if (changed & IEEE80211_RC_SMPS_CHANGED) 1998 mt7915_mcu_add_smps(dev, vif, sta); 1999 2000 spin_lock_bh(&dev->mt76.sta_poll_lock); 2001 } 2002 2003 spin_unlock_bh(&dev->mt76.sta_poll_lock); 2004 } 2005 2006 void mt7915_mac_work(struct work_struct *work) 2007 { 2008 struct mt7915_phy *phy; 2009 struct mt76_phy *mphy; 2010 2011 mphy = (struct mt76_phy *)container_of(work, struct mt76_phy, 2012 mac_work.work); 2013 phy = mphy->priv; 2014 2015 mutex_lock(&mphy->dev->mutex); 2016 2017 mt76_update_survey(mphy); 2018 if (++mphy->mac_work_count == 5) { 2019 mphy->mac_work_count = 0; 2020 2021 mt7915_mac_update_stats(phy); 2022 mt7915_mac_severe_check(phy); 2023 2024 if (phy->dev->muru_debug) 2025 mt7915_mcu_muru_debug_get(phy); 2026 } 2027 2028 mutex_unlock(&mphy->dev->mutex); 2029 2030 mt76_tx_status_check(mphy->dev, false); 2031 2032 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, 2033 MT7915_WATCHDOG_TIME); 2034 } 2035 2036 static void mt7915_dfs_stop_radar_detector(struct mt7915_phy *phy) 2037 { 2038 struct mt7915_dev *dev = phy->dev; 2039 int rdd_idx = mt7915_get_rdd_idx(phy, false); 2040 2041 if (rdd_idx < 0) 2042 return; 2043 2044 mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_STOP, rdd_idx, 0, 0); 2045 } 2046 2047 static int mt7915_dfs_start_rdd(struct mt7915_dev *dev, int rdd_idx) 2048 { 2049 int err, region; 2050 2051 switch (dev->mt76.region) { 2052 case NL80211_DFS_ETSI: 2053 region = 0; 2054 break; 2055 case NL80211_DFS_JP: 2056 region = 2; 2057 break; 2058 case NL80211_DFS_FCC: 2059 default: 2060 region = 1; 2061 break; 2062 } 2063 2064 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_START, rdd_idx, 0, region); 2065 if (err < 0) 2066 return err; 2067 2068 if (is_mt7915(&dev->mt76)) { 2069 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_SET_WF_ANT, rdd_idx, 2070 0, dev->dbdc_support ? 2 : 0); 2071 if (err < 0) 2072 return err; 2073 } 2074 2075 return mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_DET_MODE, rdd_idx, 0, 1); 2076 } 2077 2078 static int mt7915_dfs_start_radar_detector(struct mt7915_phy *phy) 2079 { 2080 struct mt7915_dev *dev = phy->dev; 2081 int err, rdd_idx; 2082 2083 rdd_idx = mt7915_get_rdd_idx(phy, false); 2084 if (rdd_idx < 0) 2085 return -EINVAL; 2086 2087 /* start CAC */ 2088 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_START, rdd_idx, 0, 0); 2089 if (err < 0) 2090 return err; 2091 2092 err = mt7915_dfs_start_rdd(dev, rdd_idx); 2093 if (err < 0) 2094 return err; 2095 2096 return 0; 2097 } 2098 2099 static int 2100 mt7915_dfs_init_radar_specs(struct mt7915_phy *phy) 2101 { 2102 const struct mt7915_dfs_radar_spec *radar_specs; 2103 struct mt7915_dev *dev = phy->dev; 2104 int err, i; 2105 2106 switch (dev->mt76.region) { 2107 case NL80211_DFS_FCC: 2108 radar_specs = &fcc_radar_specs; 2109 err = mt7915_mcu_set_fcc5_lpn(dev, 8); 2110 if (err < 0) 2111 return err; 2112 break; 2113 case NL80211_DFS_ETSI: 2114 radar_specs = &etsi_radar_specs; 2115 break; 2116 case NL80211_DFS_JP: 2117 radar_specs = &jp_radar_specs; 2118 break; 2119 default: 2120 return -EINVAL; 2121 } 2122 2123 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) { 2124 err = mt7915_mcu_set_radar_th(dev, i, 2125 &radar_specs->radar_pattern[i]); 2126 if (err < 0) 2127 return err; 2128 } 2129 2130 return mt7915_mcu_set_pulse_th(dev, &radar_specs->pulse_th); 2131 } 2132 2133 int mt7915_dfs_init_radar_detector(struct mt7915_phy *phy) 2134 { 2135 struct mt7915_dev *dev = phy->dev; 2136 enum mt76_dfs_state dfs_state, prev_state; 2137 int err, rdd_idx = mt7915_get_rdd_idx(phy, false); 2138 2139 prev_state = phy->mt76->dfs_state; 2140 dfs_state = mt76_phy_dfs_state(phy->mt76); 2141 2142 if (prev_state == dfs_state || rdd_idx < 0) 2143 return 0; 2144 2145 if (prev_state == MT_DFS_STATE_UNKNOWN) 2146 mt7915_dfs_stop_radar_detector(phy); 2147 2148 if (dfs_state == MT_DFS_STATE_DISABLED) 2149 goto stop; 2150 2151 if (prev_state <= MT_DFS_STATE_DISABLED) { 2152 err = mt7915_dfs_init_radar_specs(phy); 2153 if (err < 0) 2154 return err; 2155 2156 err = mt7915_dfs_start_radar_detector(phy); 2157 if (err < 0) 2158 return err; 2159 2160 phy->mt76->dfs_state = MT_DFS_STATE_CAC; 2161 } 2162 2163 if (dfs_state == MT_DFS_STATE_CAC) 2164 return 0; 2165 2166 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_END, rdd_idx, 0, 0); 2167 if (err < 0) { 2168 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN; 2169 return err; 2170 } 2171 2172 phy->mt76->dfs_state = MT_DFS_STATE_ACTIVE; 2173 return 0; 2174 2175 stop: 2176 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_NORMAL_START, rdd_idx, 0, 0); 2177 if (err < 0) 2178 return err; 2179 2180 if (is_mt7915(&dev->mt76)) { 2181 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_SET_WF_ANT, 2182 rdd_idx, 0, dev->dbdc_support ? 2 : 0); 2183 if (err < 0) 2184 return err; 2185 } 2186 2187 mt7915_dfs_stop_radar_detector(phy); 2188 phy->mt76->dfs_state = MT_DFS_STATE_DISABLED; 2189 2190 return 0; 2191 } 2192 2193 static int 2194 mt7915_mac_twt_duration_align(int duration) 2195 { 2196 return duration << 8; 2197 } 2198 2199 static u64 2200 mt7915_mac_twt_sched_list_add(struct mt7915_dev *dev, 2201 struct mt7915_twt_flow *flow) 2202 { 2203 struct mt7915_twt_flow *iter, *iter_next; 2204 u32 duration = flow->duration << 8; 2205 u64 start_tsf; 2206 2207 iter = list_first_entry_or_null(&dev->twt_list, 2208 struct mt7915_twt_flow, list); 2209 if (!iter || !iter->sched || iter->start_tsf > duration) { 2210 /* add flow as first entry in the list */ 2211 list_add(&flow->list, &dev->twt_list); 2212 return 0; 2213 } 2214 2215 list_for_each_entry_safe(iter, iter_next, &dev->twt_list, list) { 2216 start_tsf = iter->start_tsf + 2217 mt7915_mac_twt_duration_align(iter->duration); 2218 if (list_is_last(&iter->list, &dev->twt_list)) 2219 break; 2220 2221 if (!iter_next->sched || 2222 iter_next->start_tsf > start_tsf + duration) { 2223 list_add(&flow->list, &iter->list); 2224 goto out; 2225 } 2226 } 2227 2228 /* add flow as last entry in the list */ 2229 list_add_tail(&flow->list, &dev->twt_list); 2230 out: 2231 return start_tsf; 2232 } 2233 2234 static int mt7915_mac_check_twt_req(struct ieee80211_twt_setup *twt) 2235 { 2236 struct ieee80211_twt_params *twt_agrt; 2237 u64 interval, duration; 2238 u16 mantissa; 2239 u8 exp; 2240 2241 /* only individual agreement supported */ 2242 if (twt->control & IEEE80211_TWT_CONTROL_NEG_TYPE_BROADCAST) 2243 return -EOPNOTSUPP; 2244 2245 /* only 256us unit supported */ 2246 if (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT) 2247 return -EOPNOTSUPP; 2248 2249 twt_agrt = (struct ieee80211_twt_params *)twt->params; 2250 2251 /* explicit agreement not supported */ 2252 if (!(twt_agrt->req_type & cpu_to_le16(IEEE80211_TWT_REQTYPE_IMPLICIT))) 2253 return -EOPNOTSUPP; 2254 2255 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, 2256 le16_to_cpu(twt_agrt->req_type)); 2257 mantissa = le16_to_cpu(twt_agrt->mantissa); 2258 duration = twt_agrt->min_twt_dur << 8; 2259 2260 interval = (u64)mantissa << exp; 2261 if (interval < duration) 2262 return -EOPNOTSUPP; 2263 2264 return 0; 2265 } 2266 2267 static bool 2268 mt7915_mac_twt_param_equal(struct mt7915_sta *msta, 2269 struct ieee80211_twt_params *twt_agrt) 2270 { 2271 u16 type = le16_to_cpu(twt_agrt->req_type); 2272 u8 exp; 2273 int i; 2274 2275 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, type); 2276 for (i = 0; i < MT7915_MAX_STA_TWT_AGRT; i++) { 2277 struct mt7915_twt_flow *f; 2278 2279 if (!(msta->twt.flowid_mask & BIT(i))) 2280 continue; 2281 2282 f = &msta->twt.flow[i]; 2283 if (f->duration == twt_agrt->min_twt_dur && 2284 f->mantissa == twt_agrt->mantissa && 2285 f->exp == exp && 2286 f->protection == !!(type & IEEE80211_TWT_REQTYPE_PROTECTION) && 2287 f->flowtype == !!(type & IEEE80211_TWT_REQTYPE_FLOWTYPE) && 2288 f->trigger == !!(type & IEEE80211_TWT_REQTYPE_TRIGGER)) 2289 return true; 2290 } 2291 2292 return false; 2293 } 2294 2295 void mt7915_mac_add_twt_setup(struct ieee80211_hw *hw, 2296 struct ieee80211_sta *sta, 2297 struct ieee80211_twt_setup *twt) 2298 { 2299 enum ieee80211_twt_setup_cmd setup_cmd = TWT_SETUP_CMD_REJECT; 2300 struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv; 2301 struct ieee80211_twt_params *twt_agrt = (void *)twt->params; 2302 u16 req_type = le16_to_cpu(twt_agrt->req_type); 2303 enum ieee80211_twt_setup_cmd sta_setup_cmd; 2304 struct mt7915_dev *dev = mt7915_hw_dev(hw); 2305 struct mt7915_twt_flow *flow; 2306 int flowid, table_id; 2307 u8 exp; 2308 2309 if (mt7915_mac_check_twt_req(twt)) 2310 goto out; 2311 2312 mutex_lock(&dev->mt76.mutex); 2313 2314 if (dev->twt.n_agrt == MT7915_MAX_TWT_AGRT) 2315 goto unlock; 2316 2317 if (hweight8(msta->twt.flowid_mask) == ARRAY_SIZE(msta->twt.flow)) 2318 goto unlock; 2319 2320 if (twt_agrt->min_twt_dur < MT7915_MIN_TWT_DUR) { 2321 setup_cmd = TWT_SETUP_CMD_DICTATE; 2322 twt_agrt->min_twt_dur = MT7915_MIN_TWT_DUR; 2323 goto unlock; 2324 } 2325 2326 flowid = ffs(~msta->twt.flowid_mask) - 1; 2327 twt_agrt->req_type &= ~cpu_to_le16(IEEE80211_TWT_REQTYPE_FLOWID); 2328 twt_agrt->req_type |= le16_encode_bits(flowid, 2329 IEEE80211_TWT_REQTYPE_FLOWID); 2330 2331 table_id = ffs(~dev->twt.table_mask) - 1; 2332 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, req_type); 2333 sta_setup_cmd = FIELD_GET(IEEE80211_TWT_REQTYPE_SETUP_CMD, req_type); 2334 2335 if (mt7915_mac_twt_param_equal(msta, twt_agrt)) 2336 goto unlock; 2337 2338 flow = &msta->twt.flow[flowid]; 2339 memset(flow, 0, sizeof(*flow)); 2340 INIT_LIST_HEAD(&flow->list); 2341 flow->wcid = msta->wcid.idx; 2342 flow->table_id = table_id; 2343 flow->id = flowid; 2344 flow->duration = twt_agrt->min_twt_dur; 2345 flow->mantissa = twt_agrt->mantissa; 2346 flow->exp = exp; 2347 flow->protection = !!(req_type & IEEE80211_TWT_REQTYPE_PROTECTION); 2348 flow->flowtype = !!(req_type & IEEE80211_TWT_REQTYPE_FLOWTYPE); 2349 flow->trigger = !!(req_type & IEEE80211_TWT_REQTYPE_TRIGGER); 2350 2351 if (sta_setup_cmd == TWT_SETUP_CMD_REQUEST || 2352 sta_setup_cmd == TWT_SETUP_CMD_SUGGEST) { 2353 u64 interval = (u64)le16_to_cpu(twt_agrt->mantissa) << exp; 2354 u64 flow_tsf, curr_tsf; 2355 u32 rem; 2356 2357 flow->sched = true; 2358 flow->start_tsf = mt7915_mac_twt_sched_list_add(dev, flow); 2359 curr_tsf = __mt7915_get_tsf(hw, msta->vif); 2360 div_u64_rem(curr_tsf - flow->start_tsf, interval, &rem); 2361 flow_tsf = curr_tsf + interval - rem; 2362 twt_agrt->twt = cpu_to_le64(flow_tsf); 2363 } else { 2364 list_add_tail(&flow->list, &dev->twt_list); 2365 } 2366 flow->tsf = le64_to_cpu(twt_agrt->twt); 2367 2368 if (mt7915_mcu_twt_agrt_update(dev, msta->vif, flow, MCU_TWT_AGRT_ADD)) { 2369 list_del(&flow->list); 2370 goto unlock; 2371 } 2372 2373 setup_cmd = TWT_SETUP_CMD_ACCEPT; 2374 dev->twt.table_mask |= BIT(table_id); 2375 msta->twt.flowid_mask |= BIT(flowid); 2376 dev->twt.n_agrt++; 2377 2378 unlock: 2379 mutex_unlock(&dev->mt76.mutex); 2380 out: 2381 twt_agrt->req_type &= ~cpu_to_le16(IEEE80211_TWT_REQTYPE_SETUP_CMD); 2382 twt_agrt->req_type |= 2383 le16_encode_bits(setup_cmd, IEEE80211_TWT_REQTYPE_SETUP_CMD); 2384 twt->control = (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT) | 2385 (twt->control & IEEE80211_TWT_CONTROL_RX_DISABLED); 2386 } 2387 2388 void mt7915_mac_twt_teardown_flow(struct mt7915_dev *dev, 2389 struct mt7915_sta *msta, 2390 u8 flowid) 2391 { 2392 struct mt7915_twt_flow *flow; 2393 2394 lockdep_assert_held(&dev->mt76.mutex); 2395 2396 if (flowid >= ARRAY_SIZE(msta->twt.flow)) 2397 return; 2398 2399 if (!(msta->twt.flowid_mask & BIT(flowid))) 2400 return; 2401 2402 flow = &msta->twt.flow[flowid]; 2403 if (mt7915_mcu_twt_agrt_update(dev, msta->vif, flow, 2404 MCU_TWT_AGRT_DELETE)) 2405 return; 2406 2407 list_del_init(&flow->list); 2408 msta->twt.flowid_mask &= ~BIT(flowid); 2409 dev->twt.table_mask &= ~BIT(flow->table_id); 2410 dev->twt.n_agrt--; 2411 } 2412