1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include <linux/etherdevice.h> 5 #include <linux/timekeeping.h> 6 #include "coredump.h" 7 #include "mt7915.h" 8 #include "../dma.h" 9 #include "mac.h" 10 #include "mcu.h" 11 12 #define to_rssi(field, rcpi) ((FIELD_GET(field, rcpi) - 220) / 2) 13 14 static const struct mt7915_dfs_radar_spec etsi_radar_specs = { 15 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 16 .radar_pattern = { 17 [5] = { 1, 0, 6, 32, 28, 0, 990, 5010, 17, 1, 1 }, 18 [6] = { 1, 0, 9, 32, 28, 0, 615, 5010, 27, 1, 1 }, 19 [7] = { 1, 0, 15, 32, 28, 0, 240, 445, 27, 1, 1 }, 20 [8] = { 1, 0, 12, 32, 28, 0, 240, 510, 42, 1, 1 }, 21 [9] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 12, 32, 28, { }, 126 }, 22 [10] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 15, 32, 24, { }, 126 }, 23 [11] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 18, 32, 28, { }, 54 }, 24 [12] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 27, 32, 24, { }, 54 }, 25 }, 26 }; 27 28 static const struct mt7915_dfs_radar_spec fcc_radar_specs = { 29 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 30 .radar_pattern = { 31 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 }, 32 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 }, 33 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 }, 34 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 }, 35 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 }, 36 }, 37 }; 38 39 static const struct mt7915_dfs_radar_spec jp_radar_specs = { 40 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 41 .radar_pattern = { 42 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 }, 43 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 }, 44 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 }, 45 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 }, 46 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 }, 47 [13] = { 1, 0, 7, 32, 28, 0, 3836, 3856, 14, 1, 1 }, 48 [14] = { 1, 0, 6, 32, 28, 0, 615, 5010, 110, 1, 1 }, 49 [15] = { 1, 1, 0, 0, 0, 0, 15, 5010, 110, 0, 0, 12, 32, 28 }, 50 }, 51 }; 52 53 static struct mt76_wcid *mt7915_rx_get_wcid(struct mt7915_dev *dev, 54 u16 idx, bool unicast) 55 { 56 struct mt7915_sta *sta; 57 struct mt76_wcid *wcid; 58 59 if (idx >= ARRAY_SIZE(dev->mt76.wcid)) 60 return NULL; 61 62 wcid = rcu_dereference(dev->mt76.wcid[idx]); 63 if (unicast || !wcid) 64 return wcid; 65 66 if (!wcid->sta) 67 return NULL; 68 69 sta = container_of(wcid, struct mt7915_sta, wcid); 70 if (!sta->vif) 71 return NULL; 72 73 return &sta->vif->sta.wcid; 74 } 75 76 bool mt7915_mac_wtbl_update(struct mt7915_dev *dev, int idx, u32 mask) 77 { 78 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX, 79 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask); 80 81 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 82 0, 5000); 83 } 84 85 u32 mt7915_mac_wtbl_lmac_addr(struct mt7915_dev *dev, u16 wcid, u8 dw) 86 { 87 mt76_wr(dev, MT_WTBLON_TOP_WDUCR, 88 FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (wcid >> 7))); 89 90 return MT_WTBL_LMAC_OFFS(wcid, dw); 91 } 92 93 static void mt7915_mac_sta_poll(struct mt7915_dev *dev) 94 { 95 static const u8 ac_to_tid[] = { 96 [IEEE80211_AC_BE] = 0, 97 [IEEE80211_AC_BK] = 1, 98 [IEEE80211_AC_VI] = 4, 99 [IEEE80211_AC_VO] = 6 100 }; 101 struct ieee80211_sta *sta; 102 struct mt7915_sta *msta; 103 struct rate_info *rate; 104 u32 tx_time[IEEE80211_NUM_ACS], rx_time[IEEE80211_NUM_ACS]; 105 LIST_HEAD(sta_poll_list); 106 int i; 107 108 spin_lock_bh(&dev->mt76.sta_poll_lock); 109 list_splice_init(&dev->mt76.sta_poll_list, &sta_poll_list); 110 spin_unlock_bh(&dev->mt76.sta_poll_lock); 111 112 rcu_read_lock(); 113 114 while (true) { 115 bool clear = false; 116 u32 addr, val; 117 u16 idx; 118 s8 rssi[4]; 119 u8 bw; 120 121 spin_lock_bh(&dev->mt76.sta_poll_lock); 122 if (list_empty(&sta_poll_list)) { 123 spin_unlock_bh(&dev->mt76.sta_poll_lock); 124 break; 125 } 126 msta = list_first_entry(&sta_poll_list, 127 struct mt7915_sta, wcid.poll_list); 128 list_del_init(&msta->wcid.poll_list); 129 spin_unlock_bh(&dev->mt76.sta_poll_lock); 130 131 idx = msta->wcid.idx; 132 133 /* refresh peer's airtime reporting */ 134 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 20); 135 136 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 137 u32 tx_last = msta->airtime_ac[i]; 138 u32 rx_last = msta->airtime_ac[i + 4]; 139 140 msta->airtime_ac[i] = mt76_rr(dev, addr); 141 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4); 142 143 if (msta->airtime_ac[i] <= tx_last) 144 tx_time[i] = 0; 145 else 146 tx_time[i] = msta->airtime_ac[i] - tx_last; 147 148 if (msta->airtime_ac[i + 4] <= rx_last) 149 rx_time[i] = 0; 150 else 151 rx_time[i] = msta->airtime_ac[i + 4] - rx_last; 152 153 if ((tx_last | rx_last) & BIT(30)) 154 clear = true; 155 156 addr += 8; 157 } 158 159 if (clear) { 160 mt7915_mac_wtbl_update(dev, idx, 161 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 162 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac)); 163 } 164 165 if (!msta->wcid.sta) 166 continue; 167 168 sta = container_of((void *)msta, struct ieee80211_sta, 169 drv_priv); 170 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 171 u8 queue = mt76_connac_lmac_mapping(i); 172 u32 tx_cur = tx_time[queue]; 173 u32 rx_cur = rx_time[queue]; 174 u8 tid = ac_to_tid[i]; 175 176 if (!tx_cur && !rx_cur) 177 continue; 178 179 ieee80211_sta_register_airtime(sta, tid, tx_cur, 180 rx_cur); 181 } 182 183 /* 184 * We don't support reading GI info from txs packets. 185 * For accurate tx status reporting and AQL improvement, 186 * we need to make sure that flags match so polling GI 187 * from per-sta counters directly. 188 */ 189 rate = &msta->wcid.rate; 190 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 7); 191 val = mt76_rr(dev, addr); 192 193 switch (rate->bw) { 194 case RATE_INFO_BW_160: 195 bw = IEEE80211_STA_RX_BW_160; 196 break; 197 case RATE_INFO_BW_80: 198 bw = IEEE80211_STA_RX_BW_80; 199 break; 200 case RATE_INFO_BW_40: 201 bw = IEEE80211_STA_RX_BW_40; 202 break; 203 default: 204 bw = IEEE80211_STA_RX_BW_20; 205 break; 206 } 207 208 if (rate->flags & RATE_INFO_FLAGS_HE_MCS) { 209 u8 offs = 24 + 2 * bw; 210 211 rate->he_gi = (val & (0x3 << offs)) >> offs; 212 } else if (rate->flags & 213 (RATE_INFO_FLAGS_VHT_MCS | RATE_INFO_FLAGS_MCS)) { 214 if (val & BIT(12 + bw)) 215 rate->flags |= RATE_INFO_FLAGS_SHORT_GI; 216 else 217 rate->flags &= ~RATE_INFO_FLAGS_SHORT_GI; 218 } 219 220 /* get signal strength of resp frames (CTS/BA/ACK) */ 221 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 30); 222 val = mt76_rr(dev, addr); 223 224 rssi[0] = to_rssi(GENMASK(7, 0), val); 225 rssi[1] = to_rssi(GENMASK(15, 8), val); 226 rssi[2] = to_rssi(GENMASK(23, 16), val); 227 rssi[3] = to_rssi(GENMASK(31, 14), val); 228 229 msta->ack_signal = 230 mt76_rx_signal(msta->vif->phy->mt76->antenna_mask, rssi); 231 232 ewma_avg_signal_add(&msta->avg_ack_signal, -msta->ack_signal); 233 } 234 235 rcu_read_unlock(); 236 } 237 238 void mt7915_mac_enable_rtscts(struct mt7915_dev *dev, 239 struct ieee80211_vif *vif, bool enable) 240 { 241 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv; 242 u32 addr; 243 244 addr = mt7915_mac_wtbl_lmac_addr(dev, mvif->sta.wcid.idx, 5); 245 if (enable) 246 mt76_set(dev, addr, BIT(5)); 247 else 248 mt76_clear(dev, addr, BIT(5)); 249 } 250 251 static void 252 mt7915_wed_check_ppe(struct mt7915_dev *dev, struct mt76_queue *q, 253 struct mt7915_sta *msta, struct sk_buff *skb, 254 u32 info) 255 { 256 struct ieee80211_vif *vif; 257 struct wireless_dev *wdev; 258 259 if (!msta || !msta->vif) 260 return; 261 262 if (!mt76_queue_is_wed_rx(q)) 263 return; 264 265 if (!(info & MT_DMA_INFO_PPE_VLD)) 266 return; 267 268 vif = container_of((void *)msta->vif, struct ieee80211_vif, 269 drv_priv); 270 wdev = ieee80211_vif_to_wdev(vif); 271 skb->dev = wdev->netdev; 272 273 mtk_wed_device_ppe_check(&dev->mt76.mmio.wed, skb, 274 FIELD_GET(MT_DMA_PPE_CPU_REASON, info), 275 FIELD_GET(MT_DMA_PPE_ENTRY, info)); 276 } 277 278 static int 279 mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb, 280 enum mt76_rxq_id q, u32 *info) 281 { 282 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 283 struct mt76_phy *mphy = &dev->mt76.phy; 284 struct mt7915_phy *phy = &dev->phy; 285 struct ieee80211_supported_band *sband; 286 __le32 *rxd = (__le32 *)skb->data; 287 __le32 *rxv = NULL; 288 u32 rxd0 = le32_to_cpu(rxd[0]); 289 u32 rxd1 = le32_to_cpu(rxd[1]); 290 u32 rxd2 = le32_to_cpu(rxd[2]); 291 u32 rxd3 = le32_to_cpu(rxd[3]); 292 u32 rxd4 = le32_to_cpu(rxd[4]); 293 u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM; 294 bool unicast, insert_ccmp_hdr = false; 295 u8 remove_pad, amsdu_info; 296 u8 mode = 0, qos_ctl = 0; 297 struct mt7915_sta *msta = NULL; 298 u32 csum_status = *(u32 *)skb->cb; 299 bool hdr_trans; 300 u16 hdr_gap; 301 u16 seq_ctrl = 0; 302 __le16 fc = 0; 303 int idx; 304 305 memset(status, 0, sizeof(*status)); 306 307 if ((rxd1 & MT_RXD1_NORMAL_BAND_IDX) && !phy->mt76->band_idx) { 308 mphy = dev->mt76.phys[MT_BAND1]; 309 if (!mphy) 310 return -EINVAL; 311 312 phy = mphy->priv; 313 status->phy_idx = 1; 314 } 315 316 if (!test_bit(MT76_STATE_RUNNING, &mphy->state)) 317 return -EINVAL; 318 319 if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR) 320 return -EINVAL; 321 322 hdr_trans = rxd2 & MT_RXD2_NORMAL_HDR_TRANS; 323 if (hdr_trans && (rxd1 & MT_RXD1_NORMAL_CM)) 324 return -EINVAL; 325 326 /* ICV error or CCMP/BIP/WPI MIC error */ 327 if (rxd1 & MT_RXD1_NORMAL_ICV_ERR) 328 status->flag |= RX_FLAG_ONLY_MONITOR; 329 330 unicast = FIELD_GET(MT_RXD3_NORMAL_ADDR_TYPE, rxd3) == MT_RXD3_NORMAL_U2M; 331 idx = FIELD_GET(MT_RXD1_NORMAL_WLAN_IDX, rxd1); 332 status->wcid = mt7915_rx_get_wcid(dev, idx, unicast); 333 334 if (status->wcid) { 335 msta = container_of(status->wcid, struct mt7915_sta, wcid); 336 mt76_wcid_add_poll(&dev->mt76, &msta->wcid); 337 } 338 339 status->freq = mphy->chandef.chan->center_freq; 340 status->band = mphy->chandef.chan->band; 341 if (status->band == NL80211_BAND_5GHZ) 342 sband = &mphy->sband_5g.sband; 343 else if (status->band == NL80211_BAND_6GHZ) 344 sband = &mphy->sband_6g.sband; 345 else 346 sband = &mphy->sband_2g.sband; 347 348 if (!sband->channels) 349 return -EINVAL; 350 351 if ((rxd0 & csum_mask) == csum_mask && 352 !(csum_status & (BIT(0) | BIT(2) | BIT(3)))) 353 skb->ip_summed = CHECKSUM_UNNECESSARY; 354 355 if (rxd1 & MT_RXD1_NORMAL_FCS_ERR) 356 status->flag |= RX_FLAG_FAILED_FCS_CRC; 357 358 if (rxd1 & MT_RXD1_NORMAL_TKIP_MIC_ERR) 359 status->flag |= RX_FLAG_MMIC_ERROR; 360 361 if (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1) != 0 && 362 !(rxd1 & (MT_RXD1_NORMAL_CLM | MT_RXD1_NORMAL_CM))) { 363 status->flag |= RX_FLAG_DECRYPTED; 364 status->flag |= RX_FLAG_IV_STRIPPED; 365 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED; 366 } 367 368 remove_pad = FIELD_GET(MT_RXD2_NORMAL_HDR_OFFSET, rxd2); 369 370 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR) 371 return -EINVAL; 372 373 rxd += 6; 374 if (rxd1 & MT_RXD1_NORMAL_GROUP_4) { 375 u32 v0 = le32_to_cpu(rxd[0]); 376 u32 v2 = le32_to_cpu(rxd[2]); 377 378 fc = cpu_to_le16(FIELD_GET(MT_RXD6_FRAME_CONTROL, v0)); 379 qos_ctl = FIELD_GET(MT_RXD8_QOS_CTL, v2); 380 seq_ctrl = FIELD_GET(MT_RXD8_SEQ_CTRL, v2); 381 382 rxd += 4; 383 if ((u8 *)rxd - skb->data >= skb->len) 384 return -EINVAL; 385 } 386 387 if (rxd1 & MT_RXD1_NORMAL_GROUP_1) { 388 u8 *data = (u8 *)rxd; 389 390 if (status->flag & RX_FLAG_DECRYPTED) { 391 switch (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1)) { 392 case MT_CIPHER_AES_CCMP: 393 case MT_CIPHER_CCMP_CCX: 394 case MT_CIPHER_CCMP_256: 395 insert_ccmp_hdr = 396 FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2); 397 fallthrough; 398 case MT_CIPHER_TKIP: 399 case MT_CIPHER_TKIP_NO_MIC: 400 case MT_CIPHER_GCMP: 401 case MT_CIPHER_GCMP_256: 402 status->iv[0] = data[5]; 403 status->iv[1] = data[4]; 404 status->iv[2] = data[3]; 405 status->iv[3] = data[2]; 406 status->iv[4] = data[1]; 407 status->iv[5] = data[0]; 408 break; 409 default: 410 break; 411 } 412 } 413 rxd += 4; 414 if ((u8 *)rxd - skb->data >= skb->len) 415 return -EINVAL; 416 } 417 418 if (rxd1 & MT_RXD1_NORMAL_GROUP_2) { 419 status->timestamp = le32_to_cpu(rxd[0]); 420 status->flag |= RX_FLAG_MACTIME_START; 421 422 if (!(rxd2 & MT_RXD2_NORMAL_NON_AMPDU)) { 423 status->flag |= RX_FLAG_AMPDU_DETAILS; 424 425 /* all subframes of an A-MPDU have the same timestamp */ 426 if (phy->rx_ampdu_ts != status->timestamp) { 427 if (!++phy->ampdu_ref) 428 phy->ampdu_ref++; 429 } 430 phy->rx_ampdu_ts = status->timestamp; 431 432 status->ampdu_ref = phy->ampdu_ref; 433 } 434 435 rxd += 2; 436 if ((u8 *)rxd - skb->data >= skb->len) 437 return -EINVAL; 438 } 439 440 /* RXD Group 3 - P-RXV */ 441 if (rxd1 & MT_RXD1_NORMAL_GROUP_3) { 442 u32 v0, v1; 443 int ret; 444 445 rxv = rxd; 446 rxd += 2; 447 if ((u8 *)rxd - skb->data >= skb->len) 448 return -EINVAL; 449 450 v0 = le32_to_cpu(rxv[0]); 451 v1 = le32_to_cpu(rxv[1]); 452 453 if (v0 & MT_PRXV_HT_AD_CODE) 454 status->enc_flags |= RX_ENC_FLAG_LDPC; 455 456 status->chains = mphy->antenna_mask; 457 status->chain_signal[0] = to_rssi(MT_PRXV_RCPI0, v1); 458 status->chain_signal[1] = to_rssi(MT_PRXV_RCPI1, v1); 459 status->chain_signal[2] = to_rssi(MT_PRXV_RCPI2, v1); 460 status->chain_signal[3] = to_rssi(MT_PRXV_RCPI3, v1); 461 462 /* RXD Group 5 - C-RXV */ 463 if (rxd1 & MT_RXD1_NORMAL_GROUP_5) { 464 rxd += 18; 465 if ((u8 *)rxd - skb->data >= skb->len) 466 return -EINVAL; 467 } 468 469 if (!is_mt7915(&dev->mt76) || (rxd1 & MT_RXD1_NORMAL_GROUP_5)) { 470 ret = mt76_connac2_mac_fill_rx_rate(&dev->mt76, status, 471 sband, rxv, &mode); 472 if (ret < 0) 473 return ret; 474 } 475 } 476 477 amsdu_info = FIELD_GET(MT_RXD4_NORMAL_PAYLOAD_FORMAT, rxd4); 478 status->amsdu = !!amsdu_info; 479 if (status->amsdu) { 480 status->first_amsdu = amsdu_info == MT_RXD4_FIRST_AMSDU_FRAME; 481 status->last_amsdu = amsdu_info == MT_RXD4_LAST_AMSDU_FRAME; 482 } 483 484 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad; 485 if (hdr_trans && ieee80211_has_morefrags(fc)) { 486 struct ieee80211_vif *vif; 487 int err; 488 489 if (!msta || !msta->vif) 490 return -EINVAL; 491 492 vif = container_of((void *)msta->vif, struct ieee80211_vif, 493 drv_priv); 494 err = mt76_connac2_reverse_frag0_hdr_trans(vif, skb, hdr_gap); 495 if (err) 496 return err; 497 498 hdr_trans = false; 499 } else { 500 int pad_start = 0; 501 502 skb_pull(skb, hdr_gap); 503 if (!hdr_trans && status->amsdu) { 504 pad_start = ieee80211_get_hdrlen_from_skb(skb); 505 } else if (hdr_trans && (rxd2 & MT_RXD2_NORMAL_HDR_TRANS_ERROR)) { 506 /* 507 * When header translation failure is indicated, 508 * the hardware will insert an extra 2-byte field 509 * containing the data length after the protocol 510 * type field. This happens either when the LLC-SNAP 511 * pattern did not match, or if a VLAN header was 512 * detected. 513 */ 514 pad_start = 12; 515 if (get_unaligned_be16(skb->data + pad_start) == ETH_P_8021Q) 516 pad_start += 4; 517 else 518 pad_start = 0; 519 } 520 521 if (pad_start) { 522 memmove(skb->data + 2, skb->data, pad_start); 523 skb_pull(skb, 2); 524 } 525 } 526 527 if (!hdr_trans) { 528 struct ieee80211_hdr *hdr; 529 530 if (insert_ccmp_hdr) { 531 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1); 532 533 mt76_insert_ccmp_hdr(skb, key_id); 534 } 535 536 hdr = mt76_skb_get_hdr(skb); 537 fc = hdr->frame_control; 538 if (ieee80211_is_data_qos(fc)) { 539 seq_ctrl = le16_to_cpu(hdr->seq_ctrl); 540 qos_ctl = *ieee80211_get_qos_ctl(hdr); 541 } 542 } else { 543 status->flag |= RX_FLAG_8023; 544 mt7915_wed_check_ppe(dev, &dev->mt76.q_rx[q], msta, skb, 545 *info); 546 } 547 548 if (rxv && mode >= MT_PHY_TYPE_HE_SU && !(status->flag & RX_FLAG_8023)) 549 mt76_connac2_mac_decode_he_radiotap(&dev->mt76, skb, rxv, mode); 550 551 if (!status->wcid || !ieee80211_is_data_qos(fc)) 552 return 0; 553 554 status->aggr = unicast && 555 !ieee80211_is_qos_nullfunc(fc); 556 status->qos_ctl = qos_ctl; 557 status->seqno = IEEE80211_SEQ_TO_SN(seq_ctrl); 558 559 return 0; 560 } 561 562 static void 563 mt7915_mac_fill_rx_vector(struct mt7915_dev *dev, struct sk_buff *skb) 564 { 565 #ifdef CONFIG_NL80211_TESTMODE 566 struct mt7915_phy *phy = &dev->phy; 567 __le32 *rxd = (__le32 *)skb->data; 568 __le32 *rxv_hdr = rxd + 2; 569 __le32 *rxv = rxd + 4; 570 u32 rcpi, ib_rssi, wb_rssi, v20, v21; 571 u8 band_idx; 572 s32 foe; 573 u8 snr; 574 int i; 575 576 band_idx = le32_get_bits(rxv_hdr[1], MT_RXV_HDR_BAND_IDX); 577 if (band_idx && !phy->mt76->band_idx) { 578 phy = mt7915_ext_phy(dev); 579 if (!phy) 580 goto out; 581 } 582 583 rcpi = le32_to_cpu(rxv[6]); 584 ib_rssi = le32_to_cpu(rxv[7]); 585 wb_rssi = le32_to_cpu(rxv[8]) >> 5; 586 587 for (i = 0; i < 4; i++, rcpi >>= 8, ib_rssi >>= 8, wb_rssi >>= 9) { 588 if (i == 3) 589 wb_rssi = le32_to_cpu(rxv[9]); 590 591 phy->test.last_rcpi[i] = rcpi & 0xff; 592 phy->test.last_ib_rssi[i] = ib_rssi & 0xff; 593 phy->test.last_wb_rssi[i] = wb_rssi & 0xff; 594 } 595 596 v20 = le32_to_cpu(rxv[20]); 597 v21 = le32_to_cpu(rxv[21]); 598 599 foe = FIELD_GET(MT_CRXV_FOE_LO, v20) | 600 (FIELD_GET(MT_CRXV_FOE_HI, v21) << MT_CRXV_FOE_SHIFT); 601 602 snr = FIELD_GET(MT_CRXV_SNR, v20) - 16; 603 604 phy->test.last_freq_offset = foe; 605 phy->test.last_snr = snr; 606 out: 607 #endif 608 dev_kfree_skb(skb); 609 } 610 611 static void 612 mt7915_mac_write_txwi_tm(struct mt7915_phy *phy, __le32 *txwi, 613 struct sk_buff *skb) 614 { 615 #ifdef CONFIG_NL80211_TESTMODE 616 struct mt76_testmode_data *td = &phy->mt76->test; 617 const struct ieee80211_rate *r; 618 u8 bw, mode, nss = td->tx_rate_nss; 619 u8 rate_idx = td->tx_rate_idx; 620 u16 rateval = 0; 621 u32 val; 622 bool cck = false; 623 int band; 624 625 if (skb != phy->mt76->test.tx_skb) 626 return; 627 628 switch (td->tx_rate_mode) { 629 case MT76_TM_TX_MODE_HT: 630 nss = 1 + (rate_idx >> 3); 631 mode = MT_PHY_TYPE_HT; 632 break; 633 case MT76_TM_TX_MODE_VHT: 634 mode = MT_PHY_TYPE_VHT; 635 break; 636 case MT76_TM_TX_MODE_HE_SU: 637 mode = MT_PHY_TYPE_HE_SU; 638 break; 639 case MT76_TM_TX_MODE_HE_EXT_SU: 640 mode = MT_PHY_TYPE_HE_EXT_SU; 641 break; 642 case MT76_TM_TX_MODE_HE_TB: 643 mode = MT_PHY_TYPE_HE_TB; 644 break; 645 case MT76_TM_TX_MODE_HE_MU: 646 mode = MT_PHY_TYPE_HE_MU; 647 break; 648 case MT76_TM_TX_MODE_CCK: 649 cck = true; 650 fallthrough; 651 case MT76_TM_TX_MODE_OFDM: 652 band = phy->mt76->chandef.chan->band; 653 if (band == NL80211_BAND_2GHZ && !cck) 654 rate_idx += 4; 655 656 r = &phy->mt76->hw->wiphy->bands[band]->bitrates[rate_idx]; 657 val = cck ? r->hw_value_short : r->hw_value; 658 659 mode = val >> 8; 660 rate_idx = val & 0xff; 661 break; 662 default: 663 mode = MT_PHY_TYPE_OFDM; 664 break; 665 } 666 667 switch (phy->mt76->chandef.width) { 668 case NL80211_CHAN_WIDTH_40: 669 bw = 1; 670 break; 671 case NL80211_CHAN_WIDTH_80: 672 bw = 2; 673 break; 674 case NL80211_CHAN_WIDTH_80P80: 675 case NL80211_CHAN_WIDTH_160: 676 bw = 3; 677 break; 678 default: 679 bw = 0; 680 break; 681 } 682 683 if (td->tx_rate_stbc && nss == 1) { 684 nss++; 685 rateval |= MT_TX_RATE_STBC; 686 } 687 688 rateval |= FIELD_PREP(MT_TX_RATE_IDX, rate_idx) | 689 FIELD_PREP(MT_TX_RATE_MODE, mode) | 690 FIELD_PREP(MT_TX_RATE_NSS, nss - 1); 691 692 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE); 693 694 le32p_replace_bits(&txwi[3], 1, MT_TXD3_REM_TX_COUNT); 695 if (td->tx_rate_mode < MT76_TM_TX_MODE_HT) 696 txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE); 697 698 val = MT_TXD6_FIXED_BW | 699 FIELD_PREP(MT_TXD6_BW, bw) | 700 FIELD_PREP(MT_TXD6_TX_RATE, rateval) | 701 FIELD_PREP(MT_TXD6_SGI, td->tx_rate_sgi); 702 703 /* for HE_SU/HE_EXT_SU PPDU 704 * - 1x, 2x, 4x LTF + 0.8us GI 705 * - 2x LTF + 1.6us GI, 4x LTF + 3.2us GI 706 * for HE_MU PPDU 707 * - 2x, 4x LTF + 0.8us GI 708 * - 2x LTF + 1.6us GI, 4x LTF + 3.2us GI 709 * for HE_TB PPDU 710 * - 1x, 2x LTF + 1.6us GI 711 * - 4x LTF + 3.2us GI 712 */ 713 if (mode >= MT_PHY_TYPE_HE_SU) 714 val |= FIELD_PREP(MT_TXD6_HELTF, td->tx_ltf); 715 716 if (td->tx_rate_ldpc || (bw > 0 && mode >= MT_PHY_TYPE_HE_SU)) 717 val |= MT_TXD6_LDPC; 718 719 txwi[3] &= ~cpu_to_le32(MT_TXD3_SN_VALID); 720 txwi[6] |= cpu_to_le32(val); 721 txwi[7] |= cpu_to_le32(FIELD_PREP(MT_TXD7_SPE_IDX, 722 phy->test.spe_idx)); 723 #endif 724 } 725 726 void mt7915_mac_write_txwi(struct mt76_dev *dev, __le32 *txwi, 727 struct sk_buff *skb, struct mt76_wcid *wcid, int pid, 728 struct ieee80211_key_conf *key, 729 enum mt76_txq_id qid, u32 changed) 730 { 731 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 732 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2; 733 struct mt76_phy *mphy = &dev->phy; 734 735 if (phy_idx && dev->phys[MT_BAND1]) 736 mphy = dev->phys[MT_BAND1]; 737 738 mt76_connac2_mac_write_txwi(dev, txwi, skb, wcid, key, pid, qid, changed); 739 740 if (mt76_testmode_enabled(mphy)) 741 mt7915_mac_write_txwi_tm(mphy->priv, txwi, skb); 742 } 743 744 int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, 745 enum mt76_txq_id qid, struct mt76_wcid *wcid, 746 struct ieee80211_sta *sta, 747 struct mt76_tx_info *tx_info) 748 { 749 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_info->skb->data; 750 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 751 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb); 752 struct ieee80211_key_conf *key = info->control.hw_key; 753 struct ieee80211_vif *vif = info->control.vif; 754 struct mt76_connac_fw_txp *txp; 755 struct mt76_txwi_cache *t; 756 int id, i, nbuf = tx_info->nbuf - 1; 757 u8 *txwi = (u8 *)txwi_ptr; 758 int pid; 759 760 if (unlikely(tx_info->skb->len <= ETH_HLEN)) 761 return -EINVAL; 762 763 if (!wcid) 764 wcid = &dev->mt76.global_wcid; 765 766 if (sta) { 767 struct mt7915_sta *msta; 768 769 msta = (struct mt7915_sta *)sta->drv_priv; 770 771 if (time_after(jiffies, msta->jiffies + HZ / 4)) { 772 info->flags |= IEEE80211_TX_CTL_REQ_TX_STATUS; 773 msta->jiffies = jiffies; 774 } 775 } 776 777 t = (struct mt76_txwi_cache *)(txwi + mdev->drv->txwi_size); 778 t->skb = tx_info->skb; 779 780 id = mt76_token_consume(mdev, &t); 781 if (id < 0) 782 return id; 783 784 pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb); 785 mt7915_mac_write_txwi(mdev, txwi_ptr, tx_info->skb, wcid, pid, key, 786 qid, 0); 787 788 txp = (struct mt76_connac_fw_txp *)(txwi + MT_TXD_SIZE); 789 for (i = 0; i < nbuf; i++) { 790 txp->buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr); 791 txp->len[i] = cpu_to_le16(tx_info->buf[i + 1].len); 792 } 793 txp->nbuf = nbuf; 794 795 txp->flags = cpu_to_le16(MT_CT_INFO_APPLY_TXD | MT_CT_INFO_FROM_HOST); 796 797 if (!key) 798 txp->flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME); 799 800 if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && 801 ieee80211_is_mgmt(hdr->frame_control)) 802 txp->flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME); 803 804 if (vif) { 805 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv; 806 807 txp->bss_idx = mvif->mt76.idx; 808 } 809 810 txp->token = cpu_to_le16(id); 811 if (test_bit(MT_WCID_FLAG_4ADDR, &wcid->flags)) 812 txp->rept_wds_wcid = cpu_to_le16(wcid->idx); 813 else 814 txp->rept_wds_wcid = cpu_to_le16(0x3ff); 815 tx_info->skb = NULL; 816 817 /* pass partial skb header to fw */ 818 tx_info->buf[1].len = MT_CT_PARSE_LEN; 819 tx_info->buf[1].skip_unmap = true; 820 tx_info->nbuf = MT_CT_DMA_BUF_NUM; 821 822 return 0; 823 } 824 825 u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id) 826 { 827 struct mt76_connac_fw_txp *txp = ptr + MT_TXD_SIZE; 828 __le32 *txwi = ptr; 829 u32 val; 830 831 memset(ptr, 0, MT_TXD_SIZE + sizeof(*txp)); 832 833 val = FIELD_PREP(MT_TXD0_TX_BYTES, MT_TXD_SIZE) | 834 FIELD_PREP(MT_TXD0_PKT_FMT, MT_TX_TYPE_CT); 835 txwi[0] = cpu_to_le32(val); 836 837 val = MT_TXD1_LONG_FORMAT | 838 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_3); 839 txwi[1] = cpu_to_le32(val); 840 841 txp->token = cpu_to_le16(token_id); 842 txp->nbuf = 1; 843 txp->buf[0] = cpu_to_le32(phys + MT_TXD_SIZE + sizeof(*txp)); 844 845 return MT_TXD_SIZE + sizeof(*txp); 846 } 847 848 static void 849 mt7915_mac_tx_free_prepare(struct mt7915_dev *dev) 850 { 851 struct mt76_dev *mdev = &dev->mt76; 852 struct mt76_phy *mphy_ext = mdev->phys[MT_BAND1]; 853 854 /* clean DMA queues and unmap buffers first */ 855 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false); 856 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false); 857 if (mphy_ext) { 858 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_PSD], false); 859 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_BE], false); 860 } 861 } 862 863 static void 864 mt7915_mac_tx_free_done(struct mt7915_dev *dev, 865 struct list_head *free_list, bool wake) 866 { 867 struct sk_buff *skb, *tmp; 868 869 mt7915_mac_sta_poll(dev); 870 871 if (wake) 872 mt76_set_tx_blocked(&dev->mt76, false); 873 874 mt76_worker_schedule(&dev->mt76.tx_worker); 875 876 list_for_each_entry_safe(skb, tmp, free_list, list) { 877 skb_list_del_init(skb); 878 napi_consume_skb(skb, 1); 879 } 880 } 881 882 static void 883 mt7915_mac_tx_free(struct mt7915_dev *dev, void *data, int len) 884 { 885 struct mt76_connac_tx_free *free = data; 886 __le32 *tx_info = (__le32 *)(data + sizeof(*free)); 887 struct mt76_dev *mdev = &dev->mt76; 888 struct mt76_txwi_cache *txwi; 889 struct ieee80211_sta *sta = NULL; 890 struct mt76_wcid *wcid = NULL; 891 LIST_HEAD(free_list); 892 void *end = data + len; 893 bool v3, wake = false; 894 u16 total, count = 0; 895 u32 txd = le32_to_cpu(free->txd); 896 __le32 *cur_info; 897 898 mt7915_mac_tx_free_prepare(dev); 899 900 total = le16_get_bits(free->ctrl, MT_TX_FREE_MSDU_CNT); 901 v3 = (FIELD_GET(MT_TX_FREE_VER, txd) == 0x4); 902 903 for (cur_info = tx_info; count < total; cur_info++) { 904 u32 msdu, info; 905 u8 i; 906 907 if (WARN_ON_ONCE((void *)cur_info >= end)) 908 return; 909 910 /* 911 * 1'b1: new wcid pair. 912 * 1'b0: msdu_id with the same 'wcid pair' as above. 913 */ 914 info = le32_to_cpu(*cur_info); 915 if (info & MT_TX_FREE_PAIR) { 916 struct mt7915_sta *msta; 917 u16 idx; 918 919 idx = FIELD_GET(MT_TX_FREE_WLAN_ID, info); 920 wcid = rcu_dereference(dev->mt76.wcid[idx]); 921 sta = wcid_to_sta(wcid); 922 if (!sta) 923 continue; 924 925 msta = container_of(wcid, struct mt7915_sta, wcid); 926 mt76_wcid_add_poll(&dev->mt76, &msta->wcid); 927 continue; 928 } 929 930 if (!mtk_wed_device_active(&mdev->mmio.wed) && wcid) { 931 u32 tx_retries = 0, tx_failed = 0; 932 933 if (v3 && (info & MT_TX_FREE_MPDU_HEADER_V3)) { 934 tx_retries = 935 FIELD_GET(MT_TX_FREE_COUNT_V3, info) - 1; 936 tx_failed = tx_retries + 937 !!FIELD_GET(MT_TX_FREE_STAT_V3, info); 938 } else if (!v3 && (info & MT_TX_FREE_MPDU_HEADER)) { 939 tx_retries = 940 FIELD_GET(MT_TX_FREE_COUNT, info) - 1; 941 tx_failed = tx_retries + 942 !!FIELD_GET(MT_TX_FREE_STAT, info); 943 } 944 wcid->stats.tx_retries += tx_retries; 945 wcid->stats.tx_failed += tx_failed; 946 } 947 948 if (v3 && (info & MT_TX_FREE_MPDU_HEADER_V3)) 949 continue; 950 951 for (i = 0; i < 1 + v3; i++) { 952 if (v3) { 953 msdu = (info >> (15 * i)) & MT_TX_FREE_MSDU_ID_V3; 954 if (msdu == MT_TX_FREE_MSDU_ID_V3) 955 continue; 956 } else { 957 msdu = FIELD_GET(MT_TX_FREE_MSDU_ID, info); 958 } 959 count++; 960 txwi = mt76_token_release(mdev, msdu, &wake); 961 if (!txwi) 962 continue; 963 964 mt76_connac2_txwi_free(mdev, txwi, sta, &free_list); 965 } 966 } 967 968 mt7915_mac_tx_free_done(dev, &free_list, wake); 969 } 970 971 static void 972 mt7915_mac_tx_free_v0(struct mt7915_dev *dev, void *data, int len) 973 { 974 struct mt76_connac_tx_free *free = data; 975 __le16 *info = (__le16 *)(data + sizeof(*free)); 976 struct mt76_dev *mdev = &dev->mt76; 977 void *end = data + len; 978 LIST_HEAD(free_list); 979 bool wake = false; 980 u8 i, count; 981 982 mt7915_mac_tx_free_prepare(dev); 983 984 count = FIELD_GET(MT_TX_FREE_MSDU_CNT_V0, le16_to_cpu(free->ctrl)); 985 if (WARN_ON_ONCE((void *)&info[count] > end)) 986 return; 987 988 for (i = 0; i < count; i++) { 989 struct mt76_txwi_cache *txwi; 990 u16 msdu = le16_to_cpu(info[i]); 991 992 txwi = mt76_token_release(mdev, msdu, &wake); 993 if (!txwi) 994 continue; 995 996 mt76_connac2_txwi_free(mdev, txwi, NULL, &free_list); 997 } 998 999 mt7915_mac_tx_free_done(dev, &free_list, wake); 1000 } 1001 1002 static void mt7915_mac_add_txs(struct mt7915_dev *dev, void *data) 1003 { 1004 struct mt7915_sta *msta = NULL; 1005 struct mt76_wcid *wcid; 1006 __le32 *txs_data = data; 1007 u16 wcidx; 1008 u8 pid; 1009 1010 wcidx = le32_get_bits(txs_data[2], MT_TXS2_WCID); 1011 pid = le32_get_bits(txs_data[3], MT_TXS3_PID); 1012 1013 if (pid < MT_PACKET_ID_WED) 1014 return; 1015 1016 if (wcidx >= mt7915_wtbl_size(dev)) 1017 return; 1018 1019 rcu_read_lock(); 1020 1021 wcid = rcu_dereference(dev->mt76.wcid[wcidx]); 1022 if (!wcid) 1023 goto out; 1024 1025 msta = container_of(wcid, struct mt7915_sta, wcid); 1026 1027 if (pid == MT_PACKET_ID_WED) 1028 mt76_connac2_mac_fill_txs(&dev->mt76, wcid, txs_data); 1029 else 1030 mt76_connac2_mac_add_txs_skb(&dev->mt76, wcid, pid, txs_data); 1031 1032 if (!wcid->sta) 1033 goto out; 1034 1035 mt76_wcid_add_poll(&dev->mt76, &msta->wcid); 1036 1037 out: 1038 rcu_read_unlock(); 1039 } 1040 1041 bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len) 1042 { 1043 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 1044 __le32 *rxd = (__le32 *)data; 1045 __le32 *end = (__le32 *)&rxd[len / 4]; 1046 enum rx_pkt_type type; 1047 1048 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); 1049 1050 switch (type) { 1051 case PKT_TYPE_TXRX_NOTIFY: 1052 mt7915_mac_tx_free(dev, data, len); 1053 return false; 1054 case PKT_TYPE_TXRX_NOTIFY_V0: 1055 mt7915_mac_tx_free_v0(dev, data, len); 1056 return false; 1057 case PKT_TYPE_TXS: 1058 for (rxd += 2; rxd + 8 <= end; rxd += 8) 1059 mt7915_mac_add_txs(dev, rxd); 1060 return false; 1061 case PKT_TYPE_RX_FW_MONITOR: 1062 mt7915_debugfs_rx_fw_monitor(dev, data, len); 1063 return false; 1064 default: 1065 return true; 1066 } 1067 } 1068 1069 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 1070 struct sk_buff *skb, u32 *info) 1071 { 1072 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 1073 __le32 *rxd = (__le32 *)skb->data; 1074 __le32 *end = (__le32 *)&skb->data[skb->len]; 1075 enum rx_pkt_type type; 1076 1077 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); 1078 1079 switch (type) { 1080 case PKT_TYPE_TXRX_NOTIFY: 1081 mt7915_mac_tx_free(dev, skb->data, skb->len); 1082 napi_consume_skb(skb, 1); 1083 break; 1084 case PKT_TYPE_TXRX_NOTIFY_V0: 1085 mt7915_mac_tx_free_v0(dev, skb->data, skb->len); 1086 napi_consume_skb(skb, 1); 1087 break; 1088 case PKT_TYPE_RX_EVENT: 1089 mt7915_mcu_rx_event(dev, skb); 1090 break; 1091 case PKT_TYPE_TXRXV: 1092 mt7915_mac_fill_rx_vector(dev, skb); 1093 break; 1094 case PKT_TYPE_TXS: 1095 for (rxd += 2; rxd + 8 <= end; rxd += 8) 1096 mt7915_mac_add_txs(dev, rxd); 1097 dev_kfree_skb(skb); 1098 break; 1099 case PKT_TYPE_RX_FW_MONITOR: 1100 mt7915_debugfs_rx_fw_monitor(dev, skb->data, skb->len); 1101 dev_kfree_skb(skb); 1102 break; 1103 case PKT_TYPE_NORMAL: 1104 if (!mt7915_mac_fill_rx(dev, skb, q, info)) { 1105 mt76_rx(&dev->mt76, q, skb); 1106 return; 1107 } 1108 fallthrough; 1109 default: 1110 dev_kfree_skb(skb); 1111 break; 1112 } 1113 } 1114 1115 void mt7915_mac_cca_stats_reset(struct mt7915_phy *phy) 1116 { 1117 struct mt7915_dev *dev = phy->dev; 1118 u32 reg = MT_WF_PHY_RX_CTRL1(phy->mt76->band_idx); 1119 1120 mt76_clear(dev, reg, MT_WF_PHY_RX_CTRL1_STSCNT_EN); 1121 mt76_set(dev, reg, BIT(11) | BIT(9)); 1122 } 1123 1124 void mt7915_mac_reset_counters(struct mt7915_phy *phy) 1125 { 1126 struct mt7915_dev *dev = phy->dev; 1127 int i; 1128 1129 for (i = 0; i < 4; i++) { 1130 mt76_rr(dev, MT_TX_AGG_CNT(phy->mt76->band_idx, i)); 1131 mt76_rr(dev, MT_TX_AGG_CNT2(phy->mt76->band_idx, i)); 1132 } 1133 1134 phy->mt76->survey_time = ktime_get_boottime(); 1135 memset(phy->mt76->aggr_stats, 0, sizeof(phy->mt76->aggr_stats)); 1136 1137 /* reset airtime counters */ 1138 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(phy->mt76->band_idx), 1139 MT_WF_RMAC_MIB_RXTIME_CLR); 1140 1141 mt7915_mcu_get_chan_mib_info(phy, true); 1142 } 1143 1144 void mt7915_mac_set_timing(struct mt7915_phy *phy) 1145 { 1146 s16 coverage_class = phy->coverage_class; 1147 struct mt7915_dev *dev = phy->dev; 1148 struct mt7915_phy *ext_phy = mt7915_ext_phy(dev); 1149 u32 val, reg_offset; 1150 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | 1151 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); 1152 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | 1153 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28); 1154 u8 band = phy->mt76->band_idx; 1155 int eifs_ofdm = 84, sifs = 10, offset; 1156 bool a_band = !(phy->mt76->chandef.chan->band == NL80211_BAND_2GHZ); 1157 1158 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state)) 1159 return; 1160 1161 if (ext_phy) 1162 coverage_class = max_t(s16, dev->phy.coverage_class, 1163 ext_phy->coverage_class); 1164 1165 mt76_set(dev, MT_ARB_SCR(band), 1166 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1167 udelay(1); 1168 1169 offset = 3 * coverage_class; 1170 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | 1171 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); 1172 1173 if (!is_mt7915(&dev->mt76)) { 1174 if (!a_band) { 1175 mt76_wr(dev, MT_TMAC_ICR1(band), 1176 FIELD_PREP(MT_IFS_EIFS_CCK, 314)); 1177 eifs_ofdm = 78; 1178 } else { 1179 eifs_ofdm = 84; 1180 } 1181 } else if (a_band) { 1182 sifs = 16; 1183 } 1184 1185 mt76_wr(dev, MT_TMAC_CDTR(band), cck + reg_offset); 1186 mt76_wr(dev, MT_TMAC_ODTR(band), ofdm + reg_offset); 1187 mt76_wr(dev, MT_TMAC_ICR0(band), 1188 FIELD_PREP(MT_IFS_EIFS_OFDM, eifs_ofdm) | 1189 FIELD_PREP(MT_IFS_RIFS, 2) | 1190 FIELD_PREP(MT_IFS_SIFS, sifs) | 1191 FIELD_PREP(MT_IFS_SLOT, phy->slottime)); 1192 1193 if (phy->slottime < 20 || a_band) 1194 val = MT7915_CFEND_RATE_DEFAULT; 1195 else 1196 val = MT7915_CFEND_RATE_11B; 1197 1198 mt76_rmw_field(dev, MT_AGG_ACR0(band), MT_AGG_ACR_CFEND_RATE, val); 1199 mt76_clear(dev, MT_ARB_SCR(band), 1200 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1201 } 1202 1203 void mt7915_mac_enable_nf(struct mt7915_dev *dev, bool band) 1204 { 1205 u32 reg; 1206 1207 reg = is_mt7915(&dev->mt76) ? MT_WF_PHY_RXTD12(band) : 1208 MT_WF_PHY_RXTD12_MT7916(band); 1209 mt76_set(dev, reg, 1210 MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY | 1211 MT_WF_PHY_RXTD12_IRPI_SW_CLR); 1212 1213 reg = is_mt7915(&dev->mt76) ? MT_WF_PHY_RX_CTRL1(band) : 1214 MT_WF_PHY_RX_CTRL1_MT7916(band); 1215 mt76_set(dev, reg, FIELD_PREP(MT_WF_PHY_RX_CTRL1_IPI_EN, 0x5)); 1216 } 1217 1218 static u8 1219 mt7915_phy_get_nf(struct mt7915_phy *phy, int idx) 1220 { 1221 static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 }; 1222 struct mt7915_dev *dev = phy->dev; 1223 u32 val, sum = 0, n = 0; 1224 int nss, i; 1225 1226 for (nss = 0; nss < hweight8(phy->mt76->chainmask); nss++) { 1227 u32 reg = is_mt7915(&dev->mt76) ? 1228 MT_WF_IRPI_NSS(0, nss + (idx << dev->dbdc_support)) : 1229 MT_WF_IRPI_NSS_MT7916(idx, nss); 1230 1231 for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) { 1232 val = mt76_rr(dev, reg); 1233 sum += val * nf_power[i]; 1234 n += val; 1235 } 1236 } 1237 1238 if (!n) 1239 return 0; 1240 1241 return sum / n; 1242 } 1243 1244 void mt7915_update_channel(struct mt76_phy *mphy) 1245 { 1246 struct mt7915_phy *phy = mphy->priv; 1247 struct mt76_channel_state *state = mphy->chan_state; 1248 int nf; 1249 1250 mt7915_mcu_get_chan_mib_info(phy, false); 1251 1252 nf = mt7915_phy_get_nf(phy, phy->mt76->band_idx); 1253 if (!phy->noise) 1254 phy->noise = nf << 4; 1255 else if (nf) 1256 phy->noise += nf - (phy->noise >> 4); 1257 1258 state->noise = -(phy->noise >> 4); 1259 } 1260 1261 static bool 1262 mt7915_wait_reset_state(struct mt7915_dev *dev, u32 state) 1263 { 1264 bool ret; 1265 1266 ret = wait_event_timeout(dev->reset_wait, 1267 (READ_ONCE(dev->recovery.state) & state), 1268 MT7915_RESET_TIMEOUT); 1269 1270 WARN(!ret, "Timeout waiting for MCU reset state %x\n", state); 1271 return ret; 1272 } 1273 1274 static void 1275 mt7915_update_vif_beacon(void *priv, u8 *mac, struct ieee80211_vif *vif) 1276 { 1277 struct ieee80211_hw *hw = priv; 1278 1279 switch (vif->type) { 1280 case NL80211_IFTYPE_MESH_POINT: 1281 case NL80211_IFTYPE_ADHOC: 1282 case NL80211_IFTYPE_AP: 1283 mt7915_mcu_add_beacon(hw, vif, vif->bss_conf.enable_beacon, 1284 BSS_CHANGED_BEACON_ENABLED); 1285 break; 1286 default: 1287 break; 1288 } 1289 } 1290 1291 static void 1292 mt7915_update_beacons(struct mt7915_dev *dev) 1293 { 1294 struct mt76_phy *mphy_ext = dev->mt76.phys[MT_BAND1]; 1295 1296 ieee80211_iterate_active_interfaces(dev->mt76.hw, 1297 IEEE80211_IFACE_ITER_RESUME_ALL, 1298 mt7915_update_vif_beacon, dev->mt76.hw); 1299 1300 if (!mphy_ext) 1301 return; 1302 1303 ieee80211_iterate_active_interfaces(mphy_ext->hw, 1304 IEEE80211_IFACE_ITER_RESUME_ALL, 1305 mt7915_update_vif_beacon, mphy_ext->hw); 1306 } 1307 1308 static int 1309 mt7915_mac_restart(struct mt7915_dev *dev) 1310 { 1311 struct mt7915_phy *phy2; 1312 struct mt76_phy *ext_phy; 1313 struct mt76_dev *mdev = &dev->mt76; 1314 int i, ret; 1315 1316 ext_phy = dev->mt76.phys[MT_BAND1]; 1317 phy2 = ext_phy ? ext_phy->priv : NULL; 1318 1319 if (dev->hif2) { 1320 mt76_wr(dev, MT_INT1_MASK_CSR, 0x0); 1321 mt76_wr(dev, MT_INT1_SOURCE_CSR, ~0); 1322 } 1323 1324 if (dev_is_pci(mdev->dev)) { 1325 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0); 1326 if (dev->hif2) { 1327 if (is_mt7915(mdev)) 1328 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE, 0x0); 1329 else 1330 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE_MT7916, 0x0); 1331 } 1332 } 1333 1334 set_bit(MT76_RESET, &dev->mphy.state); 1335 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1336 wake_up(&dev->mt76.mcu.wait); 1337 if (ext_phy) 1338 set_bit(MT76_RESET, &ext_phy->state); 1339 1340 /* lock/unlock all queues to ensure that no tx is pending */ 1341 mt76_txq_schedule_all(&dev->mphy); 1342 if (ext_phy) 1343 mt76_txq_schedule_all(ext_phy); 1344 1345 /* disable all tx/rx napi */ 1346 mt76_worker_disable(&dev->mt76.tx_worker); 1347 mt76_for_each_q_rx(mdev, i) { 1348 if (mdev->q_rx[i].ndesc) 1349 napi_disable(&dev->mt76.napi[i]); 1350 } 1351 napi_disable(&dev->mt76.tx_napi); 1352 1353 /* token reinit */ 1354 mt76_connac2_tx_token_put(&dev->mt76); 1355 idr_init(&dev->mt76.token); 1356 1357 mt7915_dma_reset(dev, true); 1358 1359 local_bh_disable(); 1360 mt76_for_each_q_rx(mdev, i) { 1361 if (mdev->q_rx[i].ndesc) { 1362 napi_enable(&dev->mt76.napi[i]); 1363 napi_schedule(&dev->mt76.napi[i]); 1364 } 1365 } 1366 local_bh_enable(); 1367 clear_bit(MT76_MCU_RESET, &dev->mphy.state); 1368 clear_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state); 1369 1370 mt76_wr(dev, MT_INT_MASK_CSR, dev->mt76.mmio.irqmask); 1371 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 1372 1373 if (dev->hif2) { 1374 mt76_wr(dev, MT_INT1_MASK_CSR, dev->mt76.mmio.irqmask); 1375 mt76_wr(dev, MT_INT1_SOURCE_CSR, ~0); 1376 } 1377 if (dev_is_pci(mdev->dev)) { 1378 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff); 1379 if (dev->hif2) { 1380 mt76_wr(dev, MT_PCIE_RECOG_ID, 1381 dev->hif2->index | MT_PCIE_RECOG_ID_SEM); 1382 if (is_mt7915(mdev)) 1383 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE, 0xff); 1384 else 1385 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE_MT7916, 0xff); 1386 } 1387 } 1388 1389 /* load firmware */ 1390 ret = mt7915_mcu_init_firmware(dev); 1391 if (ret) 1392 goto out; 1393 1394 /* set the necessary init items */ 1395 ret = mt7915_mcu_set_eeprom(dev); 1396 if (ret) 1397 goto out; 1398 1399 mt7915_mac_init(dev); 1400 mt7915_init_txpower(&dev->phy); 1401 mt7915_init_txpower(phy2); 1402 ret = mt7915_txbf_init(dev); 1403 1404 if (test_bit(MT76_STATE_RUNNING, &dev->mphy.state)) { 1405 ret = mt7915_run(dev->mphy.hw); 1406 if (ret) 1407 goto out; 1408 } 1409 1410 if (ext_phy && test_bit(MT76_STATE_RUNNING, &ext_phy->state)) { 1411 ret = mt7915_run(ext_phy->hw); 1412 if (ret) 1413 goto out; 1414 } 1415 1416 out: 1417 /* reset done */ 1418 clear_bit(MT76_RESET, &dev->mphy.state); 1419 if (phy2) 1420 clear_bit(MT76_RESET, &phy2->mt76->state); 1421 1422 local_bh_disable(); 1423 napi_enable(&dev->mt76.tx_napi); 1424 napi_schedule(&dev->mt76.tx_napi); 1425 local_bh_enable(); 1426 1427 mt76_worker_enable(&dev->mt76.tx_worker); 1428 1429 return ret; 1430 } 1431 1432 static void 1433 mt7915_mac_full_reset(struct mt7915_dev *dev) 1434 { 1435 struct mt76_phy *ext_phy; 1436 struct mt7915_phy *phy2; 1437 int i; 1438 1439 ext_phy = dev->mt76.phys[MT_BAND1]; 1440 phy2 = ext_phy ? ext_phy->priv : NULL; 1441 1442 dev->recovery.hw_full_reset = true; 1443 1444 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1445 wake_up(&dev->mt76.mcu.wait); 1446 ieee80211_stop_queues(mt76_hw(dev)); 1447 if (ext_phy) 1448 ieee80211_stop_queues(ext_phy->hw); 1449 1450 cancel_delayed_work_sync(&dev->mphy.mac_work); 1451 if (ext_phy) 1452 cancel_delayed_work_sync(&ext_phy->mac_work); 1453 1454 mutex_lock(&dev->mt76.mutex); 1455 for (i = 0; i < 10; i++) { 1456 if (!mt7915_mac_restart(dev)) 1457 break; 1458 } 1459 1460 if (i == 10) 1461 dev_err(dev->mt76.dev, "chip full reset failed\n"); 1462 1463 spin_lock_bh(&dev->mt76.sta_poll_lock); 1464 while (!list_empty(&dev->mt76.sta_poll_list)) 1465 list_del_init(dev->mt76.sta_poll_list.next); 1466 spin_unlock_bh(&dev->mt76.sta_poll_lock); 1467 1468 memset(dev->mt76.wcid_mask, 0, sizeof(dev->mt76.wcid_mask)); 1469 dev->mt76.vif_mask = 0; 1470 dev->phy.omac_mask = 0; 1471 if (phy2) 1472 phy2->omac_mask = 0; 1473 1474 i = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7915_WTBL_STA); 1475 dev->mt76.global_wcid.idx = i; 1476 dev->recovery.hw_full_reset = false; 1477 1478 mutex_unlock(&dev->mt76.mutex); 1479 1480 ieee80211_restart_hw(mt76_hw(dev)); 1481 if (ext_phy) 1482 ieee80211_restart_hw(ext_phy->hw); 1483 } 1484 1485 /* system error recovery */ 1486 void mt7915_mac_reset_work(struct work_struct *work) 1487 { 1488 struct mt7915_phy *phy2; 1489 struct mt76_phy *ext_phy; 1490 struct mt7915_dev *dev; 1491 int i; 1492 1493 dev = container_of(work, struct mt7915_dev, reset_work); 1494 ext_phy = dev->mt76.phys[MT_BAND1]; 1495 phy2 = ext_phy ? ext_phy->priv : NULL; 1496 1497 /* chip full reset */ 1498 if (dev->recovery.restart) { 1499 /* disable WA/WM WDT */ 1500 mt76_clear(dev, MT_WFDMA0_MCU_HOST_INT_ENA, 1501 MT_MCU_CMD_WDT_MASK); 1502 1503 if (READ_ONCE(dev->recovery.state) & MT_MCU_CMD_WA_WDT) 1504 dev->recovery.wa_reset_count++; 1505 else 1506 dev->recovery.wm_reset_count++; 1507 1508 mt7915_mac_full_reset(dev); 1509 1510 /* enable mcu irq */ 1511 mt7915_irq_enable(dev, MT_INT_MCU_CMD); 1512 mt7915_irq_disable(dev, 0); 1513 1514 /* enable WA/WM WDT */ 1515 mt76_set(dev, MT_WFDMA0_MCU_HOST_INT_ENA, MT_MCU_CMD_WDT_MASK); 1516 1517 dev->recovery.state = MT_MCU_CMD_NORMAL_STATE; 1518 dev->recovery.restart = false; 1519 return; 1520 } 1521 1522 /* chip partial reset */ 1523 if (!(READ_ONCE(dev->recovery.state) & MT_MCU_CMD_STOP_DMA)) 1524 return; 1525 1526 ieee80211_stop_queues(mt76_hw(dev)); 1527 if (ext_phy) 1528 ieee80211_stop_queues(ext_phy->hw); 1529 1530 set_bit(MT76_RESET, &dev->mphy.state); 1531 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1532 wake_up(&dev->mt76.mcu.wait); 1533 cancel_delayed_work_sync(&dev->mphy.mac_work); 1534 if (phy2) { 1535 set_bit(MT76_RESET, &phy2->mt76->state); 1536 cancel_delayed_work_sync(&phy2->mt76->mac_work); 1537 } 1538 1539 mutex_lock(&dev->mt76.mutex); 1540 1541 mt76_worker_disable(&dev->mt76.tx_worker); 1542 mt76_for_each_q_rx(&dev->mt76, i) 1543 napi_disable(&dev->mt76.napi[i]); 1544 napi_disable(&dev->mt76.tx_napi); 1545 1546 1547 if (mtk_wed_device_active(&dev->mt76.mmio.wed)) 1548 mtk_wed_device_stop(&dev->mt76.mmio.wed); 1549 1550 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_STOPPED); 1551 1552 if (mt7915_wait_reset_state(dev, MT_MCU_CMD_RESET_DONE)) { 1553 mt7915_dma_reset(dev, false); 1554 1555 mt76_connac2_tx_token_put(&dev->mt76); 1556 idr_init(&dev->mt76.token); 1557 1558 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_INIT); 1559 mt7915_wait_reset_state(dev, MT_MCU_CMD_RECOVERY_DONE); 1560 } 1561 1562 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_RESET_DONE); 1563 mt7915_wait_reset_state(dev, MT_MCU_CMD_NORMAL_STATE); 1564 1565 /* enable DMA Tx/Rx and interrupt */ 1566 mt7915_dma_start(dev, false, false); 1567 1568 clear_bit(MT76_MCU_RESET, &dev->mphy.state); 1569 clear_bit(MT76_RESET, &dev->mphy.state); 1570 if (phy2) 1571 clear_bit(MT76_RESET, &phy2->mt76->state); 1572 1573 local_bh_disable(); 1574 mt76_for_each_q_rx(&dev->mt76, i) { 1575 napi_enable(&dev->mt76.napi[i]); 1576 napi_schedule(&dev->mt76.napi[i]); 1577 } 1578 local_bh_enable(); 1579 1580 tasklet_schedule(&dev->mt76.irq_tasklet); 1581 1582 mt76_worker_enable(&dev->mt76.tx_worker); 1583 1584 local_bh_disable(); 1585 napi_enable(&dev->mt76.tx_napi); 1586 napi_schedule(&dev->mt76.tx_napi); 1587 local_bh_enable(); 1588 1589 ieee80211_wake_queues(mt76_hw(dev)); 1590 if (ext_phy) 1591 ieee80211_wake_queues(ext_phy->hw); 1592 1593 mutex_unlock(&dev->mt76.mutex); 1594 1595 mt7915_update_beacons(dev); 1596 1597 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work, 1598 MT7915_WATCHDOG_TIME); 1599 if (phy2) 1600 ieee80211_queue_delayed_work(ext_phy->hw, 1601 &phy2->mt76->mac_work, 1602 MT7915_WATCHDOG_TIME); 1603 } 1604 1605 /* firmware coredump */ 1606 void mt7915_mac_dump_work(struct work_struct *work) 1607 { 1608 const struct mt7915_mem_region *mem_region; 1609 struct mt7915_crash_data *crash_data; 1610 struct mt7915_dev *dev; 1611 struct mt7915_mem_hdr *hdr; 1612 size_t buf_len; 1613 int i; 1614 u32 num; 1615 u8 *buf; 1616 1617 dev = container_of(work, struct mt7915_dev, dump_work); 1618 1619 mutex_lock(&dev->dump_mutex); 1620 1621 crash_data = mt7915_coredump_new(dev); 1622 if (!crash_data) { 1623 mutex_unlock(&dev->dump_mutex); 1624 goto skip_coredump; 1625 } 1626 1627 mem_region = mt7915_coredump_get_mem_layout(dev, &num); 1628 if (!mem_region || !crash_data->memdump_buf_len) { 1629 mutex_unlock(&dev->dump_mutex); 1630 goto skip_memdump; 1631 } 1632 1633 buf = crash_data->memdump_buf; 1634 buf_len = crash_data->memdump_buf_len; 1635 1636 /* dumping memory content... */ 1637 memset(buf, 0, buf_len); 1638 for (i = 0; i < num; i++) { 1639 if (mem_region->len > buf_len) { 1640 dev_warn(dev->mt76.dev, "%s len %lu is too large\n", 1641 mem_region->name, 1642 (unsigned long)mem_region->len); 1643 break; 1644 } 1645 1646 /* reserve space for the header */ 1647 hdr = (void *)buf; 1648 buf += sizeof(*hdr); 1649 buf_len -= sizeof(*hdr); 1650 1651 mt7915_memcpy_fromio(dev, buf, mem_region->start, 1652 mem_region->len); 1653 1654 hdr->start = mem_region->start; 1655 hdr->len = mem_region->len; 1656 1657 if (!mem_region->len) 1658 /* note: the header remains, just with zero length */ 1659 break; 1660 1661 buf += mem_region->len; 1662 buf_len -= mem_region->len; 1663 1664 mem_region++; 1665 } 1666 1667 mutex_unlock(&dev->dump_mutex); 1668 1669 skip_memdump: 1670 mt7915_coredump_submit(dev); 1671 skip_coredump: 1672 queue_work(dev->mt76.wq, &dev->reset_work); 1673 } 1674 1675 void mt7915_reset(struct mt7915_dev *dev) 1676 { 1677 if (!dev->recovery.hw_init_done) 1678 return; 1679 1680 if (dev->recovery.hw_full_reset) 1681 return; 1682 1683 /* wm/wa exception: do full recovery */ 1684 if (READ_ONCE(dev->recovery.state) & MT_MCU_CMD_WDT_MASK) { 1685 dev->recovery.restart = true; 1686 dev_info(dev->mt76.dev, 1687 "%s indicated firmware crash, attempting recovery\n", 1688 wiphy_name(dev->mt76.hw->wiphy)); 1689 1690 mt7915_irq_disable(dev, MT_INT_MCU_CMD); 1691 queue_work(dev->mt76.wq, &dev->dump_work); 1692 return; 1693 } 1694 1695 if ((READ_ONCE(dev->recovery.state) & MT_MCU_CMD_STOP_DMA)) { 1696 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1697 wake_up(&dev->mt76.mcu.wait); 1698 } 1699 1700 queue_work(dev->mt76.wq, &dev->reset_work); 1701 wake_up(&dev->reset_wait); 1702 } 1703 1704 void mt7915_mac_update_stats(struct mt7915_phy *phy) 1705 { 1706 struct mt76_mib_stats *mib = &phy->mib; 1707 struct mt7915_dev *dev = phy->dev; 1708 int i, aggr0 = 0, aggr1, cnt; 1709 u8 band = phy->mt76->band_idx; 1710 u32 val; 1711 1712 cnt = mt76_rr(dev, MT_MIB_SDR3(band)); 1713 mib->fcs_err_cnt += is_mt7915(&dev->mt76) ? 1714 FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK, cnt) : 1715 FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK_MT7916, cnt); 1716 1717 cnt = mt76_rr(dev, MT_MIB_SDR4(band)); 1718 mib->rx_fifo_full_cnt += FIELD_GET(MT_MIB_SDR4_RX_FIFO_FULL_MASK, cnt); 1719 1720 cnt = mt76_rr(dev, MT_MIB_SDR5(band)); 1721 mib->rx_mpdu_cnt += cnt; 1722 1723 cnt = mt76_rr(dev, MT_MIB_SDR6(band)); 1724 mib->channel_idle_cnt += FIELD_GET(MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK, cnt); 1725 1726 cnt = mt76_rr(dev, MT_MIB_SDR7(band)); 1727 mib->rx_vector_mismatch_cnt += 1728 FIELD_GET(MT_MIB_SDR7_RX_VECTOR_MISMATCH_CNT_MASK, cnt); 1729 1730 cnt = mt76_rr(dev, MT_MIB_SDR8(band)); 1731 mib->rx_delimiter_fail_cnt += 1732 FIELD_GET(MT_MIB_SDR8_RX_DELIMITER_FAIL_CNT_MASK, cnt); 1733 1734 cnt = mt76_rr(dev, MT_MIB_SDR10(band)); 1735 mib->rx_mrdy_cnt += is_mt7915(&dev->mt76) ? 1736 FIELD_GET(MT_MIB_SDR10_MRDY_COUNT_MASK, cnt) : 1737 FIELD_GET(MT_MIB_SDR10_MRDY_COUNT_MASK_MT7916, cnt); 1738 1739 cnt = mt76_rr(dev, MT_MIB_SDR11(band)); 1740 mib->rx_len_mismatch_cnt += 1741 FIELD_GET(MT_MIB_SDR11_RX_LEN_MISMATCH_CNT_MASK, cnt); 1742 1743 cnt = mt76_rr(dev, MT_MIB_SDR12(band)); 1744 mib->tx_ampdu_cnt += cnt; 1745 1746 cnt = mt76_rr(dev, MT_MIB_SDR13(band)); 1747 mib->tx_stop_q_empty_cnt += 1748 FIELD_GET(MT_MIB_SDR13_TX_STOP_Q_EMPTY_CNT_MASK, cnt); 1749 1750 cnt = mt76_rr(dev, MT_MIB_SDR14(band)); 1751 mib->tx_mpdu_attempts_cnt += is_mt7915(&dev->mt76) ? 1752 FIELD_GET(MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK, cnt) : 1753 FIELD_GET(MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK_MT7916, cnt); 1754 1755 cnt = mt76_rr(dev, MT_MIB_SDR15(band)); 1756 mib->tx_mpdu_success_cnt += is_mt7915(&dev->mt76) ? 1757 FIELD_GET(MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK, cnt) : 1758 FIELD_GET(MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK_MT7916, cnt); 1759 1760 cnt = mt76_rr(dev, MT_MIB_SDR16(band)); 1761 mib->primary_cca_busy_time += 1762 FIELD_GET(MT_MIB_SDR16_PRIMARY_CCA_BUSY_TIME_MASK, cnt); 1763 1764 cnt = mt76_rr(dev, MT_MIB_SDR17(band)); 1765 mib->secondary_cca_busy_time += 1766 FIELD_GET(MT_MIB_SDR17_SECONDARY_CCA_BUSY_TIME_MASK, cnt); 1767 1768 cnt = mt76_rr(dev, MT_MIB_SDR18(band)); 1769 mib->primary_energy_detect_time += 1770 FIELD_GET(MT_MIB_SDR18_PRIMARY_ENERGY_DETECT_TIME_MASK, cnt); 1771 1772 cnt = mt76_rr(dev, MT_MIB_SDR19(band)); 1773 mib->cck_mdrdy_time += FIELD_GET(MT_MIB_SDR19_CCK_MDRDY_TIME_MASK, cnt); 1774 1775 cnt = mt76_rr(dev, MT_MIB_SDR20(band)); 1776 mib->ofdm_mdrdy_time += 1777 FIELD_GET(MT_MIB_SDR20_OFDM_VHT_MDRDY_TIME_MASK, cnt); 1778 1779 cnt = mt76_rr(dev, MT_MIB_SDR21(band)); 1780 mib->green_mdrdy_time += 1781 FIELD_GET(MT_MIB_SDR21_GREEN_MDRDY_TIME_MASK, cnt); 1782 1783 cnt = mt76_rr(dev, MT_MIB_SDR22(band)); 1784 mib->rx_ampdu_cnt += cnt; 1785 1786 cnt = mt76_rr(dev, MT_MIB_SDR23(band)); 1787 mib->rx_ampdu_bytes_cnt += cnt; 1788 1789 cnt = mt76_rr(dev, MT_MIB_SDR24(band)); 1790 mib->rx_ampdu_valid_subframe_cnt += is_mt7915(&dev->mt76) ? 1791 FIELD_GET(MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK, cnt) : 1792 FIELD_GET(MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK_MT7916, cnt); 1793 1794 cnt = mt76_rr(dev, MT_MIB_SDR25(band)); 1795 mib->rx_ampdu_valid_subframe_bytes_cnt += cnt; 1796 1797 cnt = mt76_rr(dev, MT_MIB_SDR27(band)); 1798 mib->tx_rwp_fail_cnt += 1799 FIELD_GET(MT_MIB_SDR27_TX_RWP_FAIL_CNT_MASK, cnt); 1800 1801 cnt = mt76_rr(dev, MT_MIB_SDR28(band)); 1802 mib->tx_rwp_need_cnt += 1803 FIELD_GET(MT_MIB_SDR28_TX_RWP_NEED_CNT_MASK, cnt); 1804 1805 cnt = mt76_rr(dev, MT_MIB_SDR29(band)); 1806 mib->rx_pfdrop_cnt += is_mt7915(&dev->mt76) ? 1807 FIELD_GET(MT_MIB_SDR29_RX_PFDROP_CNT_MASK, cnt) : 1808 FIELD_GET(MT_MIB_SDR29_RX_PFDROP_CNT_MASK_MT7916, cnt); 1809 1810 cnt = mt76_rr(dev, MT_MIB_SDRVEC(band)); 1811 mib->rx_vec_queue_overflow_drop_cnt += is_mt7915(&dev->mt76) ? 1812 FIELD_GET(MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK, cnt) : 1813 FIELD_GET(MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK_MT7916, cnt); 1814 1815 cnt = mt76_rr(dev, MT_MIB_SDR31(band)); 1816 mib->rx_ba_cnt += cnt; 1817 1818 cnt = mt76_rr(dev, MT_MIB_SDRMUBF(band)); 1819 mib->tx_bf_cnt += FIELD_GET(MT_MIB_MU_BF_TX_CNT, cnt); 1820 1821 cnt = mt76_rr(dev, MT_MIB_DR8(band)); 1822 mib->tx_mu_mpdu_cnt += cnt; 1823 1824 cnt = mt76_rr(dev, MT_MIB_DR9(band)); 1825 mib->tx_mu_acked_mpdu_cnt += cnt; 1826 1827 cnt = mt76_rr(dev, MT_MIB_DR11(band)); 1828 mib->tx_su_acked_mpdu_cnt += cnt; 1829 1830 cnt = mt76_rr(dev, MT_ETBF_PAR_RPT0(band)); 1831 mib->tx_bf_rx_fb_bw = FIELD_GET(MT_ETBF_PAR_RPT0_FB_BW, cnt); 1832 mib->tx_bf_rx_fb_nc_cnt += FIELD_GET(MT_ETBF_PAR_RPT0_FB_NC, cnt); 1833 mib->tx_bf_rx_fb_nr_cnt += FIELD_GET(MT_ETBF_PAR_RPT0_FB_NR, cnt); 1834 1835 for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) { 1836 cnt = mt76_rr(dev, MT_PLE_AMSDU_PACK_MSDU_CNT(i)); 1837 mib->tx_amsdu[i] += cnt; 1838 mib->tx_amsdu_cnt += cnt; 1839 } 1840 1841 if (is_mt7915(&dev->mt76)) { 1842 for (i = 0, aggr1 = aggr0 + 8; i < 4; i++) { 1843 val = mt76_rr(dev, MT_MIB_MB_SDR1(band, (i << 4))); 1844 mib->ba_miss_cnt += 1845 FIELD_GET(MT_MIB_BA_MISS_COUNT_MASK, val); 1846 mib->ack_fail_cnt += 1847 FIELD_GET(MT_MIB_ACK_FAIL_COUNT_MASK, val); 1848 1849 val = mt76_rr(dev, MT_MIB_MB_SDR0(band, (i << 4))); 1850 mib->rts_cnt += FIELD_GET(MT_MIB_RTS_COUNT_MASK, val); 1851 mib->rts_retries_cnt += 1852 FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, val); 1853 1854 val = mt76_rr(dev, MT_TX_AGG_CNT(band, i)); 1855 phy->mt76->aggr_stats[aggr0++] += val & 0xffff; 1856 phy->mt76->aggr_stats[aggr0++] += val >> 16; 1857 1858 val = mt76_rr(dev, MT_TX_AGG_CNT2(band, i)); 1859 phy->mt76->aggr_stats[aggr1++] += val & 0xffff; 1860 phy->mt76->aggr_stats[aggr1++] += val >> 16; 1861 } 1862 1863 cnt = mt76_rr(dev, MT_MIB_SDR32(band)); 1864 mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt); 1865 1866 cnt = mt76_rr(dev, MT_MIB_SDR33(band)); 1867 mib->tx_pkt_ibf_cnt += FIELD_GET(MT_MIB_SDR33_TX_PKT_IBF_CNT, cnt); 1868 1869 cnt = mt76_rr(dev, MT_ETBF_TX_APP_CNT(band)); 1870 mib->tx_bf_ibf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_IBF_CNT, cnt); 1871 mib->tx_bf_ebf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_EBF_CNT, cnt); 1872 1873 cnt = mt76_rr(dev, MT_ETBF_TX_NDP_BFRP(band)); 1874 mib->tx_bf_fb_cpl_cnt += FIELD_GET(MT_ETBF_TX_FB_CPL, cnt); 1875 mib->tx_bf_fb_trig_cnt += FIELD_GET(MT_ETBF_TX_FB_TRI, cnt); 1876 1877 cnt = mt76_rr(dev, MT_ETBF_RX_FB_CNT(band)); 1878 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_ETBF_RX_FB_ALL, cnt); 1879 mib->tx_bf_rx_fb_he_cnt += FIELD_GET(MT_ETBF_RX_FB_HE, cnt); 1880 mib->tx_bf_rx_fb_vht_cnt += FIELD_GET(MT_ETBF_RX_FB_VHT, cnt); 1881 mib->tx_bf_rx_fb_ht_cnt += FIELD_GET(MT_ETBF_RX_FB_HT, cnt); 1882 } else { 1883 for (i = 0; i < 2; i++) { 1884 /* rts count */ 1885 val = mt76_rr(dev, MT_MIB_MB_SDR0(band, (i << 2))); 1886 mib->rts_cnt += FIELD_GET(GENMASK(15, 0), val); 1887 mib->rts_cnt += FIELD_GET(GENMASK(31, 16), val); 1888 1889 /* rts retry count */ 1890 val = mt76_rr(dev, MT_MIB_MB_SDR1(band, (i << 2))); 1891 mib->rts_retries_cnt += FIELD_GET(GENMASK(15, 0), val); 1892 mib->rts_retries_cnt += FIELD_GET(GENMASK(31, 16), val); 1893 1894 /* ba miss count */ 1895 val = mt76_rr(dev, MT_MIB_MB_SDR2(band, (i << 2))); 1896 mib->ba_miss_cnt += FIELD_GET(GENMASK(15, 0), val); 1897 mib->ba_miss_cnt += FIELD_GET(GENMASK(31, 16), val); 1898 1899 /* ack fail count */ 1900 val = mt76_rr(dev, MT_MIB_MB_BFTF(band, (i << 2))); 1901 mib->ack_fail_cnt += FIELD_GET(GENMASK(15, 0), val); 1902 mib->ack_fail_cnt += FIELD_GET(GENMASK(31, 16), val); 1903 } 1904 1905 for (i = 0; i < 8; i++) { 1906 val = mt76_rr(dev, MT_TX_AGG_CNT(band, i)); 1907 phy->mt76->aggr_stats[aggr0++] += FIELD_GET(GENMASK(15, 0), val); 1908 phy->mt76->aggr_stats[aggr0++] += FIELD_GET(GENMASK(31, 16), val); 1909 } 1910 1911 cnt = mt76_rr(dev, MT_MIB_SDR32(band)); 1912 mib->tx_pkt_ibf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_IBF_CNT, cnt); 1913 mib->tx_bf_ibf_ppdu_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_IBF_CNT, cnt); 1914 mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt); 1915 mib->tx_bf_ebf_ppdu_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt); 1916 1917 cnt = mt76_rr(dev, MT_MIB_BFCR7(band)); 1918 mib->tx_bf_fb_cpl_cnt += FIELD_GET(MT_MIB_BFCR7_BFEE_TX_FB_CPL, cnt); 1919 1920 cnt = mt76_rr(dev, MT_MIB_BFCR2(band)); 1921 mib->tx_bf_fb_trig_cnt += FIELD_GET(MT_MIB_BFCR2_BFEE_TX_FB_TRIG, cnt); 1922 1923 cnt = mt76_rr(dev, MT_MIB_BFCR0(band)); 1924 mib->tx_bf_rx_fb_vht_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_VHT, cnt); 1925 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_VHT, cnt); 1926 mib->tx_bf_rx_fb_ht_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_HT, cnt); 1927 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_HT, cnt); 1928 1929 cnt = mt76_rr(dev, MT_MIB_BFCR1(band)); 1930 mib->tx_bf_rx_fb_he_cnt += FIELD_GET(MT_MIB_BFCR1_RX_FB_HE, cnt); 1931 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR1_RX_FB_HE, cnt); 1932 } 1933 } 1934 1935 static void mt7915_mac_severe_check(struct mt7915_phy *phy) 1936 { 1937 struct mt7915_dev *dev = phy->dev; 1938 u32 trb; 1939 1940 if (!phy->omac_mask) 1941 return; 1942 1943 /* In rare cases, TRB pointers might be out of sync leads to RMAC 1944 * stopping Rx, so check status periodically to see if TRB hardware 1945 * requires minimal recovery. 1946 */ 1947 trb = mt76_rr(dev, MT_TRB_RXPSR0(phy->mt76->band_idx)); 1948 1949 if ((FIELD_GET(MT_TRB_RXPSR0_RX_RMAC_PTR, trb) != 1950 FIELD_GET(MT_TRB_RXPSR0_RX_WTBL_PTR, trb)) && 1951 (FIELD_GET(MT_TRB_RXPSR0_RX_RMAC_PTR, phy->trb_ts) != 1952 FIELD_GET(MT_TRB_RXPSR0_RX_WTBL_PTR, phy->trb_ts)) && 1953 trb == phy->trb_ts) 1954 mt7915_mcu_set_ser(dev, SER_RECOVER, SER_SET_RECOVER_L3_RX_ABORT, 1955 phy->mt76->band_idx); 1956 1957 phy->trb_ts = trb; 1958 } 1959 1960 void mt7915_mac_sta_rc_work(struct work_struct *work) 1961 { 1962 struct mt7915_dev *dev = container_of(work, struct mt7915_dev, rc_work); 1963 struct ieee80211_sta *sta; 1964 struct ieee80211_vif *vif; 1965 struct mt7915_sta *msta; 1966 u32 changed; 1967 LIST_HEAD(list); 1968 1969 spin_lock_bh(&dev->mt76.sta_poll_lock); 1970 list_splice_init(&dev->sta_rc_list, &list); 1971 1972 while (!list_empty(&list)) { 1973 msta = list_first_entry(&list, struct mt7915_sta, rc_list); 1974 list_del_init(&msta->rc_list); 1975 changed = msta->changed; 1976 msta->changed = 0; 1977 spin_unlock_bh(&dev->mt76.sta_poll_lock); 1978 1979 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv); 1980 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); 1981 1982 if (changed & (IEEE80211_RC_SUPP_RATES_CHANGED | 1983 IEEE80211_RC_NSS_CHANGED | 1984 IEEE80211_RC_BW_CHANGED)) 1985 mt7915_mcu_add_rate_ctrl(dev, vif, sta, true); 1986 1987 if (changed & IEEE80211_RC_SMPS_CHANGED) 1988 mt7915_mcu_add_smps(dev, vif, sta); 1989 1990 spin_lock_bh(&dev->mt76.sta_poll_lock); 1991 } 1992 1993 spin_unlock_bh(&dev->mt76.sta_poll_lock); 1994 } 1995 1996 void mt7915_mac_work(struct work_struct *work) 1997 { 1998 struct mt7915_phy *phy; 1999 struct mt76_phy *mphy; 2000 2001 mphy = (struct mt76_phy *)container_of(work, struct mt76_phy, 2002 mac_work.work); 2003 phy = mphy->priv; 2004 2005 mutex_lock(&mphy->dev->mutex); 2006 2007 mt76_update_survey(mphy); 2008 if (++mphy->mac_work_count == 5) { 2009 mphy->mac_work_count = 0; 2010 2011 mt7915_mac_update_stats(phy); 2012 mt7915_mac_severe_check(phy); 2013 2014 if (phy->dev->muru_debug) 2015 mt7915_mcu_muru_debug_get(phy); 2016 } 2017 2018 mutex_unlock(&mphy->dev->mutex); 2019 2020 mt76_tx_status_check(mphy->dev, false); 2021 2022 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, 2023 MT7915_WATCHDOG_TIME); 2024 } 2025 2026 static void mt7915_dfs_stop_radar_detector(struct mt7915_phy *phy) 2027 { 2028 struct mt7915_dev *dev = phy->dev; 2029 2030 if (phy->rdd_state & BIT(0)) 2031 mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_STOP, 0, 2032 MT_RX_SEL0, 0); 2033 if (phy->rdd_state & BIT(1)) 2034 mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_STOP, 1, 2035 MT_RX_SEL0, 0); 2036 } 2037 2038 static int mt7915_dfs_start_rdd(struct mt7915_dev *dev, int chain) 2039 { 2040 int err, region; 2041 2042 switch (dev->mt76.region) { 2043 case NL80211_DFS_ETSI: 2044 region = 0; 2045 break; 2046 case NL80211_DFS_JP: 2047 region = 2; 2048 break; 2049 case NL80211_DFS_FCC: 2050 default: 2051 region = 1; 2052 break; 2053 } 2054 2055 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_START, chain, 2056 MT_RX_SEL0, region); 2057 if (err < 0) 2058 return err; 2059 2060 if (is_mt7915(&dev->mt76)) { 2061 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_SET_WF_ANT, chain, 2062 0, dev->dbdc_support ? 2 : 0); 2063 if (err < 0) 2064 return err; 2065 } 2066 2067 return mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_DET_MODE, chain, 2068 MT_RX_SEL0, 1); 2069 } 2070 2071 static int mt7915_dfs_start_radar_detector(struct mt7915_phy *phy) 2072 { 2073 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 2074 struct mt7915_dev *dev = phy->dev; 2075 int err; 2076 2077 /* start CAC */ 2078 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_START, 2079 phy->mt76->band_idx, MT_RX_SEL0, 0); 2080 if (err < 0) 2081 return err; 2082 2083 err = mt7915_dfs_start_rdd(dev, phy->mt76->band_idx); 2084 if (err < 0) 2085 return err; 2086 2087 phy->rdd_state |= BIT(phy->mt76->band_idx); 2088 2089 if (!is_mt7915(&dev->mt76)) 2090 return 0; 2091 2092 if (chandef->width == NL80211_CHAN_WIDTH_160 || 2093 chandef->width == NL80211_CHAN_WIDTH_80P80) { 2094 err = mt7915_dfs_start_rdd(dev, 1); 2095 if (err < 0) 2096 return err; 2097 2098 phy->rdd_state |= BIT(1); 2099 } 2100 2101 return 0; 2102 } 2103 2104 static int 2105 mt7915_dfs_init_radar_specs(struct mt7915_phy *phy) 2106 { 2107 const struct mt7915_dfs_radar_spec *radar_specs; 2108 struct mt7915_dev *dev = phy->dev; 2109 int err, i; 2110 2111 switch (dev->mt76.region) { 2112 case NL80211_DFS_FCC: 2113 radar_specs = &fcc_radar_specs; 2114 err = mt7915_mcu_set_fcc5_lpn(dev, 8); 2115 if (err < 0) 2116 return err; 2117 break; 2118 case NL80211_DFS_ETSI: 2119 radar_specs = &etsi_radar_specs; 2120 break; 2121 case NL80211_DFS_JP: 2122 radar_specs = &jp_radar_specs; 2123 break; 2124 default: 2125 return -EINVAL; 2126 } 2127 2128 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) { 2129 err = mt7915_mcu_set_radar_th(dev, i, 2130 &radar_specs->radar_pattern[i]); 2131 if (err < 0) 2132 return err; 2133 } 2134 2135 return mt7915_mcu_set_pulse_th(dev, &radar_specs->pulse_th); 2136 } 2137 2138 int mt7915_dfs_init_radar_detector(struct mt7915_phy *phy) 2139 { 2140 struct mt7915_dev *dev = phy->dev; 2141 enum mt76_dfs_state dfs_state, prev_state; 2142 int err; 2143 2144 prev_state = phy->mt76->dfs_state; 2145 dfs_state = mt76_phy_dfs_state(phy->mt76); 2146 2147 if (prev_state == dfs_state) 2148 return 0; 2149 2150 if (prev_state == MT_DFS_STATE_UNKNOWN) 2151 mt7915_dfs_stop_radar_detector(phy); 2152 2153 if (dfs_state == MT_DFS_STATE_DISABLED) 2154 goto stop; 2155 2156 if (prev_state <= MT_DFS_STATE_DISABLED) { 2157 err = mt7915_dfs_init_radar_specs(phy); 2158 if (err < 0) 2159 return err; 2160 2161 err = mt7915_dfs_start_radar_detector(phy); 2162 if (err < 0) 2163 return err; 2164 2165 phy->mt76->dfs_state = MT_DFS_STATE_CAC; 2166 } 2167 2168 if (dfs_state == MT_DFS_STATE_CAC) 2169 return 0; 2170 2171 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_END, 2172 phy->mt76->band_idx, MT_RX_SEL0, 0); 2173 if (err < 0) { 2174 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN; 2175 return err; 2176 } 2177 2178 phy->mt76->dfs_state = MT_DFS_STATE_ACTIVE; 2179 return 0; 2180 2181 stop: 2182 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_NORMAL_START, 2183 phy->mt76->band_idx, MT_RX_SEL0, 0); 2184 if (err < 0) 2185 return err; 2186 2187 if (is_mt7915(&dev->mt76)) { 2188 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_SET_WF_ANT, 2189 phy->mt76->band_idx, 0, 2190 dev->dbdc_support ? 2 : 0); 2191 if (err < 0) 2192 return err; 2193 } 2194 2195 mt7915_dfs_stop_radar_detector(phy); 2196 phy->mt76->dfs_state = MT_DFS_STATE_DISABLED; 2197 2198 return 0; 2199 } 2200 2201 static int 2202 mt7915_mac_twt_duration_align(int duration) 2203 { 2204 return duration << 8; 2205 } 2206 2207 static u64 2208 mt7915_mac_twt_sched_list_add(struct mt7915_dev *dev, 2209 struct mt7915_twt_flow *flow) 2210 { 2211 struct mt7915_twt_flow *iter, *iter_next; 2212 u32 duration = flow->duration << 8; 2213 u64 start_tsf; 2214 2215 iter = list_first_entry_or_null(&dev->twt_list, 2216 struct mt7915_twt_flow, list); 2217 if (!iter || !iter->sched || iter->start_tsf > duration) { 2218 /* add flow as first entry in the list */ 2219 list_add(&flow->list, &dev->twt_list); 2220 return 0; 2221 } 2222 2223 list_for_each_entry_safe(iter, iter_next, &dev->twt_list, list) { 2224 start_tsf = iter->start_tsf + 2225 mt7915_mac_twt_duration_align(iter->duration); 2226 if (list_is_last(&iter->list, &dev->twt_list)) 2227 break; 2228 2229 if (!iter_next->sched || 2230 iter_next->start_tsf > start_tsf + duration) { 2231 list_add(&flow->list, &iter->list); 2232 goto out; 2233 } 2234 } 2235 2236 /* add flow as last entry in the list */ 2237 list_add_tail(&flow->list, &dev->twt_list); 2238 out: 2239 return start_tsf; 2240 } 2241 2242 static int mt7915_mac_check_twt_req(struct ieee80211_twt_setup *twt) 2243 { 2244 struct ieee80211_twt_params *twt_agrt; 2245 u64 interval, duration; 2246 u16 mantissa; 2247 u8 exp; 2248 2249 /* only individual agreement supported */ 2250 if (twt->control & IEEE80211_TWT_CONTROL_NEG_TYPE_BROADCAST) 2251 return -EOPNOTSUPP; 2252 2253 /* only 256us unit supported */ 2254 if (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT) 2255 return -EOPNOTSUPP; 2256 2257 twt_agrt = (struct ieee80211_twt_params *)twt->params; 2258 2259 /* explicit agreement not supported */ 2260 if (!(twt_agrt->req_type & cpu_to_le16(IEEE80211_TWT_REQTYPE_IMPLICIT))) 2261 return -EOPNOTSUPP; 2262 2263 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, 2264 le16_to_cpu(twt_agrt->req_type)); 2265 mantissa = le16_to_cpu(twt_agrt->mantissa); 2266 duration = twt_agrt->min_twt_dur << 8; 2267 2268 interval = (u64)mantissa << exp; 2269 if (interval < duration) 2270 return -EOPNOTSUPP; 2271 2272 return 0; 2273 } 2274 2275 static bool 2276 mt7915_mac_twt_param_equal(struct mt7915_sta *msta, 2277 struct ieee80211_twt_params *twt_agrt) 2278 { 2279 u16 type = le16_to_cpu(twt_agrt->req_type); 2280 u8 exp; 2281 int i; 2282 2283 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, type); 2284 for (i = 0; i < MT7915_MAX_STA_TWT_AGRT; i++) { 2285 struct mt7915_twt_flow *f; 2286 2287 if (!(msta->twt.flowid_mask & BIT(i))) 2288 continue; 2289 2290 f = &msta->twt.flow[i]; 2291 if (f->duration == twt_agrt->min_twt_dur && 2292 f->mantissa == twt_agrt->mantissa && 2293 f->exp == exp && 2294 f->protection == !!(type & IEEE80211_TWT_REQTYPE_PROTECTION) && 2295 f->flowtype == !!(type & IEEE80211_TWT_REQTYPE_FLOWTYPE) && 2296 f->trigger == !!(type & IEEE80211_TWT_REQTYPE_TRIGGER)) 2297 return true; 2298 } 2299 2300 return false; 2301 } 2302 2303 void mt7915_mac_add_twt_setup(struct ieee80211_hw *hw, 2304 struct ieee80211_sta *sta, 2305 struct ieee80211_twt_setup *twt) 2306 { 2307 enum ieee80211_twt_setup_cmd setup_cmd = TWT_SETUP_CMD_REJECT; 2308 struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv; 2309 struct ieee80211_twt_params *twt_agrt = (void *)twt->params; 2310 u16 req_type = le16_to_cpu(twt_agrt->req_type); 2311 enum ieee80211_twt_setup_cmd sta_setup_cmd; 2312 struct mt7915_dev *dev = mt7915_hw_dev(hw); 2313 struct mt7915_twt_flow *flow; 2314 int flowid, table_id; 2315 u8 exp; 2316 2317 if (mt7915_mac_check_twt_req(twt)) 2318 goto out; 2319 2320 mutex_lock(&dev->mt76.mutex); 2321 2322 if (dev->twt.n_agrt == MT7915_MAX_TWT_AGRT) 2323 goto unlock; 2324 2325 if (hweight8(msta->twt.flowid_mask) == ARRAY_SIZE(msta->twt.flow)) 2326 goto unlock; 2327 2328 if (twt_agrt->min_twt_dur < MT7915_MIN_TWT_DUR) { 2329 setup_cmd = TWT_SETUP_CMD_DICTATE; 2330 twt_agrt->min_twt_dur = MT7915_MIN_TWT_DUR; 2331 goto unlock; 2332 } 2333 2334 flowid = ffs(~msta->twt.flowid_mask) - 1; 2335 twt_agrt->req_type &= ~cpu_to_le16(IEEE80211_TWT_REQTYPE_FLOWID); 2336 twt_agrt->req_type |= le16_encode_bits(flowid, 2337 IEEE80211_TWT_REQTYPE_FLOWID); 2338 2339 table_id = ffs(~dev->twt.table_mask) - 1; 2340 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, req_type); 2341 sta_setup_cmd = FIELD_GET(IEEE80211_TWT_REQTYPE_SETUP_CMD, req_type); 2342 2343 if (mt7915_mac_twt_param_equal(msta, twt_agrt)) 2344 goto unlock; 2345 2346 flow = &msta->twt.flow[flowid]; 2347 memset(flow, 0, sizeof(*flow)); 2348 INIT_LIST_HEAD(&flow->list); 2349 flow->wcid = msta->wcid.idx; 2350 flow->table_id = table_id; 2351 flow->id = flowid; 2352 flow->duration = twt_agrt->min_twt_dur; 2353 flow->mantissa = twt_agrt->mantissa; 2354 flow->exp = exp; 2355 flow->protection = !!(req_type & IEEE80211_TWT_REQTYPE_PROTECTION); 2356 flow->flowtype = !!(req_type & IEEE80211_TWT_REQTYPE_FLOWTYPE); 2357 flow->trigger = !!(req_type & IEEE80211_TWT_REQTYPE_TRIGGER); 2358 2359 if (sta_setup_cmd == TWT_SETUP_CMD_REQUEST || 2360 sta_setup_cmd == TWT_SETUP_CMD_SUGGEST) { 2361 u64 interval = (u64)le16_to_cpu(twt_agrt->mantissa) << exp; 2362 u64 flow_tsf, curr_tsf; 2363 u32 rem; 2364 2365 flow->sched = true; 2366 flow->start_tsf = mt7915_mac_twt_sched_list_add(dev, flow); 2367 curr_tsf = __mt7915_get_tsf(hw, msta->vif); 2368 div_u64_rem(curr_tsf - flow->start_tsf, interval, &rem); 2369 flow_tsf = curr_tsf + interval - rem; 2370 twt_agrt->twt = cpu_to_le64(flow_tsf); 2371 } else { 2372 list_add_tail(&flow->list, &dev->twt_list); 2373 } 2374 flow->tsf = le64_to_cpu(twt_agrt->twt); 2375 2376 if (mt7915_mcu_twt_agrt_update(dev, msta->vif, flow, MCU_TWT_AGRT_ADD)) 2377 goto unlock; 2378 2379 setup_cmd = TWT_SETUP_CMD_ACCEPT; 2380 dev->twt.table_mask |= BIT(table_id); 2381 msta->twt.flowid_mask |= BIT(flowid); 2382 dev->twt.n_agrt++; 2383 2384 unlock: 2385 mutex_unlock(&dev->mt76.mutex); 2386 out: 2387 twt_agrt->req_type &= ~cpu_to_le16(IEEE80211_TWT_REQTYPE_SETUP_CMD); 2388 twt_agrt->req_type |= 2389 le16_encode_bits(setup_cmd, IEEE80211_TWT_REQTYPE_SETUP_CMD); 2390 twt->control = (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT) | 2391 (twt->control & IEEE80211_TWT_CONTROL_RX_DISABLED); 2392 } 2393 2394 void mt7915_mac_twt_teardown_flow(struct mt7915_dev *dev, 2395 struct mt7915_sta *msta, 2396 u8 flowid) 2397 { 2398 struct mt7915_twt_flow *flow; 2399 2400 lockdep_assert_held(&dev->mt76.mutex); 2401 2402 if (flowid >= ARRAY_SIZE(msta->twt.flow)) 2403 return; 2404 2405 if (!(msta->twt.flowid_mask & BIT(flowid))) 2406 return; 2407 2408 flow = &msta->twt.flow[flowid]; 2409 if (mt7915_mcu_twt_agrt_update(dev, msta->vif, flow, 2410 MCU_TWT_AGRT_DELETE)) 2411 return; 2412 2413 list_del_init(&flow->list); 2414 msta->twt.flowid_mask &= ~BIT(flowid); 2415 dev->twt.table_mask &= ~BIT(flow->table_id); 2416 dev->twt.n_agrt--; 2417 } 2418